1/*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Copyright (C) 2005-2007 Freescale Semiconductor, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __LINUX_DMA_IPU_DMA_H
13#define __LINUX_DMA_IPU_DMA_H
14
15#include <linux/types.h>
16#include <linux/dmaengine.h>
17
18/* IPU DMA Controller channel definitions. */
19enum ipu_channel {
20	IDMAC_IC_0 = 0,		/* IC (encoding task) to memory */
21	IDMAC_IC_1 = 1,		/* IC (viewfinder task) to memory */
22	IDMAC_ADC_0 = 1,
23	IDMAC_IC_2 = 2,
24	IDMAC_ADC_1 = 2,
25	IDMAC_IC_3 = 3,
26	IDMAC_IC_4 = 4,
27	IDMAC_IC_5 = 5,
28	IDMAC_IC_6 = 6,
29	IDMAC_IC_7 = 7,		/* IC (sensor data) to memory */
30	IDMAC_IC_8 = 8,
31	IDMAC_IC_9 = 9,
32	IDMAC_IC_10 = 10,
33	IDMAC_IC_11 = 11,
34	IDMAC_IC_12 = 12,
35	IDMAC_IC_13 = 13,
36	IDMAC_SDC_0 = 14,	/* Background synchronous display data */
37	IDMAC_SDC_1 = 15,	/* Foreground data (overlay) */
38	IDMAC_SDC_2 = 16,
39	IDMAC_SDC_3 = 17,
40	IDMAC_ADC_2 = 18,
41	IDMAC_ADC_3 = 19,
42	IDMAC_ADC_4 = 20,
43	IDMAC_ADC_5 = 21,
44	IDMAC_ADC_6 = 22,
45	IDMAC_ADC_7 = 23,
46	IDMAC_PF_0 = 24,
47	IDMAC_PF_1 = 25,
48	IDMAC_PF_2 = 26,
49	IDMAC_PF_3 = 27,
50	IDMAC_PF_4 = 28,
51	IDMAC_PF_5 = 29,
52	IDMAC_PF_6 = 30,
53	IDMAC_PF_7 = 31,
54};
55
56/* Order significant! */
57enum ipu_channel_status {
58	IPU_CHANNEL_FREE,
59	IPU_CHANNEL_INITIALIZED,
60	IPU_CHANNEL_READY,
61	IPU_CHANNEL_ENABLED,
62};
63
64#define IPU_CHANNELS_NUM 32
65
66enum pixel_fmt {
67	/* 1 byte */
68	IPU_PIX_FMT_GENERIC,
69	IPU_PIX_FMT_RGB332,
70	IPU_PIX_FMT_YUV420P,
71	IPU_PIX_FMT_YUV422P,
72	IPU_PIX_FMT_YUV420P2,
73	IPU_PIX_FMT_YVU422P,
74	/* 2 bytes */
75	IPU_PIX_FMT_RGB565,
76	IPU_PIX_FMT_RGB666,
77	IPU_PIX_FMT_BGR666,
78	IPU_PIX_FMT_YUYV,
79	IPU_PIX_FMT_UYVY,
80	/* 3 bytes */
81	IPU_PIX_FMT_RGB24,
82	IPU_PIX_FMT_BGR24,
83	/* 4 bytes */
84	IPU_PIX_FMT_GENERIC_32,
85	IPU_PIX_FMT_RGB32,
86	IPU_PIX_FMT_BGR32,
87	IPU_PIX_FMT_ABGR32,
88	IPU_PIX_FMT_BGRA32,
89	IPU_PIX_FMT_RGBA32,
90};
91
92enum ipu_color_space {
93	IPU_COLORSPACE_RGB,
94	IPU_COLORSPACE_YCBCR,
95	IPU_COLORSPACE_YUV
96};
97
98/*
99 * Enumeration of IPU rotation modes
100 */
101enum ipu_rotate_mode {
102	/* Note the enum values correspond to BAM value */
103	IPU_ROTATE_NONE = 0,
104	IPU_ROTATE_VERT_FLIP = 1,
105	IPU_ROTATE_HORIZ_FLIP = 2,
106	IPU_ROTATE_180 = 3,
107	IPU_ROTATE_90_RIGHT = 4,
108	IPU_ROTATE_90_RIGHT_VFLIP = 5,
109	IPU_ROTATE_90_RIGHT_HFLIP = 6,
110	IPU_ROTATE_90_LEFT = 7,
111};
112
113/*
114 * Enumeration of DI ports for ADC.
115 */
116enum display_port {
117	DISP0,
118	DISP1,
119	DISP2,
120	DISP3
121};
122
123struct idmac_video_param {
124	unsigned short		in_width;
125	unsigned short		in_height;
126	uint32_t		in_pixel_fmt;
127	unsigned short		out_width;
128	unsigned short		out_height;
129	uint32_t		out_pixel_fmt;
130	unsigned short		out_stride;
131	bool			graphics_combine_en;
132	bool			global_alpha_en;
133	bool			key_color_en;
134	enum display_port	disp;
135	unsigned short		out_left;
136	unsigned short		out_top;
137};
138
139/*
140 * Union of initialization parameters for a logical channel. So far only video
141 * parameters are used.
142 */
143union ipu_channel_param {
144	struct idmac_video_param video;
145};
146
147struct idmac_tx_desc {
148	struct dma_async_tx_descriptor	txd;
149	struct scatterlist		*sg;	/* scatterlist for this */
150	unsigned int			sg_len;	/* tx-descriptor. */
151	struct list_head		list;
152};
153
154struct idmac_channel {
155	struct dma_chan		dma_chan;
156	dma_cookie_t		completed;	/* last completed cookie	   */
157	union ipu_channel_param	params;
158	enum ipu_channel	link;	/* input channel, linked to the output	   */
159	enum ipu_channel_status	status;
160	void			*client;	/* Only one client per channel	   */
161	unsigned int		n_tx_desc;
162	struct idmac_tx_desc	*desc;		/* allocated tx-descriptors	   */
163	struct scatterlist	*sg[2];	/* scatterlist elements in buffer-0 and -1 */
164	struct list_head	free_list;	/* free tx-descriptors		   */
165	struct list_head	queue;		/* queued tx-descriptors	   */
166	spinlock_t		lock;		/* protects sg[0,1], queue	   */
167	struct mutex		chan_mutex; /* protects status, cookie, free_list  */
168	bool			sec_chan_en;
169	int			active_buffer;
170	unsigned int		eof_irq;
171	char			eof_name[16];	/* EOF IRQ name for request_irq()  */
172};
173
174#define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd)
175#define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan)
176
177#endif /* __LINUX_DMA_IPU_DMA_H */
178