1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 7 */ 8#ifndef __LINUX_IRQCHIP_MIPS_GIC_H 9#define __LINUX_IRQCHIP_MIPS_GIC_H 10 11#include <linux/clocksource.h> 12 13#define GIC_MAX_INTRS 256 14 15/* Constants */ 16#define GIC_POL_POS 1 17#define GIC_POL_NEG 0 18#define GIC_TRIG_EDGE 1 19#define GIC_TRIG_LEVEL 0 20#define GIC_TRIG_DUAL_ENABLE 1 21#define GIC_TRIG_DUAL_DISABLE 0 22 23#define MSK(n) ((1 << (n)) - 1) 24 25/* Accessors */ 26#define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS) 27 28/* GIC Address Space */ 29#define SHARED_SECTION_OFS 0x0000 30#define SHARED_SECTION_SIZE 0x8000 31#define VPE_LOCAL_SECTION_OFS 0x8000 32#define VPE_LOCAL_SECTION_SIZE 0x4000 33#define VPE_OTHER_SECTION_OFS 0xc000 34#define VPE_OTHER_SECTION_SIZE 0x4000 35#define USM_VISIBLE_SECTION_OFS 0x10000 36#define USM_VISIBLE_SECTION_SIZE 0x10000 37 38/* Register Map for Shared Section */ 39 40#define GIC_SH_CONFIG_OFS 0x0000 41 42/* Shared Global Counter */ 43#define GIC_SH_COUNTER_31_00_OFS 0x0010 44#define GIC_SH_COUNTER_63_32_OFS 0x0014 45#define GIC_SH_REVISIONID_OFS 0x0020 46 47/* Convert an interrupt number to a byte offset/bit for multi-word registers */ 48#define GIC_INTR_OFS(intr) (((intr) / 32) * 4) 49#define GIC_INTR_BIT(intr) ((intr) % 32) 50 51/* Polarity : Reset Value is always 0 */ 52#define GIC_SH_SET_POLARITY_OFS 0x0100 53 54/* Triggering : Reset Value is always 0 */ 55#define GIC_SH_SET_TRIGGER_OFS 0x0180 56 57/* Dual edge triggering : Reset Value is always 0 */ 58#define GIC_SH_SET_DUAL_OFS 0x0200 59 60/* Set/Clear corresponding bit in Edge Detect Register */ 61#define GIC_SH_WEDGE_OFS 0x0280 62 63/* Mask manipulation */ 64#define GIC_SH_RMASK_OFS 0x0300 65#define GIC_SH_SMASK_OFS 0x0380 66 67/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ 68#define GIC_SH_MASK_OFS 0x0400 69 70/* Pending Global Interrupts (RO) */ 71#define GIC_SH_PEND_OFS 0x0480 72 73/* Maps Interrupt X to a Pin */ 74#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 75#define GIC_SH_MAP_TO_PIN(intr) (4 * (intr)) 76 77/* Maps Interrupt X to a VPE */ 78#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000 79#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ 80 ((32 * (intr)) + (((vpe) / 32) * 4)) 81#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) 82 83/* Register Map for Local Section */ 84#define GIC_VPE_CTL_OFS 0x0000 85#define GIC_VPE_PEND_OFS 0x0004 86#define GIC_VPE_MASK_OFS 0x0008 87#define GIC_VPE_RMASK_OFS 0x000c 88#define GIC_VPE_SMASK_OFS 0x0010 89#define GIC_VPE_WD_MAP_OFS 0x0040 90#define GIC_VPE_COMPARE_MAP_OFS 0x0044 91#define GIC_VPE_TIMER_MAP_OFS 0x0048 92#define GIC_VPE_FDC_MAP_OFS 0x004c 93#define GIC_VPE_PERFCTR_MAP_OFS 0x0050 94#define GIC_VPE_SWINT0_MAP_OFS 0x0054 95#define GIC_VPE_SWINT1_MAP_OFS 0x0058 96#define GIC_VPE_OTHER_ADDR_OFS 0x0080 97#define GIC_VPE_WD_CONFIG0_OFS 0x0090 98#define GIC_VPE_WD_COUNT0_OFS 0x0094 99#define GIC_VPE_WD_INITIAL0_OFS 0x0098 100#define GIC_VPE_COMPARE_LO_OFS 0x00a0 101#define GIC_VPE_COMPARE_HI_OFS 0x00a4 102 103#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS 0x0100 104#define GIC_VPE_EIC_SS(intr) (4 * (intr)) 105 106#define GIC_VPE_EIC_VEC_BASE_OFS 0x0800 107#define GIC_VPE_EIC_VEC(intr) (4 * (intr)) 108 109#define GIC_VPE_TENABLE_NMI_OFS 0x1000 110#define GIC_VPE_TENABLE_YQ_OFS 0x1004 111#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080 112#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084 113 114/* User Mode Visible Section Register Map */ 115#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 116#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 117 118/* Masks */ 119#define GIC_SH_CONFIG_COUNTSTOP_SHF 28 120#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) 121 122#define GIC_SH_CONFIG_COUNTBITS_SHF 24 123#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF) 124 125#define GIC_SH_CONFIG_NUMINTRS_SHF 16 126#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF) 127 128#define GIC_SH_CONFIG_NUMVPES_SHF 0 129#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF) 130 131#define GIC_SH_WEDGE_SET(intr) ((intr) | (0x1 << 31)) 132#define GIC_SH_WEDGE_CLR(intr) ((intr) & ~(0x1 << 31)) 133 134#define GIC_MAP_TO_PIN_SHF 31 135#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF) 136#define GIC_MAP_TO_NMI_SHF 30 137#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF) 138#define GIC_MAP_TO_YQ_SHF 29 139#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF) 140#define GIC_MAP_SHF 0 141#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF) 142 143/* GIC_VPE_CTL Masks */ 144#define GIC_VPE_CTL_FDC_RTBL_SHF 4 145#define GIC_VPE_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF) 146#define GIC_VPE_CTL_SWINT_RTBL_SHF 3 147#define GIC_VPE_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF) 148#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2 149#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF) 150#define GIC_VPE_CTL_TIMER_RTBL_SHF 1 151#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF) 152#define GIC_VPE_CTL_EIC_MODE_SHF 0 153#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF) 154 155/* GIC_VPE_PEND Masks */ 156#define GIC_VPE_PEND_WD_SHF 0 157#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF) 158#define GIC_VPE_PEND_CMP_SHF 1 159#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF) 160#define GIC_VPE_PEND_TIMER_SHF 2 161#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF) 162#define GIC_VPE_PEND_PERFCOUNT_SHF 3 163#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF) 164#define GIC_VPE_PEND_SWINT0_SHF 4 165#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF) 166#define GIC_VPE_PEND_SWINT1_SHF 5 167#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF) 168#define GIC_VPE_PEND_FDC_SHF 6 169#define GIC_VPE_PEND_FDC_MSK (MSK(1) << GIC_VPE_PEND_FDC_SHF) 170 171/* GIC_VPE_RMASK Masks */ 172#define GIC_VPE_RMASK_WD_SHF 0 173#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF) 174#define GIC_VPE_RMASK_CMP_SHF 1 175#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF) 176#define GIC_VPE_RMASK_TIMER_SHF 2 177#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF) 178#define GIC_VPE_RMASK_PERFCNT_SHF 3 179#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF) 180#define GIC_VPE_RMASK_SWINT0_SHF 4 181#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF) 182#define GIC_VPE_RMASK_SWINT1_SHF 5 183#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF) 184#define GIC_VPE_RMASK_FDC_SHF 6 185#define GIC_VPE_RMASK_FDC_MSK (MSK(1) << GIC_VPE_RMASK_FDC_SHF) 186 187/* GIC_VPE_SMASK Masks */ 188#define GIC_VPE_SMASK_WD_SHF 0 189#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF) 190#define GIC_VPE_SMASK_CMP_SHF 1 191#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF) 192#define GIC_VPE_SMASK_TIMER_SHF 2 193#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF) 194#define GIC_VPE_SMASK_PERFCNT_SHF 3 195#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF) 196#define GIC_VPE_SMASK_SWINT0_SHF 4 197#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF) 198#define GIC_VPE_SMASK_SWINT1_SHF 5 199#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF) 200#define GIC_VPE_SMASK_FDC_SHF 6 201#define GIC_VPE_SMASK_FDC_MSK (MSK(1) << GIC_VPE_SMASK_FDC_SHF) 202 203/* GIC nomenclature for Core Interrupt Pins. */ 204#define GIC_CPU_INT0 0 /* Core Interrupt 2 */ 205#define GIC_CPU_INT1 1 /* . */ 206#define GIC_CPU_INT2 2 /* . */ 207#define GIC_CPU_INT3 3 /* . */ 208#define GIC_CPU_INT4 4 /* . */ 209#define GIC_CPU_INT5 5 /* Core Interrupt 7 */ 210 211/* Add 2 to convert GIC CPU pin to core interrupt */ 212#define GIC_CPU_PIN_OFFSET 2 213 214/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */ 215#define GIC_CPU_TO_VEC_OFFSET 2 216 217/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ 218#define GIC_PIN_TO_VEC_OFFSET 1 219 220/* Local GIC interrupts. */ 221#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */ 222#define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */ 223#define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */ 224#define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */ 225#define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */ 226#define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */ 227#define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */ 228#define GIC_NUM_LOCAL_INTRS 7 229 230/* Convert between local/shared IRQ number and GIC HW IRQ number. */ 231#define GIC_LOCAL_HWIRQ_BASE 0 232#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x)) 233#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE) 234#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS 235#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x)) 236#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE) 237 238extern unsigned int gic_present; 239 240extern void gic_init(unsigned long gic_base_addr, 241 unsigned long gic_addrspace_size, unsigned int cpu_vec, 242 unsigned int irqbase); 243extern void gic_clocksource_init(unsigned int); 244extern cycle_t gic_read_count(void); 245extern unsigned int gic_get_count_width(void); 246extern cycle_t gic_read_compare(void); 247extern void gic_write_compare(cycle_t cnt); 248extern void gic_write_cpu_compare(cycle_t cnt, int cpu); 249extern void gic_start_count(void); 250extern void gic_stop_count(void); 251extern void gic_send_ipi(unsigned int intr); 252extern unsigned int plat_ipi_call_int_xlate(unsigned int); 253extern unsigned int plat_ipi_resched_int_xlate(unsigned int); 254extern int gic_get_c0_compare_int(void); 255extern int gic_get_c0_perfcount_int(void); 256extern int gic_get_c0_fdc_int(void); 257#endif /* __LINUX_IRQCHIP_MIPS_GIC_H */ 258