1/* 2 * Copyright (C) ST-Ericsson SA 2010 3 * 4 * License Terms: GNU General Public License v2 5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> 6 */ 7#ifndef MFD_AB8500_H 8#define MFD_AB8500_H 9 10#include <linux/atomic.h> 11#include <linux/mutex.h> 12#include <linux/irqdomain.h> 13 14struct device; 15 16/* 17 * AB IC versions 18 * 19 * AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a 20 * non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the 21 * print of version string. 22 */ 23enum ab8500_version { 24 AB8500_VERSION_AB8500 = 0x0, 25 AB8500_VERSION_AB8505 = 0x1, 26 AB8500_VERSION_AB9540 = 0x2, 27 AB8500_VERSION_AB8540 = 0x4, 28 AB8500_VERSION_UNDEFINED, 29}; 30 31/* AB8500 CIDs*/ 32#define AB8500_CUTEARLY 0x00 33#define AB8500_CUT1P0 0x10 34#define AB8500_CUT1P1 0x11 35#define AB8500_CUT1P2 0x12 /* Only valid for AB8540 */ 36#define AB8500_CUT2P0 0x20 37#define AB8500_CUT3P0 0x30 38#define AB8500_CUT3P3 0x33 39 40/* 41 * AB8500 bank addresses 42 */ 43#define AB8500_M_FSM_RANK 0x0 44#define AB8500_SYS_CTRL1_BLOCK 0x1 45#define AB8500_SYS_CTRL2_BLOCK 0x2 46#define AB8500_REGU_CTRL1 0x3 47#define AB8500_REGU_CTRL2 0x4 48#define AB8500_USB 0x5 49#define AB8500_TVOUT 0x6 50#define AB8500_DBI 0x7 51#define AB8500_ECI_AV_ACC 0x8 52#define AB8500_RESERVED 0x9 53#define AB8500_GPADC 0xA 54#define AB8500_CHARGER 0xB 55#define AB8500_GAS_GAUGE 0xC 56#define AB8500_AUDIO 0xD 57#define AB8500_INTERRUPT 0xE 58#define AB8500_RTC 0xF 59#define AB8500_MISC 0x10 60#define AB8500_DEVELOPMENT 0x11 61#define AB8500_DEBUG 0x12 62#define AB8500_PROD_TEST 0x13 63#define AB8500_STE_TEST 0x14 64#define AB8500_OTP_EMUL 0x15 65 66/* 67 * Interrupts 68 * Values used to index into array ab8500_irq_regoffset[] defined in 69 * drivers/mdf/ab8500-core.c 70 */ 71/* Definitions for AB8500, AB9540 and AB8540 */ 72/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */ 73#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */ 74#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540/8540 */ 75#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540/8540 */ 76#define AB8500_INT_TEMP_WARM 3 77#define AB8500_INT_PON_KEY2DB_F 4 78#define AB8500_INT_PON_KEY2DB_R 5 79#define AB8500_INT_PON_KEY1DB_F 6 80#define AB8500_INT_PON_KEY1DB_R 7 81/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */ 82#define AB8500_INT_BATT_OVV 8 83#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505/8540 */ 84#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505/8540 */ 85#define AB8500_INT_VBUS_DET_F 14 86#define AB8500_INT_VBUS_DET_R 15 87/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */ 88#define AB8500_INT_VBUS_CH_DROP_END 16 89#define AB8500_INT_RTC_60S 17 90#define AB8500_INT_RTC_ALARM 18 91#define AB8540_INT_BIF_INT 19 92#define AB8500_INT_BAT_CTRL_INDB 20 93#define AB8500_INT_CH_WD_EXP 21 94#define AB8500_INT_VBUS_OVV 22 95#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540/8540 */ 96/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */ 97#define AB8500_INT_CCN_CONV_ACC 24 98#define AB8500_INT_INT_AUD 25 99#define AB8500_INT_CCEOC 26 100#define AB8500_INT_CC_INT_CALIB 27 101#define AB8500_INT_LOW_BAT_F 28 102#define AB8500_INT_LOW_BAT_R 29 103#define AB8500_INT_BUP_CHG_NOT_OK 30 104#define AB8500_INT_BUP_CHG_OK 31 105/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */ 106#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505/8540 */ 107#define AB8500_INT_ACC_DETECT_1DB_F 33 108#define AB8500_INT_ACC_DETECT_1DB_R 34 109#define AB8500_INT_ACC_DETECT_22DB_F 35 110#define AB8500_INT_ACC_DETECT_22DB_R 36 111#define AB8500_INT_ACC_DETECT_21DB_F 37 112#define AB8500_INT_ACC_DETECT_21DB_R 38 113#define AB8500_INT_GP_SW_ADC_CONV_END 39 114/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */ 115#define AB8500_INT_GPIO6R 40 /* not 8505/9540/8540 */ 116#define AB8500_INT_GPIO7R 41 /* not 8505/9540/8540 */ 117#define AB8500_INT_GPIO8R 42 /* not 8505/9540/8540 */ 118#define AB8500_INT_GPIO9R 43 /* not 8505/9540/8540 */ 119#define AB8500_INT_GPIO10R 44 /* not 8540 */ 120#define AB8500_INT_GPIO11R 45 /* not 8540 */ 121#define AB8500_INT_GPIO12R 46 /* not 8505/8540 */ 122#define AB8500_INT_GPIO13R 47 /* not 8540 */ 123/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */ 124#define AB8500_INT_GPIO24R 48 /* not 8505/8540 */ 125#define AB8500_INT_GPIO25R 49 /* not 8505/8540 */ 126#define AB8500_INT_GPIO36R 50 /* not 8505/9540/8540 */ 127#define AB8500_INT_GPIO37R 51 /* not 8505/9540/8540 */ 128#define AB8500_INT_GPIO38R 52 /* not 8505/9540/8540 */ 129#define AB8500_INT_GPIO39R 53 /* not 8505/9540/8540 */ 130#define AB8500_INT_GPIO40R 54 /* not 8540 */ 131#define AB8500_INT_GPIO41R 55 /* not 8540 */ 132/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */ 133#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */ 134#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */ 135#define AB8500_INT_GPIO8F 58 /* not 8505/9540 */ 136#define AB8500_INT_GPIO9F 59 /* not 8505/9540 */ 137#define AB8500_INT_GPIO10F 60 138#define AB8500_INT_GPIO11F 61 139#define AB8500_INT_GPIO12F 62 /* not 8505 */ 140#define AB8500_INT_GPIO13F 63 141/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */ 142#define AB8500_INT_GPIO24F 64 /* not 8505/8540 */ 143#define AB8500_INT_GPIO25F 65 /* not 8505/8540 */ 144#define AB8500_INT_GPIO36F 66 /* not 8505/9540/8540 */ 145#define AB8500_INT_GPIO37F 67 /* not 8505/9540/8540 */ 146#define AB8500_INT_GPIO38F 68 /* not 8505/9540/8540 */ 147#define AB8500_INT_GPIO39F 69 /* not 8505/9540/8540 */ 148#define AB8500_INT_GPIO40F 70 /* not 8540 */ 149#define AB8500_INT_GPIO41F 71 /* not 8540 */ 150/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */ 151#define AB8500_INT_ADP_SOURCE_ERROR 72 152#define AB8500_INT_ADP_SINK_ERROR 73 153#define AB8500_INT_ADP_PROBE_PLUG 74 154#define AB8500_INT_ADP_PROBE_UNPLUG 75 155#define AB8500_INT_ADP_SENSE_OFF 76 156#define AB8500_INT_USB_PHY_POWER_ERR 78 157#define AB8500_INT_USB_LINK_STATUS 79 158/* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */ 159#define AB8500_INT_BTEMP_LOW 80 160#define AB8500_INT_BTEMP_LOW_MEDIUM 81 161#define AB8500_INT_BTEMP_MEDIUM_HIGH 82 162#define AB8500_INT_BTEMP_HIGH 83 163/* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */ 164#define AB8500_INT_SRP_DETECT 88 165#define AB8500_INT_USB_CHARGER_NOT_OKR 89 166#define AB8500_INT_ID_WAKEUP_R 90 167#define AB8500_INT_ID_DET_PLUGR 91 /* 8505/9540 cut2.0 */ 168#define AB8500_INT_ID_DET_R1R 92 169#define AB8500_INT_ID_DET_R2R 93 170#define AB8500_INT_ID_DET_R3R 94 171#define AB8500_INT_ID_DET_R4R 95 172/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */ 173#define AB8500_INT_ID_WAKEUP_F 96 /* not 8505/9540 */ 174#define AB8500_INT_ID_DET_PLUGF 97 /* 8505/9540 cut2.0 */ 175#define AB8500_INT_ID_DET_R1F 98 /* not 8505/9540 */ 176#define AB8500_INT_ID_DET_R2F 99 /* not 8505/9540 */ 177#define AB8500_INT_ID_DET_R3F 100 /* not 8505/9540 */ 178#define AB8500_INT_ID_DET_R4F 101 /* not 8505/9540 */ 179#define AB8500_INT_CHAUTORESTARTAFTSEC 102 /* not 8505/9540 */ 180#define AB8500_INT_CHSTOPBYSEC 103 181/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */ 182#define AB8500_INT_USB_CH_TH_PROT_F 104 183#define AB8500_INT_USB_CH_TH_PROT_R 105 184#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */ 185#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */ 186#define AB8500_INT_CHCURLIMNOHSCHIRP 109 187#define AB8500_INT_CHCURLIMHSCHIRP 110 188#define AB8500_INT_XTAL32K_KO 111 189 190/* Definitions for AB9540 / AB8505 */ 191/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */ 192#define AB9540_INT_GPIO50R 113 /* not 8540 */ 193#define AB9540_INT_GPIO51R 114 /* not 8505/8540 */ 194#define AB9540_INT_GPIO52R 115 /* not 8540 */ 195#define AB9540_INT_GPIO53R 116 /* not 8540 */ 196#define AB9540_INT_GPIO54R 117 /* not 8505/8540 */ 197#define AB9540_INT_IEXT_CH_RF_BFN_R 118 198/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */ 199#define AB9540_INT_GPIO50F 121 /* not 8540 */ 200#define AB9540_INT_GPIO51F 122 /* not 8505/8540 */ 201#define AB9540_INT_GPIO52F 123 /* not 8540 */ 202#define AB9540_INT_GPIO53F 124 /* not 8540 */ 203#define AB9540_INT_GPIO54F 125 /* not 8505/8540 */ 204#define AB9540_INT_IEXT_CH_RF_BFN_F 126 205/* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */ 206#define AB8505_INT_KEYSTUCK 128 207#define AB8505_INT_IKR 129 208#define AB8505_INT_IKP 130 209#define AB8505_INT_KP 131 210#define AB8505_INT_KEYDEGLITCH 132 211#define AB8505_INT_MODPWRSTATUSF 134 212#define AB8505_INT_MODPWRSTATUSR 135 213/* ab8500_irq_regoffset[17] -> IT[Source|Latch|Mask]6 */ 214#define AB8500_INT_HOOK_DET_NEG_F 138 215#define AB8500_INT_HOOK_DET_NEG_R 139 216#define AB8500_INT_HOOK_DET_POS_F 140 217#define AB8500_INT_HOOK_DET_POS_R 141 218#define AB8500_INT_PLUG_DET_COMP_F 142 219#define AB8500_INT_PLUG_DET_COMP_R 143 220/* ab8500_irq_regoffset[18] -> IT[Source|Latch|Mask]23 */ 221#define AB8505_INT_COLL 144 222#define AB8505_INT_RESERR 145 223#define AB8505_INT_FRAERR 146 224#define AB8505_INT_COMERR 147 225#define AB8505_INT_SPDSET 148 226#define AB8505_INT_DSENT 149 227#define AB8505_INT_DREC 150 228#define AB8505_INT_ACC_INT 151 229/* ab8500_irq_regoffset[19] -> IT[Source|Latch|Mask]24 */ 230#define AB8505_INT_NOPINT 152 231/* ab8540_irq_regoffset[20] -> IT[Source|Latch|Mask]26 */ 232#define AB8540_INT_IDPLUGDETCOMPF 160 233#define AB8540_INT_IDPLUGDETCOMPR 161 234#define AB8540_INT_FMDETCOMPLOF 162 235#define AB8540_INT_FMDETCOMPLOR 163 236#define AB8540_INT_FMDETCOMPHIF 164 237#define AB8540_INT_FMDETCOMPHIR 165 238#define AB8540_INT_ID5VDETCOMPF 166 239#define AB8540_INT_ID5VDETCOMPR 167 240/* ab8540_irq_regoffset[21] -> IT[Source|Latch|Mask]27 */ 241#define AB8540_INT_GPIO43F 168 242#define AB8540_INT_GPIO43R 169 243#define AB8540_INT_GPIO44F 170 244#define AB8540_INT_GPIO44R 171 245#define AB8540_INT_KEYPOSDETCOMPF 172 246#define AB8540_INT_KEYPOSDETCOMPR 173 247#define AB8540_INT_KEYNEGDETCOMPF 174 248#define AB8540_INT_KEYNEGDETCOMPR 175 249/* ab8540_irq_regoffset[22] -> IT[Source|Latch|Mask]28 */ 250#define AB8540_INT_GPIO1VBATF 176 251#define AB8540_INT_GPIO1VBATR 177 252#define AB8540_INT_GPIO2VBATF 178 253#define AB8540_INT_GPIO2VBATR 179 254#define AB8540_INT_GPIO3VBATF 180 255#define AB8540_INT_GPIO3VBATR 181 256#define AB8540_INT_GPIO4VBATF 182 257#define AB8540_INT_GPIO4VBATR 183 258/* ab8540_irq_regoffset[23] -> IT[Source|Latch|Mask]29 */ 259#define AB8540_INT_SYSCLKREQ2F 184 260#define AB8540_INT_SYSCLKREQ2R 185 261#define AB8540_INT_SYSCLKREQ3F 186 262#define AB8540_INT_SYSCLKREQ3R 187 263#define AB8540_INT_SYSCLKREQ4F 188 264#define AB8540_INT_SYSCLKREQ4R 189 265#define AB8540_INT_SYSCLKREQ5F 190 266#define AB8540_INT_SYSCLKREQ5R 191 267/* ab8540_irq_regoffset[24] -> IT[Source|Latch|Mask]30 */ 268#define AB8540_INT_PWMOUT1F 192 269#define AB8540_INT_PWMOUT1R 193 270#define AB8540_INT_PWMCTRL0F 194 271#define AB8540_INT_PWMCTRL0R 195 272#define AB8540_INT_PWMCTRL1F 196 273#define AB8540_INT_PWMCTRL1R 197 274#define AB8540_INT_SYSCLKREQ6F 198 275#define AB8540_INT_SYSCLKREQ6R 199 276/* ab8540_irq_regoffset[25] -> IT[Source|Latch|Mask]31 */ 277#define AB8540_INT_PWMEXTVIBRA1F 200 278#define AB8540_INT_PWMEXTVIBRA1R 201 279#define AB8540_INT_PWMEXTVIBRA2F 202 280#define AB8540_INT_PWMEXTVIBRA2R 203 281#define AB8540_INT_PWMOUT2F 204 282#define AB8540_INT_PWMOUT2R 205 283#define AB8540_INT_PWMOUT3F 206 284#define AB8540_INT_PWMOUT3R 207 285/* ab8540_irq_regoffset[26] -> IT[Source|Latch|Mask]32 */ 286#define AB8540_INT_ADDATA2F 208 287#define AB8540_INT_ADDATA2R 209 288#define AB8540_INT_DADATA2F 210 289#define AB8540_INT_DADATA2R 211 290#define AB8540_INT_FSYNC2F 212 291#define AB8540_INT_FSYNC2R 213 292#define AB8540_INT_BITCLK2F 214 293#define AB8540_INT_BITCLK2R 215 294/* ab8540_irq_regoffset[27] -> IT[Source|Latch|Mask]33 */ 295#define AB8540_INT_RTC_1S 216 296 297/* 298 * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the 299 * entire platform. This is a "compile time" constant so this must be set to 300 * the largest possible value that may be encountered with different AB SOCs. 301 * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540 302 * which is larger. 303 */ 304#define AB8500_NR_IRQS 112 305#define AB8505_NR_IRQS 153 306#define AB9540_NR_IRQS 153 307#define AB8540_NR_IRQS 216 308/* This is set to the roof of any AB8500 chip variant IRQ counts */ 309#define AB8500_MAX_NR_IRQS AB8540_NR_IRQS 310 311#define AB8500_NUM_IRQ_REGS 14 312#define AB9540_NUM_IRQ_REGS 20 313#define AB8540_NUM_IRQ_REGS 27 314 315/* Turn On Status Event */ 316#define AB8500_POR_ON_VBAT 0x01 317#define AB8500_POW_KEY_1_ON 0x02 318#define AB8500_POW_KEY_2_ON 0x04 319#define AB8500_RTC_ALARM 0x08 320#define AB8500_MAIN_CH_DET 0x10 321#define AB8500_VBUS_DET 0x20 322#define AB8500_USB_ID_DET 0x40 323 324/** 325 * struct ab8500 - ab8500 internal structure 326 * @dev: parent device 327 * @lock: read/write operations lock 328 * @irq_lock: genirq bus lock 329 * @transfer_ongoing: 0 if no transfer ongoing 330 * @irq: irq line 331 * @irq_domain: irq domain 332 * @version: chip version id (e.g. ab8500 or ab9540) 333 * @chip_id: chip revision id 334 * @write: register write 335 * @write_masked: masked register write 336 * @read: register read 337 * @rx_buf: rx buf for SPI 338 * @tx_buf: tx buf for SPI 339 * @mask: cache of IRQ regs for bus lock 340 * @oldmask: cache of previous IRQ regs for bus lock 341 * @mask_size: Actual number of valid entries in mask[], oldmask[] and 342 * irq_reg_offset 343 * @irq_reg_offset: Array of offsets into IRQ registers 344 */ 345struct ab8500 { 346 struct device *dev; 347 struct mutex lock; 348 struct mutex irq_lock; 349 atomic_t transfer_ongoing; 350 int irq; 351 struct irq_domain *domain; 352 enum ab8500_version version; 353 u8 chip_id; 354 355 int (*write)(struct ab8500 *ab8500, u16 addr, u8 data); 356 int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data); 357 int (*read)(struct ab8500 *ab8500, u16 addr); 358 359 unsigned long tx_buf[4]; 360 unsigned long rx_buf[4]; 361 362 u8 *mask; 363 u8 *oldmask; 364 int mask_size; 365 const int *irq_reg_offset; 366 int it_latchhier_num; 367}; 368 369struct ab8500_regulator_platform_data; 370struct ab8500_codec_platform_data; 371struct ab8500_sysctrl_platform_data; 372 373/** 374 * struct ab8500_platform_data - AB8500 platform data 375 * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used 376 * @init: board-specific initialization after detection of ab8500 377 * @regulator: machine-specific constraints for regulators 378 */ 379struct ab8500_platform_data { 380 void (*init) (struct ab8500 *); 381 struct ab8500_regulator_platform_data *regulator; 382 struct ab8500_codec_platform_data *codec; 383 struct ab8500_sysctrl_platform_data *sysctrl; 384}; 385 386extern int ab8500_init(struct ab8500 *ab8500, 387 enum ab8500_version version); 388extern int ab8500_exit(struct ab8500 *ab8500); 389 390extern int ab8500_suspend(struct ab8500 *ab8500); 391 392static inline int is_ab8500(struct ab8500 *ab) 393{ 394 return ab->version == AB8500_VERSION_AB8500; 395} 396 397static inline int is_ab8505(struct ab8500 *ab) 398{ 399 return ab->version == AB8500_VERSION_AB8505; 400} 401 402static inline int is_ab9540(struct ab8500 *ab) 403{ 404 return ab->version == AB8500_VERSION_AB9540; 405} 406 407static inline int is_ab8540(struct ab8500 *ab) 408{ 409 return ab->version == AB8500_VERSION_AB8540; 410} 411 412/* exclude also ab8505, ab9540... */ 413static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab) 414{ 415 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0)); 416} 417 418/* exclude also ab8505, ab9540... */ 419static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab) 420{ 421 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1)); 422} 423 424/* exclude also ab8505, ab9540... */ 425static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab) 426{ 427 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0)); 428} 429 430static inline int is_ab8500_3p3_or_earlier(struct ab8500 *ab) 431{ 432 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT3P3)); 433} 434 435/* exclude also ab8505, ab9540... */ 436static inline int is_ab8500_2p0(struct ab8500 *ab) 437{ 438 return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0)); 439} 440 441static inline int is_ab8505_1p0_or_earlier(struct ab8500 *ab) 442{ 443 return (is_ab8505(ab) && (ab->chip_id <= AB8500_CUT1P0)); 444} 445 446static inline int is_ab8505_2p0(struct ab8500 *ab) 447{ 448 return (is_ab8505(ab) && (ab->chip_id == AB8500_CUT2P0)); 449} 450 451static inline int is_ab9540_1p0_or_earlier(struct ab8500 *ab) 452{ 453 return (is_ab9540(ab) && (ab->chip_id <= AB8500_CUT1P0)); 454} 455 456static inline int is_ab9540_2p0(struct ab8500 *ab) 457{ 458 return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT2P0)); 459} 460 461/* 462 * Be careful, the marketing name for this chip is 2.1 463 * but the value read from the chip is 3.0 (0x30) 464 */ 465static inline int is_ab9540_3p0(struct ab8500 *ab) 466{ 467 return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT3P0)); 468} 469 470static inline int is_ab8540_1p0_or_earlier(struct ab8500 *ab) 471{ 472 return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P0); 473} 474 475static inline int is_ab8540_1p1_or_earlier(struct ab8500 *ab) 476{ 477 return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P1); 478} 479 480static inline int is_ab8540_1p2_or_earlier(struct ab8500 *ab) 481{ 482 return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P2); 483} 484 485static inline int is_ab8540_2p0_or_earlier(struct ab8500 *ab) 486{ 487 return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT2P0); 488} 489 490static inline int is_ab8540_2p0(struct ab8500 *ab) 491{ 492 return is_ab8540(ab) && (ab->chip_id == AB8500_CUT2P0); 493} 494 495static inline int is_ab8505_2p0_earlier(struct ab8500 *ab) 496{ 497 return (is_ab8505(ab) && (ab->chip_id < AB8500_CUT2P0)); 498} 499 500static inline int is_ab9540_2p0_or_earlier(struct ab8500 *ab) 501{ 502 return (is_ab9540(ab) && (ab->chip_id < AB8500_CUT2P0)); 503} 504 505void ab8500_override_turn_on_stat(u8 mask, u8 set); 506 507#ifdef CONFIG_AB8500_DEBUG 508extern int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 509void ab8500_dump_all_banks(struct device *dev); 510void ab8500_debug_register_interrupt(int line); 511#else 512static inline void ab8500_dump_all_banks(struct device *dev) {} 513static inline void ab8500_debug_register_interrupt(int line) {} 514#endif 515 516#endif /* MFD_AB8500_H */ 517