1/* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#ifndef MLX4_DEVICE_H 34#define MLX4_DEVICE_H 35 36#include <linux/if_ether.h> 37#include <linux/pci.h> 38#include <linux/completion.h> 39#include <linux/radix-tree.h> 40#include <linux/cpu_rmap.h> 41#include <linux/crash_dump.h> 42 43#include <linux/atomic.h> 44 45#include <linux/timecounter.h> 46 47#define MAX_MSIX_P_PORT 17 48#define MAX_MSIX 64 49#define MSIX_LEGACY_SZ 4 50#define MIN_MSIX_P_PORT 5 51 52#define MLX4_MAX_100M_UNITS_VAL 255 /* 53 * work around: can't set values 54 * greater then this value when 55 * using 100 Mbps units. 56 */ 57#define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 58#define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 59#define MLX4_RATELIMIT_DEFAULT 0x00ff 60 61#define MLX4_ROCE_MAX_GIDS 128 62#define MLX4_ROCE_PF_GIDS 16 63 64enum { 65 MLX4_FLAG_MSI_X = 1 << 0, 66 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 67 MLX4_FLAG_MASTER = 1 << 2, 68 MLX4_FLAG_SLAVE = 1 << 3, 69 MLX4_FLAG_SRIOV = 1 << 4, 70 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 71 MLX4_FLAG_BONDED = 1 << 7 72}; 73 74enum { 75 MLX4_PORT_CAP_IS_SM = 1 << 1, 76 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 77}; 78 79enum { 80 MLX4_MAX_PORTS = 2, 81 MLX4_MAX_PORT_PKEYS = 128 82}; 83 84/* base qkey for use in sriov tunnel-qp/proxy-qp communication. 85 * These qkeys must not be allowed for general use. This is a 64k range, 86 * and to test for violation, we use the mask (protect against future chg). 87 */ 88#define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 89#define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 90 91enum { 92 MLX4_BOARD_ID_LEN = 64 93}; 94 95enum { 96 MLX4_MAX_NUM_PF = 16, 97 MLX4_MAX_NUM_VF = 126, 98 MLX4_MAX_NUM_VF_P_PORT = 64, 99 MLX4_MFUNC_MAX = 128, 100 MLX4_MAX_EQ_NUM = 1024, 101 MLX4_MFUNC_EQ_NUM = 4, 102 MLX4_MFUNC_MAX_EQES = 8, 103 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 104}; 105 106/* Driver supports 3 diffrent device methods to manage traffic steering: 107 * -device managed - High level API for ib and eth flow steering. FW is 108 * managing flow steering tables. 109 * - B0 steering mode - Common low level API for ib and (if supported) eth. 110 * - A0 steering mode - Limited low level API for eth. In case of IB, 111 * B0 mode is in use. 112 */ 113enum { 114 MLX4_STEERING_MODE_A0, 115 MLX4_STEERING_MODE_B0, 116 MLX4_STEERING_MODE_DEVICE_MANAGED 117}; 118 119enum { 120 MLX4_STEERING_DMFS_A0_DEFAULT, 121 MLX4_STEERING_DMFS_A0_DYNAMIC, 122 MLX4_STEERING_DMFS_A0_STATIC, 123 MLX4_STEERING_DMFS_A0_DISABLE, 124 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED 125}; 126 127static inline const char *mlx4_steering_mode_str(int steering_mode) 128{ 129 switch (steering_mode) { 130 case MLX4_STEERING_MODE_A0: 131 return "A0 steering"; 132 133 case MLX4_STEERING_MODE_B0: 134 return "B0 steering"; 135 136 case MLX4_STEERING_MODE_DEVICE_MANAGED: 137 return "Device managed flow steering"; 138 139 default: 140 return "Unrecognize steering mode"; 141 } 142} 143 144enum { 145 MLX4_TUNNEL_OFFLOAD_MODE_NONE, 146 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN 147}; 148 149enum { 150 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 151 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 152 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 153 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 154 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 155 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 156 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 157 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 158 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 159 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 160 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 161 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 162 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 163 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 164 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 165 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 166 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 167 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 168 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 169 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 170 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 171 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 172 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 173 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 174 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 175 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, 176 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 177 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 178 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 179 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 180 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 181}; 182 183enum { 184 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 185 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 186 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 187 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 188 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, 189 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 190 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 191 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 192 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, 193 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, 194 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, 195 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, 196 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, 197 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, 198 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, 199 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, 200 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, 201 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, 202 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 203 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, 204 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, 205 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, 206 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, 207 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, 208 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, 209 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, 210 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, 211 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, 212 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, 213}; 214 215enum { 216 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, 217 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 218}; 219 220enum { 221 MLX4_VF_CAP_FLAG_RESET = 1 << 0 222}; 223 224/* bit enums for an 8-bit flags field indicating special use 225 * QPs which require special handling in qp_reserve_range. 226 * Currently, this only includes QPs used by the ETH interface, 227 * where we expect to use blueflame. These QPs must not have 228 * bits 6 and 7 set in their qp number. 229 * 230 * This enum may use only bits 0..7. 231 */ 232enum { 233 MLX4_RESERVE_A0_QP = 1 << 6, 234 MLX4_RESERVE_ETH_BF_QP = 1 << 7, 235}; 236 237enum { 238 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 239 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, 240 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, 241 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 242}; 243 244enum { 245 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 246}; 247 248enum { 249 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, 250 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, 251 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 252}; 253 254 255#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 256 257enum { 258 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 259 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 260 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 261 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 262 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 263 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 264 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24, 265 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, 266}; 267 268enum { 269 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP 270}; 271 272enum mlx4_event { 273 MLX4_EVENT_TYPE_COMP = 0x00, 274 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 275 MLX4_EVENT_TYPE_COMM_EST = 0x02, 276 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 277 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 278 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 279 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 280 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 281 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 282 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 283 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 284 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 285 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 286 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 287 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 288 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 289 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 290 MLX4_EVENT_TYPE_CMD = 0x0a, 291 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 292 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 293 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 294 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 295 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 296 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 297 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 298 MLX4_EVENT_TYPE_NONE = 0xff, 299}; 300 301enum { 302 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 303 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 304}; 305 306enum { 307 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 308 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 309}; 310 311enum { 312 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 313}; 314 315enum slave_port_state { 316 SLAVE_PORT_DOWN = 0, 317 SLAVE_PENDING_UP, 318 SLAVE_PORT_UP, 319}; 320 321enum slave_port_gen_event { 322 SLAVE_PORT_GEN_EVENT_DOWN = 0, 323 SLAVE_PORT_GEN_EVENT_UP, 324 SLAVE_PORT_GEN_EVENT_NONE, 325}; 326 327enum slave_port_state_event { 328 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 329 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 330 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 331 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 332}; 333 334enum { 335 MLX4_PERM_LOCAL_READ = 1 << 10, 336 MLX4_PERM_LOCAL_WRITE = 1 << 11, 337 MLX4_PERM_REMOTE_READ = 1 << 12, 338 MLX4_PERM_REMOTE_WRITE = 1 << 13, 339 MLX4_PERM_ATOMIC = 1 << 14, 340 MLX4_PERM_BIND_MW = 1 << 15, 341 MLX4_PERM_MASK = 0xFC00 342}; 343 344enum { 345 MLX4_OPCODE_NOP = 0x00, 346 MLX4_OPCODE_SEND_INVAL = 0x01, 347 MLX4_OPCODE_RDMA_WRITE = 0x08, 348 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 349 MLX4_OPCODE_SEND = 0x0a, 350 MLX4_OPCODE_SEND_IMM = 0x0b, 351 MLX4_OPCODE_LSO = 0x0e, 352 MLX4_OPCODE_RDMA_READ = 0x10, 353 MLX4_OPCODE_ATOMIC_CS = 0x11, 354 MLX4_OPCODE_ATOMIC_FA = 0x12, 355 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 356 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 357 MLX4_OPCODE_BIND_MW = 0x18, 358 MLX4_OPCODE_FMR = 0x19, 359 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 360 MLX4_OPCODE_CONFIG_CMD = 0x1f, 361 362 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 363 MLX4_RECV_OPCODE_SEND = 0x01, 364 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 365 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 366 367 MLX4_CQE_OPCODE_ERROR = 0x1e, 368 MLX4_CQE_OPCODE_RESIZE = 0x16, 369}; 370 371enum { 372 MLX4_STAT_RATE_OFFSET = 5 373}; 374 375enum mlx4_protocol { 376 MLX4_PROT_IB_IPV6 = 0, 377 MLX4_PROT_ETH, 378 MLX4_PROT_IB_IPV4, 379 MLX4_PROT_FCOE 380}; 381 382enum { 383 MLX4_MTT_FLAG_PRESENT = 1 384}; 385 386enum mlx4_qp_region { 387 MLX4_QP_REGION_FW = 0, 388 MLX4_QP_REGION_RSS_RAW_ETH, 389 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, 390 MLX4_QP_REGION_ETH_ADDR, 391 MLX4_QP_REGION_FC_ADDR, 392 MLX4_QP_REGION_FC_EXCH, 393 MLX4_NUM_QP_REGION 394}; 395 396enum mlx4_port_type { 397 MLX4_PORT_TYPE_NONE = 0, 398 MLX4_PORT_TYPE_IB = 1, 399 MLX4_PORT_TYPE_ETH = 2, 400 MLX4_PORT_TYPE_AUTO = 3 401}; 402 403enum mlx4_special_vlan_idx { 404 MLX4_NO_VLAN_IDX = 0, 405 MLX4_VLAN_MISS_IDX, 406 MLX4_VLAN_REGULAR 407}; 408 409enum mlx4_steer_type { 410 MLX4_MC_STEER = 0, 411 MLX4_UC_STEER, 412 MLX4_NUM_STEERS 413}; 414 415enum { 416 MLX4_NUM_FEXCH = 64 * 1024, 417}; 418 419enum { 420 MLX4_MAX_FAST_REG_PAGES = 511, 421}; 422 423enum { 424 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 425 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 426 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 427}; 428 429/* Port mgmt change event handling */ 430enum { 431 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 432 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 433 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 434 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 435 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 436}; 437 438enum { 439 MLX4_DEVICE_STATE_UP = 1 << 0, 440 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, 441}; 442 443enum { 444 MLX4_INTERFACE_STATE_UP = 1 << 0, 445 MLX4_INTERFACE_STATE_DELETION = 1 << 1, 446}; 447 448#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 449 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 450 451enum mlx4_module_id { 452 MLX4_MODULE_ID_SFP = 0x3, 453 MLX4_MODULE_ID_QSFP = 0xC, 454 MLX4_MODULE_ID_QSFP_PLUS = 0xD, 455 MLX4_MODULE_ID_QSFP28 = 0x11, 456}; 457 458enum { /* rl */ 459 MLX4_QP_RATE_LIMIT_NONE = 0, 460 MLX4_QP_RATE_LIMIT_KBS = 1, 461 MLX4_QP_RATE_LIMIT_MBS = 2, 462 MLX4_QP_RATE_LIMIT_GBS = 3 463}; 464 465struct mlx4_rate_limit_caps { 466 u16 num_rates; /* Number of different rates */ 467 u8 min_unit; 468 u16 min_val; 469 u8 max_unit; 470 u16 max_val; 471}; 472 473static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 474{ 475 return (major << 32) | (minor << 16) | subminor; 476} 477 478struct mlx4_phys_caps { 479 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 480 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 481 u32 num_phys_eqs; 482 u32 base_sqpn; 483 u32 base_proxy_sqpn; 484 u32 base_tunnel_sqpn; 485}; 486 487struct mlx4_caps { 488 u64 fw_ver; 489 u32 function; 490 int num_ports; 491 int vl_cap[MLX4_MAX_PORTS + 1]; 492 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 493 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 494 u64 def_mac[MLX4_MAX_PORTS + 1]; 495 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 496 int gid_table_len[MLX4_MAX_PORTS + 1]; 497 int pkey_table_len[MLX4_MAX_PORTS + 1]; 498 int trans_type[MLX4_MAX_PORTS + 1]; 499 int vendor_oui[MLX4_MAX_PORTS + 1]; 500 int wavelength[MLX4_MAX_PORTS + 1]; 501 u64 trans_code[MLX4_MAX_PORTS + 1]; 502 int local_ca_ack_delay; 503 int num_uars; 504 u32 uar_page_size; 505 int bf_reg_size; 506 int bf_regs_per_page; 507 int max_sq_sg; 508 int max_rq_sg; 509 int num_qps; 510 int max_wqes; 511 int max_sq_desc_sz; 512 int max_rq_desc_sz; 513 int max_qp_init_rdma; 514 int max_qp_dest_rdma; 515 u32 *qp0_qkey; 516 u32 *qp0_proxy; 517 u32 *qp1_proxy; 518 u32 *qp0_tunnel; 519 u32 *qp1_tunnel; 520 int num_srqs; 521 int max_srq_wqes; 522 int max_srq_sge; 523 int reserved_srqs; 524 int num_cqs; 525 int max_cqes; 526 int reserved_cqs; 527 int num_sys_eqs; 528 int num_eqs; 529 int reserved_eqs; 530 int num_comp_vectors; 531 int comp_pool; 532 int num_mpts; 533 int max_fmr_maps; 534 int num_mtts; 535 int fmr_reserved_mtts; 536 int reserved_mtts; 537 int reserved_mrws; 538 int reserved_uars; 539 int num_mgms; 540 int num_amgms; 541 int reserved_mcgs; 542 int num_qp_per_mgm; 543 int steering_mode; 544 int dmfs_high_steer_mode; 545 int fs_log_max_ucast_qp_range_size; 546 int num_pds; 547 int reserved_pds; 548 int max_xrcds; 549 int reserved_xrcds; 550 int mtt_entry_sz; 551 u32 max_msg_sz; 552 u32 page_size_cap; 553 u64 flags; 554 u64 flags2; 555 u32 bmme_flags; 556 u32 reserved_lkey; 557 u16 stat_rate_support; 558 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 559 int max_gso_sz; 560 int max_rss_tbl_sz; 561 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 562 int reserved_qps; 563 int reserved_qps_base[MLX4_NUM_QP_REGION]; 564 int log_num_macs; 565 int log_num_vlans; 566 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 567 u8 supported_type[MLX4_MAX_PORTS + 1]; 568 u8 suggested_type[MLX4_MAX_PORTS + 1]; 569 u8 default_sense[MLX4_MAX_PORTS + 1]; 570 u32 port_mask[MLX4_MAX_PORTS + 1]; 571 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 572 u32 max_counters; 573 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 574 u16 sqp_demux; 575 u32 eqe_size; 576 u32 cqe_size; 577 u8 eqe_factor; 578 u32 userspace_caps; /* userspace must be aware of these */ 579 u32 function_caps; /* VFs must be aware of these */ 580 u16 hca_core_clock; 581 u64 phys_port_id[MLX4_MAX_PORTS + 1]; 582 int tunnel_offload_mode; 583 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; 584 u8 alloc_res_qp_mask; 585 u32 dmfs_high_rate_qpn_base; 586 u32 dmfs_high_rate_qpn_range; 587 u32 vf_caps; 588 struct mlx4_rate_limit_caps rl_caps; 589}; 590 591struct mlx4_buf_list { 592 void *buf; 593 dma_addr_t map; 594}; 595 596struct mlx4_buf { 597 struct mlx4_buf_list direct; 598 struct mlx4_buf_list *page_list; 599 int nbufs; 600 int npages; 601 int page_shift; 602}; 603 604struct mlx4_mtt { 605 u32 offset; 606 int order; 607 int page_shift; 608}; 609 610enum { 611 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 612}; 613 614struct mlx4_db_pgdir { 615 struct list_head list; 616 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 617 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 618 unsigned long *bits[2]; 619 __be32 *db_page; 620 dma_addr_t db_dma; 621}; 622 623struct mlx4_ib_user_db_page; 624 625struct mlx4_db { 626 __be32 *db; 627 union { 628 struct mlx4_db_pgdir *pgdir; 629 struct mlx4_ib_user_db_page *user_page; 630 } u; 631 dma_addr_t dma; 632 int index; 633 int order; 634}; 635 636struct mlx4_hwq_resources { 637 struct mlx4_db db; 638 struct mlx4_mtt mtt; 639 struct mlx4_buf buf; 640}; 641 642struct mlx4_mr { 643 struct mlx4_mtt mtt; 644 u64 iova; 645 u64 size; 646 u32 key; 647 u32 pd; 648 u32 access; 649 int enabled; 650}; 651 652enum mlx4_mw_type { 653 MLX4_MW_TYPE_1 = 1, 654 MLX4_MW_TYPE_2 = 2, 655}; 656 657struct mlx4_mw { 658 u32 key; 659 u32 pd; 660 enum mlx4_mw_type type; 661 int enabled; 662}; 663 664struct mlx4_fmr { 665 struct mlx4_mr mr; 666 struct mlx4_mpt_entry *mpt; 667 __be64 *mtts; 668 dma_addr_t dma_handle; 669 int max_pages; 670 int max_maps; 671 int maps; 672 u8 page_shift; 673}; 674 675struct mlx4_uar { 676 unsigned long pfn; 677 int index; 678 struct list_head bf_list; 679 unsigned free_bf_bmap; 680 void __iomem *map; 681 void __iomem *bf_map; 682}; 683 684struct mlx4_bf { 685 unsigned int offset; 686 int buf_size; 687 struct mlx4_uar *uar; 688 void __iomem *reg; 689}; 690 691struct mlx4_cq { 692 void (*comp) (struct mlx4_cq *); 693 void (*event) (struct mlx4_cq *, enum mlx4_event); 694 695 struct mlx4_uar *uar; 696 697 u32 cons_index; 698 699 u16 irq; 700 __be32 *set_ci_db; 701 __be32 *arm_db; 702 int arm_sn; 703 704 int cqn; 705 unsigned vector; 706 707 atomic_t refcount; 708 struct completion free; 709 struct { 710 struct list_head list; 711 void (*comp)(struct mlx4_cq *); 712 void *priv; 713 } tasklet_ctx; 714 int reset_notify_added; 715 struct list_head reset_notify; 716}; 717 718struct mlx4_qp { 719 void (*event) (struct mlx4_qp *, enum mlx4_event); 720 721 int qpn; 722 723 atomic_t refcount; 724 struct completion free; 725}; 726 727struct mlx4_srq { 728 void (*event) (struct mlx4_srq *, enum mlx4_event); 729 730 int srqn; 731 int max; 732 int max_gs; 733 int wqe_shift; 734 735 atomic_t refcount; 736 struct completion free; 737}; 738 739struct mlx4_av { 740 __be32 port_pd; 741 u8 reserved1; 742 u8 g_slid; 743 __be16 dlid; 744 u8 reserved2; 745 u8 gid_index; 746 u8 stat_rate; 747 u8 hop_limit; 748 __be32 sl_tclass_flowlabel; 749 u8 dgid[16]; 750}; 751 752struct mlx4_eth_av { 753 __be32 port_pd; 754 u8 reserved1; 755 u8 smac_idx; 756 u16 reserved2; 757 u8 reserved3; 758 u8 gid_index; 759 u8 stat_rate; 760 u8 hop_limit; 761 __be32 sl_tclass_flowlabel; 762 u8 dgid[16]; 763 u8 s_mac[6]; 764 u8 reserved4[2]; 765 __be16 vlan; 766 u8 mac[ETH_ALEN]; 767}; 768 769union mlx4_ext_av { 770 struct mlx4_av ib; 771 struct mlx4_eth_av eth; 772}; 773 774struct mlx4_counter { 775 u8 reserved1[3]; 776 u8 counter_mode; 777 __be32 num_ifc; 778 u32 reserved2[2]; 779 __be64 rx_frames; 780 __be64 rx_bytes; 781 __be64 tx_frames; 782 __be64 tx_bytes; 783}; 784 785struct mlx4_quotas { 786 int qp; 787 int cq; 788 int srq; 789 int mpt; 790 int mtt; 791 int counter; 792 int xrcd; 793}; 794 795struct mlx4_vf_dev { 796 u8 min_port; 797 u8 n_ports; 798}; 799 800struct mlx4_dev_persistent { 801 struct pci_dev *pdev; 802 struct mlx4_dev *dev; 803 int nvfs[MLX4_MAX_PORTS + 1]; 804 int num_vfs; 805 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; 806 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; 807 struct work_struct catas_work; 808 struct workqueue_struct *catas_wq; 809 struct mutex device_state_mutex; /* protect HW state */ 810 u8 state; 811 struct mutex interface_state_mutex; /* protect SW state */ 812 u8 interface_state; 813}; 814 815struct mlx4_dev { 816 struct mlx4_dev_persistent *persist; 817 unsigned long flags; 818 unsigned long num_slaves; 819 struct mlx4_caps caps; 820 struct mlx4_phys_caps phys_caps; 821 struct mlx4_quotas quotas; 822 struct radix_tree_root qp_table_tree; 823 u8 rev_id; 824 char board_id[MLX4_BOARD_ID_LEN]; 825 int numa_node; 826 int oper_log_mgm_entry_size; 827 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 828 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 829 struct mlx4_vf_dev *dev_vfs; 830}; 831 832struct mlx4_eqe { 833 u8 reserved1; 834 u8 type; 835 u8 reserved2; 836 u8 subtype; 837 union { 838 u32 raw[6]; 839 struct { 840 __be32 cqn; 841 } __packed comp; 842 struct { 843 u16 reserved1; 844 __be16 token; 845 u32 reserved2; 846 u8 reserved3[3]; 847 u8 status; 848 __be64 out_param; 849 } __packed cmd; 850 struct { 851 __be32 qpn; 852 } __packed qp; 853 struct { 854 __be32 srqn; 855 } __packed srq; 856 struct { 857 __be32 cqn; 858 u32 reserved1; 859 u8 reserved2[3]; 860 u8 syndrome; 861 } __packed cq_err; 862 struct { 863 u32 reserved1[2]; 864 __be32 port; 865 } __packed port_change; 866 struct { 867 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 868 u32 reserved; 869 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 870 } __packed comm_channel_arm; 871 struct { 872 u8 port; 873 u8 reserved[3]; 874 __be64 mac; 875 } __packed mac_update; 876 struct { 877 __be32 slave_id; 878 } __packed flr_event; 879 struct { 880 __be16 current_temperature; 881 __be16 warning_threshold; 882 } __packed warming; 883 struct { 884 u8 reserved[3]; 885 u8 port; 886 union { 887 struct { 888 __be16 mstr_sm_lid; 889 __be16 port_lid; 890 __be32 changed_attr; 891 u8 reserved[3]; 892 u8 mstr_sm_sl; 893 __be64 gid_prefix; 894 } __packed port_info; 895 struct { 896 __be32 block_ptr; 897 __be32 tbl_entries_mask; 898 } __packed tbl_change_info; 899 } params; 900 } __packed port_mgmt_change; 901 struct { 902 u8 reserved[3]; 903 u8 port; 904 u32 reserved1[5]; 905 } __packed bad_cable; 906 } event; 907 u8 slave_id; 908 u8 reserved3[2]; 909 u8 owner; 910} __packed; 911 912struct mlx4_init_port_param { 913 int set_guid0; 914 int set_node_guid; 915 int set_si_guid; 916 u16 mtu; 917 int port_width_cap; 918 u16 vl_cap; 919 u16 max_gid; 920 u16 max_pkey; 921 u64 guid0; 922 u64 node_guid; 923 u64 si_guid; 924}; 925 926#define MAD_IFC_DATA_SZ 192 927/* MAD IFC Mailbox */ 928struct mlx4_mad_ifc { 929 u8 base_version; 930 u8 mgmt_class; 931 u8 class_version; 932 u8 method; 933 __be16 status; 934 __be16 class_specific; 935 __be64 tid; 936 __be16 attr_id; 937 __be16 resv; 938 __be32 attr_mod; 939 __be64 mkey; 940 __be16 dr_slid; 941 __be16 dr_dlid; 942 u8 reserved[28]; 943 u8 data[MAD_IFC_DATA_SZ]; 944} __packed; 945 946#define mlx4_foreach_port(port, dev, type) \ 947 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 948 if ((type) == (dev)->caps.port_mask[(port)]) 949 950#define mlx4_foreach_non_ib_transport_port(port, dev) \ 951 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 952 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) 953 954#define mlx4_foreach_ib_transport_port(port, dev) \ 955 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 956 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 957 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 958 959#define MLX4_INVALID_SLAVE_ID 0xFF 960 961void handle_port_mgmt_change_event(struct work_struct *work); 962 963static inline int mlx4_master_func_num(struct mlx4_dev *dev) 964{ 965 return dev->caps.function; 966} 967 968static inline int mlx4_is_master(struct mlx4_dev *dev) 969{ 970 return dev->flags & MLX4_FLAG_MASTER; 971} 972 973static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 974{ 975 return dev->phys_caps.base_sqpn + 8 + 976 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 977} 978 979static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 980{ 981 return (qpn < dev->phys_caps.base_sqpn + 8 + 982 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && 983 qpn >= dev->phys_caps.base_sqpn) || 984 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); 985} 986 987static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 988{ 989 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 990 991 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 992 return 1; 993 994 return 0; 995} 996 997static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 998{ 999 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 1000} 1001 1002static inline int mlx4_is_slave(struct mlx4_dev *dev) 1003{ 1004 return dev->flags & MLX4_FLAG_SLAVE; 1005} 1006 1007static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) 1008{ 1009 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; 1010} 1011 1012int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 1013 struct mlx4_buf *buf, gfp_t gfp); 1014void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 1015static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 1016{ 1017 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 1018 return buf->direct.buf + offset; 1019 else 1020 return buf->page_list[offset >> PAGE_SHIFT].buf + 1021 (offset & (PAGE_SIZE - 1)); 1022} 1023 1024int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 1025void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 1026int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1027void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1028 1029int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 1030void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 1031int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 1032void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 1033 1034int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 1035 struct mlx4_mtt *mtt); 1036void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1037u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1038 1039int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 1040 int npages, int page_shift, struct mlx4_mr *mr); 1041int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 1042int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 1043int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 1044 struct mlx4_mw *mw); 1045void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 1046int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 1047int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1048 int start_index, int npages, u64 *page_list); 1049int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1050 struct mlx4_buf *buf, gfp_t gfp); 1051 1052int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, 1053 gfp_t gfp); 1054void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 1055 1056int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1057 int size, int max_direct); 1058void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 1059 int size); 1060 1061int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 1062 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 1063 unsigned vector, int collapsed, int timestamp_en); 1064void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 1065int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1066 int *base, u8 flags); 1067void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1068 1069int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, 1070 gfp_t gfp); 1071void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1072 1073int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1074 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1075void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1076int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1077int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1078 1079int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1080int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1081 1082int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1083 int block_mcast_loopback, enum mlx4_protocol prot); 1084int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1085 enum mlx4_protocol prot); 1086int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1087 u8 port, int block_mcast_loopback, 1088 enum mlx4_protocol protocol, u64 *reg_id); 1089int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1090 enum mlx4_protocol protocol, u64 reg_id); 1091 1092enum { 1093 MLX4_DOMAIN_UVERBS = 0x1000, 1094 MLX4_DOMAIN_ETHTOOL = 0x2000, 1095 MLX4_DOMAIN_RFS = 0x3000, 1096 MLX4_DOMAIN_NIC = 0x5000, 1097}; 1098 1099enum mlx4_net_trans_rule_id { 1100 MLX4_NET_TRANS_RULE_ID_ETH = 0, 1101 MLX4_NET_TRANS_RULE_ID_IB, 1102 MLX4_NET_TRANS_RULE_ID_IPV6, 1103 MLX4_NET_TRANS_RULE_ID_IPV4, 1104 MLX4_NET_TRANS_RULE_ID_TCP, 1105 MLX4_NET_TRANS_RULE_ID_UDP, 1106 MLX4_NET_TRANS_RULE_ID_VXLAN, 1107 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 1108}; 1109 1110extern const u16 __sw_id_hw[]; 1111 1112static inline int map_hw_to_sw_id(u16 header_id) 1113{ 1114 1115 int i; 1116 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1117 if (header_id == __sw_id_hw[i]) 1118 return i; 1119 } 1120 return -EINVAL; 1121} 1122 1123enum mlx4_net_trans_promisc_mode { 1124 MLX4_FS_REGULAR = 1, 1125 MLX4_FS_ALL_DEFAULT, 1126 MLX4_FS_MC_DEFAULT, 1127 MLX4_FS_UC_SNIFFER, 1128 MLX4_FS_MC_SNIFFER, 1129 MLX4_FS_MODE_NUM, /* should be last */ 1130}; 1131 1132struct mlx4_spec_eth { 1133 u8 dst_mac[ETH_ALEN]; 1134 u8 dst_mac_msk[ETH_ALEN]; 1135 u8 src_mac[ETH_ALEN]; 1136 u8 src_mac_msk[ETH_ALEN]; 1137 u8 ether_type_enable; 1138 __be16 ether_type; 1139 __be16 vlan_id_msk; 1140 __be16 vlan_id; 1141}; 1142 1143struct mlx4_spec_tcp_udp { 1144 __be16 dst_port; 1145 __be16 dst_port_msk; 1146 __be16 src_port; 1147 __be16 src_port_msk; 1148}; 1149 1150struct mlx4_spec_ipv4 { 1151 __be32 dst_ip; 1152 __be32 dst_ip_msk; 1153 __be32 src_ip; 1154 __be32 src_ip_msk; 1155}; 1156 1157struct mlx4_spec_ib { 1158 __be32 l3_qpn; 1159 __be32 qpn_msk; 1160 u8 dst_gid[16]; 1161 u8 dst_gid_msk[16]; 1162}; 1163 1164struct mlx4_spec_vxlan { 1165 __be32 vni; 1166 __be32 vni_mask; 1167 1168}; 1169 1170struct mlx4_spec_list { 1171 struct list_head list; 1172 enum mlx4_net_trans_rule_id id; 1173 union { 1174 struct mlx4_spec_eth eth; 1175 struct mlx4_spec_ib ib; 1176 struct mlx4_spec_ipv4 ipv4; 1177 struct mlx4_spec_tcp_udp tcp_udp; 1178 struct mlx4_spec_vxlan vxlan; 1179 }; 1180}; 1181 1182enum mlx4_net_trans_hw_rule_queue { 1183 MLX4_NET_TRANS_Q_FIFO, 1184 MLX4_NET_TRANS_Q_LIFO, 1185}; 1186 1187struct mlx4_net_trans_rule { 1188 struct list_head list; 1189 enum mlx4_net_trans_hw_rule_queue queue_mode; 1190 bool exclusive; 1191 bool allow_loopback; 1192 enum mlx4_net_trans_promisc_mode promisc_mode; 1193 u8 port; 1194 u16 priority; 1195 u32 qpn; 1196}; 1197 1198struct mlx4_net_trans_rule_hw_ctrl { 1199 __be16 prio; 1200 u8 type; 1201 u8 flags; 1202 u8 rsvd1; 1203 u8 funcid; 1204 u8 vep; 1205 u8 port; 1206 __be32 qpn; 1207 __be32 rsvd2; 1208}; 1209 1210struct mlx4_net_trans_rule_hw_ib { 1211 u8 size; 1212 u8 rsvd1; 1213 __be16 id; 1214 u32 rsvd2; 1215 __be32 l3_qpn; 1216 __be32 qpn_mask; 1217 u8 dst_gid[16]; 1218 u8 dst_gid_msk[16]; 1219} __packed; 1220 1221struct mlx4_net_trans_rule_hw_eth { 1222 u8 size; 1223 u8 rsvd; 1224 __be16 id; 1225 u8 rsvd1[6]; 1226 u8 dst_mac[6]; 1227 u16 rsvd2; 1228 u8 dst_mac_msk[6]; 1229 u16 rsvd3; 1230 u8 src_mac[6]; 1231 u16 rsvd4; 1232 u8 src_mac_msk[6]; 1233 u8 rsvd5; 1234 u8 ether_type_enable; 1235 __be16 ether_type; 1236 __be16 vlan_tag_msk; 1237 __be16 vlan_tag; 1238} __packed; 1239 1240struct mlx4_net_trans_rule_hw_tcp_udp { 1241 u8 size; 1242 u8 rsvd; 1243 __be16 id; 1244 __be16 rsvd1[3]; 1245 __be16 dst_port; 1246 __be16 rsvd2; 1247 __be16 dst_port_msk; 1248 __be16 rsvd3; 1249 __be16 src_port; 1250 __be16 rsvd4; 1251 __be16 src_port_msk; 1252} __packed; 1253 1254struct mlx4_net_trans_rule_hw_ipv4 { 1255 u8 size; 1256 u8 rsvd; 1257 __be16 id; 1258 __be32 rsvd1; 1259 __be32 dst_ip; 1260 __be32 dst_ip_msk; 1261 __be32 src_ip; 1262 __be32 src_ip_msk; 1263} __packed; 1264 1265struct mlx4_net_trans_rule_hw_vxlan { 1266 u8 size; 1267 u8 rsvd; 1268 __be16 id; 1269 __be32 rsvd1; 1270 __be32 vni; 1271 __be32 vni_mask; 1272} __packed; 1273 1274struct _rule_hw { 1275 union { 1276 struct { 1277 u8 size; 1278 u8 rsvd; 1279 __be16 id; 1280 }; 1281 struct mlx4_net_trans_rule_hw_eth eth; 1282 struct mlx4_net_trans_rule_hw_ib ib; 1283 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1284 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1285 struct mlx4_net_trans_rule_hw_vxlan vxlan; 1286 }; 1287}; 1288 1289enum { 1290 VXLAN_STEER_BY_OUTER_MAC = 1 << 0, 1291 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, 1292 VXLAN_STEER_BY_VSID_VNI = 1 << 2, 1293 VXLAN_STEER_BY_INNER_MAC = 1 << 3, 1294 VXLAN_STEER_BY_INNER_VLAN = 1 << 4, 1295}; 1296 1297 1298int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1299 enum mlx4_net_trans_promisc_mode mode); 1300int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1301 enum mlx4_net_trans_promisc_mode mode); 1302int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1303int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1304int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1305int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1306int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1307 1308int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1309void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1310int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1311int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1312int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1313 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1314int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1315 u8 promisc); 1316int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); 1317int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, 1318 u8 ignore_fcs_value); 1319int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); 1320int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); 1321int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1322int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1323void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1324 1325int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1326 int npages, u64 iova, u32 *lkey, u32 *rkey); 1327int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1328 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1329int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1330void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1331 u32 *lkey, u32 *rkey); 1332int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1333int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1334int mlx4_test_interrupts(struct mlx4_dev *dev); 1335int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, 1336 int *vector); 1337void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1338 1339int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); 1340 1341int mlx4_get_phys_port_id(struct mlx4_dev *dev); 1342int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1343int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1344 1345int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1346void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1347 1348void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, 1349 int port); 1350__be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port); 1351void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port); 1352int mlx4_flow_attach(struct mlx4_dev *dev, 1353 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1354int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1355int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1356 enum mlx4_net_trans_promisc_mode flow_type); 1357int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1358 enum mlx4_net_trans_rule_id id); 1359int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1360 1361int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, 1362 int port, int qpn, u16 prio, u64 *reg_id); 1363 1364void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1365 int i, int val); 1366 1367int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1368 1369int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1370int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1371int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1372int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1373int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1374enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1375int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1376 1377void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1378__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1379 1380int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, 1381 int *slave_id); 1382int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, 1383 u8 *gid); 1384 1385int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1386 u32 max_range_qpn); 1387 1388cycle_t mlx4_read_clock(struct mlx4_dev *dev); 1389 1390struct mlx4_active_ports { 1391 DECLARE_BITMAP(ports, MLX4_MAX_PORTS); 1392}; 1393/* Returns a bitmap of the physical ports which are assigned to slave */ 1394struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); 1395 1396/* Returns the physical port that represents the virtual port of the slave, */ 1397/* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ 1398/* mapping is returned. */ 1399int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); 1400 1401struct mlx4_slaves_pport { 1402 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); 1403}; 1404/* Returns a bitmap of all slaves that are assigned to port. */ 1405struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 1406 int port); 1407 1408/* Returns a bitmap of all slaves that are assigned exactly to all the */ 1409/* the ports that are set in crit_ports. */ 1410struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 1411 struct mlx4_dev *dev, 1412 const struct mlx4_active_ports *crit_ports); 1413 1414/* Returns the slave's virtual port that represents the physical port. */ 1415int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); 1416 1417int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1418 1419int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1420int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis); 1421int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2); 1422int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); 1423int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); 1424int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 1425 int enable); 1426int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1427 struct mlx4_mpt_entry ***mpt_entry); 1428int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1429 struct mlx4_mpt_entry **mpt_entry); 1430int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, 1431 u32 pdn); 1432int mlx4_mr_hw_change_access(struct mlx4_dev *dev, 1433 struct mlx4_mpt_entry *mpt_entry, 1434 u32 access); 1435void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, 1436 struct mlx4_mpt_entry **mpt_entry); 1437void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); 1438int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, 1439 u64 iova, u64 size, int npages, 1440 int page_shift, struct mlx4_mpt_entry *mpt_entry); 1441 1442int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, 1443 u16 offset, u16 size, u8 *data); 1444 1445/* Returns true if running in low memory profile (kdump kernel) */ 1446static inline bool mlx4_low_memory_profile(void) 1447{ 1448 return is_kdump_kernel(); 1449} 1450 1451/* ACCESS REG commands */ 1452enum mlx4_access_reg_method { 1453 MLX4_ACCESS_REG_QUERY = 0x1, 1454 MLX4_ACCESS_REG_WRITE = 0x2, 1455}; 1456 1457/* ACCESS PTYS Reg command */ 1458enum mlx4_ptys_proto { 1459 MLX4_PTYS_IB = 1<<0, 1460 MLX4_PTYS_EN = 1<<2, 1461}; 1462 1463struct mlx4_ptys_reg { 1464 u8 resrvd1; 1465 u8 local_port; 1466 u8 resrvd2; 1467 u8 proto_mask; 1468 __be32 resrvd3[2]; 1469 __be32 eth_proto_cap; 1470 __be16 ib_width_cap; 1471 __be16 ib_speed_cap; 1472 __be32 resrvd4; 1473 __be32 eth_proto_admin; 1474 __be16 ib_width_admin; 1475 __be16 ib_speed_admin; 1476 __be32 resrvd5; 1477 __be32 eth_proto_oper; 1478 __be16 ib_width_oper; 1479 __be16 ib_speed_oper; 1480 __be32 resrvd6; 1481 __be32 eth_proto_lp_adv; 1482} __packed; 1483 1484int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 1485 enum mlx4_access_reg_method method, 1486 struct mlx4_ptys_reg *ptys_reg); 1487 1488#endif /* MLX4_DEVICE_H */ 1489