1/* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16#ifndef LINUX_PCI_H 17#define LINUX_PCI_H 18 19 20#include <linux/mod_devicetable.h> 21 22#include <linux/types.h> 23#include <linux/init.h> 24#include <linux/ioport.h> 25#include <linux/list.h> 26#include <linux/compiler.h> 27#include <linux/errno.h> 28#include <linux/kobject.h> 29#include <linux/atomic.h> 30#include <linux/device.h> 31#include <linux/io.h> 32#include <linux/resource_ext.h> 33#include <uapi/linux/pci.h> 34 35#include <linux/pci_ids.h> 36 37/* 38 * The PCI interface treats multi-function devices as independent 39 * devices. The slot/function address of each device is encoded 40 * in a single byte as follows: 41 * 42 * 7:3 = slot 43 * 2:0 = function 44 * 45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 46 * In the interest of not exposing interfaces to user-space unnecessarily, 47 * the following kernel-only defines are being added here. 48 */ 49#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 50/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 51#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 52 53/* pci_slot represents a physical slot */ 54struct pci_slot { 55 struct pci_bus *bus; /* The bus this slot is on */ 56 struct list_head list; /* node in list of slots on this bus */ 57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 59 struct kobject kobj; 60}; 61 62static inline const char *pci_slot_name(const struct pci_slot *slot) 63{ 64 return kobject_name(&slot->kobj); 65} 66 67/* File state for mmap()s on /proc/bus/pci/X/Y */ 68enum pci_mmap_state { 69 pci_mmap_io, 70 pci_mmap_mem 71}; 72 73/* This defines the direction arg to the DMA mapping routines. */ 74#define PCI_DMA_BIDIRECTIONAL 0 75#define PCI_DMA_TODEVICE 1 76#define PCI_DMA_FROMDEVICE 2 77#define PCI_DMA_NONE 3 78 79/* 80 * For PCI devices, the region numbers are assigned this way: 81 */ 82enum { 83 /* #0-5: standard PCI resources */ 84 PCI_STD_RESOURCES, 85 PCI_STD_RESOURCE_END = 5, 86 87 /* #6: expansion ROM resource */ 88 PCI_ROM_RESOURCE, 89 90 /* device specific resources */ 91#ifdef CONFIG_PCI_IOV 92 PCI_IOV_RESOURCES, 93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 94#endif 95 96 /* resources assigned to buses behind the bridge */ 97#define PCI_BRIDGE_RESOURCE_NUM 4 98 99 PCI_BRIDGE_RESOURCES, 100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 101 PCI_BRIDGE_RESOURCE_NUM - 1, 102 103 /* total resources associated with a PCI device */ 104 PCI_NUM_RESOURCES, 105 106 /* preserve this for compatibility */ 107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 108}; 109 110typedef int __bitwise pci_power_t; 111 112#define PCI_D0 ((pci_power_t __force) 0) 113#define PCI_D1 ((pci_power_t __force) 1) 114#define PCI_D2 ((pci_power_t __force) 2) 115#define PCI_D3hot ((pci_power_t __force) 3) 116#define PCI_D3cold ((pci_power_t __force) 4) 117#define PCI_UNKNOWN ((pci_power_t __force) 5) 118#define PCI_POWER_ERROR ((pci_power_t __force) -1) 119 120/* Remember to update this when the list above changes! */ 121extern const char *pci_power_names[]; 122 123static inline const char *pci_power_name(pci_power_t state) 124{ 125 return pci_power_names[1 + (int) state]; 126} 127 128#define PCI_PM_D2_DELAY 200 129#define PCI_PM_D3_WAIT 10 130#define PCI_PM_D3COLD_WAIT 100 131#define PCI_PM_BUS_WAIT 50 132 133/** The pci_channel state describes connectivity between the CPU and 134 * the pci device. If some PCI bus between here and the pci device 135 * has crashed or locked up, this info is reflected here. 136 */ 137typedef unsigned int __bitwise pci_channel_state_t; 138 139enum pci_channel_state { 140 /* I/O channel is in normal state */ 141 pci_channel_io_normal = (__force pci_channel_state_t) 1, 142 143 /* I/O to channel is blocked */ 144 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 145 146 /* PCI card is dead */ 147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 148}; 149 150typedef unsigned int __bitwise pcie_reset_state_t; 151 152enum pcie_reset_state { 153 /* Reset is NOT asserted (Use to deassert reset) */ 154 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 155 156 /* Use #PERST to reset PCIe device */ 157 pcie_warm_reset = (__force pcie_reset_state_t) 2, 158 159 /* Use PCIe Hot Reset to reset device */ 160 pcie_hot_reset = (__force pcie_reset_state_t) 3 161}; 162 163typedef unsigned short __bitwise pci_dev_flags_t; 164enum pci_dev_flags { 165 /* INTX_DISABLE in PCI_COMMAND register disables MSI 166 * generation too. 167 */ 168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 169 /* Device configuration is irrevocably lost if disabled into D3 */ 170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 171 /* Provide indication device is assigned by a Virtual Machine Manager */ 172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 173 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 174 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 175 /* Flag to indicate the device uses dma_alias_devfn */ 176 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4), 177 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 178 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 179 /* Do not use bus resets for device */ 180 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 181 /* Do not use PM reset even if device advertises NoSoftRst- */ 182 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 183 /* Get VPD from function 0 VPD */ 184 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 185}; 186 187enum pci_irq_reroute_variant { 188 INTEL_IRQ_REROUTE_VARIANT = 1, 189 MAX_IRQ_REROUTE_VARIANTS = 3 190}; 191 192typedef unsigned short __bitwise pci_bus_flags_t; 193enum pci_bus_flags { 194 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 195 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 196}; 197 198/* These values come from the PCI Express Spec */ 199enum pcie_link_width { 200 PCIE_LNK_WIDTH_RESRV = 0x00, 201 PCIE_LNK_X1 = 0x01, 202 PCIE_LNK_X2 = 0x02, 203 PCIE_LNK_X4 = 0x04, 204 PCIE_LNK_X8 = 0x08, 205 PCIE_LNK_X12 = 0x0C, 206 PCIE_LNK_X16 = 0x10, 207 PCIE_LNK_X32 = 0x20, 208 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 209}; 210 211/* Based on the PCI Hotplug Spec, but some values are made up by us */ 212enum pci_bus_speed { 213 PCI_SPEED_33MHz = 0x00, 214 PCI_SPEED_66MHz = 0x01, 215 PCI_SPEED_66MHz_PCIX = 0x02, 216 PCI_SPEED_100MHz_PCIX = 0x03, 217 PCI_SPEED_133MHz_PCIX = 0x04, 218 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 219 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 220 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 221 PCI_SPEED_66MHz_PCIX_266 = 0x09, 222 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 223 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 224 AGP_UNKNOWN = 0x0c, 225 AGP_1X = 0x0d, 226 AGP_2X = 0x0e, 227 AGP_4X = 0x0f, 228 AGP_8X = 0x10, 229 PCI_SPEED_66MHz_PCIX_533 = 0x11, 230 PCI_SPEED_100MHz_PCIX_533 = 0x12, 231 PCI_SPEED_133MHz_PCIX_533 = 0x13, 232 PCIE_SPEED_2_5GT = 0x14, 233 PCIE_SPEED_5_0GT = 0x15, 234 PCIE_SPEED_8_0GT = 0x16, 235 PCI_SPEED_UNKNOWN = 0xff, 236}; 237 238struct pci_cap_saved_data { 239 u16 cap_nr; 240 bool cap_extended; 241 unsigned int size; 242 u32 data[0]; 243}; 244 245struct pci_cap_saved_state { 246 struct hlist_node next; 247 struct pci_cap_saved_data cap; 248}; 249 250struct pcie_link_state; 251struct pci_vpd; 252struct pci_sriov; 253struct pci_ats; 254 255/* 256 * The pci_dev structure is used to describe PCI devices. 257 */ 258struct pci_dev { 259 struct list_head bus_list; /* node in per-bus list */ 260 struct pci_bus *bus; /* bus this device is on */ 261 struct pci_bus *subordinate; /* bus this device bridges to */ 262 263 void *sysdata; /* hook for sys-specific extension */ 264 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 265 struct pci_slot *slot; /* Physical slot this device is in */ 266 267 unsigned int devfn; /* encoded device & function index */ 268 unsigned short vendor; 269 unsigned short device; 270 unsigned short subsystem_vendor; 271 unsigned short subsystem_device; 272 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 273 u8 revision; /* PCI revision, low byte of class word */ 274 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 275 u8 pcie_cap; /* PCIe capability offset */ 276 u8 msi_cap; /* MSI capability offset */ 277 u8 msix_cap; /* MSI-X capability offset */ 278 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 279 u8 rom_base_reg; /* which config register controls the ROM */ 280 u8 pin; /* which interrupt pin this device uses */ 281 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 282 u8 dma_alias_devfn;/* devfn of DMA alias, if any */ 283 284 struct pci_driver *driver; /* which driver has allocated this device */ 285 u64 dma_mask; /* Mask of the bits of bus address this 286 device implements. Normally this is 287 0xffffffff. You only need to change 288 this if your device has broken DMA 289 or supports 64-bit transfers. */ 290 291 struct device_dma_parameters dma_parms; 292 293 pci_power_t current_state; /* Current operating state. In ACPI-speak, 294 this is D0-D3, D0 being fully functional, 295 and D3 being off. */ 296 u8 pm_cap; /* PM capability offset */ 297 unsigned int pme_support:5; /* Bitmask of states from which PME# 298 can be generated */ 299 unsigned int pme_interrupt:1; 300 unsigned int pme_poll:1; /* Poll device's PME status bit */ 301 unsigned int d1_support:1; /* Low power state D1 is supported */ 302 unsigned int d2_support:1; /* Low power state D2 is supported */ 303 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 304 unsigned int no_d3cold:1; /* D3cold is forbidden */ 305 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 306 unsigned int mmio_always_on:1; /* disallow turning off io/mem 307 decoding during bar sizing */ 308 unsigned int wakeup_prepared:1; 309 unsigned int runtime_d3cold:1; /* whether go through runtime 310 D3cold, not set for devices 311 powered on/off by the 312 corresponding bridge */ 313 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 314 unsigned int d3_delay; /* D3->D0 transition time in ms */ 315 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 316 317#ifdef CONFIG_PCIEASPM 318 struct pcie_link_state *link_state; /* ASPM link state */ 319#endif 320 321 pci_channel_state_t error_state; /* current connectivity state */ 322 struct device dev; /* Generic device interface */ 323 324 int cfg_size; /* Size of configuration space */ 325 326 /* 327 * Instead of touching interrupt line and base address registers 328 * directly, use the values stored here. They might be different! 329 */ 330 unsigned int irq; 331 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 332 333 bool match_driver; /* Skip attaching driver */ 334 /* These fields are used by common fixups */ 335 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 336 unsigned int multifunction:1;/* Part of multi-function device */ 337 /* keep track of device state */ 338 unsigned int is_added:1; 339 unsigned int is_busmaster:1; /* device is busmaster */ 340 unsigned int no_msi:1; /* device may not use msi */ 341 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 342 unsigned int block_cfg_access:1; /* config space access is blocked */ 343 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 344 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 345 unsigned int msi_enabled:1; 346 unsigned int msix_enabled:1; 347 unsigned int ari_enabled:1; /* ARI forwarding */ 348 unsigned int is_managed:1; 349 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 350 unsigned int state_saved:1; 351 unsigned int is_physfn:1; 352 unsigned int is_virtfn:1; 353 unsigned int reset_fn:1; 354 unsigned int is_hotplug_bridge:1; 355 unsigned int __aer_firmware_first_valid:1; 356 unsigned int __aer_firmware_first:1; 357 unsigned int broken_intx_masking:1; 358 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 359 unsigned int irq_managed:1; 360 unsigned int has_secondary_link:1; 361 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */ 362 pci_dev_flags_t dev_flags; 363 atomic_t enable_cnt; /* pci_enable_device has been called */ 364 365 u32 saved_config_space[16]; /* config space saved at suspend time */ 366 struct hlist_head saved_cap_space; 367 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 368 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 369 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 370 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 371#ifdef CONFIG_PCI_MSI 372 struct list_head msi_list; 373 const struct attribute_group **msi_irq_groups; 374#endif 375 struct pci_vpd *vpd; 376#ifdef CONFIG_PCI_ATS 377 union { 378 struct pci_sriov *sriov; /* SR-IOV capability related */ 379 struct pci_dev *physfn; /* the PF this VF is associated with */ 380 }; 381 struct pci_ats *ats; /* Address Translation Service */ 382#endif 383 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 384 size_t romlen; /* Length of ROM if it's not from the BAR */ 385 char *driver_override; /* Driver name to force a match */ 386}; 387 388static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 389{ 390#ifdef CONFIG_PCI_IOV 391 if (dev->is_virtfn) 392 dev = dev->physfn; 393#endif 394 return dev; 395} 396 397struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 398 399#define to_pci_dev(n) container_of(n, struct pci_dev, dev) 400#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 401 402static inline int pci_channel_offline(struct pci_dev *pdev) 403{ 404 return (pdev->error_state != pci_channel_io_normal); 405} 406 407struct pci_host_bridge { 408 struct device dev; 409 struct pci_bus *bus; /* root bus */ 410 struct list_head windows; /* resource_entry */ 411 void (*release_fn)(struct pci_host_bridge *); 412 void *release_data; 413 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 414}; 415 416#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 417void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 418 void (*release_fn)(struct pci_host_bridge *), 419 void *release_data); 420 421int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 422 423/* 424 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 425 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 426 * buses below host bridges or subtractive decode bridges) go in the list. 427 * Use pci_bus_for_each_resource() to iterate through all the resources. 428 */ 429 430/* 431 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 432 * and there's no way to program the bridge with the details of the window. 433 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 434 * decode bit set, because they are explicit and can be programmed with _SRS. 435 */ 436#define PCI_SUBTRACTIVE_DECODE 0x1 437 438struct pci_bus_resource { 439 struct list_head list; 440 struct resource *res; 441 unsigned int flags; 442}; 443 444#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 445 446struct pci_bus { 447 struct list_head node; /* node in list of buses */ 448 struct pci_bus *parent; /* parent bus this bridge is on */ 449 struct list_head children; /* list of child buses */ 450 struct list_head devices; /* list of devices on this bus */ 451 struct pci_dev *self; /* bridge device as seen by parent */ 452 struct list_head slots; /* list of slots on this bus */ 453 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 454 struct list_head resources; /* address space routed to this bus */ 455 struct resource busn_res; /* bus numbers routed to this bus */ 456 457 struct pci_ops *ops; /* configuration access functions */ 458 struct msi_controller *msi; /* MSI controller */ 459 void *sysdata; /* hook for sys-specific extension */ 460 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 461 462 unsigned char number; /* bus number */ 463 unsigned char primary; /* number of primary bridge */ 464 unsigned char max_bus_speed; /* enum pci_bus_speed */ 465 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 466#ifdef CONFIG_PCI_DOMAINS_GENERIC 467 int domain_nr; 468#endif 469 470 char name[48]; 471 472 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 473 pci_bus_flags_t bus_flags; /* inherited by child buses */ 474 struct device *bridge; 475 struct device dev; 476 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 477 struct bin_attribute *legacy_mem; /* legacy mem */ 478 unsigned int is_added:1; 479}; 480 481#define to_pci_bus(n) container_of(n, struct pci_bus, dev) 482 483/* 484 * Returns true if the PCI bus is root (behind host-PCI bridge), 485 * false otherwise 486 * 487 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 488 * This is incorrect because "virtual" buses added for SR-IOV (via 489 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 490 */ 491static inline bool pci_is_root_bus(struct pci_bus *pbus) 492{ 493 return !(pbus->parent); 494} 495 496/** 497 * pci_is_bridge - check if the PCI device is a bridge 498 * @dev: PCI device 499 * 500 * Return true if the PCI device is bridge whether it has subordinate 501 * or not. 502 */ 503static inline bool pci_is_bridge(struct pci_dev *dev) 504{ 505 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 506 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 507} 508 509static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 510{ 511 dev = pci_physfn(dev); 512 if (pci_is_root_bus(dev->bus)) 513 return NULL; 514 515 return dev->bus->self; 516} 517 518struct device *pci_get_host_bridge_device(struct pci_dev *dev); 519void pci_put_host_bridge_device(struct device *dev); 520 521#ifdef CONFIG_PCI_MSI 522static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 523{ 524 return pci_dev->msi_enabled || pci_dev->msix_enabled; 525} 526#else 527static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 528#endif 529 530/* 531 * Error values that may be returned by PCI functions. 532 */ 533#define PCIBIOS_SUCCESSFUL 0x00 534#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 535#define PCIBIOS_BAD_VENDOR_ID 0x83 536#define PCIBIOS_DEVICE_NOT_FOUND 0x86 537#define PCIBIOS_BAD_REGISTER_NUMBER 0x87 538#define PCIBIOS_SET_FAILED 0x88 539#define PCIBIOS_BUFFER_TOO_SMALL 0x89 540 541/* 542 * Translate above to generic errno for passing back through non-PCI code. 543 */ 544static inline int pcibios_err_to_errno(int err) 545{ 546 if (err <= PCIBIOS_SUCCESSFUL) 547 return err; /* Assume already errno */ 548 549 switch (err) { 550 case PCIBIOS_FUNC_NOT_SUPPORTED: 551 return -ENOENT; 552 case PCIBIOS_BAD_VENDOR_ID: 553 return -ENOTTY; 554 case PCIBIOS_DEVICE_NOT_FOUND: 555 return -ENODEV; 556 case PCIBIOS_BAD_REGISTER_NUMBER: 557 return -EFAULT; 558 case PCIBIOS_SET_FAILED: 559 return -EIO; 560 case PCIBIOS_BUFFER_TOO_SMALL: 561 return -ENOSPC; 562 } 563 564 return -ERANGE; 565} 566 567/* Low-level architecture-dependent routines */ 568 569struct pci_ops { 570 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 571 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 572 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 573}; 574 575/* 576 * ACPI needs to be able to access PCI config space before we've done a 577 * PCI bus scan and created pci_bus structures. 578 */ 579int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 580 int reg, int len, u32 *val); 581int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 582 int reg, int len, u32 val); 583 584#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT 585typedef u64 pci_bus_addr_t; 586#else 587typedef u32 pci_bus_addr_t; 588#endif 589 590struct pci_bus_region { 591 pci_bus_addr_t start; 592 pci_bus_addr_t end; 593}; 594 595struct pci_dynids { 596 spinlock_t lock; /* protects list, index */ 597 struct list_head list; /* for IDs added at runtime */ 598}; 599 600 601/* 602 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 603 * a set of callbacks in struct pci_error_handlers, that device driver 604 * will be notified of PCI bus errors, and will be driven to recovery 605 * when an error occurs. 606 */ 607 608typedef unsigned int __bitwise pci_ers_result_t; 609 610enum pci_ers_result { 611 /* no result/none/not supported in device driver */ 612 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 613 614 /* Device driver can recover without slot reset */ 615 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 616 617 /* Device driver wants slot to be reset. */ 618 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 619 620 /* Device has completely failed, is unrecoverable */ 621 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 622 623 /* Device driver is fully recovered and operational */ 624 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 625 626 /* No AER capabilities registered for the driver */ 627 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 628}; 629 630/* PCI bus error event callbacks */ 631struct pci_error_handlers { 632 /* PCI bus error detected on this device */ 633 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 634 enum pci_channel_state error); 635 636 /* MMIO has been re-enabled, but not DMA */ 637 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 638 639 /* PCI Express link has been reset */ 640 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 641 642 /* PCI slot has been reset */ 643 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 644 645 /* PCI function reset prepare or completed */ 646 void (*reset_notify)(struct pci_dev *dev, bool prepare); 647 648 /* Device driver may resume normal operations */ 649 void (*resume)(struct pci_dev *dev); 650}; 651 652 653struct module; 654struct pci_driver { 655 struct list_head node; 656 const char *name; 657 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 658 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 659 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 660 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 661 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 662 int (*resume_early) (struct pci_dev *dev); 663 int (*resume) (struct pci_dev *dev); /* Device woken up */ 664 void (*shutdown) (struct pci_dev *dev); 665 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 666 const struct pci_error_handlers *err_handler; 667 struct device_driver driver; 668 struct pci_dynids dynids; 669}; 670 671#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 672 673/** 674 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 675 * @_table: device table name 676 * 677 * This macro is deprecated and should not be used in new code. 678 */ 679#define DEFINE_PCI_DEVICE_TABLE(_table) \ 680 const struct pci_device_id _table[] 681 682/** 683 * PCI_DEVICE - macro used to describe a specific pci device 684 * @vend: the 16 bit PCI Vendor ID 685 * @dev: the 16 bit PCI Device ID 686 * 687 * This macro is used to create a struct pci_device_id that matches a 688 * specific device. The subvendor and subdevice fields will be set to 689 * PCI_ANY_ID. 690 */ 691#define PCI_DEVICE(vend,dev) \ 692 .vendor = (vend), .device = (dev), \ 693 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 694 695/** 696 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 697 * @vend: the 16 bit PCI Vendor ID 698 * @dev: the 16 bit PCI Device ID 699 * @subvend: the 16 bit PCI Subvendor ID 700 * @subdev: the 16 bit PCI Subdevice ID 701 * 702 * This macro is used to create a struct pci_device_id that matches a 703 * specific device with subsystem information. 704 */ 705#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 706 .vendor = (vend), .device = (dev), \ 707 .subvendor = (subvend), .subdevice = (subdev) 708 709/** 710 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 711 * @dev_class: the class, subclass, prog-if triple for this device 712 * @dev_class_mask: the class mask for this device 713 * 714 * This macro is used to create a struct pci_device_id that matches a 715 * specific PCI class. The vendor, device, subvendor, and subdevice 716 * fields will be set to PCI_ANY_ID. 717 */ 718#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 719 .class = (dev_class), .class_mask = (dev_class_mask), \ 720 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 721 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 722 723/** 724 * PCI_VDEVICE - macro used to describe a specific pci device in short form 725 * @vend: the vendor name 726 * @dev: the 16 bit PCI Device ID 727 * 728 * This macro is used to create a struct pci_device_id that matches a 729 * specific PCI device. The subvendor, and subdevice fields will be set 730 * to PCI_ANY_ID. The macro allows the next field to follow as the device 731 * private data. 732 */ 733 734#define PCI_VDEVICE(vend, dev) \ 735 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 736 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 737 738/* these external functions are only available when PCI support is enabled */ 739#ifdef CONFIG_PCI 740 741void pcie_bus_configure_settings(struct pci_bus *bus); 742 743enum pcie_bus_config_types { 744 PCIE_BUS_TUNE_OFF, 745 PCIE_BUS_SAFE, 746 PCIE_BUS_PERFORMANCE, 747 PCIE_BUS_PEER2PEER, 748}; 749 750extern enum pcie_bus_config_types pcie_bus_config; 751 752extern struct bus_type pci_bus_type; 753 754/* Do NOT directly access these two variables, unless you are arch-specific PCI 755 * code, or PCI core code. */ 756extern struct list_head pci_root_buses; /* list of all known PCI buses */ 757/* Some device drivers need know if PCI is initiated */ 758int no_pci_devices(void); 759 760void pcibios_resource_survey_bus(struct pci_bus *bus); 761void pcibios_add_bus(struct pci_bus *bus); 762void pcibios_remove_bus(struct pci_bus *bus); 763void pcibios_fixup_bus(struct pci_bus *); 764int __must_check pcibios_enable_device(struct pci_dev *, int mask); 765/* Architecture-specific versions may override this (weak) */ 766char *pcibios_setup(char *str); 767 768/* Used only when drivers/pci/setup.c is used */ 769resource_size_t pcibios_align_resource(void *, const struct resource *, 770 resource_size_t, 771 resource_size_t); 772void pcibios_update_irq(struct pci_dev *, int irq); 773 774/* Weak but can be overriden by arch */ 775void pci_fixup_cardbus(struct pci_bus *); 776 777/* Generic PCI functions used internally */ 778 779void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 780 struct resource *res); 781void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 782 struct pci_bus_region *region); 783void pcibios_scan_specific_bus(int busn); 784struct pci_bus *pci_find_bus(int domain, int busnr); 785void pci_bus_add_devices(const struct pci_bus *bus); 786struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, 787 struct pci_ops *ops, void *sysdata); 788struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 789struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 790 struct pci_ops *ops, void *sysdata, 791 struct list_head *resources); 792int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 793int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 794void pci_bus_release_busn_res(struct pci_bus *b); 795struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 796 struct pci_ops *ops, void *sysdata, 797 struct list_head *resources); 798struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 799 int busnr); 800void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 801struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 802 const char *name, 803 struct hotplug_slot *hotplug); 804void pci_destroy_slot(struct pci_slot *slot); 805int pci_scan_slot(struct pci_bus *bus, int devfn); 806struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 807void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 808unsigned int pci_scan_child_bus(struct pci_bus *bus); 809void pci_bus_add_device(struct pci_dev *dev); 810void pci_read_bridge_bases(struct pci_bus *child); 811struct resource *pci_find_parent_resource(const struct pci_dev *dev, 812 struct resource *res); 813u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 814int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 815u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 816struct pci_dev *pci_dev_get(struct pci_dev *dev); 817void pci_dev_put(struct pci_dev *dev); 818void pci_remove_bus(struct pci_bus *b); 819void pci_stop_and_remove_bus_device(struct pci_dev *dev); 820void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 821void pci_stop_root_bus(struct pci_bus *bus); 822void pci_remove_root_bus(struct pci_bus *bus); 823void pci_setup_cardbus(struct pci_bus *bus); 824void pci_sort_breadthfirst(void); 825#define dev_is_pci(d) ((d)->bus == &pci_bus_type) 826#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 827#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) 828 829/* Generic PCI functions exported to card drivers */ 830 831enum pci_lost_interrupt_reason { 832 PCI_LOST_IRQ_NO_INFORMATION = 0, 833 PCI_LOST_IRQ_DISABLE_MSI, 834 PCI_LOST_IRQ_DISABLE_MSIX, 835 PCI_LOST_IRQ_DISABLE_ACPI, 836}; 837enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 838int pci_find_capability(struct pci_dev *dev, int cap); 839int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 840int pci_find_ext_capability(struct pci_dev *dev, int cap); 841int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 842int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 843int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 844struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 845 846struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 847 struct pci_dev *from); 848struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 849 unsigned int ss_vendor, unsigned int ss_device, 850 struct pci_dev *from); 851struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 852struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 853 unsigned int devfn); 854static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 855 unsigned int devfn) 856{ 857 return pci_get_domain_bus_and_slot(0, bus, devfn); 858} 859struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 860int pci_dev_present(const struct pci_device_id *ids); 861 862int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 863 int where, u8 *val); 864int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 865 int where, u16 *val); 866int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 867 int where, u32 *val); 868int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 869 int where, u8 val); 870int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 871 int where, u16 val); 872int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 873 int where, u32 val); 874 875int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 876 int where, int size, u32 *val); 877int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 878 int where, int size, u32 val); 879int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 880 int where, int size, u32 *val); 881int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 882 int where, int size, u32 val); 883 884struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 885 886static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) 887{ 888 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 889} 890static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) 891{ 892 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 893} 894static inline int pci_read_config_dword(const struct pci_dev *dev, int where, 895 u32 *val) 896{ 897 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 898} 899static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) 900{ 901 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 902} 903static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) 904{ 905 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 906} 907static inline int pci_write_config_dword(const struct pci_dev *dev, int where, 908 u32 val) 909{ 910 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 911} 912 913int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 914int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 915int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 916int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 917int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 918 u16 clear, u16 set); 919int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 920 u32 clear, u32 set); 921 922static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 923 u16 set) 924{ 925 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 926} 927 928static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 929 u32 set) 930{ 931 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 932} 933 934static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 935 u16 clear) 936{ 937 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 938} 939 940static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 941 u32 clear) 942{ 943 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 944} 945 946/* user-space driven config access */ 947int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 948int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 949int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 950int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 951int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 952int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 953 954int __must_check pci_enable_device(struct pci_dev *dev); 955int __must_check pci_enable_device_io(struct pci_dev *dev); 956int __must_check pci_enable_device_mem(struct pci_dev *dev); 957int __must_check pci_reenable_device(struct pci_dev *); 958int __must_check pcim_enable_device(struct pci_dev *pdev); 959void pcim_pin_device(struct pci_dev *pdev); 960 961static inline int pci_is_enabled(struct pci_dev *pdev) 962{ 963 return (atomic_read(&pdev->enable_cnt) > 0); 964} 965 966static inline int pci_is_managed(struct pci_dev *pdev) 967{ 968 return pdev->is_managed; 969} 970 971void pci_disable_device(struct pci_dev *dev); 972 973extern unsigned int pcibios_max_latency; 974void pci_set_master(struct pci_dev *dev); 975void pci_clear_master(struct pci_dev *dev); 976 977int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 978int pci_set_cacheline_size(struct pci_dev *dev); 979#define HAVE_PCI_SET_MWI 980int __must_check pci_set_mwi(struct pci_dev *dev); 981int pci_try_set_mwi(struct pci_dev *dev); 982void pci_clear_mwi(struct pci_dev *dev); 983void pci_intx(struct pci_dev *dev, int enable); 984bool pci_intx_mask_supported(struct pci_dev *dev); 985bool pci_check_and_mask_intx(struct pci_dev *dev); 986bool pci_check_and_unmask_intx(struct pci_dev *dev); 987void pci_msi_off(struct pci_dev *dev); 988int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); 989int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); 990int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 991int pci_wait_for_pending_transaction(struct pci_dev *dev); 992int pcix_get_max_mmrbc(struct pci_dev *dev); 993int pcix_get_mmrbc(struct pci_dev *dev); 994int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 995int pcie_get_readrq(struct pci_dev *dev); 996int pcie_set_readrq(struct pci_dev *dev, int rq); 997int pcie_get_mps(struct pci_dev *dev); 998int pcie_set_mps(struct pci_dev *dev, int mps); 999int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 1000 enum pcie_link_width *width); 1001int __pci_reset_function(struct pci_dev *dev); 1002int __pci_reset_function_locked(struct pci_dev *dev); 1003int pci_reset_function(struct pci_dev *dev); 1004int pci_try_reset_function(struct pci_dev *dev); 1005int pci_probe_reset_slot(struct pci_slot *slot); 1006int pci_reset_slot(struct pci_slot *slot); 1007int pci_try_reset_slot(struct pci_slot *slot); 1008int pci_probe_reset_bus(struct pci_bus *bus); 1009int pci_reset_bus(struct pci_bus *bus); 1010int pci_try_reset_bus(struct pci_bus *bus); 1011void pci_reset_secondary_bus(struct pci_dev *dev); 1012void pcibios_reset_secondary_bus(struct pci_dev *dev); 1013void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1014void pci_update_resource(struct pci_dev *dev, int resno); 1015int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1016int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1017int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1018bool pci_device_is_present(struct pci_dev *pdev); 1019void pci_ignore_hotplug(struct pci_dev *dev); 1020 1021/* ROM control related routines */ 1022int pci_enable_rom(struct pci_dev *pdev); 1023void pci_disable_rom(struct pci_dev *pdev); 1024void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1025void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1026size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1027void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1028 1029/* Power management related routines */ 1030int pci_save_state(struct pci_dev *dev); 1031void pci_restore_state(struct pci_dev *dev); 1032struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1033int pci_load_saved_state(struct pci_dev *dev, 1034 struct pci_saved_state *state); 1035int pci_load_and_free_saved_state(struct pci_dev *dev, 1036 struct pci_saved_state **state); 1037struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1038struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1039 u16 cap); 1040int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1041int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1042 u16 cap, unsigned int size); 1043int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1044int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1045pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1046bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1047void pci_pme_active(struct pci_dev *dev, bool enable); 1048int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1049 bool runtime, bool enable); 1050int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1051int pci_prepare_to_sleep(struct pci_dev *dev); 1052int pci_back_from_sleep(struct pci_dev *dev); 1053bool pci_dev_run_wake(struct pci_dev *dev); 1054bool pci_check_pme_status(struct pci_dev *dev); 1055void pci_pme_wakeup_bus(struct pci_bus *bus); 1056 1057static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1058 bool enable) 1059{ 1060 return __pci_enable_wake(dev, state, false, enable); 1061} 1062 1063/* PCI Virtual Channel */ 1064int pci_save_vc_state(struct pci_dev *dev); 1065void pci_restore_vc_state(struct pci_dev *dev); 1066void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1067 1068/* For use by arch with custom probe code */ 1069void set_pcie_port_type(struct pci_dev *pdev); 1070void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1071 1072/* Functions for PCI Hotplug drivers to use */ 1073int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1074unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1075unsigned int pci_rescan_bus(struct pci_bus *bus); 1076void pci_lock_rescan_remove(void); 1077void pci_unlock_rescan_remove(void); 1078 1079/* Vital product data routines */ 1080ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1081ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1082 1083/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1084resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1085void pci_bus_assign_resources(const struct pci_bus *bus); 1086void pci_bus_size_bridges(struct pci_bus *bus); 1087int pci_claim_resource(struct pci_dev *, int); 1088int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1089void pci_assign_unassigned_resources(void); 1090void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1091void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1092void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1093void pdev_enable_device(struct pci_dev *); 1094int pci_enable_resources(struct pci_dev *, int mask); 1095void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1096 int (*)(const struct pci_dev *, u8, u8)); 1097#define HAVE_PCI_REQ_REGIONS 2 1098int __must_check pci_request_regions(struct pci_dev *, const char *); 1099int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1100void pci_release_regions(struct pci_dev *); 1101int __must_check pci_request_region(struct pci_dev *, int, const char *); 1102int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1103void pci_release_region(struct pci_dev *, int); 1104int pci_request_selected_regions(struct pci_dev *, int, const char *); 1105int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1106void pci_release_selected_regions(struct pci_dev *, int); 1107 1108/* drivers/pci/bus.c */ 1109struct pci_bus *pci_bus_get(struct pci_bus *bus); 1110void pci_bus_put(struct pci_bus *bus); 1111void pci_add_resource(struct list_head *resources, struct resource *res); 1112void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1113 resource_size_t offset); 1114void pci_free_resource_list(struct list_head *resources); 1115void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); 1116struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1117void pci_bus_remove_resources(struct pci_bus *bus); 1118 1119#define pci_bus_for_each_resource(bus, res, i) \ 1120 for (i = 0; \ 1121 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1122 i++) 1123 1124int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1125 struct resource *res, resource_size_t size, 1126 resource_size_t align, resource_size_t min, 1127 unsigned long type_mask, 1128 resource_size_t (*alignf)(void *, 1129 const struct resource *, 1130 resource_size_t, 1131 resource_size_t), 1132 void *alignf_data); 1133 1134 1135int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1136 1137static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1138{ 1139 struct pci_bus_region region; 1140 1141 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1142 return region.start; 1143} 1144 1145/* Proper probing supporting hot-pluggable devices */ 1146int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1147 const char *mod_name); 1148 1149/* 1150 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1151 */ 1152#define pci_register_driver(driver) \ 1153 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1154 1155void pci_unregister_driver(struct pci_driver *dev); 1156 1157/** 1158 * module_pci_driver() - Helper macro for registering a PCI driver 1159 * @__pci_driver: pci_driver struct 1160 * 1161 * Helper macro for PCI drivers which do not do anything special in module 1162 * init/exit. This eliminates a lot of boilerplate. Each module may only 1163 * use this macro once, and calling it replaces module_init() and module_exit() 1164 */ 1165#define module_pci_driver(__pci_driver) \ 1166 module_driver(__pci_driver, pci_register_driver, \ 1167 pci_unregister_driver) 1168 1169struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1170int pci_add_dynid(struct pci_driver *drv, 1171 unsigned int vendor, unsigned int device, 1172 unsigned int subvendor, unsigned int subdevice, 1173 unsigned int class, unsigned int class_mask, 1174 unsigned long driver_data); 1175const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1176 struct pci_dev *dev); 1177int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1178 int pass); 1179 1180void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1181 void *userdata); 1182int pci_cfg_space_size(struct pci_dev *dev); 1183unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1184void pci_setup_bridge(struct pci_bus *bus); 1185resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1186 unsigned long type); 1187resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1188 1189#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1190#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1191 1192int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1193 unsigned int command_bits, u32 flags); 1194/* kmem_cache style wrapper around pci_alloc_consistent() */ 1195 1196#include <linux/pci-dma.h> 1197#include <linux/dmapool.h> 1198 1199#define pci_pool dma_pool 1200#define pci_pool_create(name, pdev, size, align, allocation) \ 1201 dma_pool_create(name, &pdev->dev, size, align, allocation) 1202#define pci_pool_destroy(pool) dma_pool_destroy(pool) 1203#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1204#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1205 1206enum pci_dma_burst_strategy { 1207 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, 1208 strategy_parameter is N/A */ 1209 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter 1210 byte boundaries */ 1211 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of 1212 strategy_parameter byte boundaries */ 1213}; 1214 1215struct msix_entry { 1216 u32 vector; /* kernel uses to write allocated vector */ 1217 u16 entry; /* driver uses to specify entry, OS writes */ 1218}; 1219 1220 1221#ifdef CONFIG_PCI_MSI 1222int pci_msi_vec_count(struct pci_dev *dev); 1223void pci_msi_shutdown(struct pci_dev *dev); 1224void pci_disable_msi(struct pci_dev *dev); 1225int pci_msix_vec_count(struct pci_dev *dev); 1226int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); 1227void pci_msix_shutdown(struct pci_dev *dev); 1228void pci_disable_msix(struct pci_dev *dev); 1229void pci_restore_msi_state(struct pci_dev *dev); 1230int pci_msi_enabled(void); 1231int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); 1232static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1233{ 1234 int rc = pci_enable_msi_range(dev, nvec, nvec); 1235 if (rc < 0) 1236 return rc; 1237 return 0; 1238} 1239int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1240 int minvec, int maxvec); 1241static inline int pci_enable_msix_exact(struct pci_dev *dev, 1242 struct msix_entry *entries, int nvec) 1243{ 1244 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1245 if (rc < 0) 1246 return rc; 1247 return 0; 1248} 1249#else 1250static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1251static inline void pci_msi_shutdown(struct pci_dev *dev) { } 1252static inline void pci_disable_msi(struct pci_dev *dev) { } 1253static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1254static inline int pci_enable_msix(struct pci_dev *dev, 1255 struct msix_entry *entries, int nvec) 1256{ return -ENOSYS; } 1257static inline void pci_msix_shutdown(struct pci_dev *dev) { } 1258static inline void pci_disable_msix(struct pci_dev *dev) { } 1259static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1260static inline int pci_msi_enabled(void) { return 0; } 1261static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, 1262 int maxvec) 1263{ return -ENOSYS; } 1264static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1265{ return -ENOSYS; } 1266static inline int pci_enable_msix_range(struct pci_dev *dev, 1267 struct msix_entry *entries, int minvec, int maxvec) 1268{ return -ENOSYS; } 1269static inline int pci_enable_msix_exact(struct pci_dev *dev, 1270 struct msix_entry *entries, int nvec) 1271{ return -ENOSYS; } 1272#endif 1273 1274#ifdef CONFIG_PCIEPORTBUS 1275extern bool pcie_ports_disabled; 1276extern bool pcie_ports_auto; 1277#else 1278#define pcie_ports_disabled true 1279#define pcie_ports_auto false 1280#endif 1281 1282#ifdef CONFIG_PCIEASPM 1283bool pcie_aspm_support_enabled(void); 1284#else 1285static inline bool pcie_aspm_support_enabled(void) { return false; } 1286#endif 1287 1288#ifdef CONFIG_PCIEAER 1289void pci_no_aer(void); 1290bool pci_aer_available(void); 1291#else 1292static inline void pci_no_aer(void) { } 1293static inline bool pci_aer_available(void) { return false; } 1294#endif 1295 1296#ifdef CONFIG_PCIE_ECRC 1297void pcie_set_ecrc_checking(struct pci_dev *dev); 1298void pcie_ecrc_get_policy(char *str); 1299#else 1300static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1301static inline void pcie_ecrc_get_policy(char *str) { } 1302#endif 1303 1304#define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1) 1305 1306#ifdef CONFIG_HT_IRQ 1307/* The functions a driver should call */ 1308int ht_create_irq(struct pci_dev *dev, int idx); 1309void ht_destroy_irq(unsigned int irq); 1310#endif /* CONFIG_HT_IRQ */ 1311 1312void pci_cfg_access_lock(struct pci_dev *dev); 1313bool pci_cfg_access_trylock(struct pci_dev *dev); 1314void pci_cfg_access_unlock(struct pci_dev *dev); 1315 1316/* 1317 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1318 * a PCI domain is defined to be a set of PCI buses which share 1319 * configuration space. 1320 */ 1321#ifdef CONFIG_PCI_DOMAINS 1322extern int pci_domains_supported; 1323int pci_get_new_domain_nr(void); 1324#else 1325enum { pci_domains_supported = 0 }; 1326static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1327static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1328static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1329#endif /* CONFIG_PCI_DOMAINS */ 1330 1331/* 1332 * Generic implementation for PCI domain support. If your 1333 * architecture does not need custom management of PCI 1334 * domains then this implementation will be used 1335 */ 1336#ifdef CONFIG_PCI_DOMAINS_GENERIC 1337static inline int pci_domain_nr(struct pci_bus *bus) 1338{ 1339 return bus->domain_nr; 1340} 1341void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent); 1342#else 1343static inline void pci_bus_assign_domain_nr(struct pci_bus *bus, 1344 struct device *parent) 1345{ 1346} 1347#endif 1348 1349/* some architectures require additional setup to direct VGA traffic */ 1350typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1351 unsigned int command_bits, u32 flags); 1352void pci_register_set_vga_state(arch_set_vga_state_t func); 1353 1354#else /* CONFIG_PCI is not enabled */ 1355 1356/* 1357 * If the system does not have PCI, clearly these return errors. Define 1358 * these as simple inline functions to avoid hair in drivers. 1359 */ 1360 1361#define _PCI_NOP(o, s, t) \ 1362 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1363 int where, t val) \ 1364 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1365 1366#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1367 _PCI_NOP(o, word, u16 x) \ 1368 _PCI_NOP(o, dword, u32 x) 1369_PCI_NOP_ALL(read, *) 1370_PCI_NOP_ALL(write,) 1371 1372static inline struct pci_dev *pci_get_device(unsigned int vendor, 1373 unsigned int device, 1374 struct pci_dev *from) 1375{ return NULL; } 1376 1377static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1378 unsigned int device, 1379 unsigned int ss_vendor, 1380 unsigned int ss_device, 1381 struct pci_dev *from) 1382{ return NULL; } 1383 1384static inline struct pci_dev *pci_get_class(unsigned int class, 1385 struct pci_dev *from) 1386{ return NULL; } 1387 1388#define pci_dev_present(ids) (0) 1389#define no_pci_devices() (1) 1390#define pci_dev_put(dev) do { } while (0) 1391 1392static inline void pci_set_master(struct pci_dev *dev) { } 1393static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1394static inline void pci_disable_device(struct pci_dev *dev) { } 1395static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 1396{ return -EIO; } 1397static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 1398{ return -EIO; } 1399static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, 1400 unsigned int size) 1401{ return -EIO; } 1402static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, 1403 unsigned long mask) 1404{ return -EIO; } 1405static inline int pci_assign_resource(struct pci_dev *dev, int i) 1406{ return -EBUSY; } 1407static inline int __pci_register_driver(struct pci_driver *drv, 1408 struct module *owner) 1409{ return 0; } 1410static inline int pci_register_driver(struct pci_driver *drv) 1411{ return 0; } 1412static inline void pci_unregister_driver(struct pci_driver *drv) { } 1413static inline int pci_find_capability(struct pci_dev *dev, int cap) 1414{ return 0; } 1415static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1416 int cap) 1417{ return 0; } 1418static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1419{ return 0; } 1420 1421/* Power management related routines */ 1422static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1423static inline void pci_restore_state(struct pci_dev *dev) { } 1424static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1425{ return 0; } 1426static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1427{ return 0; } 1428static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1429 pm_message_t state) 1430{ return PCI_D0; } 1431static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1432 int enable) 1433{ return 0; } 1434 1435static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1436{ return -EIO; } 1437static inline void pci_release_regions(struct pci_dev *dev) { } 1438 1439#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) 1440 1441static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1442static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1443{ return 0; } 1444static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1445 1446static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1447{ return NULL; } 1448static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1449 unsigned int devfn) 1450{ return NULL; } 1451static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1452 unsigned int devfn) 1453{ return NULL; } 1454 1455static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1456static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1457static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1458 1459#define dev_is_pci(d) (false) 1460#define dev_is_pf(d) (false) 1461#define dev_num_vf(d) (0) 1462#endif /* CONFIG_PCI */ 1463 1464/* Include architecture-dependent settings and functions */ 1465 1466#include <asm/pci.h> 1467 1468/* these helpers provide future and backwards compatibility 1469 * for accessing popular PCI BAR info */ 1470#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1471#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1472#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1473#define pci_resource_len(dev,bar) \ 1474 ((pci_resource_start((dev), (bar)) == 0 && \ 1475 pci_resource_end((dev), (bar)) == \ 1476 pci_resource_start((dev), (bar))) ? 0 : \ 1477 \ 1478 (pci_resource_end((dev), (bar)) - \ 1479 pci_resource_start((dev), (bar)) + 1)) 1480 1481/* Similar to the helpers above, these manipulate per-pci_dev 1482 * driver-specific data. They are really just a wrapper around 1483 * the generic device structure functions of these calls. 1484 */ 1485static inline void *pci_get_drvdata(struct pci_dev *pdev) 1486{ 1487 return dev_get_drvdata(&pdev->dev); 1488} 1489 1490static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1491{ 1492 dev_set_drvdata(&pdev->dev, data); 1493} 1494 1495/* If you want to know what to call your pci_dev, ask this function. 1496 * Again, it's a wrapper around the generic device. 1497 */ 1498static inline const char *pci_name(const struct pci_dev *pdev) 1499{ 1500 return dev_name(&pdev->dev); 1501} 1502 1503 1504/* Some archs don't want to expose struct resource to userland as-is 1505 * in sysfs and /proc 1506 */ 1507#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1508static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1509 const struct resource *rsrc, resource_size_t *start, 1510 resource_size_t *end) 1511{ 1512 *start = rsrc->start; 1513 *end = rsrc->end; 1514} 1515#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1516 1517 1518/* 1519 * The world is not perfect and supplies us with broken PCI devices. 1520 * For at least a part of these bugs we need a work-around, so both 1521 * generic (drivers/pci/quirks.c) and per-architecture code can define 1522 * fixup hooks to be called for particular buggy devices. 1523 */ 1524 1525struct pci_fixup { 1526 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1527 u16 device; /* You can use PCI_ANY_ID here of course */ 1528 u32 class; /* You can use PCI_ANY_ID here too */ 1529 unsigned int class_shift; /* should be 0, 8, 16 */ 1530 void (*hook)(struct pci_dev *dev); 1531}; 1532 1533enum pci_fixup_pass { 1534 pci_fixup_early, /* Before probing BARs */ 1535 pci_fixup_header, /* After reading configuration header */ 1536 pci_fixup_final, /* Final phase of device fixups */ 1537 pci_fixup_enable, /* pci_enable_device() time */ 1538 pci_fixup_resume, /* pci_device_resume() */ 1539 pci_fixup_suspend, /* pci_device_suspend() */ 1540 pci_fixup_resume_early, /* pci_device_resume_early() */ 1541 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1542}; 1543 1544/* Anonymous variables would be nice... */ 1545#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1546 class_shift, hook) \ 1547 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1548 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1549 = { vendor, device, class, class_shift, hook }; 1550 1551#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1552 class_shift, hook) \ 1553 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1554 hook, vendor, device, class, class_shift, hook) 1555#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1556 class_shift, hook) \ 1557 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1558 hook, vendor, device, class, class_shift, hook) 1559#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1560 class_shift, hook) \ 1561 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1562 hook, vendor, device, class, class_shift, hook) 1563#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1564 class_shift, hook) \ 1565 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1566 hook, vendor, device, class, class_shift, hook) 1567#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1568 class_shift, hook) \ 1569 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1570 resume##hook, vendor, device, class, \ 1571 class_shift, hook) 1572#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1573 class_shift, hook) \ 1574 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1575 resume_early##hook, vendor, device, \ 1576 class, class_shift, hook) 1577#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1578 class_shift, hook) \ 1579 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1580 suspend##hook, vendor, device, class, \ 1581 class_shift, hook) 1582#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1583 class_shift, hook) \ 1584 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1585 suspend_late##hook, vendor, device, \ 1586 class, class_shift, hook) 1587 1588#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1589 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1590 hook, vendor, device, PCI_ANY_ID, 0, hook) 1591#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1592 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1593 hook, vendor, device, PCI_ANY_ID, 0, hook) 1594#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1595 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1596 hook, vendor, device, PCI_ANY_ID, 0, hook) 1597#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1598 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1599 hook, vendor, device, PCI_ANY_ID, 0, hook) 1600#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1601 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1602 resume##hook, vendor, device, \ 1603 PCI_ANY_ID, 0, hook) 1604#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1605 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1606 resume_early##hook, vendor, device, \ 1607 PCI_ANY_ID, 0, hook) 1608#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1609 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1610 suspend##hook, vendor, device, \ 1611 PCI_ANY_ID, 0, hook) 1612#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1613 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1614 suspend_late##hook, vendor, device, \ 1615 PCI_ANY_ID, 0, hook) 1616 1617#ifdef CONFIG_PCI_QUIRKS 1618void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1619int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1620void pci_dev_specific_enable_acs(struct pci_dev *dev); 1621#else 1622static inline void pci_fixup_device(enum pci_fixup_pass pass, 1623 struct pci_dev *dev) { } 1624static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1625 u16 acs_flags) 1626{ 1627 return -ENOTTY; 1628} 1629static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { } 1630#endif 1631 1632void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1633void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1634void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1635int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1636int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1637 const char *name); 1638void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1639 1640extern int pci_pci_problems; 1641#define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1642#define PCIPCI_TRITON 2 1643#define PCIPCI_NATOMA 4 1644#define PCIPCI_VIAETBF 8 1645#define PCIPCI_VSFX 16 1646#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1647#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1648 1649extern unsigned long pci_cardbus_io_size; 1650extern unsigned long pci_cardbus_mem_size; 1651extern u8 pci_dfl_cache_line_size; 1652extern u8 pci_cache_line_size; 1653 1654extern unsigned long pci_hotplug_io_size; 1655extern unsigned long pci_hotplug_mem_size; 1656 1657/* Architecture-specific versions may override these (weak) */ 1658void pcibios_disable_device(struct pci_dev *dev); 1659void pcibios_set_master(struct pci_dev *dev); 1660int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1661 enum pcie_reset_state state); 1662int pcibios_add_device(struct pci_dev *dev); 1663void pcibios_release_device(struct pci_dev *dev); 1664void pcibios_penalize_isa_irq(int irq, int active); 1665 1666#ifdef CONFIG_HIBERNATE_CALLBACKS 1667extern struct dev_pm_ops pcibios_pm_ops; 1668#endif 1669 1670#ifdef CONFIG_PCI_MMCONFIG 1671void __init pci_mmcfg_early_init(void); 1672void __init pci_mmcfg_late_init(void); 1673#else 1674static inline void pci_mmcfg_early_init(void) { } 1675static inline void pci_mmcfg_late_init(void) { } 1676#endif 1677 1678int pci_ext_cfg_avail(void); 1679 1680void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1681 1682#ifdef CONFIG_PCI_IOV 1683int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1684int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1685 1686int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1687void pci_disable_sriov(struct pci_dev *dev); 1688int pci_num_vf(struct pci_dev *dev); 1689int pci_vfs_assigned(struct pci_dev *dev); 1690int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1691int pci_sriov_get_totalvfs(struct pci_dev *dev); 1692resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1693#else 1694static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1695{ 1696 return -ENOSYS; 1697} 1698static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1699{ 1700 return -ENOSYS; 1701} 1702static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1703{ return -ENODEV; } 1704static inline void pci_disable_sriov(struct pci_dev *dev) { } 1705static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1706static inline int pci_vfs_assigned(struct pci_dev *dev) 1707{ return 0; } 1708static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1709{ return 0; } 1710static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1711{ return 0; } 1712static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1713{ return 0; } 1714#endif 1715 1716#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1717void pci_hp_create_module_link(struct pci_slot *pci_slot); 1718void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1719#endif 1720 1721/** 1722 * pci_pcie_cap - get the saved PCIe capability offset 1723 * @dev: PCI device 1724 * 1725 * PCIe capability offset is calculated at PCI device initialization 1726 * time and saved in the data structure. This function returns saved 1727 * PCIe capability offset. Using this instead of pci_find_capability() 1728 * reduces unnecessary search in the PCI configuration space. If you 1729 * need to calculate PCIe capability offset from raw device for some 1730 * reasons, please use pci_find_capability() instead. 1731 */ 1732static inline int pci_pcie_cap(struct pci_dev *dev) 1733{ 1734 return dev->pcie_cap; 1735} 1736 1737/** 1738 * pci_is_pcie - check if the PCI device is PCI Express capable 1739 * @dev: PCI device 1740 * 1741 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1742 */ 1743static inline bool pci_is_pcie(struct pci_dev *dev) 1744{ 1745 return pci_pcie_cap(dev); 1746} 1747 1748/** 1749 * pcie_caps_reg - get the PCIe Capabilities Register 1750 * @dev: PCI device 1751 */ 1752static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1753{ 1754 return dev->pcie_flags_reg; 1755} 1756 1757/** 1758 * pci_pcie_type - get the PCIe device/port type 1759 * @dev: PCI device 1760 */ 1761static inline int pci_pcie_type(const struct pci_dev *dev) 1762{ 1763 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1764} 1765 1766void pci_request_acs(void); 1767bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 1768bool pci_acs_path_enabled(struct pci_dev *start, 1769 struct pci_dev *end, u16 acs_flags); 1770 1771#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1772#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 1773 1774/* Large Resource Data Type Tag Item Names */ 1775#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1776#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1777#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1778 1779#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1780#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 1781#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 1782 1783/* Small Resource Data Type Tag Item Names */ 1784#define PCI_VPD_STIN_END 0x78 /* End */ 1785 1786#define PCI_VPD_SRDT_END PCI_VPD_STIN_END 1787 1788#define PCI_VPD_SRDT_TIN_MASK 0x78 1789#define PCI_VPD_SRDT_LEN_MASK 0x07 1790 1791#define PCI_VPD_LRDT_TAG_SIZE 3 1792#define PCI_VPD_SRDT_TAG_SIZE 1 1793 1794#define PCI_VPD_INFO_FLD_HDR_SIZE 3 1795 1796#define PCI_VPD_RO_KEYWORD_PARTNO "PN" 1797#define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 1798#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 1799#define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 1800 1801/** 1802 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 1803 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 1804 * 1805 * Returns the extracted Large Resource Data Type length. 1806 */ 1807static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 1808{ 1809 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 1810} 1811 1812/** 1813 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 1814 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 1815 * 1816 * Returns the extracted Small Resource Data Type length. 1817 */ 1818static inline u8 pci_vpd_srdt_size(const u8 *srdt) 1819{ 1820 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 1821} 1822 1823/** 1824 * pci_vpd_info_field_size - Extracts the information field length 1825 * @lrdt: Pointer to the beginning of an information field header 1826 * 1827 * Returns the extracted information field length. 1828 */ 1829static inline u8 pci_vpd_info_field_size(const u8 *info_field) 1830{ 1831 return info_field[2]; 1832} 1833 1834/** 1835 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 1836 * @buf: Pointer to buffered vpd data 1837 * @off: The offset into the buffer at which to begin the search 1838 * @len: The length of the vpd buffer 1839 * @rdt: The Resource Data Type to search for 1840 * 1841 * Returns the index where the Resource Data Type was found or 1842 * -ENOENT otherwise. 1843 */ 1844int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 1845 1846/** 1847 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 1848 * @buf: Pointer to buffered vpd data 1849 * @off: The offset into the buffer at which to begin the search 1850 * @len: The length of the buffer area, relative to off, in which to search 1851 * @kw: The keyword to search for 1852 * 1853 * Returns the index where the information field keyword was found or 1854 * -ENOENT otherwise. 1855 */ 1856int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 1857 unsigned int len, const char *kw); 1858 1859/* PCI <-> OF binding helpers */ 1860#ifdef CONFIG_OF 1861struct device_node; 1862void pci_set_of_node(struct pci_dev *dev); 1863void pci_release_of_node(struct pci_dev *dev); 1864void pci_set_bus_of_node(struct pci_bus *bus); 1865void pci_release_bus_of_node(struct pci_bus *bus); 1866 1867/* Arch may override this (weak) */ 1868struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 1869 1870static inline struct device_node * 1871pci_device_to_OF_node(const struct pci_dev *pdev) 1872{ 1873 return pdev ? pdev->dev.of_node : NULL; 1874} 1875 1876static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 1877{ 1878 return bus ? bus->dev.of_node : NULL; 1879} 1880 1881#else /* CONFIG_OF */ 1882static inline void pci_set_of_node(struct pci_dev *dev) { } 1883static inline void pci_release_of_node(struct pci_dev *dev) { } 1884static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1885static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1886static inline struct device_node * 1887pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 1888#endif /* CONFIG_OF */ 1889 1890#ifdef CONFIG_EEH 1891static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 1892{ 1893 return pdev->dev.archdata.edev; 1894} 1895#endif 1896 1897int pci_for_each_dma_alias(struct pci_dev *pdev, 1898 int (*fn)(struct pci_dev *pdev, 1899 u16 alias, void *data), void *data); 1900 1901/* helper functions for operation of device flag */ 1902static inline void pci_set_dev_assigned(struct pci_dev *pdev) 1903{ 1904 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 1905} 1906static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 1907{ 1908 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 1909} 1910static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 1911{ 1912 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 1913} 1914#endif /* LINUX_PCI_H */ 1915