1/* 2 * TI EDMA definitions 3 * 4 * Copyright (C) 2006-2013 Texas Instruments. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/* 13 * This EDMA3 programming framework exposes two basic kinds of resource: 14 * 15 * Channel Triggers transfers, usually from a hardware event but 16 * also manually or by "chaining" from DMA completions. 17 * Each channel is coupled to a Parameter RAM (PaRAM) slot. 18 * 19 * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM 20 * "set"), source and destination addresses, a link to a 21 * next PaRAM slot (if any), options for the transfer, and 22 * instructions for updating those addresses. There are 23 * more than twice as many slots as event channels. 24 * 25 * Each PaRAM set describes a sequence of transfers, either for one large 26 * buffer or for several discontiguous smaller buffers. An EDMA transfer 27 * is driven only from a channel, which performs the transfers specified 28 * in its PaRAM slot until there are no more transfers. When that last 29 * transfer completes, the "link" field may be used to reload the channel's 30 * PaRAM slot with a new transfer descriptor. 31 * 32 * The EDMA Channel Controller (CC) maps requests from channels into physical 33 * Transfer Controller (TC) requests when the channel triggers (by hardware 34 * or software events, or by chaining). The two physical DMA channels provided 35 * by the TCs are thus shared by many logical channels. 36 * 37 * DaVinci hardware also has a "QDMA" mechanism which is not currently 38 * supported through this interface. (DSP firmware uses it though.) 39 */ 40 41#ifndef EDMA_H_ 42#define EDMA_H_ 43 44/* PaRAM slots are laid out like this */ 45struct edmacc_param { 46 u32 opt; 47 u32 src; 48 u32 a_b_cnt; 49 u32 dst; 50 u32 src_dst_bidx; 51 u32 link_bcntrld; 52 u32 src_dst_cidx; 53 u32 ccnt; 54} __packed; 55 56/* fields in edmacc_param.opt */ 57#define SAM BIT(0) 58#define DAM BIT(1) 59#define SYNCDIM BIT(2) 60#define STATIC BIT(3) 61#define EDMA_FWID (0x07 << 8) 62#define TCCMODE BIT(11) 63#define EDMA_TCC(t) ((t) << 12) 64#define TCINTEN BIT(20) 65#define ITCINTEN BIT(21) 66#define TCCHEN BIT(22) 67#define ITCCHEN BIT(23) 68 69/*ch_status paramater of callback function possible values*/ 70#define EDMA_DMA_COMPLETE 1 71#define EDMA_DMA_CC_ERROR 2 72#define EDMA_DMA_TC1_ERROR 3 73#define EDMA_DMA_TC2_ERROR 4 74 75enum address_mode { 76 INCR = 0, 77 FIFO = 1 78}; 79 80enum fifo_width { 81 W8BIT = 0, 82 W16BIT = 1, 83 W32BIT = 2, 84 W64BIT = 3, 85 W128BIT = 4, 86 W256BIT = 5 87}; 88 89enum dma_event_q { 90 EVENTQ_0 = 0, 91 EVENTQ_1 = 1, 92 EVENTQ_2 = 2, 93 EVENTQ_3 = 3, 94 EVENTQ_DEFAULT = -1 95}; 96 97enum sync_dimension { 98 ASYNC = 0, 99 ABSYNC = 1 100}; 101 102#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) 103#define EDMA_CTLR(i) ((i) >> 16) 104#define EDMA_CHAN_SLOT(i) ((i) & 0xffff) 105 106#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ 107#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ 108#define EDMA_CONT_PARAMS_ANY 1001 109#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 110#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 111 112#define EDMA_MAX_CC 2 113 114/* alloc/free DMA channels and their dedicated parameter RAM slots */ 115int edma_alloc_channel(int channel, 116 void (*callback)(unsigned channel, u16 ch_status, void *data), 117 void *data, enum dma_event_q); 118void edma_free_channel(unsigned channel); 119 120/* alloc/free parameter RAM slots */ 121int edma_alloc_slot(unsigned ctlr, int slot); 122void edma_free_slot(unsigned slot); 123 124/* alloc/free a set of contiguous parameter RAM slots */ 125int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count); 126int edma_free_cont_slots(unsigned slot, int count); 127 128/* calls that operate on part of a parameter RAM slot */ 129void edma_set_src(unsigned slot, dma_addr_t src_port, 130 enum address_mode mode, enum fifo_width); 131void edma_set_dest(unsigned slot, dma_addr_t dest_port, 132 enum address_mode mode, enum fifo_width); 133dma_addr_t edma_get_position(unsigned slot, bool dst); 134void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx); 135void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx); 136void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt, 137 u16 bcnt_rld, enum sync_dimension sync_mode); 138void edma_link(unsigned from, unsigned to); 139void edma_unlink(unsigned from); 140 141/* calls that operate on an entire parameter RAM slot */ 142void edma_write_slot(unsigned slot, const struct edmacc_param *params); 143void edma_read_slot(unsigned slot, struct edmacc_param *params); 144 145/* channel control operations */ 146int edma_start(unsigned channel); 147void edma_stop(unsigned channel); 148void edma_clean_channel(unsigned channel); 149void edma_clear_event(unsigned channel); 150void edma_pause(unsigned channel); 151void edma_resume(unsigned channel); 152 153void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no); 154 155struct edma_rsv_info { 156 157 const s16 (*rsv_chans)[2]; 158 const s16 (*rsv_slots)[2]; 159}; 160 161/* platform_data for EDMA driver */ 162struct edma_soc_info { 163 /* 164 * Default queue is expected to be a low-priority queue. 165 * This way, long transfers on the default queue started 166 * by the codec engine will not cause audio defects. 167 */ 168 enum dma_event_q default_queue; 169 170 /* Resource reservation for other cores */ 171 struct edma_rsv_info *rsv; 172 173 s8 (*queue_priority_mapping)[2]; 174 const s16 (*xbar_chans)[2]; 175}; 176 177int edma_trigger_channel(unsigned); 178 179#endif 180