1/* -*- linux-c -*- * 2 * 3 * ALSA driver for the digigram lx6464es interface 4 * low-level interface 5 * 6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, write to 20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, 21 * Boston, MA 02111-1307, USA. 22 * 23 */ 24 25/* #define RMH_DEBUG 1 */ 26 27#include <linux/bitops.h> 28#include <linux/module.h> 29#include <linux/pci.h> 30#include <linux/delay.h> 31 32#include "lx6464es.h" 33#include "lx_core.h" 34 35/* low-level register access */ 36 37static const unsigned long dsp_port_offsets[] = { 38 0, 39 0x400, 40 0x401, 41 0x402, 42 0x403, 43 0x404, 44 0x405, 45 0x406, 46 0x407, 47 0x408, 48 0x409, 49 0x40a, 50 0x40b, 51 0x40c, 52 53 0x410, 54 0x411, 55 0x412, 56 0x413, 57 0x414, 58 0x415, 59 0x416, 60 61 0x420, 62 0x430, 63 0x431, 64 0x432, 65 0x433, 66 0x434, 67 0x440 68}; 69 70static void __iomem *lx_dsp_register(struct lx6464es *chip, int port) 71{ 72 void __iomem *base_address = chip->port_dsp_bar; 73 return base_address + dsp_port_offsets[port]*4; 74} 75 76unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port) 77{ 78 void __iomem *address = lx_dsp_register(chip, port); 79 return ioread32(address); 80} 81 82static void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data, 83 u32 len) 84{ 85 u32 __iomem *address = lx_dsp_register(chip, port); 86 int i; 87 88 /* we cannot use memcpy_fromio */ 89 for (i = 0; i != len; ++i) 90 data[i] = ioread32(address + i); 91} 92 93 94void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data) 95{ 96 void __iomem *address = lx_dsp_register(chip, port); 97 iowrite32(data, address); 98} 99 100static void lx_dsp_reg_writebuf(struct lx6464es *chip, int port, 101 const u32 *data, u32 len) 102{ 103 u32 __iomem *address = lx_dsp_register(chip, port); 104 int i; 105 106 /* we cannot use memcpy_to */ 107 for (i = 0; i != len; ++i) 108 iowrite32(data[i], address + i); 109} 110 111 112static const unsigned long plx_port_offsets[] = { 113 0x04, 114 0x40, 115 0x44, 116 0x48, 117 0x4c, 118 0x50, 119 0x54, 120 0x58, 121 0x5c, 122 0x64, 123 0x68, 124 0x6C 125}; 126 127static void __iomem *lx_plx_register(struct lx6464es *chip, int port) 128{ 129 void __iomem *base_address = chip->port_plx_remapped; 130 return base_address + plx_port_offsets[port]; 131} 132 133unsigned long lx_plx_reg_read(struct lx6464es *chip, int port) 134{ 135 void __iomem *address = lx_plx_register(chip, port); 136 return ioread32(address); 137} 138 139void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data) 140{ 141 void __iomem *address = lx_plx_register(chip, port); 142 iowrite32(data, address); 143} 144 145/* rmh */ 146 147#ifdef CONFIG_SND_DEBUG 148#define CMD_NAME(a) a 149#else 150#define CMD_NAME(a) NULL 151#endif 152 153#define Reg_CSM_MR 0x00000002 154#define Reg_CSM_MC 0x00000001 155 156struct dsp_cmd_info { 157 u32 dcCodeOp; /* Op Code of the command (usually 1st 24-bits 158 * word).*/ 159 u16 dcCmdLength; /* Command length in words of 24 bits.*/ 160 u16 dcStatusType; /* Status type: 0 for fixed length, 1 for 161 * random. */ 162 u16 dcStatusLength; /* Status length (if fixed).*/ 163 char *dcOpName; 164}; 165 166/* 167 Initialization and control data for the Microblaze interface 168 - OpCode: 169 the opcode field of the command set at the proper offset 170 - CmdLength 171 the number of command words 172 - StatusType 173 offset in the status registers: 0 means that the return value may be 174 different from 0, and must be read 175 - StatusLength 176 the number of status words (in addition to the return value) 177*/ 178 179static struct dsp_cmd_info dsp_commands[] = 180{ 181 { (CMD_00_INFO_DEBUG << OPCODE_OFFSET) , 1 /*custom*/ 182 , 1 , 0 /**/ , CMD_NAME("INFO_DEBUG") }, 183 { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET) , 1 /**/ 184 , 1 , 2 /**/ , CMD_NAME("GET_SYS_CFG") }, 185 { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET) , 1 /**/ 186 , 1 , 0 /**/ , CMD_NAME("SET_GRANULARITY") }, 187 { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET) , 1 /**/ 188 , 1 , 0 /**/ , CMD_NAME("SET_TIMER_IRQ") }, 189 { (CMD_04_GET_EVENT << OPCODE_OFFSET) , 1 /**/ 190 , 1 , 0 /*up to 10*/ , CMD_NAME("GET_EVENT") }, 191 { (CMD_05_GET_PIPES << OPCODE_OFFSET) , 1 /**/ 192 , 1 , 2 /*up to 4*/ , CMD_NAME("GET_PIPES") }, 193 { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET) , 1 /**/ 194 , 0 , 0 /**/ , CMD_NAME("ALLOCATE_PIPE") }, 195 { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET) , 1 /**/ 196 , 0 , 0 /**/ , CMD_NAME("RELEASE_PIPE") }, 197 { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET) , 1 /**/ 198 , 1 , MAX_STREAM_BUFFER , CMD_NAME("ASK_BUFFERS") }, 199 { (CMD_09_STOP_PIPE << OPCODE_OFFSET) , 1 /**/ 200 , 0 , 0 /*up to 2*/ , CMD_NAME("STOP_PIPE") }, 201 { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET) , 1 /**/ 202 , 1 , 1 /*up to 2*/ , CMD_NAME("GET_PIPE_SPL_COUNT") }, 203 { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET) , 1 /*up to 5*/ 204 , 1 , 0 /**/ , CMD_NAME("TOGGLE_PIPE_STATE") }, 205 { (CMD_0C_DEF_STREAM << OPCODE_OFFSET) , 1 /*up to 4*/ 206 , 1 , 0 /**/ , CMD_NAME("DEF_STREAM") }, 207 { (CMD_0D_SET_MUTE << OPCODE_OFFSET) , 3 /**/ 208 , 1 , 0 /**/ , CMD_NAME("SET_MUTE") }, 209 { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET) , 1/**/ 210 , 1 , 2 /**/ , CMD_NAME("GET_STREAM_SPL_COUNT") }, 211 { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET) , 3 /*up to 4*/ 212 , 0 , 1 /**/ , CMD_NAME("UPDATE_BUFFER") }, 213 { (CMD_10_GET_BUFFER << OPCODE_OFFSET) , 1 /**/ 214 , 1 , 4 /**/ , CMD_NAME("GET_BUFFER") }, 215 { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET) , 1 /**/ 216 , 1 , 1 /*up to 4*/ , CMD_NAME("CANCEL_BUFFER") }, 217 { (CMD_12_GET_PEAK << OPCODE_OFFSET) , 1 /**/ 218 , 1 , 1 /**/ , CMD_NAME("GET_PEAK") }, 219 { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET) , 1 /**/ 220 , 1 , 0 /**/ , CMD_NAME("SET_STREAM_STATE") }, 221}; 222 223static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd) 224{ 225 snd_BUG_ON(cmd >= CMD_14_INVALID); 226 227 rmh->cmd[0] = dsp_commands[cmd].dcCodeOp; 228 rmh->cmd_len = dsp_commands[cmd].dcCmdLength; 229 rmh->stat_len = dsp_commands[cmd].dcStatusLength; 230 rmh->dsp_stat = dsp_commands[cmd].dcStatusType; 231 rmh->cmd_idx = cmd; 232 memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32)); 233 234#ifdef CONFIG_SND_DEBUG 235 memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32)); 236#endif 237#ifdef RMH_DEBUG 238 rmh->cmd_idx = cmd; 239#endif 240} 241 242#ifdef RMH_DEBUG 243#define LXRMH "lx6464es rmh: " 244static void lx_message_dump(struct lx_rmh *rmh) 245{ 246 u8 idx = rmh->cmd_idx; 247 int i; 248 249 snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName); 250 251 for (i = 0; i != rmh->cmd_len; ++i) 252 snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]); 253 254 for (i = 0; i != rmh->stat_len; ++i) 255 snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]); 256 snd_printk("\n"); 257} 258#else 259static inline void lx_message_dump(struct lx_rmh *rmh) 260{} 261#endif 262 263 264 265/* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */ 266#define XILINX_TIMEOUT_MS 40 267#define XILINX_POLL_NO_SLEEP 100 268#define XILINX_POLL_ITERATIONS 150 269 270 271static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh) 272{ 273 u32 reg = ED_DSP_TIMED_OUT; 274 int dwloop; 275 276 if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) { 277 dev_err(chip->card->dev, "PIOSendMessage eReg_CSM %x\n", reg); 278 return -EBUSY; 279 } 280 281 /* write command */ 282 lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len); 283 284 /* MicoBlaze gogogo */ 285 lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC); 286 287 /* wait for device to answer */ 288 for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) { 289 if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) { 290 if (rmh->dsp_stat == 0) 291 reg = lx_dsp_reg_read(chip, eReg_CRM1); 292 else 293 reg = 0; 294 goto polling_successful; 295 } else 296 udelay(1); 297 } 298 dev_warn(chip->card->dev, "TIMEOUT lx_message_send_atomic! " 299 "polling failed\n"); 300 301polling_successful: 302 if ((reg & ERROR_VALUE) == 0) { 303 /* read response */ 304 if (rmh->stat_len) { 305 snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1)); 306 lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat, 307 rmh->stat_len); 308 } 309 } else 310 dev_err(chip->card->dev, "rmh error: %08x\n", reg); 311 312 /* clear Reg_CSM_MR */ 313 lx_dsp_reg_write(chip, eReg_CSM, 0); 314 315 switch (reg) { 316 case ED_DSP_TIMED_OUT: 317 dev_warn(chip->card->dev, "lx_message_send: dsp timeout\n"); 318 return -ETIMEDOUT; 319 320 case ED_DSP_CRASHED: 321 dev_warn(chip->card->dev, "lx_message_send: dsp crashed\n"); 322 return -EAGAIN; 323 } 324 325 lx_message_dump(rmh); 326 327 return reg; 328} 329 330 331/* low-level dsp access */ 332int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version) 333{ 334 u16 ret; 335 336 mutex_lock(&chip->msg_lock); 337 338 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); 339 ret = lx_message_send_atomic(chip, &chip->rmh); 340 341 *rdsp_version = chip->rmh.stat[1]; 342 mutex_unlock(&chip->msg_lock); 343 return ret; 344} 345 346int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq) 347{ 348 u16 ret = 0; 349 u32 freq_raw = 0; 350 u32 freq = 0; 351 u32 frequency = 0; 352 353 mutex_lock(&chip->msg_lock); 354 355 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); 356 ret = lx_message_send_atomic(chip, &chip->rmh); 357 358 if (ret == 0) { 359 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET; 360 freq = freq_raw & XES_FREQ_COUNT8_MASK; 361 362 if ((freq < XES_FREQ_COUNT8_48_MAX) || 363 (freq > XES_FREQ_COUNT8_44_MIN)) 364 frequency = 0; /* unknown */ 365 else if (freq >= XES_FREQ_COUNT8_44_MAX) 366 frequency = 44100; 367 else 368 frequency = 48000; 369 } 370 371 mutex_unlock(&chip->msg_lock); 372 373 *rfreq = frequency * chip->freq_ratio; 374 375 return ret; 376} 377 378int lx_dsp_get_mac(struct lx6464es *chip) 379{ 380 u32 macmsb, maclsb; 381 382 macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF; 383 maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF; 384 385 /* todo: endianess handling */ 386 chip->mac_address[5] = ((u8 *)(&maclsb))[0]; 387 chip->mac_address[4] = ((u8 *)(&maclsb))[1]; 388 chip->mac_address[3] = ((u8 *)(&maclsb))[2]; 389 chip->mac_address[2] = ((u8 *)(&macmsb))[0]; 390 chip->mac_address[1] = ((u8 *)(&macmsb))[1]; 391 chip->mac_address[0] = ((u8 *)(&macmsb))[2]; 392 393 return 0; 394} 395 396 397int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran) 398{ 399 int ret; 400 401 mutex_lock(&chip->msg_lock); 402 403 lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY); 404 chip->rmh.cmd[0] |= gran; 405 406 ret = lx_message_send_atomic(chip, &chip->rmh); 407 mutex_unlock(&chip->msg_lock); 408 return ret; 409} 410 411int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data) 412{ 413 int ret; 414 415 mutex_lock(&chip->msg_lock); 416 417 lx_message_init(&chip->rmh, CMD_04_GET_EVENT); 418 chip->rmh.stat_len = 9; /* we don't necessarily need the full length */ 419 420 ret = lx_message_send_atomic(chip, &chip->rmh); 421 422 if (!ret) 423 memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32)); 424 425 mutex_unlock(&chip->msg_lock); 426 return ret; 427} 428 429#define PIPE_INFO_TO_CMD(capture, pipe) \ 430 ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET) 431 432 433 434/* low-level pipe handling */ 435int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture, 436 int channels) 437{ 438 int err; 439 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 440 441 mutex_lock(&chip->msg_lock); 442 lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE); 443 444 chip->rmh.cmd[0] |= pipe_cmd; 445 chip->rmh.cmd[0] |= channels; 446 447 err = lx_message_send_atomic(chip, &chip->rmh); 448 mutex_unlock(&chip->msg_lock); 449 450 if (err != 0) 451 dev_err(chip->card->dev, "could not allocate pipe\n"); 452 453 return err; 454} 455 456int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture) 457{ 458 int err; 459 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 460 461 mutex_lock(&chip->msg_lock); 462 lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE); 463 464 chip->rmh.cmd[0] |= pipe_cmd; 465 466 err = lx_message_send_atomic(chip, &chip->rmh); 467 mutex_unlock(&chip->msg_lock); 468 469 return err; 470} 471 472int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture, 473 u32 *r_needed, u32 *r_freed, u32 *size_array) 474{ 475 int err; 476 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 477 478#ifdef CONFIG_SND_DEBUG 479 if (size_array) 480 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER); 481#endif 482 483 *r_needed = 0; 484 *r_freed = 0; 485 486 mutex_lock(&chip->msg_lock); 487 lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS); 488 489 chip->rmh.cmd[0] |= pipe_cmd; 490 491 err = lx_message_send_atomic(chip, &chip->rmh); 492 493 if (!err) { 494 int i; 495 for (i = 0; i < MAX_STREAM_BUFFER; ++i) { 496 u32 stat = chip->rmh.stat[i]; 497 if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) { 498 /* finished */ 499 *r_freed += 1; 500 if (size_array) 501 size_array[i] = stat & MASK_DATA_SIZE; 502 } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET)) 503 == 0) 504 /* free */ 505 *r_needed += 1; 506 } 507 508 dev_dbg(chip->card->dev, 509 "CMD_08_ASK_BUFFERS: needed %d, freed %d\n", 510 *r_needed, *r_freed); 511 for (i = 0; i < MAX_STREAM_BUFFER; ++i) { 512 for (i = 0; i != chip->rmh.stat_len; ++i) 513 dev_dbg(chip->card->dev, 514 " stat[%d]: %x, %x\n", i, 515 chip->rmh.stat[i], 516 chip->rmh.stat[i] & MASK_DATA_SIZE); 517 } 518 } 519 520 mutex_unlock(&chip->msg_lock); 521 return err; 522} 523 524 525int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture) 526{ 527 int err; 528 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 529 530 mutex_lock(&chip->msg_lock); 531 lx_message_init(&chip->rmh, CMD_09_STOP_PIPE); 532 533 chip->rmh.cmd[0] |= pipe_cmd; 534 535 err = lx_message_send_atomic(chip, &chip->rmh); 536 537 mutex_unlock(&chip->msg_lock); 538 return err; 539} 540 541static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture) 542{ 543 int err; 544 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 545 546 mutex_lock(&chip->msg_lock); 547 lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE); 548 549 chip->rmh.cmd[0] |= pipe_cmd; 550 551 err = lx_message_send_atomic(chip, &chip->rmh); 552 553 mutex_unlock(&chip->msg_lock); 554 return err; 555} 556 557 558int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture) 559{ 560 int err; 561 562 err = lx_pipe_wait_for_idle(chip, pipe, is_capture); 563 if (err < 0) 564 return err; 565 566 err = lx_pipe_toggle_state(chip, pipe, is_capture); 567 568 return err; 569} 570 571int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture) 572{ 573 int err = 0; 574 575 err = lx_pipe_wait_for_start(chip, pipe, is_capture); 576 if (err < 0) 577 return err; 578 579 err = lx_pipe_toggle_state(chip, pipe, is_capture); 580 581 return err; 582} 583 584 585int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture, 586 u64 *rsample_count) 587{ 588 int err; 589 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 590 591 mutex_lock(&chip->msg_lock); 592 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); 593 594 chip->rmh.cmd[0] |= pipe_cmd; 595 chip->rmh.stat_len = 2; /* need all words here! */ 596 597 err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */ 598 599 if (err != 0) 600 dev_err(chip->card->dev, 601 "could not query pipe's sample count\n"); 602 else { 603 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI) 604 << 24) /* hi part */ 605 + chip->rmh.stat[1]; /* lo part */ 606 } 607 608 mutex_unlock(&chip->msg_lock); 609 return err; 610} 611 612int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate) 613{ 614 int err; 615 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 616 617 mutex_lock(&chip->msg_lock); 618 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); 619 620 chip->rmh.cmd[0] |= pipe_cmd; 621 622 err = lx_message_send_atomic(chip, &chip->rmh); 623 624 if (err != 0) 625 dev_err(chip->card->dev, "could not query pipe's state\n"); 626 else 627 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F; 628 629 mutex_unlock(&chip->msg_lock); 630 return err; 631} 632 633static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe, 634 int is_capture, u16 state) 635{ 636 int i; 637 638 /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms: 639 * timeout 50 ms */ 640 for (i = 0; i != 50; ++i) { 641 u16 current_state; 642 int err = lx_pipe_state(chip, pipe, is_capture, ¤t_state); 643 644 if (err < 0) 645 return err; 646 647 if (current_state == state) 648 return 0; 649 650 mdelay(1); 651 } 652 653 return -ETIMEDOUT; 654} 655 656int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture) 657{ 658 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN); 659} 660 661int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture) 662{ 663 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE); 664} 665 666/* low-level stream handling */ 667int lx_stream_set_state(struct lx6464es *chip, u32 pipe, 668 int is_capture, enum stream_state_t state) 669{ 670 int err; 671 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 672 673 mutex_lock(&chip->msg_lock); 674 lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE); 675 676 chip->rmh.cmd[0] |= pipe_cmd; 677 chip->rmh.cmd[0] |= state; 678 679 err = lx_message_send_atomic(chip, &chip->rmh); 680 mutex_unlock(&chip->msg_lock); 681 682 return err; 683} 684 685int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime, 686 u32 pipe, int is_capture) 687{ 688 int err; 689 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 690 u32 channels = runtime->channels; 691 692 if (runtime->channels != channels) 693 dev_err(chip->card->dev, "channel count mismatch: %d vs %d", 694 runtime->channels, channels); 695 696 mutex_lock(&chip->msg_lock); 697 lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM); 698 699 chip->rmh.cmd[0] |= pipe_cmd; 700 701 if (runtime->sample_bits == 16) 702 /* 16 bit format */ 703 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET); 704 705 if (snd_pcm_format_little_endian(runtime->format)) 706 /* little endian/intel format */ 707 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET); 708 709 chip->rmh.cmd[0] |= channels-1; 710 711 err = lx_message_send_atomic(chip, &chip->rmh); 712 mutex_unlock(&chip->msg_lock); 713 714 return err; 715} 716 717int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture, 718 int *rstate) 719{ 720 int err; 721 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 722 723 mutex_lock(&chip->msg_lock); 724 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); 725 726 chip->rmh.cmd[0] |= pipe_cmd; 727 728 err = lx_message_send_atomic(chip, &chip->rmh); 729 730 *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE; 731 732 mutex_unlock(&chip->msg_lock); 733 return err; 734} 735 736int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture, 737 u64 *r_bytepos) 738{ 739 int err; 740 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 741 742 mutex_lock(&chip->msg_lock); 743 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); 744 745 chip->rmh.cmd[0] |= pipe_cmd; 746 747 err = lx_message_send_atomic(chip, &chip->rmh); 748 749 *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI) 750 << 32) /* hi part */ 751 + chip->rmh.stat[1]; /* lo part */ 752 753 mutex_unlock(&chip->msg_lock); 754 return err; 755} 756 757/* low-level buffer handling */ 758int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture, 759 u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi, 760 u32 *r_buffer_index) 761{ 762 int err; 763 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 764 765 mutex_lock(&chip->msg_lock); 766 lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER); 767 768 chip->rmh.cmd[0] |= pipe_cmd; 769 chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */ 770 771 /* todo: pause request, circular buffer */ 772 773 chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE; 774 chip->rmh.cmd[2] = buf_address_lo; 775 776 if (buf_address_hi) { 777 chip->rmh.cmd_len = 4; 778 chip->rmh.cmd[3] = buf_address_hi; 779 chip->rmh.cmd[0] |= BF_64BITS_ADR; 780 } 781 782 err = lx_message_send_atomic(chip, &chip->rmh); 783 784 if (err == 0) { 785 *r_buffer_index = chip->rmh.stat[0]; 786 goto done; 787 } 788 789 if (err == EB_RBUFFERS_TABLE_OVERFLOW) 790 dev_err(chip->card->dev, 791 "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n"); 792 793 if (err == EB_INVALID_STREAM) 794 dev_err(chip->card->dev, 795 "lx_buffer_give EB_INVALID_STREAM\n"); 796 797 if (err == EB_CMD_REFUSED) 798 dev_err(chip->card->dev, 799 "lx_buffer_give EB_CMD_REFUSED\n"); 800 801 done: 802 mutex_unlock(&chip->msg_lock); 803 return err; 804} 805 806int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture, 807 u32 *r_buffer_size) 808{ 809 int err; 810 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 811 812 mutex_lock(&chip->msg_lock); 813 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); 814 815 chip->rmh.cmd[0] |= pipe_cmd; 816 chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the 817 * microblaze will seek for it */ 818 819 err = lx_message_send_atomic(chip, &chip->rmh); 820 821 if (err == 0) 822 *r_buffer_size = chip->rmh.stat[0] & MASK_DATA_SIZE; 823 824 mutex_unlock(&chip->msg_lock); 825 return err; 826} 827 828int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture, 829 u32 buffer_index) 830{ 831 int err; 832 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 833 834 mutex_lock(&chip->msg_lock); 835 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); 836 837 chip->rmh.cmd[0] |= pipe_cmd; 838 chip->rmh.cmd[0] |= buffer_index; 839 840 err = lx_message_send_atomic(chip, &chip->rmh); 841 842 mutex_unlock(&chip->msg_lock); 843 return err; 844} 845 846 847/* low-level gain/peak handling 848 * 849 * \todo: can we unmute capture/playback channels independently? 850 * 851 * */ 852int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute) 853{ 854 int err; 855 /* bit set to 1: channel muted */ 856 u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU; 857 858 mutex_lock(&chip->msg_lock); 859 lx_message_init(&chip->rmh, CMD_0D_SET_MUTE); 860 861 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0); 862 863 chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32); /* hi part */ 864 chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */ 865 866 dev_dbg(chip->card->dev, 867 "mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1], 868 chip->rmh.cmd[2]); 869 870 err = lx_message_send_atomic(chip, &chip->rmh); 871 872 mutex_unlock(&chip->msg_lock); 873 return err; 874} 875 876static u32 peak_map[] = { 877 0x00000109, /* -90.308dB */ 878 0x0000083B, /* -72.247dB */ 879 0x000020C4, /* -60.205dB */ 880 0x00008273, /* -48.030dB */ 881 0x00020756, /* -36.005dB */ 882 0x00040C37, /* -30.001dB */ 883 0x00081385, /* -24.002dB */ 884 0x00101D3F, /* -18.000dB */ 885 0x0016C310, /* -15.000dB */ 886 0x002026F2, /* -12.001dB */ 887 0x002D6A86, /* -9.000dB */ 888 0x004026E6, /* -6.004dB */ 889 0x005A9DF6, /* -3.000dB */ 890 0x0065AC8B, /* -2.000dB */ 891 0x00721481, /* -1.000dB */ 892 0x007FFFFF, /* FS */ 893}; 894 895int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels, 896 u32 *r_levels) 897{ 898 int err = 0; 899 int i; 900 901 mutex_lock(&chip->msg_lock); 902 for (i = 0; i < channels; i += 4) { 903 u32 s0, s1, s2, s3; 904 905 lx_message_init(&chip->rmh, CMD_12_GET_PEAK); 906 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i); 907 908 err = lx_message_send_atomic(chip, &chip->rmh); 909 910 if (err == 0) { 911 s0 = peak_map[chip->rmh.stat[0] & 0x0F]; 912 s1 = peak_map[(chip->rmh.stat[0] >> 4) & 0xf]; 913 s2 = peak_map[(chip->rmh.stat[0] >> 8) & 0xf]; 914 s3 = peak_map[(chip->rmh.stat[0] >> 12) & 0xf]; 915 } else 916 s0 = s1 = s2 = s3 = 0; 917 918 r_levels[0] = s0; 919 r_levels[1] = s1; 920 r_levels[2] = s2; 921 r_levels[3] = s3; 922 923 r_levels += 4; 924 } 925 926 mutex_unlock(&chip->msg_lock); 927 return err; 928} 929 930/* interrupt handling */ 931#define PCX_IRQ_NONE 0 932#define IRQCS_ACTIVE_PCIDB BIT(13) 933#define IRQCS_ENABLE_PCIIRQ BIT(8) 934#define IRQCS_ENABLE_PCIDB BIT(9) 935 936static u32 lx_interrupt_test_ack(struct lx6464es *chip) 937{ 938 u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS); 939 940 /* Test if PCI Doorbell interrupt is active */ 941 if (irqcs & IRQCS_ACTIVE_PCIDB) { 942 u32 temp; 943 irqcs = PCX_IRQ_NONE; 944 945 while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) { 946 /* RAZ interrupt */ 947 irqcs |= temp; 948 lx_plx_reg_write(chip, ePLX_L2PCIDB, temp); 949 } 950 951 return irqcs; 952 } 953 return PCX_IRQ_NONE; 954} 955 956static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc, 957 int *r_async_pending, int *r_async_escmd) 958{ 959 u32 irq_async; 960 u32 irqsrc = lx_interrupt_test_ack(chip); 961 962 if (irqsrc == PCX_IRQ_NONE) 963 return 0; 964 965 *r_irqsrc = irqsrc; 966 967 irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response 968 * (set by xilinx) + EOB */ 969 970 if (irq_async & MASK_SYS_STATUS_ESA) { 971 irq_async &= ~MASK_SYS_STATUS_ESA; 972 *r_async_escmd = 1; 973 } 974 975 if (irq_async) { 976 /* dev_dbg(chip->card->dev, "interrupt: async event pending\n"); */ 977 *r_async_pending = 1; 978 } 979 980 return 1; 981} 982 983static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc, 984 int *r_freq_changed, 985 u64 *r_notified_in_pipe_mask, 986 u64 *r_notified_out_pipe_mask) 987{ 988 int err; 989 u32 stat[9]; /* answer from CMD_04_GET_EVENT */ 990 991 /* We can optimize this to not read dumb events. 992 * Answer words are in the following order: 993 * Stat[0] general status 994 * Stat[1] end of buffer OUT pF 995 * Stat[2] end of buffer OUT pf 996 * Stat[3] end of buffer IN pF 997 * Stat[4] end of buffer IN pf 998 * Stat[5] MSB underrun 999 * Stat[6] LSB underrun 1000 * Stat[7] MSB overrun 1001 * Stat[8] LSB overrun 1002 * */ 1003 1004 u64 orun_mask; 1005 u64 urun_mask; 1006 int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0; 1007 int eb_pending_in = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0; 1008 1009 *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0; 1010 1011 err = lx_dsp_read_async_events(chip, stat); 1012 if (err < 0) 1013 return err; 1014 1015 if (eb_pending_in) { 1016 *r_notified_in_pipe_mask = ((u64)stat[3] << 32) 1017 + stat[4]; 1018 dev_dbg(chip->card->dev, "interrupt: EOBI pending %llx\n", 1019 *r_notified_in_pipe_mask); 1020 } 1021 if (eb_pending_out) { 1022 *r_notified_out_pipe_mask = ((u64)stat[1] << 32) 1023 + stat[2]; 1024 dev_dbg(chip->card->dev, "interrupt: EOBO pending %llx\n", 1025 *r_notified_out_pipe_mask); 1026 } 1027 1028 orun_mask = ((u64)stat[7] << 32) + stat[8]; 1029 urun_mask = ((u64)stat[5] << 32) + stat[6]; 1030 1031 /* todo: handle xrun notification */ 1032 1033 return err; 1034} 1035 1036static int lx_interrupt_request_new_buffer(struct lx6464es *chip, 1037 struct lx_stream *lx_stream) 1038{ 1039 struct snd_pcm_substream *substream = lx_stream->stream; 1040 const unsigned int is_capture = lx_stream->is_capture; 1041 int err; 1042 1043 const u32 channels = substream->runtime->channels; 1044 const u32 bytes_per_frame = channels * 3; 1045 const u32 period_size = substream->runtime->period_size; 1046 const u32 period_bytes = period_size * bytes_per_frame; 1047 const u32 pos = lx_stream->frame_pos; 1048 const u32 next_pos = ((pos+1) == substream->runtime->periods) ? 1049 0 : pos + 1; 1050 1051 dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes; 1052 u32 buf_hi = 0; 1053 u32 buf_lo = 0; 1054 u32 buffer_index = 0; 1055 1056 u32 needed, freed; 1057 u32 size_array[MAX_STREAM_BUFFER]; 1058 1059 dev_dbg(chip->card->dev, "->lx_interrupt_request_new_buffer\n"); 1060 1061 mutex_lock(&chip->lock); 1062 1063 err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array); 1064 dev_dbg(chip->card->dev, 1065 "interrupt: needed %d, freed %d\n", needed, freed); 1066 1067 unpack_pointer(buf, &buf_lo, &buf_hi); 1068 err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi, 1069 &buffer_index); 1070 dev_dbg(chip->card->dev, 1071 "interrupt: gave buffer index %x on 0x%lx (%d bytes)\n", 1072 buffer_index, (unsigned long)buf, period_bytes); 1073 1074 lx_stream->frame_pos = next_pos; 1075 mutex_unlock(&chip->lock); 1076 1077 return err; 1078} 1079 1080irqreturn_t lx_interrupt(int irq, void *dev_id) 1081{ 1082 struct lx6464es *chip = dev_id; 1083 int async_pending, async_escmd; 1084 u32 irqsrc; 1085 bool wake_thread = false; 1086 1087 dev_dbg(chip->card->dev, 1088 "**************************************************\n"); 1089 1090 if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) { 1091 dev_dbg(chip->card->dev, "IRQ_NONE\n"); 1092 return IRQ_NONE; /* this device did not cause the interrupt */ 1093 } 1094 1095 if (irqsrc & MASK_SYS_STATUS_CMD_DONE) 1096 return IRQ_HANDLED; 1097 1098 if (irqsrc & MASK_SYS_STATUS_EOBI) 1099 dev_dbg(chip->card->dev, "interrupt: EOBI\n"); 1100 1101 if (irqsrc & MASK_SYS_STATUS_EOBO) 1102 dev_dbg(chip->card->dev, "interrupt: EOBO\n"); 1103 1104 if (irqsrc & MASK_SYS_STATUS_URUN) 1105 dev_dbg(chip->card->dev, "interrupt: URUN\n"); 1106 1107 if (irqsrc & MASK_SYS_STATUS_ORUN) 1108 dev_dbg(chip->card->dev, "interrupt: ORUN\n"); 1109 1110 if (async_pending) { 1111 wake_thread = true; 1112 chip->irqsrc = irqsrc; 1113 } 1114 1115 if (async_escmd) { 1116 /* backdoor for ethersound commands 1117 * 1118 * for now, we do not need this 1119 * 1120 * */ 1121 1122 dev_dbg(chip->card->dev, "interrupt requests escmd handling\n"); 1123 } 1124 1125 return wake_thread ? IRQ_WAKE_THREAD : IRQ_HANDLED; 1126} 1127 1128irqreturn_t lx_threaded_irq(int irq, void *dev_id) 1129{ 1130 struct lx6464es *chip = dev_id; 1131 u64 notified_in_pipe_mask = 0; 1132 u64 notified_out_pipe_mask = 0; 1133 int freq_changed; 1134 int err; 1135 1136 /* handle async events */ 1137 err = lx_interrupt_handle_async_events(chip, chip->irqsrc, 1138 &freq_changed, 1139 ¬ified_in_pipe_mask, 1140 ¬ified_out_pipe_mask); 1141 if (err) 1142 dev_err(chip->card->dev, "error handling async events\n"); 1143 1144 if (notified_in_pipe_mask) { 1145 struct lx_stream *lx_stream = &chip->capture_stream; 1146 1147 dev_dbg(chip->card->dev, 1148 "requesting audio transfer for capture\n"); 1149 err = lx_interrupt_request_new_buffer(chip, lx_stream); 1150 if (err < 0) 1151 dev_err(chip->card->dev, 1152 "cannot request new buffer for capture\n"); 1153 snd_pcm_period_elapsed(lx_stream->stream); 1154 } 1155 1156 if (notified_out_pipe_mask) { 1157 struct lx_stream *lx_stream = &chip->playback_stream; 1158 1159 dev_dbg(chip->card->dev, 1160 "requesting audio transfer for playback\n"); 1161 err = lx_interrupt_request_new_buffer(chip, lx_stream); 1162 if (err < 0) 1163 dev_err(chip->card->dev, 1164 "cannot request new buffer for playback\n"); 1165 snd_pcm_period_elapsed(lx_stream->stream); 1166 } 1167 1168 return IRQ_HANDLED; 1169} 1170 1171 1172static void lx_irq_set(struct lx6464es *chip, int enable) 1173{ 1174 u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS); 1175 1176 /* enable/disable interrupts 1177 * 1178 * Set the Doorbell and PCI interrupt enable bits 1179 * 1180 * */ 1181 if (enable) 1182 reg |= (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); 1183 else 1184 reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); 1185 lx_plx_reg_write(chip, ePLX_IRQCS, reg); 1186} 1187 1188void lx_irq_enable(struct lx6464es *chip) 1189{ 1190 dev_dbg(chip->card->dev, "->lx_irq_enable\n"); 1191 lx_irq_set(chip, 1); 1192} 1193 1194void lx_irq_disable(struct lx6464es *chip) 1195{ 1196 dev_dbg(chip->card->dev, "->lx_irq_disable\n"); 1197 lx_irq_set(chip, 0); 1198} 1199