1/*
2 * linux/sound/soc/ep93xx-i2s.c
3 * EP93xx I2S driver
4 *
5 * Copyright (C) 2010 Ryan Mallon
6 *
7 * Based on the original driver by:
8 *   Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
9 *   Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/slab.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22
23#include <sound/core.h>
24#include <sound/dmaengine_pcm.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/initval.h>
28#include <sound/soc.h>
29
30#include <mach/hardware.h>
31#include <mach/ep93xx-regs.h>
32#include <linux/platform_data/dma-ep93xx.h>
33
34#include "ep93xx-pcm.h"
35
36#define EP93XX_I2S_TXCLKCFG		0x00
37#define EP93XX_I2S_RXCLKCFG		0x04
38#define EP93XX_I2S_GLCTRL		0x0C
39
40#define EP93XX_I2S_TXLINCTRLDATA	0x28
41#define EP93XX_I2S_TXCTRL		0x2C
42#define EP93XX_I2S_TXWRDLEN		0x30
43#define EP93XX_I2S_TX0EN		0x34
44
45#define EP93XX_I2S_RXLINCTRLDATA	0x58
46#define EP93XX_I2S_RXCTRL		0x5C
47#define EP93XX_I2S_RXWRDLEN		0x60
48#define EP93XX_I2S_RX0EN		0x64
49
50#define EP93XX_I2S_WRDLEN_16		(0 << 0)
51#define EP93XX_I2S_WRDLEN_24		(1 << 0)
52#define EP93XX_I2S_WRDLEN_32		(2 << 0)
53
54#define EP93XX_I2S_LINCTRLDATA_R_JUST	(1 << 2) /* Right justify */
55
56#define EP93XX_I2S_CLKCFG_LRS		(1 << 0) /* lrclk polarity */
57#define EP93XX_I2S_CLKCFG_CKP		(1 << 1) /* Bit clock polarity */
58#define EP93XX_I2S_CLKCFG_REL		(1 << 2) /* First bit transition */
59#define EP93XX_I2S_CLKCFG_MASTER	(1 << 3) /* Master mode */
60#define EP93XX_I2S_CLKCFG_NBCG		(1 << 4) /* Not bit clock gating */
61
62struct ep93xx_i2s_info {
63	struct clk			*mclk;
64	struct clk			*sclk;
65	struct clk			*lrclk;
66	void __iomem			*regs;
67	struct snd_dmaengine_dai_dma_data dma_params_rx;
68	struct snd_dmaengine_dai_dma_data dma_params_tx;
69};
70
71static struct ep93xx_dma_data ep93xx_i2s_dma_data[] = {
72	[SNDRV_PCM_STREAM_PLAYBACK] = {
73		.name		= "i2s-pcm-out",
74		.port		= EP93XX_DMA_I2S1,
75		.direction	= DMA_MEM_TO_DEV,
76	},
77	[SNDRV_PCM_STREAM_CAPTURE] = {
78		.name		= "i2s-pcm-in",
79		.port		= EP93XX_DMA_I2S1,
80		.direction	= DMA_DEV_TO_MEM,
81	},
82};
83
84static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
85					unsigned reg, unsigned val)
86{
87	__raw_writel(val, info->regs + reg);
88}
89
90static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
91					   unsigned reg)
92{
93	return __raw_readl(info->regs + reg);
94}
95
96static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
97{
98	unsigned base_reg;
99	int i;
100
101	if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
102	    (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
103		/* Enable clocks */
104		clk_enable(info->mclk);
105		clk_enable(info->sclk);
106		clk_enable(info->lrclk);
107
108		/* Enable i2s */
109		ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
110	}
111
112	/* Enable fifos */
113	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
114		base_reg = EP93XX_I2S_TX0EN;
115	else
116		base_reg = EP93XX_I2S_RX0EN;
117	for (i = 0; i < 3; i++)
118		ep93xx_i2s_write_reg(info, base_reg + (i * 4), 1);
119}
120
121static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
122{
123	unsigned base_reg;
124	int i;
125
126	/* Disable fifos */
127	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
128		base_reg = EP93XX_I2S_TX0EN;
129	else
130		base_reg = EP93XX_I2S_RX0EN;
131	for (i = 0; i < 3; i++)
132		ep93xx_i2s_write_reg(info, base_reg + (i * 4), 0);
133
134	if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
135	    (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
136		/* Disable i2s */
137		ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
138
139		/* Disable clocks */
140		clk_disable(info->lrclk);
141		clk_disable(info->sclk);
142		clk_disable(info->mclk);
143	}
144}
145
146static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai)
147{
148	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
149
150	info->dma_params_tx.filter_data =
151		&ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK];
152	info->dma_params_rx.filter_data =
153		&ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE];
154
155	dai->playback_dma_data = &info->dma_params_tx;
156	dai->capture_dma_data = &info->dma_params_rx;
157
158	return 0;
159}
160
161static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
162				struct snd_soc_dai *dai)
163{
164	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
165
166	ep93xx_i2s_disable(info, substream->stream);
167}
168
169static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
170				  unsigned int fmt)
171{
172	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
173	unsigned int clk_cfg, lin_ctrl;
174
175	clk_cfg  = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
176	lin_ctrl = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXLINCTRLDATA);
177
178	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
179	case SND_SOC_DAIFMT_I2S:
180		clk_cfg |= EP93XX_I2S_CLKCFG_REL;
181		lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
182		break;
183
184	case SND_SOC_DAIFMT_LEFT_J:
185		clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
186		lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
187		break;
188
189	case SND_SOC_DAIFMT_RIGHT_J:
190		clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
191		lin_ctrl |= EP93XX_I2S_LINCTRLDATA_R_JUST;
192		break;
193
194	default:
195		return -EINVAL;
196	}
197
198	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
199	case SND_SOC_DAIFMT_CBS_CFS:
200		/* CPU is master */
201		clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
202		break;
203
204	case SND_SOC_DAIFMT_CBM_CFM:
205		/* Codec is master */
206		clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
207		break;
208
209	default:
210		return -EINVAL;
211	}
212
213	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
214	case SND_SOC_DAIFMT_NB_NF:
215		/* Negative bit clock, lrclk low on left word */
216		clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL);
217		break;
218
219	case SND_SOC_DAIFMT_NB_IF:
220		/* Negative bit clock, lrclk low on right word */
221		clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
222		clk_cfg |= EP93XX_I2S_CLKCFG_REL;
223		break;
224
225	case SND_SOC_DAIFMT_IB_NF:
226		/* Positive bit clock, lrclk low on left word */
227		clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
228		clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
229		break;
230
231	case SND_SOC_DAIFMT_IB_IF:
232		/* Positive bit clock, lrclk low on right word */
233		clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL;
234		break;
235	}
236
237	/* Write new register values */
238	ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
239	ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
240	ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, lin_ctrl);
241	ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, lin_ctrl);
242	return 0;
243}
244
245static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
246				struct snd_pcm_hw_params *params,
247				struct snd_soc_dai *dai)
248{
249	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
250	unsigned word_len, div, sdiv, lrdiv;
251	int err;
252
253	switch (params_format(params)) {
254	case SNDRV_PCM_FORMAT_S16_LE:
255		word_len = EP93XX_I2S_WRDLEN_16;
256		break;
257
258	case SNDRV_PCM_FORMAT_S24_LE:
259		word_len = EP93XX_I2S_WRDLEN_24;
260		break;
261
262	case SNDRV_PCM_FORMAT_S32_LE:
263		word_len = EP93XX_I2S_WRDLEN_32;
264		break;
265
266	default:
267		return -EINVAL;
268	}
269
270	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
271		ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
272	else
273		ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
274
275	/*
276	 * EP93xx I2S module can be setup so SCLK / LRCLK value can be
277	 * 32, 64, 128. MCLK / SCLK value can be 2 and 4.
278	 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK
279	 * value is 64, because our sample size is 32 bit * 2 channels.
280	 * I2S standard permits us to transmit more bits than
281	 * the codec uses.
282	 */
283	div = clk_get_rate(info->mclk) / params_rate(params);
284	sdiv = 4;
285	if (div > (256 + 512) / 2) {
286		lrdiv = 128;
287	} else {
288		lrdiv = 64;
289		if (div < (128 + 256) / 2)
290			sdiv = 2;
291	}
292
293	err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
294	if (err)
295		return err;
296
297	err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
298	if (err)
299		return err;
300
301	ep93xx_i2s_enable(info, substream->stream);
302	return 0;
303}
304
305static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
306				 unsigned int freq, int dir)
307{
308	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
309
310	if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
311		return -EINVAL;
312
313	return clk_set_rate(info->mclk, freq);
314}
315
316#ifdef CONFIG_PM
317static int ep93xx_i2s_suspend(struct snd_soc_dai *dai)
318{
319	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
320
321	if (!dai->active)
322		return 0;
323
324	ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
325	ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
326
327	return 0;
328}
329
330static int ep93xx_i2s_resume(struct snd_soc_dai *dai)
331{
332	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
333
334	if (!dai->active)
335		return 0;
336
337	ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
338	ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
339
340	return 0;
341}
342#else
343#define ep93xx_i2s_suspend	NULL
344#define ep93xx_i2s_resume	NULL
345#endif
346
347static const struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
348	.shutdown	= ep93xx_i2s_shutdown,
349	.hw_params	= ep93xx_i2s_hw_params,
350	.set_sysclk	= ep93xx_i2s_set_sysclk,
351	.set_fmt	= ep93xx_i2s_set_dai_fmt,
352};
353
354#define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
355
356static struct snd_soc_dai_driver ep93xx_i2s_dai = {
357	.symmetric_rates= 1,
358	.probe		= ep93xx_i2s_dai_probe,
359	.suspend	= ep93xx_i2s_suspend,
360	.resume		= ep93xx_i2s_resume,
361	.playback	= {
362		.channels_min	= 2,
363		.channels_max	= 2,
364		.rates		= SNDRV_PCM_RATE_8000_192000,
365		.formats	= EP93XX_I2S_FORMATS,
366	},
367	.capture	= {
368		 .channels_min	= 2,
369		 .channels_max	= 2,
370		 .rates		= SNDRV_PCM_RATE_8000_192000,
371		 .formats	= EP93XX_I2S_FORMATS,
372	},
373	.ops		= &ep93xx_i2s_dai_ops,
374};
375
376static const struct snd_soc_component_driver ep93xx_i2s_component = {
377	.name		= "ep93xx-i2s",
378};
379
380static int ep93xx_i2s_probe(struct platform_device *pdev)
381{
382	struct ep93xx_i2s_info *info;
383	struct resource *res;
384	int err;
385
386	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
387	if (!info)
388		return -ENOMEM;
389
390	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
391	info->regs = devm_ioremap_resource(&pdev->dev, res);
392	if (IS_ERR(info->regs))
393		return PTR_ERR(info->regs);
394
395	info->mclk = clk_get(&pdev->dev, "mclk");
396	if (IS_ERR(info->mclk)) {
397		err = PTR_ERR(info->mclk);
398		goto fail;
399	}
400
401	info->sclk = clk_get(&pdev->dev, "sclk");
402	if (IS_ERR(info->sclk)) {
403		err = PTR_ERR(info->sclk);
404		goto fail_put_mclk;
405	}
406
407	info->lrclk = clk_get(&pdev->dev, "lrclk");
408	if (IS_ERR(info->lrclk)) {
409		err = PTR_ERR(info->lrclk);
410		goto fail_put_sclk;
411	}
412
413	dev_set_drvdata(&pdev->dev, info);
414
415	err = snd_soc_register_component(&pdev->dev, &ep93xx_i2s_component,
416					 &ep93xx_i2s_dai, 1);
417	if (err)
418		goto fail_put_lrclk;
419
420	err = devm_ep93xx_pcm_platform_register(&pdev->dev);
421	if (err)
422		goto fail_unregister;
423
424	return 0;
425
426fail_unregister:
427	snd_soc_unregister_component(&pdev->dev);
428fail_put_lrclk:
429	clk_put(info->lrclk);
430fail_put_sclk:
431	clk_put(info->sclk);
432fail_put_mclk:
433	clk_put(info->mclk);
434fail:
435	return err;
436}
437
438static int ep93xx_i2s_remove(struct platform_device *pdev)
439{
440	struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev);
441
442	snd_soc_unregister_component(&pdev->dev);
443	clk_put(info->lrclk);
444	clk_put(info->sclk);
445	clk_put(info->mclk);
446	return 0;
447}
448
449static struct platform_driver ep93xx_i2s_driver = {
450	.probe	= ep93xx_i2s_probe,
451	.remove	= ep93xx_i2s_remove,
452	.driver	= {
453		.name	= "ep93xx-i2s",
454	},
455};
456
457module_platform_driver(ep93xx_i2s_driver);
458
459MODULE_ALIAS("platform:ep93xx-i2s");
460MODULE_AUTHOR("Ryan Mallon");
461MODULE_DESCRIPTION("EP93XX I2S driver");
462MODULE_LICENSE("GPL");
463