1/* 2 * wm8993.c -- WM8993 ALSA SoC audio driver 3 * 4 * Copyright 2009-12 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13#include <linux/module.h> 14#include <linux/moduleparam.h> 15#include <linux/init.h> 16#include <linux/delay.h> 17#include <linux/pm.h> 18#include <linux/i2c.h> 19#include <linux/regmap.h> 20#include <linux/regulator/consumer.h> 21#include <linux/spi/spi.h> 22#include <linux/slab.h> 23#include <sound/core.h> 24#include <sound/pcm.h> 25#include <sound/pcm_params.h> 26#include <sound/tlv.h> 27#include <sound/soc.h> 28#include <sound/initval.h> 29#include <sound/wm8993.h> 30 31#include "wm8993.h" 32#include "wm_hubs.h" 33 34#define WM8993_NUM_SUPPLIES 6 35static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = { 36 "DCVDD", 37 "DBVDD", 38 "AVDD1", 39 "AVDD2", 40 "CPVDD", 41 "SPKVDD", 42}; 43 44static struct reg_default wm8993_reg_defaults[] = { 45 { 1, 0x0000 }, /* R1 - Power Management (1) */ 46 { 2, 0x6000 }, /* R2 - Power Management (2) */ 47 { 3, 0x0000 }, /* R3 - Power Management (3) */ 48 { 4, 0x4050 }, /* R4 - Audio Interface (1) */ 49 { 5, 0x4000 }, /* R5 - Audio Interface (2) */ 50 { 6, 0x01C8 }, /* R6 - Clocking 1 */ 51 { 7, 0x0000 }, /* R7 - Clocking 2 */ 52 { 8, 0x0000 }, /* R8 - Audio Interface (3) */ 53 { 9, 0x0040 }, /* R9 - Audio Interface (4) */ 54 { 10, 0x0004 }, /* R10 - DAC CTRL */ 55 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */ 56 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */ 57 { 13, 0x0000 }, /* R13 - Digital Side Tone */ 58 { 14, 0x0300 }, /* R14 - ADC CTRL */ 59 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */ 60 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */ 61 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */ 62 { 19, 0x0010 }, /* R19 - GPIO1 */ 63 { 20, 0x0000 }, /* R20 - IRQ_DEBOUNCE */ 64 { 21, 0x0000 }, /* R21 - Inputs Clamp */ 65 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */ 66 { 23, 0x0800 }, /* R23 - GPIO_POL */ 67 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */ 68 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */ 69 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */ 70 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */ 71 { 28, 0x006D }, /* R28 - Left Output Volume */ 72 { 29, 0x006D }, /* R29 - Right Output Volume */ 73 { 30, 0x0066 }, /* R30 - Line Outputs Volume */ 74 { 31, 0x0020 }, /* R31 - HPOUT2 Volume */ 75 { 32, 0x0079 }, /* R32 - Left OPGA Volume */ 76 { 33, 0x0079 }, /* R33 - Right OPGA Volume */ 77 { 34, 0x0003 }, /* R34 - SPKMIXL Attenuation */ 78 { 35, 0x0003 }, /* R35 - SPKMIXR Attenuation */ 79 { 36, 0x0011 }, /* R36 - SPKOUT Mixers */ 80 { 37, 0x0100 }, /* R37 - SPKOUT Boost */ 81 { 38, 0x0079 }, /* R38 - Speaker Volume Left */ 82 { 39, 0x0079 }, /* R39 - Speaker Volume Right */ 83 { 40, 0x0000 }, /* R40 - Input Mixer2 */ 84 { 41, 0x0000 }, /* R41 - Input Mixer3 */ 85 { 42, 0x0000 }, /* R42 - Input Mixer4 */ 86 { 43, 0x0000 }, /* R43 - Input Mixer5 */ 87 { 44, 0x0000 }, /* R44 - Input Mixer6 */ 88 { 45, 0x0000 }, /* R45 - Output Mixer1 */ 89 { 46, 0x0000 }, /* R46 - Output Mixer2 */ 90 { 47, 0x0000 }, /* R47 - Output Mixer3 */ 91 { 48, 0x0000 }, /* R48 - Output Mixer4 */ 92 { 49, 0x0000 }, /* R49 - Output Mixer5 */ 93 { 50, 0x0000 }, /* R50 - Output Mixer6 */ 94 { 51, 0x0000 }, /* R51 - HPOUT2 Mixer */ 95 { 52, 0x0000 }, /* R52 - Line Mixer1 */ 96 { 53, 0x0000 }, /* R53 - Line Mixer2 */ 97 { 54, 0x0000 }, /* R54 - Speaker Mixer */ 98 { 55, 0x0000 }, /* R55 - Additional Control */ 99 { 56, 0x0000 }, /* R56 - AntiPOP1 */ 100 { 57, 0x0000 }, /* R57 - AntiPOP2 */ 101 { 58, 0x0000 }, /* R58 - MICBIAS */ 102 { 60, 0x0000 }, /* R60 - FLL Control 1 */ 103 { 61, 0x0000 }, /* R61 - FLL Control 2 */ 104 { 62, 0x0000 }, /* R62 - FLL Control 3 */ 105 { 63, 0x2EE0 }, /* R63 - FLL Control 4 */ 106 { 64, 0x0002 }, /* R64 - FLL Control 5 */ 107 { 65, 0x2287 }, /* R65 - Clocking 3 */ 108 { 66, 0x025F }, /* R66 - Clocking 4 */ 109 { 67, 0x0000 }, /* R67 - MW Slave Control */ 110 { 69, 0x0002 }, /* R69 - Bus Control 1 */ 111 { 70, 0x0000 }, /* R70 - Write Sequencer 0 */ 112 { 71, 0x0000 }, /* R71 - Write Sequencer 1 */ 113 { 72, 0x0000 }, /* R72 - Write Sequencer 2 */ 114 { 73, 0x0000 }, /* R73 - Write Sequencer 3 */ 115 { 74, 0x0000 }, /* R74 - Write Sequencer 4 */ 116 { 75, 0x0000 }, /* R75 - Write Sequencer 5 */ 117 { 76, 0x1F25 }, /* R76 - Charge Pump 1 */ 118 { 81, 0x0000 }, /* R81 - Class W 0 */ 119 { 85, 0x054A }, /* R85 - DC Servo 1 */ 120 { 87, 0x0000 }, /* R87 - DC Servo 3 */ 121 { 96, 0x0100 }, /* R96 - Analogue HP 0 */ 122 { 98, 0x0000 }, /* R98 - EQ1 */ 123 { 99, 0x000C }, /* R99 - EQ2 */ 124 { 100, 0x000C }, /* R100 - EQ3 */ 125 { 101, 0x000C }, /* R101 - EQ4 */ 126 { 102, 0x000C }, /* R102 - EQ5 */ 127 { 103, 0x000C }, /* R103 - EQ6 */ 128 { 104, 0x0FCA }, /* R104 - EQ7 */ 129 { 105, 0x0400 }, /* R105 - EQ8 */ 130 { 106, 0x00D8 }, /* R106 - EQ9 */ 131 { 107, 0x1EB5 }, /* R107 - EQ10 */ 132 { 108, 0xF145 }, /* R108 - EQ11 */ 133 { 109, 0x0B75 }, /* R109 - EQ12 */ 134 { 110, 0x01C5 }, /* R110 - EQ13 */ 135 { 111, 0x1C58 }, /* R111 - EQ14 */ 136 { 112, 0xF373 }, /* R112 - EQ15 */ 137 { 113, 0x0A54 }, /* R113 - EQ16 */ 138 { 114, 0x0558 }, /* R114 - EQ17 */ 139 { 115, 0x168E }, /* R115 - EQ18 */ 140 { 116, 0xF829 }, /* R116 - EQ19 */ 141 { 117, 0x07AD }, /* R117 - EQ20 */ 142 { 118, 0x1103 }, /* R118 - EQ21 */ 143 { 119, 0x0564 }, /* R119 - EQ22 */ 144 { 120, 0x0559 }, /* R120 - EQ23 */ 145 { 121, 0x4000 }, /* R121 - EQ24 */ 146 { 122, 0x0000 }, /* R122 - Digital Pulls */ 147 { 123, 0x0F08 }, /* R123 - DRC Control 1 */ 148 { 124, 0x0000 }, /* R124 - DRC Control 2 */ 149 { 125, 0x0080 }, /* R125 - DRC Control 3 */ 150 { 126, 0x0000 }, /* R126 - DRC Control 4 */ 151}; 152 153static struct { 154 int ratio; 155 int clk_sys_rate; 156} clk_sys_rates[] = { 157 { 64, 0 }, 158 { 128, 1 }, 159 { 192, 2 }, 160 { 256, 3 }, 161 { 384, 4 }, 162 { 512, 5 }, 163 { 768, 6 }, 164 { 1024, 7 }, 165 { 1408, 8 }, 166 { 1536, 9 }, 167}; 168 169static struct { 170 int rate; 171 int sample_rate; 172} sample_rates[] = { 173 { 8000, 0 }, 174 { 11025, 1 }, 175 { 12000, 1 }, 176 { 16000, 2 }, 177 { 22050, 3 }, 178 { 24000, 3 }, 179 { 32000, 4 }, 180 { 44100, 5 }, 181 { 48000, 5 }, 182}; 183 184static struct { 185 int div; /* *10 due to .5s */ 186 int bclk_div; 187} bclk_divs[] = { 188 { 10, 0 }, 189 { 15, 1 }, 190 { 20, 2 }, 191 { 30, 3 }, 192 { 40, 4 }, 193 { 55, 5 }, 194 { 60, 6 }, 195 { 80, 7 }, 196 { 110, 8 }, 197 { 120, 9 }, 198 { 160, 10 }, 199 { 220, 11 }, 200 { 240, 12 }, 201 { 320, 13 }, 202 { 440, 14 }, 203 { 480, 15 }, 204}; 205 206struct wm8993_priv { 207 struct wm_hubs_data hubs_data; 208 struct device *dev; 209 struct regmap *regmap; 210 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES]; 211 struct wm8993_platform_data pdata; 212 struct completion fll_lock; 213 int master; 214 int sysclk_source; 215 int tdm_slots; 216 int tdm_width; 217 unsigned int mclk_rate; 218 unsigned int sysclk_rate; 219 unsigned int fs; 220 unsigned int bclk; 221 unsigned int fll_fref; 222 unsigned int fll_fout; 223 int fll_src; 224}; 225 226static bool wm8993_volatile(struct device *dev, unsigned int reg) 227{ 228 switch (reg) { 229 case WM8993_SOFTWARE_RESET: 230 case WM8993_GPIO_CTRL_1: 231 case WM8993_DC_SERVO_0: 232 case WM8993_DC_SERVO_READBACK_0: 233 case WM8993_DC_SERVO_READBACK_1: 234 case WM8993_DC_SERVO_READBACK_2: 235 return true; 236 default: 237 return false; 238 } 239} 240 241static bool wm8993_readable(struct device *dev, unsigned int reg) 242{ 243 switch (reg) { 244 case WM8993_SOFTWARE_RESET: 245 case WM8993_POWER_MANAGEMENT_1: 246 case WM8993_POWER_MANAGEMENT_2: 247 case WM8993_POWER_MANAGEMENT_3: 248 case WM8993_AUDIO_INTERFACE_1: 249 case WM8993_AUDIO_INTERFACE_2: 250 case WM8993_CLOCKING_1: 251 case WM8993_CLOCKING_2: 252 case WM8993_AUDIO_INTERFACE_3: 253 case WM8993_AUDIO_INTERFACE_4: 254 case WM8993_DAC_CTRL: 255 case WM8993_LEFT_DAC_DIGITAL_VOLUME: 256 case WM8993_RIGHT_DAC_DIGITAL_VOLUME: 257 case WM8993_DIGITAL_SIDE_TONE: 258 case WM8993_ADC_CTRL: 259 case WM8993_LEFT_ADC_DIGITAL_VOLUME: 260 case WM8993_RIGHT_ADC_DIGITAL_VOLUME: 261 case WM8993_GPIO_CTRL_1: 262 case WM8993_GPIO1: 263 case WM8993_IRQ_DEBOUNCE: 264 case WM8993_GPIOCTRL_2: 265 case WM8993_GPIO_POL: 266 case WM8993_LEFT_LINE_INPUT_1_2_VOLUME: 267 case WM8993_LEFT_LINE_INPUT_3_4_VOLUME: 268 case WM8993_RIGHT_LINE_INPUT_1_2_VOLUME: 269 case WM8993_RIGHT_LINE_INPUT_3_4_VOLUME: 270 case WM8993_LEFT_OUTPUT_VOLUME: 271 case WM8993_RIGHT_OUTPUT_VOLUME: 272 case WM8993_LINE_OUTPUTS_VOLUME: 273 case WM8993_HPOUT2_VOLUME: 274 case WM8993_LEFT_OPGA_VOLUME: 275 case WM8993_RIGHT_OPGA_VOLUME: 276 case WM8993_SPKMIXL_ATTENUATION: 277 case WM8993_SPKMIXR_ATTENUATION: 278 case WM8993_SPKOUT_MIXERS: 279 case WM8993_SPKOUT_BOOST: 280 case WM8993_SPEAKER_VOLUME_LEFT: 281 case WM8993_SPEAKER_VOLUME_RIGHT: 282 case WM8993_INPUT_MIXER2: 283 case WM8993_INPUT_MIXER3: 284 case WM8993_INPUT_MIXER4: 285 case WM8993_INPUT_MIXER5: 286 case WM8993_INPUT_MIXER6: 287 case WM8993_OUTPUT_MIXER1: 288 case WM8993_OUTPUT_MIXER2: 289 case WM8993_OUTPUT_MIXER3: 290 case WM8993_OUTPUT_MIXER4: 291 case WM8993_OUTPUT_MIXER5: 292 case WM8993_OUTPUT_MIXER6: 293 case WM8993_HPOUT2_MIXER: 294 case WM8993_LINE_MIXER1: 295 case WM8993_LINE_MIXER2: 296 case WM8993_SPEAKER_MIXER: 297 case WM8993_ADDITIONAL_CONTROL: 298 case WM8993_ANTIPOP1: 299 case WM8993_ANTIPOP2: 300 case WM8993_MICBIAS: 301 case WM8993_FLL_CONTROL_1: 302 case WM8993_FLL_CONTROL_2: 303 case WM8993_FLL_CONTROL_3: 304 case WM8993_FLL_CONTROL_4: 305 case WM8993_FLL_CONTROL_5: 306 case WM8993_CLOCKING_3: 307 case WM8993_CLOCKING_4: 308 case WM8993_MW_SLAVE_CONTROL: 309 case WM8993_BUS_CONTROL_1: 310 case WM8993_WRITE_SEQUENCER_0: 311 case WM8993_WRITE_SEQUENCER_1: 312 case WM8993_WRITE_SEQUENCER_2: 313 case WM8993_WRITE_SEQUENCER_3: 314 case WM8993_WRITE_SEQUENCER_4: 315 case WM8993_WRITE_SEQUENCER_5: 316 case WM8993_CHARGE_PUMP_1: 317 case WM8993_CLASS_W_0: 318 case WM8993_DC_SERVO_0: 319 case WM8993_DC_SERVO_1: 320 case WM8993_DC_SERVO_3: 321 case WM8993_DC_SERVO_READBACK_0: 322 case WM8993_DC_SERVO_READBACK_1: 323 case WM8993_DC_SERVO_READBACK_2: 324 case WM8993_ANALOGUE_HP_0: 325 case WM8993_EQ1: 326 case WM8993_EQ2: 327 case WM8993_EQ3: 328 case WM8993_EQ4: 329 case WM8993_EQ5: 330 case WM8993_EQ6: 331 case WM8993_EQ7: 332 case WM8993_EQ8: 333 case WM8993_EQ9: 334 case WM8993_EQ10: 335 case WM8993_EQ11: 336 case WM8993_EQ12: 337 case WM8993_EQ13: 338 case WM8993_EQ14: 339 case WM8993_EQ15: 340 case WM8993_EQ16: 341 case WM8993_EQ17: 342 case WM8993_EQ18: 343 case WM8993_EQ19: 344 case WM8993_EQ20: 345 case WM8993_EQ21: 346 case WM8993_EQ22: 347 case WM8993_EQ23: 348 case WM8993_EQ24: 349 case WM8993_DIGITAL_PULLS: 350 case WM8993_DRC_CONTROL_1: 351 case WM8993_DRC_CONTROL_2: 352 case WM8993_DRC_CONTROL_3: 353 case WM8993_DRC_CONTROL_4: 354 return true; 355 default: 356 return false; 357 } 358} 359 360struct _fll_div { 361 u16 fll_fratio; 362 u16 fll_outdiv; 363 u16 fll_clk_ref_div; 364 u16 n; 365 u16 k; 366}; 367 368/* The size in bits of the FLL divide multiplied by 10 369 * to allow rounding later */ 370#define FIXED_FLL_SIZE ((1 << 16) * 10) 371 372static struct { 373 unsigned int min; 374 unsigned int max; 375 u16 fll_fratio; 376 int ratio; 377} fll_fratios[] = { 378 { 0, 64000, 4, 16 }, 379 { 64000, 128000, 3, 8 }, 380 { 128000, 256000, 2, 4 }, 381 { 256000, 1000000, 1, 2 }, 382 { 1000000, 13500000, 0, 1 }, 383}; 384 385static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 386 unsigned int Fout) 387{ 388 u64 Kpart; 389 unsigned int K, Ndiv, Nmod, target; 390 unsigned int div; 391 int i; 392 393 /* Fref must be <=13.5MHz */ 394 div = 1; 395 fll_div->fll_clk_ref_div = 0; 396 while ((Fref / div) > 13500000) { 397 div *= 2; 398 fll_div->fll_clk_ref_div++; 399 400 if (div > 8) { 401 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 402 Fref); 403 return -EINVAL; 404 } 405 } 406 407 pr_debug("Fref=%u Fout=%u\n", Fref, Fout); 408 409 /* Apply the division for our remaining calculations */ 410 Fref /= div; 411 412 /* Fvco should be 90-100MHz; don't check the upper bound */ 413 div = 0; 414 target = Fout * 2; 415 while (target < 90000000) { 416 div++; 417 target *= 2; 418 if (div > 7) { 419 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 420 Fout); 421 return -EINVAL; 422 } 423 } 424 fll_div->fll_outdiv = div; 425 426 pr_debug("Fvco=%dHz\n", target); 427 428 /* Find an appropriate FLL_FRATIO and factor it out of the target */ 429 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 430 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 431 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 432 target /= fll_fratios[i].ratio; 433 break; 434 } 435 } 436 if (i == ARRAY_SIZE(fll_fratios)) { 437 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 438 return -EINVAL; 439 } 440 441 /* Now, calculate N.K */ 442 Ndiv = target / Fref; 443 444 fll_div->n = Ndiv; 445 Nmod = target % Fref; 446 pr_debug("Nmod=%d\n", Nmod); 447 448 /* Calculate fractional part - scale up so we can round. */ 449 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 450 451 do_div(Kpart, Fref); 452 453 K = Kpart & 0xFFFFFFFF; 454 455 if ((K % 10) >= 5) 456 K += 5; 457 458 /* Move down to proper range now rounding is done */ 459 fll_div->k = K / 10; 460 461 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", 462 fll_div->n, fll_div->k, 463 fll_div->fll_fratio, fll_div->fll_outdiv, 464 fll_div->fll_clk_ref_div); 465 466 return 0; 467} 468 469static int _wm8993_set_fll(struct snd_soc_codec *codec, int fll_id, int source, 470 unsigned int Fref, unsigned int Fout) 471{ 472 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 473 struct i2c_client *i2c = to_i2c_client(codec->dev); 474 u16 reg1, reg4, reg5; 475 struct _fll_div fll_div; 476 unsigned int timeout; 477 int ret; 478 479 /* Any change? */ 480 if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout) 481 return 0; 482 483 /* Disable the FLL */ 484 if (Fout == 0) { 485 dev_dbg(codec->dev, "FLL disabled\n"); 486 wm8993->fll_fref = 0; 487 wm8993->fll_fout = 0; 488 489 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1); 490 reg1 &= ~WM8993_FLL_ENA; 491 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); 492 493 return 0; 494 } 495 496 ret = fll_factors(&fll_div, Fref, Fout); 497 if (ret != 0) 498 return ret; 499 500 reg5 = snd_soc_read(codec, WM8993_FLL_CONTROL_5); 501 reg5 &= ~WM8993_FLL_CLK_SRC_MASK; 502 503 switch (fll_id) { 504 case WM8993_FLL_MCLK: 505 break; 506 507 case WM8993_FLL_LRCLK: 508 reg5 |= 1; 509 break; 510 511 case WM8993_FLL_BCLK: 512 reg5 |= 2; 513 break; 514 515 default: 516 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); 517 return -EINVAL; 518 } 519 520 /* Any FLL configuration change requires that the FLL be 521 * disabled first. */ 522 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1); 523 reg1 &= ~WM8993_FLL_ENA; 524 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); 525 526 /* Apply the configuration */ 527 if (fll_div.k) 528 reg1 |= WM8993_FLL_FRAC_MASK; 529 else 530 reg1 &= ~WM8993_FLL_FRAC_MASK; 531 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); 532 533 snd_soc_write(codec, WM8993_FLL_CONTROL_2, 534 (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) | 535 (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT)); 536 snd_soc_write(codec, WM8993_FLL_CONTROL_3, fll_div.k); 537 538 reg4 = snd_soc_read(codec, WM8993_FLL_CONTROL_4); 539 reg4 &= ~WM8993_FLL_N_MASK; 540 reg4 |= fll_div.n << WM8993_FLL_N_SHIFT; 541 snd_soc_write(codec, WM8993_FLL_CONTROL_4, reg4); 542 543 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK; 544 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT; 545 snd_soc_write(codec, WM8993_FLL_CONTROL_5, reg5); 546 547 /* If we've got an interrupt wired up make sure we get it */ 548 if (i2c->irq) 549 timeout = msecs_to_jiffies(20); 550 else if (Fref < 1000000) 551 timeout = msecs_to_jiffies(3); 552 else 553 timeout = msecs_to_jiffies(1); 554 555 try_wait_for_completion(&wm8993->fll_lock); 556 557 /* Enable the FLL */ 558 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA); 559 560 timeout = wait_for_completion_timeout(&wm8993->fll_lock, timeout); 561 if (i2c->irq && !timeout) 562 dev_warn(codec->dev, "Timed out waiting for FLL\n"); 563 564 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout); 565 566 wm8993->fll_fref = Fref; 567 wm8993->fll_fout = Fout; 568 wm8993->fll_src = source; 569 570 return 0; 571} 572 573static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source, 574 unsigned int Fref, unsigned int Fout) 575{ 576 return _wm8993_set_fll(dai->codec, fll_id, source, Fref, Fout); 577} 578 579static int configure_clock(struct snd_soc_codec *codec) 580{ 581 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 582 unsigned int reg; 583 584 /* This should be done on init() for bypass paths */ 585 switch (wm8993->sysclk_source) { 586 case WM8993_SYSCLK_MCLK: 587 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate); 588 589 reg = snd_soc_read(codec, WM8993_CLOCKING_2); 590 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC); 591 if (wm8993->mclk_rate > 13500000) { 592 reg |= WM8993_MCLK_DIV; 593 wm8993->sysclk_rate = wm8993->mclk_rate / 2; 594 } else { 595 reg &= ~WM8993_MCLK_DIV; 596 wm8993->sysclk_rate = wm8993->mclk_rate; 597 } 598 snd_soc_write(codec, WM8993_CLOCKING_2, reg); 599 break; 600 601 case WM8993_SYSCLK_FLL: 602 dev_dbg(codec->dev, "Using %dHz FLL clock\n", 603 wm8993->fll_fout); 604 605 reg = snd_soc_read(codec, WM8993_CLOCKING_2); 606 reg |= WM8993_SYSCLK_SRC; 607 if (wm8993->fll_fout > 13500000) { 608 reg |= WM8993_MCLK_DIV; 609 wm8993->sysclk_rate = wm8993->fll_fout / 2; 610 } else { 611 reg &= ~WM8993_MCLK_DIV; 612 wm8993->sysclk_rate = wm8993->fll_fout; 613 } 614 snd_soc_write(codec, WM8993_CLOCKING_2, reg); 615 break; 616 617 default: 618 dev_err(codec->dev, "System clock not configured\n"); 619 return -EINVAL; 620 } 621 622 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate); 623 624 return 0; 625} 626 627static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); 628static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0); 629static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0); 630static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0); 631static const unsigned int drc_max_tlv[] = { 632 TLV_DB_RANGE_HEAD(2), 633 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0), 634 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0), 635}; 636static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0); 637static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0); 638static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 639static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 640static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 641 642static const char *dac_deemph_text[] = { 643 "None", 644 "32kHz", 645 "44.1kHz", 646 "48kHz", 647}; 648 649static SOC_ENUM_SINGLE_DECL(dac_deemph, 650 WM8993_DAC_CTRL, 4, dac_deemph_text); 651 652static const char *adc_hpf_text[] = { 653 "Hi-Fi", 654 "Voice 1", 655 "Voice 2", 656 "Voice 3", 657}; 658 659static SOC_ENUM_SINGLE_DECL(adc_hpf, 660 WM8993_ADC_CTRL, 5, adc_hpf_text); 661 662static const char *drc_path_text[] = { 663 "ADC", 664 "DAC" 665}; 666 667static SOC_ENUM_SINGLE_DECL(drc_path, 668 WM8993_DRC_CONTROL_1, 14, drc_path_text); 669 670static const char *drc_r0_text[] = { 671 "1", 672 "1/2", 673 "1/4", 674 "1/8", 675 "1/16", 676 "0", 677}; 678 679static SOC_ENUM_SINGLE_DECL(drc_r0, 680 WM8993_DRC_CONTROL_3, 8, drc_r0_text); 681 682static const char *drc_r1_text[] = { 683 "1", 684 "1/2", 685 "1/4", 686 "1/8", 687 "0", 688}; 689 690static SOC_ENUM_SINGLE_DECL(drc_r1, 691 WM8993_DRC_CONTROL_4, 13, drc_r1_text); 692 693static const char *drc_attack_text[] = { 694 "Reserved", 695 "181us", 696 "363us", 697 "726us", 698 "1.45ms", 699 "2.9ms", 700 "5.8ms", 701 "11.6ms", 702 "23.2ms", 703 "46.4ms", 704 "92.8ms", 705 "185.6ms", 706}; 707 708static SOC_ENUM_SINGLE_DECL(drc_attack, 709 WM8993_DRC_CONTROL_2, 12, drc_attack_text); 710 711static const char *drc_decay_text[] = { 712 "186ms", 713 "372ms", 714 "743ms", 715 "1.49s", 716 "2.97ms", 717 "5.94ms", 718 "11.89ms", 719 "23.78ms", 720 "47.56ms", 721}; 722 723static SOC_ENUM_SINGLE_DECL(drc_decay, 724 WM8993_DRC_CONTROL_2, 8, drc_decay_text); 725 726static const char *drc_ff_text[] = { 727 "5 samples", 728 "9 samples", 729}; 730 731static SOC_ENUM_SINGLE_DECL(drc_ff, 732 WM8993_DRC_CONTROL_3, 7, drc_ff_text); 733 734static const char *drc_qr_rate_text[] = { 735 "0.725ms", 736 "1.45ms", 737 "5.8ms", 738}; 739 740static SOC_ENUM_SINGLE_DECL(drc_qr_rate, 741 WM8993_DRC_CONTROL_3, 0, drc_qr_rate_text); 742 743static const char *drc_smooth_text[] = { 744 "Low", 745 "Medium", 746 "High", 747}; 748 749static SOC_ENUM_SINGLE_DECL(drc_smooth, 750 WM8993_DRC_CONTROL_1, 4, drc_smooth_text); 751 752static const struct snd_kcontrol_new wm8993_snd_controls[] = { 753SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE, 754 5, 9, 12, 0, sidetone_tlv), 755 756SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0), 757SOC_ENUM("DRC Path", drc_path), 758SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2, 759 2, 60, 1, drc_comp_threash), 760SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3, 761 11, 30, 1, drc_comp_amp), 762SOC_ENUM("DRC R0", drc_r0), 763SOC_ENUM("DRC R1", drc_r1), 764SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1, 765 drc_min_tlv), 766SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0, 767 drc_max_tlv), 768SOC_ENUM("DRC Attack Rate", drc_attack), 769SOC_ENUM("DRC Decay Rate", drc_decay), 770SOC_ENUM("DRC FF Delay", drc_ff), 771SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0), 772SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0), 773SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0, 774 drc_qr_tlv), 775SOC_ENUM("DRC Quick Release Rate", drc_qr_rate), 776SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0), 777SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0), 778SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth), 779SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0, 780 drc_startup_tlv), 781 782SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0), 783 784SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME, 785 WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv), 786SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0), 787SOC_ENUM("ADC High Pass Filter Mode", adc_hpf), 788 789SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME, 790 WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv), 791SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0, 792 dac_boost_tlv), 793SOC_ENUM("DAC Deemphasis", dac_deemph), 794 795SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION, 796 2, 1, 1, wm_hubs_spkmix_tlv), 797 798SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION, 799 2, 1, 1, wm_hubs_spkmix_tlv), 800}; 801 802static const struct snd_kcontrol_new wm8993_eq_controls[] = { 803SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv), 804SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv), 805SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv), 806SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv), 807SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv), 808}; 809 810static int clk_sys_event(struct snd_soc_dapm_widget *w, 811 struct snd_kcontrol *kcontrol, int event) 812{ 813 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 814 815 switch (event) { 816 case SND_SOC_DAPM_PRE_PMU: 817 return configure_clock(codec); 818 819 case SND_SOC_DAPM_POST_PMD: 820 break; 821 } 822 823 return 0; 824} 825 826static const struct snd_kcontrol_new left_speaker_mixer[] = { 827SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0), 828SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0), 829SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0), 830SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0), 831}; 832 833static const struct snd_kcontrol_new right_speaker_mixer[] = { 834SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0), 835SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0), 836SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0), 837SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0), 838}; 839 840static const char *aif_text[] = { 841 "Left", "Right" 842}; 843 844static SOC_ENUM_SINGLE_DECL(aifoutl_enum, 845 WM8993_AUDIO_INTERFACE_1, 15, aif_text); 846 847static const struct snd_kcontrol_new aifoutl_mux = 848 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); 849 850static SOC_ENUM_SINGLE_DECL(aifoutr_enum, 851 WM8993_AUDIO_INTERFACE_1, 14, aif_text); 852 853static const struct snd_kcontrol_new aifoutr_mux = 854 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); 855 856static SOC_ENUM_SINGLE_DECL(aifinl_enum, 857 WM8993_AUDIO_INTERFACE_2, 15, aif_text); 858 859static const struct snd_kcontrol_new aifinl_mux = 860 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); 861 862static SOC_ENUM_SINGLE_DECL(aifinr_enum, 863 WM8993_AUDIO_INTERFACE_2, 14, aif_text); 864 865static const struct snd_kcontrol_new aifinr_mux = 866 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); 867 868static const char *sidetone_text[] = { 869 "None", "Left", "Right" 870}; 871 872static SOC_ENUM_SINGLE_DECL(sidetonel_enum, 873 WM8993_DIGITAL_SIDE_TONE, 2, sidetone_text); 874 875static const struct snd_kcontrol_new sidetonel_mux = 876 SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum); 877 878static SOC_ENUM_SINGLE_DECL(sidetoner_enum, 879 WM8993_DIGITAL_SIDE_TONE, 0, sidetone_text); 880 881static const struct snd_kcontrol_new sidetoner_mux = 882 SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum); 883 884static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = { 885SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event, 886 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 887SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0), 888SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0), 889SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0), 890 891SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0), 892SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0), 893 894SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), 895SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), 896 897SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), 898SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), 899 900SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), 901SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), 902 903SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), 904SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), 905 906SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux), 907SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux), 908 909SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0), 910SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0), 911 912SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux), 913SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux), 914 915SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0, 916 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 917SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0, 918 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 919SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), 920}; 921 922static const struct snd_soc_dapm_route routes[] = { 923 { "MICBIAS1", NULL, "VMID" }, 924 { "MICBIAS2", NULL, "VMID" }, 925 926 { "ADCL", NULL, "CLK_SYS" }, 927 { "ADCL", NULL, "CLK_DSP" }, 928 { "ADCR", NULL, "CLK_SYS" }, 929 { "ADCR", NULL, "CLK_DSP" }, 930 931 { "AIFOUTL Mux", "Left", "ADCL" }, 932 { "AIFOUTL Mux", "Right", "ADCR" }, 933 { "AIFOUTR Mux", "Left", "ADCL" }, 934 { "AIFOUTR Mux", "Right", "ADCR" }, 935 936 { "AIFOUTL", NULL, "AIFOUTL Mux" }, 937 { "AIFOUTR", NULL, "AIFOUTR Mux" }, 938 939 { "DACL Mux", "Left", "AIFINL" }, 940 { "DACL Mux", "Right", "AIFINR" }, 941 { "DACR Mux", "Left", "AIFINL" }, 942 { "DACR Mux", "Right", "AIFINR" }, 943 944 { "DACL Sidetone", "Left", "ADCL" }, 945 { "DACL Sidetone", "Right", "ADCR" }, 946 { "DACR Sidetone", "Left", "ADCL" }, 947 { "DACR Sidetone", "Right", "ADCR" }, 948 949 { "DACL", NULL, "CLK_SYS" }, 950 { "DACL", NULL, "CLK_DSP" }, 951 { "DACL", NULL, "DACL Mux" }, 952 { "DACL", NULL, "DACL Sidetone" }, 953 { "DACR", NULL, "CLK_SYS" }, 954 { "DACR", NULL, "CLK_DSP" }, 955 { "DACR", NULL, "DACR Mux" }, 956 { "DACR", NULL, "DACR Sidetone" }, 957 958 { "Left Output Mixer", "DAC Switch", "DACL" }, 959 960 { "Right Output Mixer", "DAC Switch", "DACR" }, 961 962 { "Left Output PGA", NULL, "CLK_SYS" }, 963 964 { "Right Output PGA", NULL, "CLK_SYS" }, 965 966 { "SPKL", "DAC Switch", "DACL" }, 967 { "SPKL", NULL, "CLK_SYS" }, 968 969 { "SPKR", "DAC Switch", "DACR" }, 970 { "SPKR", NULL, "CLK_SYS" }, 971 972 { "Left Headphone Mux", "DAC", "DACL" }, 973 { "Right Headphone Mux", "DAC", "DACR" }, 974}; 975 976static int wm8993_set_bias_level(struct snd_soc_codec *codec, 977 enum snd_soc_bias_level level) 978{ 979 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 980 int ret; 981 982 wm_hubs_set_bias_level(codec, level); 983 984 switch (level) { 985 case SND_SOC_BIAS_ON: 986 case SND_SOC_BIAS_PREPARE: 987 /* VMID=2*40k */ 988 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 989 WM8993_VMID_SEL_MASK, 0x2); 990 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2, 991 WM8993_TSHUT_ENA, WM8993_TSHUT_ENA); 992 break; 993 994 case SND_SOC_BIAS_STANDBY: 995 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 996 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies), 997 wm8993->supplies); 998 if (ret != 0) 999 return ret; 1000 1001 regcache_cache_only(wm8993->regmap, false); 1002 regcache_sync(wm8993->regmap); 1003 1004 wm_hubs_vmid_ena(codec); 1005 1006 /* Bring up VMID with fast soft start */ 1007 snd_soc_update_bits(codec, WM8993_ANTIPOP2, 1008 WM8993_STARTUP_BIAS_ENA | 1009 WM8993_VMID_BUF_ENA | 1010 WM8993_VMID_RAMP_MASK | 1011 WM8993_BIAS_SRC, 1012 WM8993_STARTUP_BIAS_ENA | 1013 WM8993_VMID_BUF_ENA | 1014 WM8993_VMID_RAMP_MASK | 1015 WM8993_BIAS_SRC); 1016 1017 /* If either line output is single ended we 1018 * need the VMID buffer */ 1019 if (!wm8993->pdata.lineout1_diff || 1020 !wm8993->pdata.lineout2_diff) 1021 snd_soc_update_bits(codec, WM8993_ANTIPOP1, 1022 WM8993_LINEOUT_VMID_BUF_ENA, 1023 WM8993_LINEOUT_VMID_BUF_ENA); 1024 1025 /* VMID=2*40k */ 1026 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 1027 WM8993_VMID_SEL_MASK | 1028 WM8993_BIAS_ENA, 1029 WM8993_BIAS_ENA | 0x2); 1030 msleep(32); 1031 1032 /* Switch to normal bias */ 1033 snd_soc_update_bits(codec, WM8993_ANTIPOP2, 1034 WM8993_BIAS_SRC | 1035 WM8993_STARTUP_BIAS_ENA, 0); 1036 } 1037 1038 /* VMID=2*240k */ 1039 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 1040 WM8993_VMID_SEL_MASK, 0x4); 1041 1042 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2, 1043 WM8993_TSHUT_ENA, 0); 1044 break; 1045 1046 case SND_SOC_BIAS_OFF: 1047 snd_soc_update_bits(codec, WM8993_ANTIPOP1, 1048 WM8993_LINEOUT_VMID_BUF_ENA, 0); 1049 1050 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 1051 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA, 1052 0); 1053 1054 snd_soc_update_bits(codec, WM8993_ANTIPOP2, 1055 WM8993_STARTUP_BIAS_ENA | 1056 WM8993_VMID_BUF_ENA | 1057 WM8993_VMID_RAMP_MASK | 1058 WM8993_BIAS_SRC, 0); 1059 1060 regcache_cache_only(wm8993->regmap, true); 1061 regcache_mark_dirty(wm8993->regmap); 1062 1063 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), 1064 wm8993->supplies); 1065 break; 1066 } 1067 1068 codec->dapm.bias_level = level; 1069 1070 return 0; 1071} 1072 1073static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai, 1074 int clk_id, unsigned int freq, int dir) 1075{ 1076 struct snd_soc_codec *codec = codec_dai->codec; 1077 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1078 1079 switch (clk_id) { 1080 case WM8993_SYSCLK_MCLK: 1081 wm8993->mclk_rate = freq; 1082 case WM8993_SYSCLK_FLL: 1083 wm8993->sysclk_source = clk_id; 1084 break; 1085 1086 default: 1087 return -EINVAL; 1088 } 1089 1090 return 0; 1091} 1092 1093static int wm8993_set_dai_fmt(struct snd_soc_dai *dai, 1094 unsigned int fmt) 1095{ 1096 struct snd_soc_codec *codec = dai->codec; 1097 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1098 unsigned int aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1); 1099 unsigned int aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4); 1100 1101 aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV | 1102 WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK); 1103 aif4 &= ~WM8993_LRCLK_DIR; 1104 1105 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1106 case SND_SOC_DAIFMT_CBS_CFS: 1107 wm8993->master = 0; 1108 break; 1109 case SND_SOC_DAIFMT_CBS_CFM: 1110 aif4 |= WM8993_LRCLK_DIR; 1111 wm8993->master = 1; 1112 break; 1113 case SND_SOC_DAIFMT_CBM_CFS: 1114 aif1 |= WM8993_BCLK_DIR; 1115 wm8993->master = 1; 1116 break; 1117 case SND_SOC_DAIFMT_CBM_CFM: 1118 aif1 |= WM8993_BCLK_DIR; 1119 aif4 |= WM8993_LRCLK_DIR; 1120 wm8993->master = 1; 1121 break; 1122 default: 1123 return -EINVAL; 1124 } 1125 1126 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1127 case SND_SOC_DAIFMT_DSP_B: 1128 aif1 |= WM8993_AIF_LRCLK_INV; 1129 case SND_SOC_DAIFMT_DSP_A: 1130 aif1 |= 0x18; 1131 break; 1132 case SND_SOC_DAIFMT_I2S: 1133 aif1 |= 0x10; 1134 break; 1135 case SND_SOC_DAIFMT_RIGHT_J: 1136 break; 1137 case SND_SOC_DAIFMT_LEFT_J: 1138 aif1 |= 0x8; 1139 break; 1140 default: 1141 return -EINVAL; 1142 } 1143 1144 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1145 case SND_SOC_DAIFMT_DSP_A: 1146 case SND_SOC_DAIFMT_DSP_B: 1147 /* frame inversion not valid for DSP modes */ 1148 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1149 case SND_SOC_DAIFMT_NB_NF: 1150 break; 1151 case SND_SOC_DAIFMT_IB_NF: 1152 aif1 |= WM8993_AIF_BCLK_INV; 1153 break; 1154 default: 1155 return -EINVAL; 1156 } 1157 break; 1158 1159 case SND_SOC_DAIFMT_I2S: 1160 case SND_SOC_DAIFMT_RIGHT_J: 1161 case SND_SOC_DAIFMT_LEFT_J: 1162 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1163 case SND_SOC_DAIFMT_NB_NF: 1164 break; 1165 case SND_SOC_DAIFMT_IB_IF: 1166 aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV; 1167 break; 1168 case SND_SOC_DAIFMT_IB_NF: 1169 aif1 |= WM8993_AIF_BCLK_INV; 1170 break; 1171 case SND_SOC_DAIFMT_NB_IF: 1172 aif1 |= WM8993_AIF_LRCLK_INV; 1173 break; 1174 default: 1175 return -EINVAL; 1176 } 1177 break; 1178 default: 1179 return -EINVAL; 1180 } 1181 1182 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1); 1183 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4); 1184 1185 return 0; 1186} 1187 1188static int wm8993_hw_params(struct snd_pcm_substream *substream, 1189 struct snd_pcm_hw_params *params, 1190 struct snd_soc_dai *dai) 1191{ 1192 struct snd_soc_codec *codec = dai->codec; 1193 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1194 int ret, i, best, best_val, cur_val; 1195 unsigned int clocking1, clocking3, aif1, aif4; 1196 1197 clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1); 1198 clocking1 &= ~WM8993_BCLK_DIV_MASK; 1199 1200 clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3); 1201 clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK); 1202 1203 aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1); 1204 aif1 &= ~WM8993_AIF_WL_MASK; 1205 1206 aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4); 1207 aif4 &= ~WM8993_LRCLK_RATE_MASK; 1208 1209 /* What BCLK do we need? */ 1210 wm8993->fs = params_rate(params); 1211 wm8993->bclk = 2 * wm8993->fs; 1212 if (wm8993->tdm_slots) { 1213 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", 1214 wm8993->tdm_slots, wm8993->tdm_width); 1215 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots; 1216 } else { 1217 switch (params_width(params)) { 1218 case 16: 1219 wm8993->bclk *= 16; 1220 break; 1221 case 20: 1222 wm8993->bclk *= 20; 1223 aif1 |= 0x8; 1224 break; 1225 case 24: 1226 wm8993->bclk *= 24; 1227 aif1 |= 0x10; 1228 break; 1229 case 32: 1230 wm8993->bclk *= 32; 1231 aif1 |= 0x18; 1232 break; 1233 default: 1234 return -EINVAL; 1235 } 1236 } 1237 1238 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk); 1239 1240 ret = configure_clock(codec); 1241 if (ret != 0) 1242 return ret; 1243 1244 /* Select nearest CLK_SYS_RATE */ 1245 best = 0; 1246 best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio) 1247 - wm8993->fs); 1248 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1249 cur_val = abs((wm8993->sysclk_rate / 1250 clk_sys_rates[i].ratio) - wm8993->fs); 1251 if (cur_val < best_val) { 1252 best = i; 1253 best_val = cur_val; 1254 } 1255 } 1256 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", 1257 clk_sys_rates[best].ratio); 1258 clocking3 |= (clk_sys_rates[best].clk_sys_rate 1259 << WM8993_CLK_SYS_RATE_SHIFT); 1260 1261 /* SAMPLE_RATE */ 1262 best = 0; 1263 best_val = abs(wm8993->fs - sample_rates[0].rate); 1264 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1265 /* Closest match */ 1266 cur_val = abs(wm8993->fs - sample_rates[i].rate); 1267 if (cur_val < best_val) { 1268 best = i; 1269 best_val = cur_val; 1270 } 1271 } 1272 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", 1273 sample_rates[best].rate); 1274 clocking3 |= (sample_rates[best].sample_rate 1275 << WM8993_SAMPLE_RATE_SHIFT); 1276 1277 /* BCLK_DIV */ 1278 best = 0; 1279 best_val = INT_MAX; 1280 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1281 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div) 1282 - wm8993->bclk; 1283 if (cur_val < 0) /* Table is sorted */ 1284 break; 1285 if (cur_val < best_val) { 1286 best = i; 1287 best_val = cur_val; 1288 } 1289 } 1290 wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div; 1291 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", 1292 bclk_divs[best].div, wm8993->bclk); 1293 clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT; 1294 1295 /* LRCLK is a simple fraction of BCLK */ 1296 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs); 1297 aif4 |= wm8993->bclk / wm8993->fs; 1298 1299 snd_soc_write(codec, WM8993_CLOCKING_1, clocking1); 1300 snd_soc_write(codec, WM8993_CLOCKING_3, clocking3); 1301 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1); 1302 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4); 1303 1304 /* ReTune Mobile? */ 1305 if (wm8993->pdata.num_retune_configs) { 1306 u16 eq1 = snd_soc_read(codec, WM8993_EQ1); 1307 struct wm8993_retune_mobile_setting *s; 1308 1309 best = 0; 1310 best_val = abs(wm8993->pdata.retune_configs[0].rate 1311 - wm8993->fs); 1312 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) { 1313 cur_val = abs(wm8993->pdata.retune_configs[i].rate 1314 - wm8993->fs); 1315 if (cur_val < best_val) { 1316 best_val = cur_val; 1317 best = i; 1318 } 1319 } 1320 s = &wm8993->pdata.retune_configs[best]; 1321 1322 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n", 1323 s->name, s->rate); 1324 1325 /* Disable EQ while we reconfigure */ 1326 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0); 1327 1328 for (i = 1; i < ARRAY_SIZE(s->config); i++) 1329 snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]); 1330 1331 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1); 1332 } 1333 1334 return 0; 1335} 1336 1337static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1338{ 1339 struct snd_soc_codec *codec = codec_dai->codec; 1340 unsigned int reg; 1341 1342 reg = snd_soc_read(codec, WM8993_DAC_CTRL); 1343 1344 if (mute) 1345 reg |= WM8993_DAC_MUTE; 1346 else 1347 reg &= ~WM8993_DAC_MUTE; 1348 1349 snd_soc_write(codec, WM8993_DAC_CTRL, reg); 1350 1351 return 0; 1352} 1353 1354static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1355 unsigned int rx_mask, int slots, int slot_width) 1356{ 1357 struct snd_soc_codec *codec = dai->codec; 1358 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1359 int aif1 = 0; 1360 int aif2 = 0; 1361 1362 /* Don't need to validate anything if we're turning off TDM */ 1363 if (slots == 0) { 1364 wm8993->tdm_slots = 0; 1365 goto out; 1366 } 1367 1368 /* Note that we allow configurations we can't handle ourselves - 1369 * for example, we can generate clocks for slots 2 and up even if 1370 * we can't use those slots ourselves. 1371 */ 1372 aif1 |= WM8993_AIFADC_TDM; 1373 aif2 |= WM8993_AIFDAC_TDM; 1374 1375 switch (rx_mask) { 1376 case 3: 1377 break; 1378 case 0xc: 1379 aif1 |= WM8993_AIFADC_TDM_CHAN; 1380 break; 1381 default: 1382 return -EINVAL; 1383 } 1384 1385 1386 switch (tx_mask) { 1387 case 3: 1388 break; 1389 case 0xc: 1390 aif2 |= WM8993_AIFDAC_TDM_CHAN; 1391 break; 1392 default: 1393 return -EINVAL; 1394 } 1395 1396out: 1397 wm8993->tdm_width = slot_width; 1398 wm8993->tdm_slots = slots / 2; 1399 1400 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1, 1401 WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1); 1402 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2, 1403 WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2); 1404 1405 return 0; 1406} 1407 1408static irqreturn_t wm8993_irq(int irq, void *data) 1409{ 1410 struct wm8993_priv *wm8993 = data; 1411 int mask, val, ret; 1412 1413 ret = regmap_read(wm8993->regmap, WM8993_GPIO_CTRL_1, &val); 1414 if (ret != 0) { 1415 dev_err(wm8993->dev, "Failed to read interrupt status: %d\n", 1416 ret); 1417 return IRQ_NONE; 1418 } 1419 1420 ret = regmap_read(wm8993->regmap, WM8993_GPIOCTRL_2, &mask); 1421 if (ret != 0) { 1422 dev_err(wm8993->dev, "Failed to read interrupt mask: %d\n", 1423 ret); 1424 return IRQ_NONE; 1425 } 1426 1427 /* The IRQ pin status is visible in the register too */ 1428 val &= ~(mask | WM8993_IRQ); 1429 if (!val) 1430 return IRQ_NONE; 1431 1432 if (val & WM8993_TEMPOK_EINT) 1433 dev_crit(wm8993->dev, "Thermal warning\n"); 1434 1435 if (val & WM8993_FLL_LOCK_EINT) { 1436 dev_dbg(wm8993->dev, "FLL locked\n"); 1437 complete(&wm8993->fll_lock); 1438 } 1439 1440 ret = regmap_write(wm8993->regmap, WM8993_GPIO_CTRL_1, val); 1441 if (ret != 0) 1442 dev_err(wm8993->dev, "Failed to ack interrupt: %d\n", ret); 1443 1444 return IRQ_HANDLED; 1445} 1446 1447static const struct snd_soc_dai_ops wm8993_ops = { 1448 .set_sysclk = wm8993_set_sysclk, 1449 .set_fmt = wm8993_set_dai_fmt, 1450 .hw_params = wm8993_hw_params, 1451 .digital_mute = wm8993_digital_mute, 1452 .set_pll = wm8993_set_fll, 1453 .set_tdm_slot = wm8993_set_tdm_slot, 1454}; 1455 1456#define WM8993_RATES SNDRV_PCM_RATE_8000_48000 1457 1458#define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1459 SNDRV_PCM_FMTBIT_S20_3LE |\ 1460 SNDRV_PCM_FMTBIT_S24_LE |\ 1461 SNDRV_PCM_FMTBIT_S32_LE) 1462 1463static struct snd_soc_dai_driver wm8993_dai = { 1464 .name = "wm8993-hifi", 1465 .playback = { 1466 .stream_name = "Playback", 1467 .channels_min = 1, 1468 .channels_max = 2, 1469 .rates = WM8993_RATES, 1470 .formats = WM8993_FORMATS, 1471 .sig_bits = 24, 1472 }, 1473 .capture = { 1474 .stream_name = "Capture", 1475 .channels_min = 1, 1476 .channels_max = 2, 1477 .rates = WM8993_RATES, 1478 .formats = WM8993_FORMATS, 1479 .sig_bits = 24, 1480 }, 1481 .ops = &wm8993_ops, 1482 .symmetric_rates = 1, 1483}; 1484 1485static int wm8993_probe(struct snd_soc_codec *codec) 1486{ 1487 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1488 struct snd_soc_dapm_context *dapm = &codec->dapm; 1489 1490 wm8993->hubs_data.hp_startup_mode = 1; 1491 wm8993->hubs_data.dcs_codes_l = -2; 1492 wm8993->hubs_data.dcs_codes_r = -2; 1493 wm8993->hubs_data.series_startup = 1; 1494 1495 /* Latch volume update bits and default ZC on */ 1496 snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1497 WM8993_DAC_VU, WM8993_DAC_VU); 1498 snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1499 WM8993_ADC_VU, WM8993_ADC_VU); 1500 1501 /* Manualy manage the HPOUT sequencing for independent stereo 1502 * control. */ 1503 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0, 1504 WM8993_HPOUT1_AUTO_PU, 0); 1505 1506 /* Use automatic clock configuration */ 1507 snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0); 1508 1509 wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff, 1510 wm8993->pdata.lineout2_diff, 1511 wm8993->pdata.lineout1fb, 1512 wm8993->pdata.lineout2fb, 1513 wm8993->pdata.jd_scthr, 1514 wm8993->pdata.jd_thr, 1515 wm8993->pdata.micbias1_delay, 1516 wm8993->pdata.micbias2_delay, 1517 wm8993->pdata.micbias1_lvl, 1518 wm8993->pdata.micbias2_lvl); 1519 1520 snd_soc_add_codec_controls(codec, wm8993_snd_controls, 1521 ARRAY_SIZE(wm8993_snd_controls)); 1522 if (wm8993->pdata.num_retune_configs != 0) { 1523 dev_dbg(codec->dev, "Using ReTune Mobile\n"); 1524 } else { 1525 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n"); 1526 snd_soc_add_codec_controls(codec, wm8993_eq_controls, 1527 ARRAY_SIZE(wm8993_eq_controls)); 1528 } 1529 1530 snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets, 1531 ARRAY_SIZE(wm8993_dapm_widgets)); 1532 wm_hubs_add_analogue_controls(codec); 1533 1534 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes)); 1535 wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff, 1536 wm8993->pdata.lineout2_diff); 1537 1538 /* If the line outputs are differential then we aren't presenting 1539 * VMID as an output and can disable it. 1540 */ 1541 if (wm8993->pdata.lineout1_diff && wm8993->pdata.lineout2_diff) 1542 codec->dapm.idle_bias_off = 1; 1543 1544 return 0; 1545 1546} 1547 1548#ifdef CONFIG_PM 1549static int wm8993_suspend(struct snd_soc_codec *codec) 1550{ 1551 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1552 int fll_fout = wm8993->fll_fout; 1553 int fll_fref = wm8993->fll_fref; 1554 int ret; 1555 1556 /* Stop the FLL in an orderly fashion */ 1557 ret = _wm8993_set_fll(codec, 0, 0, 0, 0); 1558 if (ret != 0) { 1559 dev_err(codec->dev, "Failed to stop FLL\n"); 1560 return ret; 1561 } 1562 1563 wm8993->fll_fout = fll_fout; 1564 wm8993->fll_fref = fll_fref; 1565 1566 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF); 1567 1568 return 0; 1569} 1570 1571static int wm8993_resume(struct snd_soc_codec *codec) 1572{ 1573 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1574 int ret; 1575 1576 wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1577 1578 /* Restart the FLL? */ 1579 if (wm8993->fll_fout) { 1580 int fll_fout = wm8993->fll_fout; 1581 int fll_fref = wm8993->fll_fref; 1582 1583 wm8993->fll_fref = 0; 1584 wm8993->fll_fout = 0; 1585 1586 ret = _wm8993_set_fll(codec, 0, wm8993->fll_src, 1587 fll_fref, fll_fout); 1588 if (ret != 0) 1589 dev_err(codec->dev, "Failed to restart FLL\n"); 1590 } 1591 1592 return 0; 1593} 1594#else 1595#define wm8993_suspend NULL 1596#define wm8993_resume NULL 1597#endif 1598 1599/* Tune DC servo configuration */ 1600static struct reg_default wm8993_regmap_patch[] = { 1601 { 0x44, 3 }, 1602 { 0x56, 3 }, 1603 { 0x44, 0 }, 1604}; 1605 1606static const struct regmap_config wm8993_regmap = { 1607 .reg_bits = 8, 1608 .val_bits = 16, 1609 1610 .max_register = WM8993_MAX_REGISTER, 1611 .volatile_reg = wm8993_volatile, 1612 .readable_reg = wm8993_readable, 1613 1614 .cache_type = REGCACHE_RBTREE, 1615 .reg_defaults = wm8993_reg_defaults, 1616 .num_reg_defaults = ARRAY_SIZE(wm8993_reg_defaults), 1617}; 1618 1619static struct snd_soc_codec_driver soc_codec_dev_wm8993 = { 1620 .probe = wm8993_probe, 1621 .suspend = wm8993_suspend, 1622 .resume = wm8993_resume, 1623 .set_bias_level = wm8993_set_bias_level, 1624}; 1625 1626static int wm8993_i2c_probe(struct i2c_client *i2c, 1627 const struct i2c_device_id *id) 1628{ 1629 struct wm8993_priv *wm8993; 1630 unsigned int reg; 1631 int ret, i; 1632 1633 wm8993 = devm_kzalloc(&i2c->dev, sizeof(struct wm8993_priv), 1634 GFP_KERNEL); 1635 if (wm8993 == NULL) 1636 return -ENOMEM; 1637 1638 wm8993->dev = &i2c->dev; 1639 init_completion(&wm8993->fll_lock); 1640 1641 wm8993->regmap = devm_regmap_init_i2c(i2c, &wm8993_regmap); 1642 if (IS_ERR(wm8993->regmap)) { 1643 ret = PTR_ERR(wm8993->regmap); 1644 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 1645 return ret; 1646 } 1647 1648 i2c_set_clientdata(i2c, wm8993); 1649 1650 for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++) 1651 wm8993->supplies[i].supply = wm8993_supply_names[i]; 1652 1653 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8993->supplies), 1654 wm8993->supplies); 1655 if (ret != 0) { 1656 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 1657 return ret; 1658 } 1659 1660 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies), 1661 wm8993->supplies); 1662 if (ret != 0) { 1663 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 1664 return ret; 1665 } 1666 1667 ret = regmap_read(wm8993->regmap, WM8993_SOFTWARE_RESET, ®); 1668 if (ret != 0) { 1669 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret); 1670 goto err_enable; 1671 } 1672 1673 if (reg != 0x8993) { 1674 dev_err(&i2c->dev, "Invalid ID register value %x\n", reg); 1675 ret = -EINVAL; 1676 goto err_enable; 1677 } 1678 1679 ret = regmap_write(wm8993->regmap, WM8993_SOFTWARE_RESET, 0xffff); 1680 if (ret != 0) 1681 goto err_enable; 1682 1683 ret = regmap_register_patch(wm8993->regmap, wm8993_regmap_patch, 1684 ARRAY_SIZE(wm8993_regmap_patch)); 1685 if (ret != 0) 1686 dev_warn(wm8993->dev, "Failed to apply regmap patch: %d\n", 1687 ret); 1688 1689 if (i2c->irq) { 1690 /* Put GPIO1 into interrupt mode (only GPIO1 can output IRQ) */ 1691 ret = regmap_update_bits(wm8993->regmap, WM8993_GPIO1, 1692 WM8993_GPIO1_PD | 1693 WM8993_GPIO1_SEL_MASK, 7); 1694 if (ret != 0) 1695 goto err_enable; 1696 1697 ret = request_threaded_irq(i2c->irq, NULL, wm8993_irq, 1698 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1699 "wm8993", wm8993); 1700 if (ret != 0) 1701 goto err_enable; 1702 1703 } 1704 1705 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); 1706 1707 regcache_cache_only(wm8993->regmap, true); 1708 1709 ret = snd_soc_register_codec(&i2c->dev, 1710 &soc_codec_dev_wm8993, &wm8993_dai, 1); 1711 if (ret != 0) { 1712 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret); 1713 goto err_irq; 1714 } 1715 1716 return 0; 1717 1718err_irq: 1719 if (i2c->irq) 1720 free_irq(i2c->irq, wm8993); 1721err_enable: 1722 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); 1723 return ret; 1724} 1725 1726static int wm8993_i2c_remove(struct i2c_client *i2c) 1727{ 1728 struct wm8993_priv *wm8993 = i2c_get_clientdata(i2c); 1729 1730 snd_soc_unregister_codec(&i2c->dev); 1731 if (i2c->irq) 1732 free_irq(i2c->irq, wm8993); 1733 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); 1734 1735 return 0; 1736} 1737 1738static const struct i2c_device_id wm8993_i2c_id[] = { 1739 { "wm8993", 0 }, 1740 { } 1741}; 1742MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id); 1743 1744static struct i2c_driver wm8993_i2c_driver = { 1745 .driver = { 1746 .name = "wm8993", 1747 .owner = THIS_MODULE, 1748 }, 1749 .probe = wm8993_i2c_probe, 1750 .remove = wm8993_i2c_remove, 1751 .id_table = wm8993_i2c_id, 1752}; 1753 1754module_i2c_driver(wm8993_i2c_driver); 1755 1756MODULE_DESCRIPTION("ASoC WM8993 driver"); 1757MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 1758MODULE_LICENSE("GPL"); 1759