871 	u32 min_clk_period = 0;  in sunxi_nand_chip_set_timings()  local
875 	if (timings->tCLS_min > min_clk_period)  in sunxi_nand_chip_set_timings()
876 		min_clk_period = timings->tCLS_min;  in sunxi_nand_chip_set_timings()
879 	if (timings->tCLH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
880 		min_clk_period = timings->tCLH_min;  in sunxi_nand_chip_set_timings()
883 	if (timings->tCS_min > min_clk_period)  in sunxi_nand_chip_set_timings()
884 		min_clk_period = timings->tCS_min;  in sunxi_nand_chip_set_timings()
887 	if (timings->tCH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
888 		min_clk_period = timings->tCH_min;  in sunxi_nand_chip_set_timings()
891 	if (timings->tWP_min > min_clk_period)  in sunxi_nand_chip_set_timings()
892 		min_clk_period = timings->tWP_min;  in sunxi_nand_chip_set_timings()
895 	if (timings->tWH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
896 		min_clk_period = timings->tWH_min;  in sunxi_nand_chip_set_timings()
899 	if (timings->tALS_min > min_clk_period)  in sunxi_nand_chip_set_timings()
900 		min_clk_period = timings->tALS_min;  in sunxi_nand_chip_set_timings()
903 	if (timings->tDS_min > min_clk_period)  in sunxi_nand_chip_set_timings()
904 		min_clk_period = timings->tDS_min;  in sunxi_nand_chip_set_timings()
907 	if (timings->tDH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
908 		min_clk_period = timings->tDH_min;  in sunxi_nand_chip_set_timings()
911 	if (timings->tRR_min > (min_clk_period * 3))  in sunxi_nand_chip_set_timings()
912 		min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);  in sunxi_nand_chip_set_timings()
915 	if (timings->tALH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
916 		min_clk_period = timings->tALH_min;  in sunxi_nand_chip_set_timings()
919 	if (timings->tRP_min > min_clk_period)  in sunxi_nand_chip_set_timings()
920 		min_clk_period = timings->tRP_min;  in sunxi_nand_chip_set_timings()
923 	if (timings->tREH_min > min_clk_period)  in sunxi_nand_chip_set_timings()
924 		min_clk_period = timings->tREH_min;  in sunxi_nand_chip_set_timings()
927 	if (timings->tRC_min > (min_clk_period * 2))  in sunxi_nand_chip_set_timings()
928 		min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);  in sunxi_nand_chip_set_timings()
931 	if (timings->tWC_min > (min_clk_period * 2))  in sunxi_nand_chip_set_timings()
932 		min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);  in sunxi_nand_chip_set_timings()
936 					min_clk_period);  in sunxi_nand_chip_set_timings()
942 	tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;  in sunxi_nand_chip_set_timings()
948 	tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;  in sunxi_nand_chip_set_timings()
955 					min_clk_period);  in sunxi_nand_chip_set_timings()
978 	min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);  in sunxi_nand_chip_set_timings()
986 	chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;  in sunxi_nand_chip_set_timings()