Lines Matching refs:mcasp
70 struct davinci_mcasp *mcasp; member
114 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, in mcasp_set_bits() argument
117 void __iomem *reg = mcasp->base + offset; in mcasp_set_bits()
121 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, in mcasp_clr_bits() argument
124 void __iomem *reg = mcasp->base + offset; in mcasp_clr_bits()
128 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, in mcasp_mod_bits() argument
131 void __iomem *reg = mcasp->base + offset; in mcasp_mod_bits()
135 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, in mcasp_set_reg() argument
138 __raw_writel(val, mcasp->base + offset); in mcasp_set_reg()
141 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) in mcasp_get_reg() argument
143 return (u32)__raw_readl(mcasp->base + offset); in mcasp_get_reg()
146 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) in mcasp_set_ctl_reg() argument
150 mcasp_set_bits(mcasp, ctl_reg, val); in mcasp_set_ctl_reg()
155 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) in mcasp_set_ctl_reg()
159 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) in mcasp_set_ctl_reg()
163 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) in mcasp_is_synchronous() argument
165 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); in mcasp_is_synchronous()
166 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); in mcasp_is_synchronous()
171 static void mcasp_start_rx(struct davinci_mcasp *mcasp) in mcasp_start_rx() argument
173 if (mcasp->rxnumevt) { /* enable FIFO */ in mcasp_start_rx()
174 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in mcasp_start_rx()
176 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_rx()
177 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_rx()
181 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); in mcasp_start_rx()
182 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); in mcasp_start_rx()
188 if (mcasp_is_synchronous(mcasp)) { in mcasp_start_rx()
189 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); in mcasp_start_rx()
190 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); in mcasp_start_rx()
194 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); in mcasp_start_rx()
196 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); in mcasp_start_rx()
198 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); in mcasp_start_rx()
199 if (mcasp_is_synchronous(mcasp)) in mcasp_start_rx()
200 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); in mcasp_start_rx()
203 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, in mcasp_start_rx()
204 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); in mcasp_start_rx()
207 static void mcasp_start_tx(struct davinci_mcasp *mcasp) in mcasp_start_tx() argument
211 if (mcasp->txnumevt) { /* enable FIFO */ in mcasp_start_tx()
212 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in mcasp_start_tx()
214 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_tx()
215 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_tx()
219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); in mcasp_start_tx()
220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); in mcasp_start_tx()
222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); in mcasp_start_tx()
226 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && in mcasp_start_tx()
231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); in mcasp_start_tx()
233 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); in mcasp_start_tx()
236 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, in mcasp_start_tx()
237 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); in mcasp_start_tx()
240 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) in davinci_mcasp_start() argument
242 mcasp->streams++; in davinci_mcasp_start()
245 mcasp_start_tx(mcasp); in davinci_mcasp_start()
247 mcasp_start_rx(mcasp); in davinci_mcasp_start()
250 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) in mcasp_stop_rx() argument
253 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, in mcasp_stop_rx()
254 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); in mcasp_stop_rx()
260 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) in mcasp_stop_rx()
261 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); in mcasp_stop_rx()
263 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); in mcasp_stop_rx()
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); in mcasp_stop_rx()
266 if (mcasp->rxnumevt) { /* disable FIFO */ in mcasp_stop_rx()
267 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in mcasp_stop_rx()
269 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_stop_rx()
273 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) in mcasp_stop_tx() argument
278 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, in mcasp_stop_tx()
279 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); in mcasp_stop_tx()
285 if (mcasp_is_synchronous(mcasp) && mcasp->streams) in mcasp_stop_tx()
288 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); in mcasp_stop_tx()
289 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); in mcasp_stop_tx()
291 if (mcasp->txnumevt) { /* disable FIFO */ in mcasp_stop_tx()
292 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in mcasp_stop_tx()
294 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_stop_tx()
298 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) in davinci_mcasp_stop() argument
300 mcasp->streams--; in davinci_mcasp_stop()
303 mcasp_stop_tx(mcasp); in davinci_mcasp_stop()
305 mcasp_stop_rx(mcasp); in davinci_mcasp_stop()
310 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; in davinci_mcasp_tx_irq_handler() local
312 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_tx_irq_handler()
316 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); in davinci_mcasp_tx_irq_handler()
318 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); in davinci_mcasp_tx_irq_handler()
321 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_tx_irq_handler()
331 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", in davinci_mcasp_tx_irq_handler()
338 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); in davinci_mcasp_tx_irq_handler()
345 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; in davinci_mcasp_rx_irq_handler() local
347 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_rx_irq_handler()
351 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); in davinci_mcasp_rx_irq_handler()
353 dev_warn(mcasp->dev, "Receive buffer overflow\n"); in davinci_mcasp_rx_irq_handler()
356 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_rx_irq_handler()
366 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", in davinci_mcasp_rx_irq_handler()
373 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); in davinci_mcasp_rx_irq_handler()
380 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; in davinci_mcasp_common_irq_handler() local
383 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) in davinci_mcasp_common_irq_handler()
386 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) in davinci_mcasp_common_irq_handler()
395 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_set_dai_fmt() local
401 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_set_dai_fmt()
404 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
405 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
411 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
412 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
418 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
419 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
427 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
428 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
437 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), in davinci_mcasp_set_dai_fmt()
439 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), in davinci_mcasp_set_dai_fmt()
445 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
446 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
448 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
449 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
451 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); in davinci_mcasp_set_dai_fmt()
452 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); in davinci_mcasp_set_dai_fmt()
453 mcasp->bclk_master = 1; in davinci_mcasp_set_dai_fmt()
457 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
458 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
460 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
461 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
463 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); in davinci_mcasp_set_dai_fmt()
464 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); in davinci_mcasp_set_dai_fmt()
465 mcasp->bclk_master = 1; in davinci_mcasp_set_dai_fmt()
469 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
470 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
472 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
473 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
475 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); in davinci_mcasp_set_dai_fmt()
476 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); in davinci_mcasp_set_dai_fmt()
477 mcasp->bclk_master = 0; in davinci_mcasp_set_dai_fmt()
481 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
482 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
484 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
485 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
487 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, in davinci_mcasp_set_dai_fmt()
489 mcasp->bclk_master = 0; in davinci_mcasp_set_dai_fmt()
498 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
499 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
503 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
504 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
508 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
509 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
514 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
526 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); in davinci_mcasp_set_dai_fmt()
527 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); in davinci_mcasp_set_dai_fmt()
529 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); in davinci_mcasp_set_dai_fmt()
530 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); in davinci_mcasp_set_dai_fmt()
533 pm_runtime_put(mcasp->dev); in davinci_mcasp_set_dai_fmt()
540 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in __davinci_mcasp_set_clkdiv() local
542 pm_runtime_get_sync(mcasp->dev); in __davinci_mcasp_set_clkdiv()
545 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, in __davinci_mcasp_set_clkdiv()
547 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, in __davinci_mcasp_set_clkdiv()
552 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, in __davinci_mcasp_set_clkdiv()
554 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, in __davinci_mcasp_set_clkdiv()
557 mcasp->bclk_div = div; in __davinci_mcasp_set_clkdiv()
570 mcasp->slot_width = div / mcasp->tdm_slots; in __davinci_mcasp_set_clkdiv()
571 if (div % mcasp->tdm_slots) in __davinci_mcasp_set_clkdiv()
572 dev_warn(mcasp->dev, in __davinci_mcasp_set_clkdiv()
574 __func__, div, mcasp->tdm_slots); in __davinci_mcasp_set_clkdiv()
581 pm_runtime_put(mcasp->dev); in __davinci_mcasp_set_clkdiv()
594 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_set_sysclk() local
596 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_set_sysclk()
598 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); in davinci_mcasp_set_sysclk()
599 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); in davinci_mcasp_set_sysclk()
600 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); in davinci_mcasp_set_sysclk()
602 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); in davinci_mcasp_set_sysclk()
603 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); in davinci_mcasp_set_sysclk()
604 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); in davinci_mcasp_set_sysclk()
607 mcasp->sysclk_freq = freq; in davinci_mcasp_set_sysclk()
609 pm_runtime_put(mcasp->dev); in davinci_mcasp_set_sysclk()
614 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, in davinci_mcasp_ch_constraint() argument
617 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; in davinci_mcasp_ch_constraint()
619 int slots = mcasp->tdm_slots; in davinci_mcasp_ch_constraint()
622 if (mcasp->tdm_mask[stream]) in davinci_mcasp_ch_constraint()
623 slots = hweight32(mcasp->tdm_mask[stream]); in davinci_mcasp_ch_constraint()
636 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) in davinci_mcasp_set_ch_constraints() argument
640 for (i = 0; i < mcasp->num_serializer; i++) in davinci_mcasp_set_ch_constraints()
641 if (mcasp->serial_dir[i] == TX_MODE) in davinci_mcasp_set_ch_constraints()
643 else if (mcasp->serial_dir[i] == RX_MODE) in davinci_mcasp_set_ch_constraints()
646 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, in davinci_mcasp_set_ch_constraints()
651 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, in davinci_mcasp_set_ch_constraints()
663 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_set_tdm_slot() local
665 dev_dbg(mcasp->dev, in davinci_mcasp_set_tdm_slot()
670 dev_err(mcasp->dev, in davinci_mcasp_set_tdm_slot()
678 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", in davinci_mcasp_set_tdm_slot()
683 mcasp->tdm_slots = slots; in davinci_mcasp_set_tdm_slot()
684 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; in davinci_mcasp_set_tdm_slot()
685 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; in davinci_mcasp_set_tdm_slot()
686 mcasp->slot_width = slot_width; in davinci_mcasp_set_tdm_slot()
688 return davinci_mcasp_set_ch_constraints(mcasp); in davinci_mcasp_set_tdm_slot()
691 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, in davinci_config_channel_size() argument
716 if (mcasp->slot_width) { in davinci_config_channel_size()
722 slot_width = mcasp->slot_width; in davinci_config_channel_size()
729 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { in davinci_config_channel_size()
730 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), in davinci_config_channel_size()
732 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), in davinci_config_channel_size()
734 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), in davinci_config_channel_size()
736 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), in davinci_config_channel_size()
738 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); in davinci_config_channel_size()
741 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); in davinci_config_channel_size()
746 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, in mcasp_common_hw_param() argument
749 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; in mcasp_common_hw_param()
753 u8 slots = mcasp->tdm_slots; in mcasp_common_hw_param()
758 if (mcasp->version < MCASP_VERSION_3) in mcasp_common_hw_param()
759 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); in mcasp_common_hw_param()
762 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); in mcasp_common_hw_param()
765 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); in mcasp_common_hw_param()
766 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); in mcasp_common_hw_param()
768 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); in mcasp_common_hw_param()
769 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); in mcasp_common_hw_param()
772 for (i = 0; i < mcasp->num_serializer; i++) { in mcasp_common_hw_param()
773 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in mcasp_common_hw_param()
774 mcasp->serial_dir[i]); in mcasp_common_hw_param()
775 if (mcasp->serial_dir[i] == TX_MODE && in mcasp_common_hw_param()
777 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); in mcasp_common_hw_param()
778 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in mcasp_common_hw_param()
781 } else if (mcasp->serial_dir[i] == RX_MODE && in mcasp_common_hw_param()
783 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); in mcasp_common_hw_param()
786 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in mcasp_common_hw_param()
793 numevt = mcasp->txnumevt; in mcasp_common_hw_param()
794 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in mcasp_common_hw_param()
797 numevt = mcasp->rxnumevt; in mcasp_common_hw_param()
798 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in mcasp_common_hw_param()
802 dev_warn(mcasp->dev, "stream has more channels (%d) than are " in mcasp_common_hw_param()
826 dev_err(mcasp->dev, "Invalid combination of period words and " in mcasp_common_hw_param()
844 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); in mcasp_common_hw_param()
845 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); in mcasp_common_hw_param()
855 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, in mcasp_i2s_hw_param() argument
864 total_slots = mcasp->tdm_slots; in mcasp_i2s_hw_param()
872 if (mcasp->tdm_mask[stream]) { in mcasp_i2s_hw_param()
873 active_slots = hweight32(mcasp->tdm_mask[stream]); in mcasp_i2s_hw_param()
879 if ((1 << i) & mcasp->tdm_mask[stream]) { in mcasp_i2s_hw_param()
896 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); in mcasp_i2s_hw_param()
898 if (!mcasp->dat_port) in mcasp_i2s_hw_param()
902 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); in mcasp_i2s_hw_param()
903 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); in mcasp_i2s_hw_param()
904 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, in mcasp_i2s_hw_param()
907 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); in mcasp_i2s_hw_param()
908 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); in mcasp_i2s_hw_param()
909 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, in mcasp_i2s_hw_param()
916 if (mcasp_is_synchronous(mcasp) && !mcasp->channels) in mcasp_i2s_hw_param()
917 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, in mcasp_i2s_hw_param()
925 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, in mcasp_dit_hw_param() argument
933 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); in mcasp_dit_hw_param()
936 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); in mcasp_dit_hw_param()
939 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); in mcasp_dit_hw_param()
942 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); in mcasp_dit_hw_param()
944 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); in mcasp_dit_hw_param()
947 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); in mcasp_dit_hw_param()
950 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); in mcasp_dit_hw_param()
989 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); in mcasp_dit_hw_param()
990 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); in mcasp_dit_hw_param()
995 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, in davinci_mcasp_calc_clk_div() argument
999 int div = mcasp->sysclk_freq / bclk_freq; in davinci_mcasp_calc_clk_div()
1000 int rem = mcasp->sysclk_freq % bclk_freq; in davinci_mcasp_calc_clk_div()
1004 ((mcasp->sysclk_freq / div) - bclk_freq) > in davinci_mcasp_calc_clk_div()
1005 (bclk_freq - (mcasp->sysclk_freq / (div+1)))) { in davinci_mcasp_calc_clk_div()
1023 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_hw_params() local
1033 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { in davinci_mcasp_hw_params()
1034 int slots = mcasp->tdm_slots; in davinci_mcasp_hw_params()
1039 if (mcasp->slot_width) in davinci_mcasp_hw_params()
1040 sbits = mcasp->slot_width; in davinci_mcasp_hw_params()
1042 div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*slots, in davinci_mcasp_hw_params()
1045 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", in davinci_mcasp_hw_params()
1051 ret = mcasp_common_hw_param(mcasp, substream->stream, in davinci_mcasp_hw_params()
1056 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in davinci_mcasp_hw_params()
1057 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); in davinci_mcasp_hw_params()
1059 ret = mcasp_i2s_hw_param(mcasp, substream->stream, in davinci_mcasp_hw_params()
1096 davinci_config_channel_size(mcasp, word_length); in davinci_mcasp_hw_params()
1098 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) in davinci_mcasp_hw_params()
1099 mcasp->channels = channels; in davinci_mcasp_hw_params()
1107 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_trigger() local
1114 davinci_mcasp_start(mcasp, substream->stream); in davinci_mcasp_trigger()
1119 davinci_mcasp_stop(mcasp, substream->stream); in davinci_mcasp_trigger()
1143 int slots = rd->mcasp->tdm_slots; in davinci_mcasp_hw_rule_rate()
1147 if (rd->mcasp->slot_width) in davinci_mcasp_hw_rule_rate()
1148 sbits = rd->mcasp->slot_width; in davinci_mcasp_hw_rule_rate()
1159 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm); in davinci_mcasp_hw_rule_rate()
1170 dev_dbg(rd->mcasp->dev, in davinci_mcasp_hw_rule_rate()
1185 int slots = rd->mcasp->tdm_slots; in davinci_mcasp_hw_rule_format()
1195 if (rd->mcasp->slot_width) in davinci_mcasp_hw_rule_format()
1196 sbits = rd->mcasp->slot_width; in davinci_mcasp_hw_rule_format()
1198 davinci_mcasp_calc_clk_div(rd->mcasp, sbits*slots*rate, in davinci_mcasp_hw_rule_format()
1206 dev_dbg(rd->mcasp->dev, in davinci_mcasp_hw_rule_format()
1216 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_startup() local
1218 &mcasp->ruledata[substream->stream]; in davinci_mcasp_startup()
1221 int tdm_slots = mcasp->tdm_slots; in davinci_mcasp_startup()
1223 if (mcasp->tdm_mask[substream->stream]) in davinci_mcasp_startup()
1224 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); in davinci_mcasp_startup()
1226 mcasp->substreams[substream->stream] = substream; in davinci_mcasp_startup()
1228 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in davinci_mcasp_startup()
1240 for (i = 0; i < mcasp->num_serializer; i++) { in davinci_mcasp_startup()
1241 if (mcasp->serial_dir[i] == dir) in davinci_mcasp_startup()
1253 if (mcasp->channels && mcasp->channels < max_channels) in davinci_mcasp_startup()
1254 max_channels = mcasp->channels; in davinci_mcasp_startup()
1268 &mcasp->chconstr[substream->stream]); in davinci_mcasp_startup()
1270 if (mcasp->slot_width) in davinci_mcasp_startup()
1273 8, mcasp->slot_width); in davinci_mcasp_startup()
1279 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { in davinci_mcasp_startup()
1282 ruledata->mcasp = mcasp; in davinci_mcasp_startup()
1306 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_shutdown() local
1308 mcasp->substreams[substream->stream] = NULL; in davinci_mcasp_shutdown()
1310 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in davinci_mcasp_shutdown()
1314 mcasp->channels = 0; in davinci_mcasp_shutdown()
1330 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_dai_probe() local
1332 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_dai_probe()
1333 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_dai_probe()
1341 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_suspend() local
1342 struct davinci_mcasp_context *context = &mcasp->context; in davinci_mcasp_suspend()
1346 context->pm_state = pm_runtime_active(mcasp->dev); in davinci_mcasp_suspend()
1348 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_suspend()
1351 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); in davinci_mcasp_suspend()
1353 if (mcasp->txnumevt) { in davinci_mcasp_suspend()
1354 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in davinci_mcasp_suspend()
1355 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); in davinci_mcasp_suspend()
1357 if (mcasp->rxnumevt) { in davinci_mcasp_suspend()
1358 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in davinci_mcasp_suspend()
1359 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); in davinci_mcasp_suspend()
1362 for (i = 0; i < mcasp->num_serializer; i++) in davinci_mcasp_suspend()
1363 context->xrsr_regs[i] = mcasp_get_reg(mcasp, in davinci_mcasp_suspend()
1366 pm_runtime_put_sync(mcasp->dev); in davinci_mcasp_suspend()
1373 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_resume() local
1374 struct davinci_mcasp_context *context = &mcasp->context; in davinci_mcasp_resume()
1378 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_resume()
1381 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); in davinci_mcasp_resume()
1383 if (mcasp->txnumevt) { in davinci_mcasp_resume()
1384 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in davinci_mcasp_resume()
1385 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); in davinci_mcasp_resume()
1387 if (mcasp->rxnumevt) { in davinci_mcasp_resume()
1388 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in davinci_mcasp_resume()
1389 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); in davinci_mcasp_resume()
1392 for (i = 0; i < mcasp->num_serializer; i++) in davinci_mcasp_resume()
1393 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in davinci_mcasp_resume()
1397 pm_runtime_put_sync(mcasp->dev); in davinci_mcasp_resume()
1662 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) in davinci_mcasp_get_dma_type() argument
1668 if (!mcasp->dev->of_node) in davinci_mcasp_get_dma_type()
1671 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; in davinci_mcasp_get_dma_type()
1672 chan = dma_request_slave_channel_reason(mcasp->dev, tmp); in davinci_mcasp_get_dma_type()
1675 dev_err(mcasp->dev, in davinci_mcasp_get_dma_type()
1686 dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); in davinci_mcasp_get_dma_type()
1692 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); in davinci_mcasp_get_dma_type()
1704 struct davinci_mcasp *mcasp; in davinci_mcasp_probe() local
1715 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), in davinci_mcasp_probe()
1717 if (!mcasp) in davinci_mcasp_probe()
1728 dev_warn(mcasp->dev, in davinci_mcasp_probe()
1737 mcasp->base = devm_ioremap_resource(&pdev->dev, mem); in davinci_mcasp_probe()
1738 if (IS_ERR(mcasp->base)) in davinci_mcasp_probe()
1739 return PTR_ERR(mcasp->base); in davinci_mcasp_probe()
1743 mcasp->op_mode = pdata->op_mode; in davinci_mcasp_probe()
1745 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { in davinci_mcasp_probe()
1749 mcasp->tdm_slots = 2; in davinci_mcasp_probe()
1753 mcasp->tdm_slots = 32; in davinci_mcasp_probe()
1755 mcasp->tdm_slots = pdata->tdm_slots; in davinci_mcasp_probe()
1759 mcasp->num_serializer = pdata->num_serializer; in davinci_mcasp_probe()
1761 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev, in davinci_mcasp_probe()
1762 sizeof(u32) * mcasp->num_serializer, in davinci_mcasp_probe()
1765 mcasp->serial_dir = pdata->serial_dir; in davinci_mcasp_probe()
1766 mcasp->version = pdata->version; in davinci_mcasp_probe()
1767 mcasp->txnumevt = pdata->txnumevt; in davinci_mcasp_probe()
1768 mcasp->rxnumevt = pdata->rxnumevt; in davinci_mcasp_probe()
1770 mcasp->dev = &pdev->dev; in davinci_mcasp_probe()
1779 irq_name, mcasp); in davinci_mcasp_probe()
1785 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; in davinci_mcasp_probe()
1786 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; in davinci_mcasp_probe()
1795 IRQF_ONESHOT, irq_name, mcasp); in davinci_mcasp_probe()
1801 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; in davinci_mcasp_probe()
1810 IRQF_ONESHOT, irq_name, mcasp); in davinci_mcasp_probe()
1816 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; in davinci_mcasp_probe()
1821 mcasp->dat_port = true; in davinci_mcasp_probe()
1823 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_probe()
1829 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_probe()
1843 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { in davinci_mcasp_probe()
1844 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_probe()
1850 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_probe()
1864 if (mcasp->version < MCASP_VERSION_3) { in davinci_mcasp_probe()
1865 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; in davinci_mcasp_probe()
1867 mcasp->dat_port = true; in davinci_mcasp_probe()
1869 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; in davinci_mcasp_probe()
1879 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = in davinci_mcasp_probe()
1880 devm_kzalloc(mcasp->dev, sizeof(unsigned int) * in davinci_mcasp_probe()
1881 (32 + mcasp->num_serializer - 2), in davinci_mcasp_probe()
1884 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = in davinci_mcasp_probe()
1885 devm_kzalloc(mcasp->dev, sizeof(unsigned int) * in davinci_mcasp_probe()
1886 (32 + mcasp->num_serializer - 2), in davinci_mcasp_probe()
1889 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || in davinci_mcasp_probe()
1890 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) in davinci_mcasp_probe()
1893 ret = davinci_mcasp_set_ch_constraints(mcasp); in davinci_mcasp_probe()
1897 dev_set_drvdata(&pdev->dev, mcasp); in davinci_mcasp_probe()
1908 ret = davinci_mcasp_get_dma_type(mcasp); in davinci_mcasp_probe()