1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_data/davinci_asp.h>
30 #include <linux/math64.h>
31
32 #include <sound/asoundef.h>
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/pcm_params.h>
36 #include <sound/initval.h>
37 #include <sound/soc.h>
38 #include <sound/dmaengine_pcm.h>
39 #include <sound/omap-pcm.h>
40
41 #include "edma-pcm.h"
42 #include "davinci-mcasp.h"
43
44 #define MCASP_MAX_AFIFO_DEPTH 64
45
46 static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
53 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
55 DAVINCI_MCASP_PDIR_REG,
56 DAVINCI_MCASP_RXMASK_REG,
57 DAVINCI_MCASP_TXMASK_REG,
58 DAVINCI_MCASP_RXTDM_REG,
59 DAVINCI_MCASP_TXTDM_REG,
60 };
61
62 struct davinci_mcasp_context {
63 u32 config_regs[ARRAY_SIZE(context_regs)];
64 u32 afifo_regs[2]; /* for read/write fifo control registers */
65 u32 *xrsr_regs; /* for serializer configuration */
66 bool pm_state;
67 };
68
69 struct davinci_mcasp_ruledata {
70 struct davinci_mcasp *mcasp;
71 int serializers;
72 };
73
74 struct davinci_mcasp {
75 struct snd_dmaengine_dai_dma_data dma_data[2];
76 void __iomem *base;
77 u32 fifo_base;
78 struct device *dev;
79 struct snd_pcm_substream *substreams[2];
80
81 /* McASP specific data */
82 int tdm_slots;
83 u32 tdm_mask[2];
84 int slot_width;
85 u8 op_mode;
86 u8 num_serializer;
87 u8 *serial_dir;
88 u8 version;
89 u8 bclk_div;
90 int streams;
91 u32 irq_request[2];
92 int dma_request[2];
93
94 int sysclk_freq;
95 bool bclk_master;
96
97 /* McASP FIFO related */
98 u8 txnumevt;
99 u8 rxnumevt;
100
101 bool dat_port;
102
103 /* Used for comstraint setting on the second stream */
104 u32 channels;
105
106 #ifdef CONFIG_PM_SLEEP
107 struct davinci_mcasp_context context;
108 #endif
109
110 struct davinci_mcasp_ruledata ruledata[2];
111 struct snd_pcm_hw_constraint_list chconstr[2];
112 };
113
mcasp_set_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)114 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
115 u32 val)
116 {
117 void __iomem *reg = mcasp->base + offset;
118 __raw_writel(__raw_readl(reg) | val, reg);
119 }
120
mcasp_clr_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)121 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
122 u32 val)
123 {
124 void __iomem *reg = mcasp->base + offset;
125 __raw_writel((__raw_readl(reg) & ~(val)), reg);
126 }
127
mcasp_mod_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val,u32 mask)128 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
129 u32 val, u32 mask)
130 {
131 void __iomem *reg = mcasp->base + offset;
132 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
133 }
134
mcasp_set_reg(struct davinci_mcasp * mcasp,u32 offset,u32 val)135 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
136 u32 val)
137 {
138 __raw_writel(val, mcasp->base + offset);
139 }
140
mcasp_get_reg(struct davinci_mcasp * mcasp,u32 offset)141 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
142 {
143 return (u32)__raw_readl(mcasp->base + offset);
144 }
145
mcasp_set_ctl_reg(struct davinci_mcasp * mcasp,u32 ctl_reg,u32 val)146 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
147 {
148 int i = 0;
149
150 mcasp_set_bits(mcasp, ctl_reg, val);
151
152 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
153 /* loop count is to avoid the lock-up */
154 for (i = 0; i < 1000; i++) {
155 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
156 break;
157 }
158
159 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
160 printk(KERN_ERR "GBLCTL write error\n");
161 }
162
mcasp_is_synchronous(struct davinci_mcasp * mcasp)163 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
164 {
165 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
166 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
167
168 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
169 }
170
mcasp_start_rx(struct davinci_mcasp * mcasp)171 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
172 {
173 if (mcasp->rxnumevt) { /* enable FIFO */
174 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
175
176 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
177 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
178 }
179
180 /* Start clocks */
181 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
182 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
183 /*
184 * When ASYNC == 0 the transmit and receive sections operate
185 * synchronously from the transmit clock and frame sync. We need to make
186 * sure that the TX signlas are enabled when starting reception.
187 */
188 if (mcasp_is_synchronous(mcasp)) {
189 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
190 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
191 }
192
193 /* Activate serializer(s) */
194 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
195 /* Release RX state machine */
196 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
197 /* Release Frame Sync generator */
198 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
199 if (mcasp_is_synchronous(mcasp))
200 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
201
202 /* enable receive IRQs */
203 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
204 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
205 }
206
mcasp_start_tx(struct davinci_mcasp * mcasp)207 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
208 {
209 u32 cnt;
210
211 if (mcasp->txnumevt) { /* enable FIFO */
212 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
213
214 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
215 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
216 }
217
218 /* Start clocks */
219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
221 /* Activate serializer(s) */
222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
223
224 /* wait for XDATA to be cleared */
225 cnt = 0;
226 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
227 (cnt < 100000))
228 cnt++;
229
230 /* Release TX state machine */
231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
232 /* Release Frame Sync generator */
233 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
234
235 /* enable transmit IRQs */
236 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
237 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
238 }
239
davinci_mcasp_start(struct davinci_mcasp * mcasp,int stream)240 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
241 {
242 mcasp->streams++;
243
244 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
245 mcasp_start_tx(mcasp);
246 else
247 mcasp_start_rx(mcasp);
248 }
249
mcasp_stop_rx(struct davinci_mcasp * mcasp)250 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
251 {
252 /* disable IRQ sources */
253 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
254 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
255
256 /*
257 * In synchronous mode stop the TX clocks if no other stream is
258 * running
259 */
260 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
261 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
262
263 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
265
266 if (mcasp->rxnumevt) { /* disable FIFO */
267 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
268
269 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
270 }
271 }
272
mcasp_stop_tx(struct davinci_mcasp * mcasp)273 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
274 {
275 u32 val = 0;
276
277 /* disable IRQ sources */
278 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
279 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
280
281 /*
282 * In synchronous mode keep TX clocks running if the capture stream is
283 * still running.
284 */
285 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
286 val = TXHCLKRST | TXCLKRST | TXFSRST;
287
288 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
289 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
290
291 if (mcasp->txnumevt) { /* disable FIFO */
292 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
293
294 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
295 }
296 }
297
davinci_mcasp_stop(struct davinci_mcasp * mcasp,int stream)298 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
299 {
300 mcasp->streams--;
301
302 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
303 mcasp_stop_tx(mcasp);
304 else
305 mcasp_stop_rx(mcasp);
306 }
307
davinci_mcasp_tx_irq_handler(int irq,void * data)308 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
309 {
310 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
311 struct snd_pcm_substream *substream;
312 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
313 u32 handled_mask = 0;
314 u32 stat;
315
316 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
317 if (stat & XUNDRN & irq_mask) {
318 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
319 handled_mask |= XUNDRN;
320
321 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
322 if (substream) {
323 snd_pcm_stream_lock_irq(substream);
324 if (snd_pcm_running(substream))
325 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
326 snd_pcm_stream_unlock_irq(substream);
327 }
328 }
329
330 if (!handled_mask)
331 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
332 stat);
333
334 if (stat & XRERR)
335 handled_mask |= XRERR;
336
337 /* Ack the handled event only */
338 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
339
340 return IRQ_RETVAL(handled_mask);
341 }
342
davinci_mcasp_rx_irq_handler(int irq,void * data)343 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
344 {
345 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
346 struct snd_pcm_substream *substream;
347 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
348 u32 handled_mask = 0;
349 u32 stat;
350
351 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
352 if (stat & ROVRN & irq_mask) {
353 dev_warn(mcasp->dev, "Receive buffer overflow\n");
354 handled_mask |= ROVRN;
355
356 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
357 if (substream) {
358 snd_pcm_stream_lock_irq(substream);
359 if (snd_pcm_running(substream))
360 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
361 snd_pcm_stream_unlock_irq(substream);
362 }
363 }
364
365 if (!handled_mask)
366 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
367 stat);
368
369 if (stat & XRERR)
370 handled_mask |= XRERR;
371
372 /* Ack the handled event only */
373 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
374
375 return IRQ_RETVAL(handled_mask);
376 }
377
davinci_mcasp_common_irq_handler(int irq,void * data)378 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
379 {
380 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
381 irqreturn_t ret = IRQ_NONE;
382
383 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
384 ret = davinci_mcasp_tx_irq_handler(irq, data);
385
386 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
387 ret |= davinci_mcasp_rx_irq_handler(irq, data);
388
389 return ret;
390 }
391
davinci_mcasp_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)392 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
393 unsigned int fmt)
394 {
395 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
396 int ret = 0;
397 u32 data_delay;
398 bool fs_pol_rising;
399 bool inv_fs = false;
400
401 pm_runtime_get_sync(mcasp->dev);
402 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
403 case SND_SOC_DAIFMT_DSP_A:
404 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
405 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
406 /* 1st data bit occur one ACLK cycle after the frame sync */
407 data_delay = 1;
408 break;
409 case SND_SOC_DAIFMT_DSP_B:
410 case SND_SOC_DAIFMT_AC97:
411 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
412 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
413 /* No delay after FS */
414 data_delay = 0;
415 break;
416 case SND_SOC_DAIFMT_I2S:
417 /* configure a full-word SYNC pulse (LRCLK) */
418 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
419 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
420 /* 1st data bit occur one ACLK cycle after the frame sync */
421 data_delay = 1;
422 /* FS need to be inverted */
423 inv_fs = true;
424 break;
425 case SND_SOC_DAIFMT_LEFT_J:
426 /* configure a full-word SYNC pulse (LRCLK) */
427 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
428 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
429 /* No delay after FS */
430 data_delay = 0;
431 break;
432 default:
433 ret = -EINVAL;
434 goto out;
435 }
436
437 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
438 FSXDLY(3));
439 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
440 FSRDLY(3));
441
442 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
443 case SND_SOC_DAIFMT_CBS_CFS:
444 /* codec is clock and frame slave */
445 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
446 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
447
448 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
449 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
450
451 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
452 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
453 mcasp->bclk_master = 1;
454 break;
455 case SND_SOC_DAIFMT_CBS_CFM:
456 /* codec is clock slave and frame master */
457 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
458 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
459
460 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
461 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
462
463 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
464 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
465 mcasp->bclk_master = 1;
466 break;
467 case SND_SOC_DAIFMT_CBM_CFS:
468 /* codec is clock master and frame slave */
469 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
470 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
471
472 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
473 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
474
475 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
476 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
477 mcasp->bclk_master = 0;
478 break;
479 case SND_SOC_DAIFMT_CBM_CFM:
480 /* codec is clock and frame master */
481 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
482 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
483
484 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
485 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
486
487 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
488 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
489 mcasp->bclk_master = 0;
490 break;
491 default:
492 ret = -EINVAL;
493 goto out;
494 }
495
496 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
497 case SND_SOC_DAIFMT_IB_NF:
498 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
499 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
500 fs_pol_rising = true;
501 break;
502 case SND_SOC_DAIFMT_NB_IF:
503 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
504 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
505 fs_pol_rising = false;
506 break;
507 case SND_SOC_DAIFMT_IB_IF:
508 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
509 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
510 fs_pol_rising = false;
511 break;
512 case SND_SOC_DAIFMT_NB_NF:
513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
514 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
515 fs_pol_rising = true;
516 break;
517 default:
518 ret = -EINVAL;
519 goto out;
520 }
521
522 if (inv_fs)
523 fs_pol_rising = !fs_pol_rising;
524
525 if (fs_pol_rising) {
526 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
527 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
528 } else {
529 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
530 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
531 }
532 out:
533 pm_runtime_put(mcasp->dev);
534 return ret;
535 }
536
__davinci_mcasp_set_clkdiv(struct snd_soc_dai * dai,int div_id,int div,bool explicit)537 static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
538 int div, bool explicit)
539 {
540 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
541
542 pm_runtime_get_sync(mcasp->dev);
543 switch (div_id) {
544 case 0: /* MCLK divider */
545 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
546 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
547 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
548 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
549 break;
550
551 case 1: /* BCLK divider */
552 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
553 ACLKXDIV(div - 1), ACLKXDIV_MASK);
554 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
555 ACLKRDIV(div - 1), ACLKRDIV_MASK);
556 if (explicit)
557 mcasp->bclk_div = div;
558 break;
559
560 case 2: /*
561 * BCLK/LRCLK ratio descries how many bit-clock cycles
562 * fit into one frame. The clock ratio is given for a
563 * full period of data (for I2S format both left and
564 * right channels), so it has to be divided by number
565 * of tdm-slots (for I2S - divided by 2).
566 * Instead of storing this ratio, we calculate a new
567 * tdm_slot width by dividing the the ratio by the
568 * number of configured tdm slots.
569 */
570 mcasp->slot_width = div / mcasp->tdm_slots;
571 if (div % mcasp->tdm_slots)
572 dev_warn(mcasp->dev,
573 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
574 __func__, div, mcasp->tdm_slots);
575 break;
576
577 default:
578 return -EINVAL;
579 }
580
581 pm_runtime_put(mcasp->dev);
582 return 0;
583 }
584
davinci_mcasp_set_clkdiv(struct snd_soc_dai * dai,int div_id,int div)585 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
586 int div)
587 {
588 return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
589 }
590
davinci_mcasp_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)591 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
592 unsigned int freq, int dir)
593 {
594 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
595
596 pm_runtime_get_sync(mcasp->dev);
597 if (dir == SND_SOC_CLOCK_OUT) {
598 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
599 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
600 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
601 } else {
602 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
603 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
604 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
605 }
606
607 mcasp->sysclk_freq = freq;
608
609 pm_runtime_put(mcasp->dev);
610 return 0;
611 }
612
613 /* All serializers must have equal number of channels */
davinci_mcasp_ch_constraint(struct davinci_mcasp * mcasp,int stream,int serializers)614 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
615 int serializers)
616 {
617 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
618 unsigned int *list = (unsigned int *) cl->list;
619 int slots = mcasp->tdm_slots;
620 int i, count = 0;
621
622 if (mcasp->tdm_mask[stream])
623 slots = hweight32(mcasp->tdm_mask[stream]);
624
625 for (i = 2; i <= slots; i++)
626 list[count++] = i;
627
628 for (i = 2; i <= serializers; i++)
629 list[count++] = i*slots;
630
631 cl->count = count;
632
633 return 0;
634 }
635
davinci_mcasp_set_ch_constraints(struct davinci_mcasp * mcasp)636 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
637 {
638 int rx_serializers = 0, tx_serializers = 0, ret, i;
639
640 for (i = 0; i < mcasp->num_serializer; i++)
641 if (mcasp->serial_dir[i] == TX_MODE)
642 tx_serializers++;
643 else if (mcasp->serial_dir[i] == RX_MODE)
644 rx_serializers++;
645
646 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
647 tx_serializers);
648 if (ret)
649 return ret;
650
651 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
652 rx_serializers);
653
654 return ret;
655 }
656
657
davinci_mcasp_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)658 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
659 unsigned int tx_mask,
660 unsigned int rx_mask,
661 int slots, int slot_width)
662 {
663 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
664
665 dev_dbg(mcasp->dev,
666 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
667 __func__, tx_mask, rx_mask, slots, slot_width);
668
669 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
670 dev_err(mcasp->dev,
671 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
672 tx_mask, rx_mask, slots);
673 return -EINVAL;
674 }
675
676 if (slot_width &&
677 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
678 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
679 __func__, slot_width);
680 return -EINVAL;
681 }
682
683 mcasp->tdm_slots = slots;
684 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
685 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
686 mcasp->slot_width = slot_width;
687
688 return davinci_mcasp_set_ch_constraints(mcasp);
689 }
690
davinci_config_channel_size(struct davinci_mcasp * mcasp,int sample_width)691 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
692 int sample_width)
693 {
694 u32 fmt;
695 u32 tx_rotate = (sample_width / 4) & 0x7;
696 u32 mask = (1ULL << sample_width) - 1;
697 u32 slot_width = sample_width;
698
699 /*
700 * For captured data we should not rotate, inversion and masking is
701 * enoguh to get the data to the right position:
702 * Format data from bus after reverse (XRBUF)
703 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
704 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
705 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
706 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
707 */
708 u32 rx_rotate = 0;
709
710 /*
711 * Setting the tdm slot width either with set_clkdiv() or
712 * set_tdm_slot() allows us to for example send 32 bits per
713 * channel to the codec, while only 16 of them carry audio
714 * payload.
715 */
716 if (mcasp->slot_width) {
717 /*
718 * When we have more bclk then it is needed for the
719 * data, we need to use the rotation to move the
720 * received samples to have correct alignment.
721 */
722 slot_width = mcasp->slot_width;
723 rx_rotate = (slot_width - sample_width) / 4;
724 }
725
726 /* mapping of the XSSZ bit-field as described in the datasheet */
727 fmt = (slot_width >> 1) - 1;
728
729 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
730 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
731 RXSSZ(0x0F));
732 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
733 TXSSZ(0x0F));
734 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
735 TXROT(7));
736 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
737 RXROT(7));
738 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
739 }
740
741 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
742
743 return 0;
744 }
745
mcasp_common_hw_param(struct davinci_mcasp * mcasp,int stream,int period_words,int channels)746 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
747 int period_words, int channels)
748 {
749 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
750 int i;
751 u8 tx_ser = 0;
752 u8 rx_ser = 0;
753 u8 slots = mcasp->tdm_slots;
754 u8 max_active_serializers = (channels + slots - 1) / slots;
755 int active_serializers, numevt;
756 u32 reg;
757 /* Default configuration */
758 if (mcasp->version < MCASP_VERSION_3)
759 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
760
761 /* All PINS as McASP */
762 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
763
764 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
765 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
766 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
767 } else {
768 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
769 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
770 }
771
772 for (i = 0; i < mcasp->num_serializer; i++) {
773 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
774 mcasp->serial_dir[i]);
775 if (mcasp->serial_dir[i] == TX_MODE &&
776 tx_ser < max_active_serializers) {
777 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
778 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
779 DISMOD_LOW, DISMOD_MASK);
780 tx_ser++;
781 } else if (mcasp->serial_dir[i] == RX_MODE &&
782 rx_ser < max_active_serializers) {
783 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
784 rx_ser++;
785 } else {
786 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
787 SRMOD_INACTIVE, SRMOD_MASK);
788 }
789 }
790
791 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
792 active_serializers = tx_ser;
793 numevt = mcasp->txnumevt;
794 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
795 } else {
796 active_serializers = rx_ser;
797 numevt = mcasp->rxnumevt;
798 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
799 }
800
801 if (active_serializers < max_active_serializers) {
802 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
803 "enabled in mcasp (%d)\n", channels,
804 active_serializers * slots);
805 return -EINVAL;
806 }
807
808 /* AFIFO is not in use */
809 if (!numevt) {
810 /* Configure the burst size for platform drivers */
811 if (active_serializers > 1) {
812 /*
813 * If more than one serializers are in use we have one
814 * DMA request to provide data for all serializers.
815 * For example if three serializers are enabled the DMA
816 * need to transfer three words per DMA request.
817 */
818 dma_data->maxburst = active_serializers;
819 } else {
820 dma_data->maxburst = 0;
821 }
822 return 0;
823 }
824
825 if (period_words % active_serializers) {
826 dev_err(mcasp->dev, "Invalid combination of period words and "
827 "active serializers: %d, %d\n", period_words,
828 active_serializers);
829 return -EINVAL;
830 }
831
832 /*
833 * Calculate the optimal AFIFO depth for platform side:
834 * The number of words for numevt need to be in steps of active
835 * serializers.
836 */
837 numevt = (numevt / active_serializers) * active_serializers;
838
839 while (period_words % numevt && numevt > 0)
840 numevt -= active_serializers;
841 if (numevt <= 0)
842 numevt = active_serializers;
843
844 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
845 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
846
847 /* Configure the burst size for platform drivers */
848 if (numevt == 1)
849 numevt = 0;
850 dma_data->maxburst = numevt;
851
852 return 0;
853 }
854
mcasp_i2s_hw_param(struct davinci_mcasp * mcasp,int stream,int channels)855 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
856 int channels)
857 {
858 int i, active_slots;
859 int total_slots;
860 int active_serializers;
861 u32 mask = 0;
862 u32 busel = 0;
863
864 total_slots = mcasp->tdm_slots;
865
866 /*
867 * If more than one serializer is needed, then use them with
868 * all the specified tdm_slots. Otherwise, one serializer can
869 * cope with the transaction using just as many slots as there
870 * are channels in the stream.
871 */
872 if (mcasp->tdm_mask[stream]) {
873 active_slots = hweight32(mcasp->tdm_mask[stream]);
874 active_serializers = (channels + active_slots - 1) /
875 active_slots;
876 if (active_serializers == 1) {
877 active_slots = channels;
878 for (i = 0; i < total_slots; i++) {
879 if ((1 << i) & mcasp->tdm_mask[stream]) {
880 mask |= (1 << i);
881 if (--active_slots <= 0)
882 break;
883 }
884 }
885 }
886 } else {
887 active_serializers = (channels + total_slots - 1) / total_slots;
888 if (active_serializers == 1)
889 active_slots = channels;
890 else
891 active_slots = total_slots;
892
893 for (i = 0; i < active_slots; i++)
894 mask |= (1 << i);
895 }
896 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
897
898 if (!mcasp->dat_port)
899 busel = TXSEL;
900
901 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
902 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
903 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
904 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
905 FSXMOD(total_slots), FSXMOD(0x1FF));
906 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
907 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
908 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
909 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
910 FSRMOD(total_slots), FSRMOD(0x1FF));
911 /*
912 * If McASP is set to be TX/RX synchronous and the playback is
913 * not running already we need to configure the TX slots in
914 * order to have correct FSX on the bus
915 */
916 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
917 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
918 FSXMOD(total_slots), FSXMOD(0x1FF));
919 }
920
921 return 0;
922 }
923
924 /* S/PDIF */
mcasp_dit_hw_param(struct davinci_mcasp * mcasp,unsigned int rate)925 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
926 unsigned int rate)
927 {
928 u32 cs_value = 0;
929 u8 *cs_bytes = (u8*) &cs_value;
930
931 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
932 and LSB first */
933 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
934
935 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
936 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
937
938 /* Set the TX tdm : for all the slots */
939 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
940
941 /* Set the TX clock controls : div = 1 and internal */
942 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
943
944 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
945
946 /* Only 44100 and 48000 are valid, both have the same setting */
947 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
948
949 /* Enable the DIT */
950 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
951
952 /* Set S/PDIF channel status bits */
953 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
954 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
955
956 switch (rate) {
957 case 22050:
958 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
959 break;
960 case 24000:
961 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
962 break;
963 case 32000:
964 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
965 break;
966 case 44100:
967 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
968 break;
969 case 48000:
970 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
971 break;
972 case 88200:
973 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
974 break;
975 case 96000:
976 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
977 break;
978 case 176400:
979 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
980 break;
981 case 192000:
982 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
983 break;
984 default:
985 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
986 return -EINVAL;
987 }
988
989 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
990 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
991
992 return 0;
993 }
994
davinci_mcasp_calc_clk_div(struct davinci_mcasp * mcasp,unsigned int bclk_freq,int * error_ppm)995 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
996 unsigned int bclk_freq,
997 int *error_ppm)
998 {
999 int div = mcasp->sysclk_freq / bclk_freq;
1000 int rem = mcasp->sysclk_freq % bclk_freq;
1001
1002 if (rem != 0) {
1003 if (div == 0 ||
1004 ((mcasp->sysclk_freq / div) - bclk_freq) >
1005 (bclk_freq - (mcasp->sysclk_freq / (div+1)))) {
1006 div++;
1007 rem = rem - bclk_freq;
1008 }
1009 }
1010 if (error_ppm)
1011 *error_ppm =
1012 (div*1000000 + (int)div64_long(1000000LL*rem,
1013 (int)bclk_freq))
1014 /div - 1000000;
1015
1016 return div;
1017 }
1018
davinci_mcasp_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)1019 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1020 struct snd_pcm_hw_params *params,
1021 struct snd_soc_dai *cpu_dai)
1022 {
1023 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1024 int word_length;
1025 int channels = params_channels(params);
1026 int period_size = params_period_size(params);
1027 int ret;
1028
1029 /*
1030 * If mcasp is BCLK master, and a BCLK divider was not provided by
1031 * the machine driver, we need to calculate the ratio.
1032 */
1033 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1034 int slots = mcasp->tdm_slots;
1035 int rate = params_rate(params);
1036 int sbits = params_width(params);
1037 int ppm, div;
1038
1039 if (mcasp->slot_width)
1040 sbits = mcasp->slot_width;
1041
1042 div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*slots,
1043 &ppm);
1044 if (ppm)
1045 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1046 ppm);
1047
1048 __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
1049 }
1050
1051 ret = mcasp_common_hw_param(mcasp, substream->stream,
1052 period_size * channels, channels);
1053 if (ret)
1054 return ret;
1055
1056 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1057 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1058 else
1059 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1060 channels);
1061
1062 if (ret)
1063 return ret;
1064
1065 switch (params_format(params)) {
1066 case SNDRV_PCM_FORMAT_U8:
1067 case SNDRV_PCM_FORMAT_S8:
1068 word_length = 8;
1069 break;
1070
1071 case SNDRV_PCM_FORMAT_U16_LE:
1072 case SNDRV_PCM_FORMAT_S16_LE:
1073 word_length = 16;
1074 break;
1075
1076 case SNDRV_PCM_FORMAT_U24_3LE:
1077 case SNDRV_PCM_FORMAT_S24_3LE:
1078 word_length = 24;
1079 break;
1080
1081 case SNDRV_PCM_FORMAT_U24_LE:
1082 case SNDRV_PCM_FORMAT_S24_LE:
1083 word_length = 24;
1084 break;
1085
1086 case SNDRV_PCM_FORMAT_U32_LE:
1087 case SNDRV_PCM_FORMAT_S32_LE:
1088 word_length = 32;
1089 break;
1090
1091 default:
1092 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1093 return -EINVAL;
1094 }
1095
1096 davinci_config_channel_size(mcasp, word_length);
1097
1098 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1099 mcasp->channels = channels;
1100
1101 return 0;
1102 }
1103
davinci_mcasp_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)1104 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1105 int cmd, struct snd_soc_dai *cpu_dai)
1106 {
1107 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1108 int ret = 0;
1109
1110 switch (cmd) {
1111 case SNDRV_PCM_TRIGGER_RESUME:
1112 case SNDRV_PCM_TRIGGER_START:
1113 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1114 davinci_mcasp_start(mcasp, substream->stream);
1115 break;
1116 case SNDRV_PCM_TRIGGER_SUSPEND:
1117 case SNDRV_PCM_TRIGGER_STOP:
1118 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1119 davinci_mcasp_stop(mcasp, substream->stream);
1120 break;
1121
1122 default:
1123 ret = -EINVAL;
1124 }
1125
1126 return ret;
1127 }
1128
1129 static const unsigned int davinci_mcasp_dai_rates[] = {
1130 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1131 88200, 96000, 176400, 192000,
1132 };
1133
1134 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1135
davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1136 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1137 struct snd_pcm_hw_rule *rule)
1138 {
1139 struct davinci_mcasp_ruledata *rd = rule->private;
1140 struct snd_interval *ri =
1141 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1142 int sbits = params_width(params);
1143 int slots = rd->mcasp->tdm_slots;
1144 struct snd_interval range;
1145 int i;
1146
1147 if (rd->mcasp->slot_width)
1148 sbits = rd->mcasp->slot_width;
1149
1150 snd_interval_any(&range);
1151 range.empty = 1;
1152
1153 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1154 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1155 uint bclk_freq = sbits*slots*
1156 davinci_mcasp_dai_rates[i];
1157 int ppm;
1158
1159 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1160 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1161 if (range.empty) {
1162 range.min = davinci_mcasp_dai_rates[i];
1163 range.empty = 0;
1164 }
1165 range.max = davinci_mcasp_dai_rates[i];
1166 }
1167 }
1168 }
1169
1170 dev_dbg(rd->mcasp->dev,
1171 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1172 ri->min, ri->max, range.min, range.max, sbits, slots);
1173
1174 return snd_interval_refine(hw_param_interval(params, rule->var),
1175 &range);
1176 }
1177
davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1178 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1179 struct snd_pcm_hw_rule *rule)
1180 {
1181 struct davinci_mcasp_ruledata *rd = rule->private;
1182 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1183 struct snd_mask nfmt;
1184 int rate = params_rate(params);
1185 int slots = rd->mcasp->tdm_slots;
1186 int i, count = 0;
1187
1188 snd_mask_none(&nfmt);
1189
1190 for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
1191 if (snd_mask_test(fmt, i)) {
1192 uint sbits = snd_pcm_format_width(i);
1193 int ppm;
1194
1195 if (rd->mcasp->slot_width)
1196 sbits = rd->mcasp->slot_width;
1197
1198 davinci_mcasp_calc_clk_div(rd->mcasp, sbits*slots*rate,
1199 &ppm);
1200 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1201 snd_mask_set(&nfmt, i);
1202 count++;
1203 }
1204 }
1205 }
1206 dev_dbg(rd->mcasp->dev,
1207 "%d possible sample format for %d Hz and %d tdm slots\n",
1208 count, rate, slots);
1209
1210 return snd_mask_refine(fmt, &nfmt);
1211 }
1212
davinci_mcasp_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1213 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1214 struct snd_soc_dai *cpu_dai)
1215 {
1216 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1217 struct davinci_mcasp_ruledata *ruledata =
1218 &mcasp->ruledata[substream->stream];
1219 u32 max_channels = 0;
1220 int i, dir;
1221 int tdm_slots = mcasp->tdm_slots;
1222
1223 if (mcasp->tdm_mask[substream->stream])
1224 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1225
1226 mcasp->substreams[substream->stream] = substream;
1227
1228 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1229 return 0;
1230
1231 /*
1232 * Limit the maximum allowed channels for the first stream:
1233 * number of serializers for the direction * tdm slots per serializer
1234 */
1235 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1236 dir = TX_MODE;
1237 else
1238 dir = RX_MODE;
1239
1240 for (i = 0; i < mcasp->num_serializer; i++) {
1241 if (mcasp->serial_dir[i] == dir)
1242 max_channels++;
1243 }
1244 ruledata->serializers = max_channels;
1245 max_channels *= tdm_slots;
1246 /*
1247 * If the already active stream has less channels than the calculated
1248 * limnit based on the seirializers * tdm_slots, we need to use that as
1249 * a constraint for the second stream.
1250 * Otherwise (first stream or less allowed channels) we use the
1251 * calculated constraint.
1252 */
1253 if (mcasp->channels && mcasp->channels < max_channels)
1254 max_channels = mcasp->channels;
1255 /*
1256 * But we can always allow channels upto the amount of
1257 * the available tdm_slots.
1258 */
1259 if (max_channels < tdm_slots)
1260 max_channels = tdm_slots;
1261
1262 snd_pcm_hw_constraint_minmax(substream->runtime,
1263 SNDRV_PCM_HW_PARAM_CHANNELS,
1264 2, max_channels);
1265
1266 snd_pcm_hw_constraint_list(substream->runtime,
1267 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1268 &mcasp->chconstr[substream->stream]);
1269
1270 if (mcasp->slot_width)
1271 snd_pcm_hw_constraint_minmax(substream->runtime,
1272 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1273 8, mcasp->slot_width);
1274
1275 /*
1276 * If we rely on implicit BCLK divider setting we should
1277 * set constraints based on what we can provide.
1278 */
1279 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1280 int ret;
1281
1282 ruledata->mcasp = mcasp;
1283
1284 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1285 SNDRV_PCM_HW_PARAM_RATE,
1286 davinci_mcasp_hw_rule_rate,
1287 ruledata,
1288 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1289 if (ret)
1290 return ret;
1291 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1292 SNDRV_PCM_HW_PARAM_FORMAT,
1293 davinci_mcasp_hw_rule_format,
1294 ruledata,
1295 SNDRV_PCM_HW_PARAM_RATE, -1);
1296 if (ret)
1297 return ret;
1298 }
1299
1300 return 0;
1301 }
1302
davinci_mcasp_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1303 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1304 struct snd_soc_dai *cpu_dai)
1305 {
1306 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1307
1308 mcasp->substreams[substream->stream] = NULL;
1309
1310 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1311 return;
1312
1313 if (!cpu_dai->active)
1314 mcasp->channels = 0;
1315 }
1316
1317 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1318 .startup = davinci_mcasp_startup,
1319 .shutdown = davinci_mcasp_shutdown,
1320 .trigger = davinci_mcasp_trigger,
1321 .hw_params = davinci_mcasp_hw_params,
1322 .set_fmt = davinci_mcasp_set_dai_fmt,
1323 .set_clkdiv = davinci_mcasp_set_clkdiv,
1324 .set_sysclk = davinci_mcasp_set_sysclk,
1325 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1326 };
1327
davinci_mcasp_dai_probe(struct snd_soc_dai * dai)1328 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1329 {
1330 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1331
1332 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1333 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1334
1335 return 0;
1336 }
1337
1338 #ifdef CONFIG_PM_SLEEP
davinci_mcasp_suspend(struct snd_soc_dai * dai)1339 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1340 {
1341 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1342 struct davinci_mcasp_context *context = &mcasp->context;
1343 u32 reg;
1344 int i;
1345
1346 context->pm_state = pm_runtime_active(mcasp->dev);
1347 if (!context->pm_state)
1348 pm_runtime_get_sync(mcasp->dev);
1349
1350 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1351 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1352
1353 if (mcasp->txnumevt) {
1354 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1355 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1356 }
1357 if (mcasp->rxnumevt) {
1358 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1359 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1360 }
1361
1362 for (i = 0; i < mcasp->num_serializer; i++)
1363 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1364 DAVINCI_MCASP_XRSRCTL_REG(i));
1365
1366 pm_runtime_put_sync(mcasp->dev);
1367
1368 return 0;
1369 }
1370
davinci_mcasp_resume(struct snd_soc_dai * dai)1371 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1372 {
1373 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1374 struct davinci_mcasp_context *context = &mcasp->context;
1375 u32 reg;
1376 int i;
1377
1378 pm_runtime_get_sync(mcasp->dev);
1379
1380 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1381 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1382
1383 if (mcasp->txnumevt) {
1384 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1385 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1386 }
1387 if (mcasp->rxnumevt) {
1388 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1389 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1390 }
1391
1392 for (i = 0; i < mcasp->num_serializer; i++)
1393 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1394 context->xrsr_regs[i]);
1395
1396 if (!context->pm_state)
1397 pm_runtime_put_sync(mcasp->dev);
1398
1399 return 0;
1400 }
1401 #else
1402 #define davinci_mcasp_suspend NULL
1403 #define davinci_mcasp_resume NULL
1404 #endif
1405
1406 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1407
1408 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1409 SNDRV_PCM_FMTBIT_U8 | \
1410 SNDRV_PCM_FMTBIT_S16_LE | \
1411 SNDRV_PCM_FMTBIT_U16_LE | \
1412 SNDRV_PCM_FMTBIT_S24_LE | \
1413 SNDRV_PCM_FMTBIT_U24_LE | \
1414 SNDRV_PCM_FMTBIT_S24_3LE | \
1415 SNDRV_PCM_FMTBIT_U24_3LE | \
1416 SNDRV_PCM_FMTBIT_S32_LE | \
1417 SNDRV_PCM_FMTBIT_U32_LE)
1418
1419 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1420 {
1421 .name = "davinci-mcasp.0",
1422 .probe = davinci_mcasp_dai_probe,
1423 .suspend = davinci_mcasp_suspend,
1424 .resume = davinci_mcasp_resume,
1425 .playback = {
1426 .channels_min = 2,
1427 .channels_max = 32 * 16,
1428 .rates = DAVINCI_MCASP_RATES,
1429 .formats = DAVINCI_MCASP_PCM_FMTS,
1430 },
1431 .capture = {
1432 .channels_min = 2,
1433 .channels_max = 32 * 16,
1434 .rates = DAVINCI_MCASP_RATES,
1435 .formats = DAVINCI_MCASP_PCM_FMTS,
1436 },
1437 .ops = &davinci_mcasp_dai_ops,
1438
1439 .symmetric_samplebits = 1,
1440 .symmetric_rates = 1,
1441 },
1442 {
1443 .name = "davinci-mcasp.1",
1444 .probe = davinci_mcasp_dai_probe,
1445 .playback = {
1446 .channels_min = 1,
1447 .channels_max = 384,
1448 .rates = DAVINCI_MCASP_RATES,
1449 .formats = DAVINCI_MCASP_PCM_FMTS,
1450 },
1451 .ops = &davinci_mcasp_dai_ops,
1452 },
1453
1454 };
1455
1456 static const struct snd_soc_component_driver davinci_mcasp_component = {
1457 .name = "davinci-mcasp",
1458 };
1459
1460 /* Some HW specific values and defaults. The rest is filled in from DT. */
1461 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1462 .tx_dma_offset = 0x400,
1463 .rx_dma_offset = 0x400,
1464 .version = MCASP_VERSION_1,
1465 };
1466
1467 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1468 .tx_dma_offset = 0x2000,
1469 .rx_dma_offset = 0x2000,
1470 .version = MCASP_VERSION_2,
1471 };
1472
1473 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1474 .tx_dma_offset = 0,
1475 .rx_dma_offset = 0,
1476 .version = MCASP_VERSION_3,
1477 };
1478
1479 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1480 .tx_dma_offset = 0x200,
1481 .rx_dma_offset = 0x284,
1482 .version = MCASP_VERSION_4,
1483 };
1484
1485 static const struct of_device_id mcasp_dt_ids[] = {
1486 {
1487 .compatible = "ti,dm646x-mcasp-audio",
1488 .data = &dm646x_mcasp_pdata,
1489 },
1490 {
1491 .compatible = "ti,da830-mcasp-audio",
1492 .data = &da830_mcasp_pdata,
1493 },
1494 {
1495 .compatible = "ti,am33xx-mcasp-audio",
1496 .data = &am33xx_mcasp_pdata,
1497 },
1498 {
1499 .compatible = "ti,dra7-mcasp-audio",
1500 .data = &dra7_mcasp_pdata,
1501 },
1502 { /* sentinel */ }
1503 };
1504 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1505
mcasp_reparent_fck(struct platform_device * pdev)1506 static int mcasp_reparent_fck(struct platform_device *pdev)
1507 {
1508 struct device_node *node = pdev->dev.of_node;
1509 struct clk *gfclk, *parent_clk;
1510 const char *parent_name;
1511 int ret;
1512
1513 if (!node)
1514 return 0;
1515
1516 parent_name = of_get_property(node, "fck_parent", NULL);
1517 if (!parent_name)
1518 return 0;
1519
1520 gfclk = clk_get(&pdev->dev, "fck");
1521 if (IS_ERR(gfclk)) {
1522 dev_err(&pdev->dev, "failed to get fck\n");
1523 return PTR_ERR(gfclk);
1524 }
1525
1526 parent_clk = clk_get(NULL, parent_name);
1527 if (IS_ERR(parent_clk)) {
1528 dev_err(&pdev->dev, "failed to get parent clock\n");
1529 ret = PTR_ERR(parent_clk);
1530 goto err1;
1531 }
1532
1533 ret = clk_set_parent(gfclk, parent_clk);
1534 if (ret) {
1535 dev_err(&pdev->dev, "failed to reparent fck\n");
1536 goto err2;
1537 }
1538
1539 err2:
1540 clk_put(parent_clk);
1541 err1:
1542 clk_put(gfclk);
1543 return ret;
1544 }
1545
davinci_mcasp_set_pdata_from_of(struct platform_device * pdev)1546 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1547 struct platform_device *pdev)
1548 {
1549 struct device_node *np = pdev->dev.of_node;
1550 struct davinci_mcasp_pdata *pdata = NULL;
1551 const struct of_device_id *match =
1552 of_match_device(mcasp_dt_ids, &pdev->dev);
1553 struct of_phandle_args dma_spec;
1554
1555 const u32 *of_serial_dir32;
1556 u32 val;
1557 int i, ret = 0;
1558
1559 if (pdev->dev.platform_data) {
1560 pdata = pdev->dev.platform_data;
1561 return pdata;
1562 } else if (match) {
1563 pdata = (struct davinci_mcasp_pdata*) match->data;
1564 } else {
1565 /* control shouldn't reach here. something is wrong */
1566 ret = -EINVAL;
1567 goto nodata;
1568 }
1569
1570 ret = of_property_read_u32(np, "op-mode", &val);
1571 if (ret >= 0)
1572 pdata->op_mode = val;
1573
1574 ret = of_property_read_u32(np, "tdm-slots", &val);
1575 if (ret >= 0) {
1576 if (val < 2 || val > 32) {
1577 dev_err(&pdev->dev,
1578 "tdm-slots must be in rage [2-32]\n");
1579 ret = -EINVAL;
1580 goto nodata;
1581 }
1582
1583 pdata->tdm_slots = val;
1584 }
1585
1586 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1587 val /= sizeof(u32);
1588 if (of_serial_dir32) {
1589 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1590 (sizeof(*of_serial_dir) * val),
1591 GFP_KERNEL);
1592 if (!of_serial_dir) {
1593 ret = -ENOMEM;
1594 goto nodata;
1595 }
1596
1597 for (i = 0; i < val; i++)
1598 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1599
1600 pdata->num_serializer = val;
1601 pdata->serial_dir = of_serial_dir;
1602 }
1603
1604 ret = of_property_match_string(np, "dma-names", "tx");
1605 if (ret < 0)
1606 goto nodata;
1607
1608 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1609 &dma_spec);
1610 if (ret < 0)
1611 goto nodata;
1612
1613 pdata->tx_dma_channel = dma_spec.args[0];
1614
1615 /* RX is not valid in DIT mode */
1616 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1617 ret = of_property_match_string(np, "dma-names", "rx");
1618 if (ret < 0)
1619 goto nodata;
1620
1621 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1622 &dma_spec);
1623 if (ret < 0)
1624 goto nodata;
1625
1626 pdata->rx_dma_channel = dma_spec.args[0];
1627 }
1628
1629 ret = of_property_read_u32(np, "tx-num-evt", &val);
1630 if (ret >= 0)
1631 pdata->txnumevt = val;
1632
1633 ret = of_property_read_u32(np, "rx-num-evt", &val);
1634 if (ret >= 0)
1635 pdata->rxnumevt = val;
1636
1637 ret = of_property_read_u32(np, "sram-size-playback", &val);
1638 if (ret >= 0)
1639 pdata->sram_size_playback = val;
1640
1641 ret = of_property_read_u32(np, "sram-size-capture", &val);
1642 if (ret >= 0)
1643 pdata->sram_size_capture = val;
1644
1645 return pdata;
1646
1647 nodata:
1648 if (ret < 0) {
1649 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1650 ret);
1651 pdata = NULL;
1652 }
1653 return pdata;
1654 }
1655
1656 enum {
1657 PCM_EDMA,
1658 PCM_SDMA,
1659 };
1660 static const char *sdma_prefix = "ti,omap";
1661
davinci_mcasp_get_dma_type(struct davinci_mcasp * mcasp)1662 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1663 {
1664 struct dma_chan *chan;
1665 const char *tmp;
1666 int ret = PCM_EDMA;
1667
1668 if (!mcasp->dev->of_node)
1669 return PCM_EDMA;
1670
1671 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1672 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1673 if (IS_ERR(chan)) {
1674 if (PTR_ERR(chan) != -EPROBE_DEFER)
1675 dev_err(mcasp->dev,
1676 "Can't verify DMA configuration (%ld)\n",
1677 PTR_ERR(chan));
1678 return PTR_ERR(chan);
1679 }
1680 BUG_ON(!chan->device || !chan->device->dev);
1681
1682 if (chan->device->dev->of_node)
1683 ret = of_property_read_string(chan->device->dev->of_node,
1684 "compatible", &tmp);
1685 else
1686 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1687
1688 dma_release_channel(chan);
1689 if (ret)
1690 return ret;
1691
1692 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1693 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1694 return PCM_SDMA;
1695
1696 return PCM_EDMA;
1697 }
1698
davinci_mcasp_probe(struct platform_device * pdev)1699 static int davinci_mcasp_probe(struct platform_device *pdev)
1700 {
1701 struct snd_dmaengine_dai_dma_data *dma_data;
1702 struct resource *mem, *res, *dat;
1703 struct davinci_mcasp_pdata *pdata;
1704 struct davinci_mcasp *mcasp;
1705 char *irq_name;
1706 int *dma;
1707 int irq;
1708 int ret;
1709
1710 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1711 dev_err(&pdev->dev, "No platform data supplied\n");
1712 return -EINVAL;
1713 }
1714
1715 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1716 GFP_KERNEL);
1717 if (!mcasp)
1718 return -ENOMEM;
1719
1720 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1721 if (!pdata) {
1722 dev_err(&pdev->dev, "no platform data\n");
1723 return -EINVAL;
1724 }
1725
1726 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1727 if (!mem) {
1728 dev_warn(mcasp->dev,
1729 "\"mpu\" mem resource not found, using index 0\n");
1730 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1731 if (!mem) {
1732 dev_err(&pdev->dev, "no mem resource?\n");
1733 return -ENODEV;
1734 }
1735 }
1736
1737 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1738 if (IS_ERR(mcasp->base))
1739 return PTR_ERR(mcasp->base);
1740
1741 pm_runtime_enable(&pdev->dev);
1742
1743 mcasp->op_mode = pdata->op_mode;
1744 /* sanity check for tdm slots parameter */
1745 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1746 if (pdata->tdm_slots < 2) {
1747 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1748 pdata->tdm_slots);
1749 mcasp->tdm_slots = 2;
1750 } else if (pdata->tdm_slots > 32) {
1751 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1752 pdata->tdm_slots);
1753 mcasp->tdm_slots = 32;
1754 } else {
1755 mcasp->tdm_slots = pdata->tdm_slots;
1756 }
1757 }
1758
1759 mcasp->num_serializer = pdata->num_serializer;
1760 #ifdef CONFIG_PM_SLEEP
1761 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1762 sizeof(u32) * mcasp->num_serializer,
1763 GFP_KERNEL);
1764 #endif
1765 mcasp->serial_dir = pdata->serial_dir;
1766 mcasp->version = pdata->version;
1767 mcasp->txnumevt = pdata->txnumevt;
1768 mcasp->rxnumevt = pdata->rxnumevt;
1769
1770 mcasp->dev = &pdev->dev;
1771
1772 irq = platform_get_irq_byname(pdev, "common");
1773 if (irq >= 0) {
1774 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1775 dev_name(&pdev->dev));
1776 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1777 davinci_mcasp_common_irq_handler,
1778 IRQF_ONESHOT | IRQF_SHARED,
1779 irq_name, mcasp);
1780 if (ret) {
1781 dev_err(&pdev->dev, "common IRQ request failed\n");
1782 goto err;
1783 }
1784
1785 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1786 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1787 }
1788
1789 irq = platform_get_irq_byname(pdev, "rx");
1790 if (irq >= 0) {
1791 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1792 dev_name(&pdev->dev));
1793 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1794 davinci_mcasp_rx_irq_handler,
1795 IRQF_ONESHOT, irq_name, mcasp);
1796 if (ret) {
1797 dev_err(&pdev->dev, "RX IRQ request failed\n");
1798 goto err;
1799 }
1800
1801 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1802 }
1803
1804 irq = platform_get_irq_byname(pdev, "tx");
1805 if (irq >= 0) {
1806 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1807 dev_name(&pdev->dev));
1808 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1809 davinci_mcasp_tx_irq_handler,
1810 IRQF_ONESHOT, irq_name, mcasp);
1811 if (ret) {
1812 dev_err(&pdev->dev, "TX IRQ request failed\n");
1813 goto err;
1814 }
1815
1816 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1817 }
1818
1819 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1820 if (dat)
1821 mcasp->dat_port = true;
1822
1823 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1824 if (dat)
1825 dma_data->addr = dat->start;
1826 else
1827 dma_data->addr = mem->start + pdata->tx_dma_offset;
1828
1829 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1830 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1831 if (res)
1832 *dma = res->start;
1833 else
1834 *dma = pdata->tx_dma_channel;
1835
1836 /* dmaengine filter data for DT and non-DT boot */
1837 if (pdev->dev.of_node)
1838 dma_data->filter_data = "tx";
1839 else
1840 dma_data->filter_data = dma;
1841
1842 /* RX is not valid in DIT mode */
1843 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1844 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1845 if (dat)
1846 dma_data->addr = dat->start;
1847 else
1848 dma_data->addr = mem->start + pdata->rx_dma_offset;
1849
1850 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1851 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1852 if (res)
1853 *dma = res->start;
1854 else
1855 *dma = pdata->rx_dma_channel;
1856
1857 /* dmaengine filter data for DT and non-DT boot */
1858 if (pdev->dev.of_node)
1859 dma_data->filter_data = "rx";
1860 else
1861 dma_data->filter_data = dma;
1862 }
1863
1864 if (mcasp->version < MCASP_VERSION_3) {
1865 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1866 /* dma_params->dma_addr is pointing to the data port address */
1867 mcasp->dat_port = true;
1868 } else {
1869 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1870 }
1871
1872 /* Allocate memory for long enough list for all possible
1873 * scenarios. Maximum number tdm slots is 32 and there cannot
1874 * be more serializers than given in the configuration. The
1875 * serializer directions could be taken into account, but it
1876 * would make code much more complex and save only couple of
1877 * bytes.
1878 */
1879 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
1880 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1881 (32 + mcasp->num_serializer - 2),
1882 GFP_KERNEL);
1883
1884 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
1885 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1886 (32 + mcasp->num_serializer - 2),
1887 GFP_KERNEL);
1888
1889 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
1890 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list)
1891 return -ENOMEM;
1892
1893 ret = davinci_mcasp_set_ch_constraints(mcasp);
1894 if (ret)
1895 goto err;
1896
1897 dev_set_drvdata(&pdev->dev, mcasp);
1898
1899 mcasp_reparent_fck(pdev);
1900
1901 ret = devm_snd_soc_register_component(&pdev->dev,
1902 &davinci_mcasp_component,
1903 &davinci_mcasp_dai[pdata->op_mode], 1);
1904
1905 if (ret != 0)
1906 goto err;
1907
1908 ret = davinci_mcasp_get_dma_type(mcasp);
1909 switch (ret) {
1910 case PCM_EDMA:
1911 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1912 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1913 IS_MODULE(CONFIG_SND_EDMA_SOC))
1914 ret = edma_pcm_platform_register(&pdev->dev);
1915 #else
1916 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
1917 ret = -EINVAL;
1918 goto err;
1919 #endif
1920 break;
1921 case PCM_SDMA:
1922 #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1923 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1924 IS_MODULE(CONFIG_SND_OMAP_SOC))
1925 ret = omap_pcm_platform_register(&pdev->dev);
1926 #else
1927 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
1928 ret = -EINVAL;
1929 goto err;
1930 #endif
1931 break;
1932 default:
1933 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
1934 case -EPROBE_DEFER:
1935 goto err;
1936 break;
1937 }
1938
1939 if (ret) {
1940 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1941 goto err;
1942 }
1943
1944 return 0;
1945
1946 err:
1947 pm_runtime_disable(&pdev->dev);
1948 return ret;
1949 }
1950
davinci_mcasp_remove(struct platform_device * pdev)1951 static int davinci_mcasp_remove(struct platform_device *pdev)
1952 {
1953 pm_runtime_disable(&pdev->dev);
1954
1955 return 0;
1956 }
1957
1958 static struct platform_driver davinci_mcasp_driver = {
1959 .probe = davinci_mcasp_probe,
1960 .remove = davinci_mcasp_remove,
1961 .driver = {
1962 .name = "davinci-mcasp",
1963 .of_match_table = mcasp_dt_ids,
1964 },
1965 };
1966
1967 module_platform_driver(davinci_mcasp_driver);
1968
1969 MODULE_AUTHOR("Steve Chen");
1970 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1971 MODULE_LICENSE("GPL");
1972