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Searched refs:enable_reg (Results 1 – 101 of 101) sorted by relevance

/linux-4.1.27/arch/arm/mach-ep93xx/
Dclock.c35 void __iomem *enable_reg; member
56 .enable_reg = EP93XX_SYSCON_DEVCFG,
63 .enable_reg = EP93XX_SYSCON_DEVCFG,
70 .enable_reg = EP93XX_SYSCON_DEVCFG,
91 .enable_reg = EP93XX_SYSCON_PWRCNT,
97 .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
112 .enable_reg = EP93XX_SYSCON_VIDCLKDIV,
119 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
127 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
135 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
[all …]
/linux-4.1.27/drivers/clk/qcom/
Dgcc-msm8660.c52 .enable_reg = 0x34c0,
129 .enable_reg = 0x29d4,
145 .enable_reg = 0x29d4,
180 .enable_reg = 0x29f4,
196 .enable_reg = 0x29f4,
231 .enable_reg = 0x2a14,
247 .enable_reg = 0x2a14,
282 .enable_reg = 0x2a34,
298 .enable_reg = 0x2a34,
333 .enable_reg = 0x2a54,
[all …]
Dgcc-ipq806x.c52 .enable_reg = 0x34c0,
79 .enable_reg = 0x34c0,
106 .enable_reg = 0x34c0,
133 .enable_reg = 0x34c0,
239 .enable_reg = 0x29d4,
255 .enable_reg = 0x29d4,
290 .enable_reg = 0x29f4,
306 .enable_reg = 0x29f4,
341 .enable_reg = 0x2a34,
357 .enable_reg = 0x2a34,
[all …]
Dgcc-msm8960.c52 .enable_reg = 0x34c0,
79 .enable_reg = 0x34c0,
106 .enable_reg = 0x34c0,
196 .enable_reg = 0x29d4,
212 .enable_reg = 0x29d4,
247 .enable_reg = 0x29f4,
263 .enable_reg = 0x29f4,
298 .enable_reg = 0x2a14,
314 .enable_reg = 0x2a14,
349 .enable_reg = 0x2a34,
[all …]
Dmmcc-apq8084.c240 .enable_reg = 0x0100,
267 .enable_reg = 0x0100,
1126 .enable_reg = 0x5104,
1141 .enable_reg = 0x5100,
1158 .enable_reg = 0x2414,
1175 .enable_reg = 0x2418,
1192 .enable_reg = 0x2410,
1209 .enable_reg = 0x241c,
1226 .enable_reg = 0x2420,
1243 .enable_reg = 0x2404,
[all …]
Dmmcc-msm8960.c170 .enable_reg = 0x0140,
185 .enable_reg = 0x0140,
219 .enable_reg = 0x0154,
234 .enable_reg = 0x0154,
268 .enable_reg = 0x0220,
283 .enable_reg = 0x0220,
323 .enable_reg = 0x0040,
338 .enable_reg = 0x0040,
354 .enable_reg = 0x0040,
387 .enable_reg = 0x0024,
[all …]
Dmmcc-msm8974.c205 .enable_reg = 0x0100,
232 .enable_reg = 0x0100,
953 .enable_reg = 0x3348,
969 .enable_reg = 0x3344,
986 .enable_reg = 0x30bc,
1002 .enable_reg = 0x30b4,
1019 .enable_reg = 0x30c4,
1036 .enable_reg = 0x30e4,
1053 .enable_reg = 0x30d4,
1070 .enable_reg = 0x3128,
[all …]
Dgcc-apq8084.c127 .enable_reg = 0x1480,
190 .enable_reg = 0x1480,
217 .enable_reg = 0x1480,
289 .enable_reg = 0x1bd0,
306 .enable_reg = 0x1bcc,
1332 .enable_reg = 0x1f14,
1386 .enable_reg = 0x1484,
1403 .enable_reg = 0x1484,
1419 .enable_reg = 0x0648,
1436 .enable_reg = 0x0644,
[all …]
Dgcc-msm8974.c83 .enable_reg = 0x1480,
146 .enable_reg = 0x1480,
173 .enable_reg = 0x1480,
1048 .enable_reg = 0x1484,
1064 .enable_reg = 0x1484,
1081 .enable_reg = 0x1484,
1097 .enable_reg = 0x0648,
1114 .enable_reg = 0x0644,
1131 .enable_reg = 0x06c8,
1148 .enable_reg = 0x06c4,
[all …]
Dgcc-msm8916.c212 .enable_reg = 0x45000,
239 .enable_reg = 0x45000,
266 .enable_reg = 0x45000,
293 .enable_reg = 0x45000,
1140 .enable_reg = 0x45004,
1156 .enable_reg = 0x01004,
1173 .enable_reg = 0x02008,
1190 .enable_reg = 0x02004,
1207 .enable_reg = 0x03010,
1224 .enable_reg = 0x0300c,
[all …]
Dlcc-msm8960.c118 .enable_reg = 0x48,
139 .enable_reg = 0x48,
156 .enable_reg = 0x48,
172 .enable_reg = 0x48,
224 .enable_reg = _ns, \
245 .enable_reg = _ns, \
276 .enable_reg = _ns, \
368 .enable_reg = 0x54,
385 .enable_reg = 0x54,
436 .enable_reg = 0xcc,
[all …]
Dlcc-ipq806x.c137 .enable_reg = 0x48,
158 .enable_reg = 0x48,
189 .enable_reg = 0x48,
251 .enable_reg = 0x54,
268 .enable_reg = 0x54,
331 .enable_reg = 0xcc,
352 .enable_reg = 0xcc,
390 .enable_reg = 0x38,
Dclk-regmap.c36 ret = regmap_read(rclk->regmap, rclk->enable_reg, &val); in clk_is_enabled_regmap()
66 return regmap_update_bits(rclk->regmap, rclk->enable_reg, in clk_enable_regmap()
90 regmap_update_bits(rclk->regmap, rclk->enable_reg, rclk->enable_mask, in clk_disable_regmap()
Dclk-regmap.h33 unsigned int enable_reg; member
Dclk-rcg.c364 if (rcg->clkr.enable_reg != rcg->ns_reg) in clk_rcg_recalc_rate()
365 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode); in clk_rcg_recalc_rate()
495 reset_reg = rcg->clkr.enable_reg; in __clk_rcg_set_rate()
509 if (rcg->clkr.enable_reg != rcg->ns_reg) { in __clk_rcg_set_rate()
510 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl); in __clk_rcg_set_rate()
512 regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl); in __clk_rcg_set_rate()
/linux-4.1.27/arch/arm/mach-omap1/
Dclock_data.c101 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
113 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
135 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
154 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
165 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
178 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
191 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
215 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
237 .enable_reg = DSP_IDLECT2,
249 .enable_reg = DSP_IDLECT2,
[all …]
Dclock.c46 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
334 val = __raw_readl(clk->enable_reg); in omap1_set_uart_rate()
341 __raw_writel(val, clk->enable_reg); in omap1_set_uart_rate()
360 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; in omap1_set_ext_clk_rate()
361 __raw_writew(ratio_bits, clk->enable_reg); in omap1_set_ext_clk_rate()
400 ratio_bits = __raw_readw(clk->enable_reg) & ~1; in omap1_init_ext_clk()
401 __raw_writew(ratio_bits, clk->enable_reg); in omap1_init_ext_clk()
457 if (unlikely(clk->enable_reg == NULL)) { in omap1_clk_enable_generic()
464 regval32 = __raw_readl(clk->enable_reg); in omap1_clk_enable_generic()
466 __raw_writel(regval32, clk->enable_reg); in omap1_clk_enable_generic()
[all …]
Dclock.h149 void __iomem *enable_reg; member
/linux-4.1.27/arch/arm/mach-lpc32xx/
Dclock.c547 tmp = __raw_readl(clk->enable_reg); in local_onoff_enable()
554 __raw_writel(tmp, clk->enable_reg); in local_onoff_enable()
563 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
570 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
577 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
584 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
591 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
598 .enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
605 .enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL,
612 .enable_reg = LPC32XX_CLKPWR_DMA_CLK_CTRL,
[all …]
Dclock.h34 void __iomem *enable_reg; member
/linux-4.1.27/drivers/regulator/
Dlp8788-ldo.c202 .enable_reg = LP8788_EN_LDO_A,
215 .enable_reg = LP8788_EN_LDO_A,
228 .enable_reg = LP8788_EN_LDO_A,
241 .enable_reg = LP8788_EN_LDO_A,
254 .enable_reg = LP8788_EN_LDO_A,
267 .enable_reg = LP8788_EN_LDO_A,
280 .enable_reg = LP8788_EN_LDO_A,
293 .enable_reg = LP8788_EN_LDO_A,
306 .enable_reg = LP8788_EN_LDO_B,
319 .enable_reg = LP8788_EN_LDO_B,
[all …]
Drk808-regulator.c119 reg = rdev->desc->enable_reg + RK808_SLP_SET_OFF_REG_OFFSET; in rk808_set_suspend_enable()
130 reg = rdev->desc->enable_reg + RK808_SLP_SET_OFF_REG_OFFSET; in rk808_set_suspend_disable()
184 .enable_reg = RK808_DCDC_EN_REG,
198 .enable_reg = RK808_DCDC_EN_REG,
208 .enable_reg = RK808_DCDC_EN_REG,
222 .enable_reg = RK808_DCDC_EN_REG,
236 .enable_reg = RK808_LDO_EN_REG,
251 .enable_reg = RK808_LDO_EN_REG,
266 .enable_reg = RK808_LDO_EN_REG,
281 .enable_reg = RK808_LDO_EN_REG,
[all …]
Dmax77686.c141 ret = regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in max77686_set_suspend_disable()
175 ret = regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in max77686_set_suspend_mode()
209 ret = regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in max77686_ldo_set_suspend_mode()
230 return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in max77686_enable()
256 return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in max77686_set_ramp_delay()
282 return regmap_update_bits(config->regmap, desc->enable_reg, in max77686_of_parse_cb()
355 .enable_reg = MAX77686_REG_LDO1CTRL1 + num - 1, \
373 .enable_reg = MAX77686_REG_LDO1CTRL1 + num - 1, \
391 .enable_reg = MAX77686_REG_LDO1CTRL1 + num - 1, \
409 .enable_reg = MAX77686_REG_LDO1CTRL1 + num - 1, \
[all …]
Dmax77802.c113 return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in max77802_set_suspend_disable()
143 return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in max77802_set_mode()
217 return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in max77802_set_suspend_mode()
230 return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in max77802_enable()
268 return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in max77802_set_ramp_delay_2bit()
282 return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in max77802_set_ramp_delay_4bit()
379 .enable_reg = MAX77802_REG_LDO1CTRL1 + num - 1, \
400 .enable_reg = MAX77802_REG_LDO1CTRL1 + num - 1, \
421 .enable_reg = MAX77802_REG_BUCK ## num ## CTRL, \
442 .enable_reg = MAX77802_REG_BUCK ## num ## CTRL1, \
[all …]
Das3722-regulator.c67 u32 enable_reg; member
96 .enable_reg = AS3722_SD_CONTROL_REG,
108 .enable_reg = AS3722_SD_CONTROL_REG,
121 .enable_reg = AS3722_SD_CONTROL_REG,
135 .enable_reg = AS3722_SD_CONTROL_REG,
149 .enable_reg = AS3722_SD_CONTROL_REG,
163 .enable_reg = AS3722_SD_CONTROL_REG,
176 .enable_reg = AS3722_SD_CONTROL_REG,
189 .enable_reg = AS3722_LDOCONTROL0_REG,
201 .enable_reg = AS3722_LDOCONTROL0_REG,
[all …]
Ds2mps11.c272 .enable_reg = S2MPS11_REG_L1CTRL + num - 1, \
288 .enable_reg = S2MPS11_REG_B1CTRL1 + (num - 1) * 2, \
304 .enable_reg = S2MPS11_REG_B5CTRL1, \
320 .enable_reg = S2MPS11_REG_B6CTRL1 + (num - 6) * 2, \
336 .enable_reg = S2MPS11_REG_B9CTRL1, \
405 .enable_reg = S2MPS13_REG_L1CTRL + num - 1, \
422 .enable_reg = S2MPS13_REG_B1CTRL + (num - 1) * 2, \
439 .enable_reg = S2MPS13_REG_B1CTRL + (num - 1) * 2, \
456 .enable_reg = S2MPS13_REG_B1CTRL + (num) * 2 - 1, \
538 return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in s2mps14_regulator_enable()
[all …]
Dtps65090-regulator.c79 ret = regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in tps65090_reg_set_overcurrent_wait()
84 rdev->desc->enable_reg); in tps65090_reg_set_overcurrent_wait()
103 ret = regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in tps65090_try_enable_fet()
108 rdev->desc->enable_reg); in tps65090_try_enable_fet()
113 ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, in tps65090_try_enable_fet()
160 ret = regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in tps65090_fet_enable()
170 rdev->desc->enable_reg, tries); in tps65090_fet_enable()
174 dev_warn(&rdev->dev, "reg %#x enable failed\n", rdev->desc->enable_reg); in tps65090_fet_enable()
203 .enable_reg = _en_reg, \
269 unsigned int reg_en_reg = ri->desc->enable_reg; in tps65090_config_ext_control()
[all …]
Dtps6586x-regulator.c63 int enable_reg[2]; member
123 .enable_reg = TPS6586X_SUPPLY##ereg0, \
130 .enable_reg[0] = TPS6586X_SUPPLY##ereg0, \
132 .enable_reg[1] = TPS6586X_SUPPLY##ereg1, \
148 .enable_reg = TPS6586X_SUPPLY##ereg0, \
155 .enable_reg[0] = TPS6586X_SUPPLY##ereg0, \
157 .enable_reg[1] = TPS6586X_SUPPLY##ereg1, \
276 if (ri->enable_reg[0] == ri->enable_reg[1] && in tps6586x_regulator_preinit()
280 ret = tps6586x_read(parent, ri->enable_reg[0], &val1); in tps6586x_regulator_preinit()
284 ret = tps6586x_read(parent, ri->enable_reg[1], &val2); in tps6586x_regulator_preinit()
[all …]
Dwm8400-regulator.c127 .enable_reg = WM8400_LDO1_CONTROL,
141 .enable_reg = WM8400_LDO2_CONTROL,
155 .enable_reg = WM8400_LDO3_CONTROL,
169 .enable_reg = WM8400_LDO4_CONTROL,
183 .enable_reg = WM8400_DCDC1_CONTROL_1,
197 .enable_reg = WM8400_DCDC2_CONTROL_1,
Dmax8925-regulator.c42 int enable_reg; member
73 return max8925_set_bits(info->i2c, info->enable_reg, in max8925_enable()
84 return max8925_set_bits(info->i2c, info->enable_reg, in max8925_disable()
95 ret = max8925_reg_read(info->i2c, info->enable_reg); in max8925_is_enabled()
117 return max8925_set_bits(info->i2c, info->enable_reg, mask, data); in max8925_set_dvm_voltage()
171 .enable_reg = MAX8925_SDCTL##_id, \
187 .enable_reg = MAX8925_LDOCTL##_id, \
Disl9305.c83 .enable_reg = ISL9305_SYSTEM_PARAMETER,
97 .enable_reg = ISL9305_SYSTEM_PARAMETER,
111 .enable_reg = ISL9305_SYSTEM_PARAMETER,
125 .enable_reg = ISL9305_SYSTEM_PARAMETER,
Dlp872x.c531 .enable_reg = LP8720_ENABLE,
544 .enable_reg = LP8720_ENABLE,
557 .enable_reg = LP8720_ENABLE,
570 .enable_reg = LP8720_ENABLE,
583 .enable_reg = LP8720_ENABLE,
594 .enable_reg = LP8720_ENABLE,
610 .enable_reg = LP8725_LDO_CTRL,
623 .enable_reg = LP8725_LDO_CTRL,
636 .enable_reg = LP8725_LDO_CTRL,
649 .enable_reg = LP8725_LDO_CTRL,
[all …]
Dhi6421-regulator.c182 .enable_reg = HI6421_REG_TO_BUS_ADDR(ereg), \
219 .enable_reg = HI6421_REG_TO_BUS_ADDR(ereg), \
256 .enable_reg = HI6421_REG_TO_BUS_ADDR(ereg), \
290 .enable_reg = HI6421_REG_TO_BUS_ADDR(ereg), \
323 .enable_reg = HI6421_REG_TO_BUS_ADDR(ereg), \
413 regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val); in hi6421_regulator_ldo_get_mode()
425 regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val); in hi6421_regulator_buck_get_mode()
450 regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in hi6421_regulator_ldo_set_mode()
474 regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in hi6421_regulator_buck_set_mode()
Dmax14577.c114 .enable_reg = MAX14577_REG_CONTROL2,
125 .enable_reg = MAX14577_CHG_REG_CHG_CTRL2,
152 .enable_reg = MAX14577_REG_CONTROL2,
163 .enable_reg = MAX14577_CHG_REG_CHG_CTRL2,
177 .enable_reg = MAX77836_LDO_REG_CNFG1_LDO1,
193 .enable_reg = MAX77836_LDO_REG_CNFG1_LDO2,
Dmax77843.c42 ret = regmap_read(regmap, rdev->desc->enable_reg, &reg); in max77843_reg_is_enabled()
126 .enable_reg = MAX77843_SYS_REG_SAFEOUTCTRL,
141 .enable_reg = MAX77843_SYS_REG_SAFEOUTCTRL,
154 .enable_reg = MAX77843_CHG_REG_CHG_CNFG_00,
Drt5033-regulator.c48 .enable_reg = RT5033_REG_CTRL,
64 .enable_reg = RT5033_REG_CTRL,
79 .enable_reg = RT5033_REG_CTRL,
Dmax77693.c45 ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, &val); in max77693_chg_is_enabled()
140 .enable_reg = MAX77693_CHG_REG_SAFEOUT_CTRL, \
155 .enable_reg = MAX77693_CHG_REG_CHG_CNFG_00,
Dmt6397-regulator.c58 .enable_reg = enreg, \
81 .enable_reg = enreg, \
97 .enable_reg = enreg, \
154 ret = regmap_read(rdev->regmap, info->desc.enable_reg, &regval); in mt6397_get_status()
Dda903x.c85 int enable_reg; member
144 return da903x_set_bits(da9034_dev, info->enable_reg, in da903x_enable()
153 return da903x_clr_bits(da9034_dev, info->enable_reg, in da903x_disable()
164 ret = da903x_read(da9034_dev, info->enable_reg, &reg_val); in da903x_is_enabled()
329 .enable_reg = _pmic##_##ereg, \
351 .enable_reg = _pmic##_##ereg, \
Dtps65218-regulator.c43 .enable_reg = _er, \
137 return tps65218_set_bits(tps, dev->desc->enable_reg, in tps65218_pmic_enable()
151 return tps65218_clear_bits(tps, dev->desc->enable_reg, in tps65218_pmic_disable()
Ds2mpa01.c249 .enable_reg = S2MPA01_REG_L1CTRL + num - 1, \
265 .enable_reg = S2MPA01_REG_B1CTRL1 + (num - 1) * 2, \
281 .enable_reg = S2MPA01_REG_B5CTRL1, \
297 .enable_reg = S2MPA01_REG_B6CTRL1 + (num - 6) * 2, \
Dmax8907-regulator.c62 .enable_reg = (base) + MAX8907_CTL, \
88 .enable_reg = (base), \
339 regmap_read(config.regmap, pmic->desc[i].enable_reg, in max8907_regulator_probe()
345 regmap_read(config.regmap, pmic->desc[i].enable_reg, in max8907_regulator_probe()
Dwm8350-regulator.c1004 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1014 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1029 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1044 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1054 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1069 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1084 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1099 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1114 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1129 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
Daxp20x-regulator.c50 .enable_reg = (_ereg), \
72 .enable_reg = (_ereg), \
104 .enable_reg = (_ereg), \
D88pm8607.c246 .enable_reg = PM8606_##ereg, \
265 .enable_reg = PM8607_##ereg, \
284 .enable_reg = PM8607_##ereg, \
Dact8865-regulator.c188 .enable_reg = _family##_##_id##_CTRL, \
207 .enable_reg = ACT8600_SUDCDC4_CTRL,
222 .enable_reg = ACT8600_LDO910_CTRL,
233 .enable_reg = ACT8600_LDO910_CTRL,
Dhelpers.c36 ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, &val); in regulator_is_enabled_regmap()
75 return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in regulator_enable_regmap()
101 return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in regulator_disable_regmap()
Dlp8788-buck.c382 .enable_reg = LP8788_EN_BUCK,
393 .enable_reg = LP8788_EN_BUCK,
406 .enable_reg = LP8788_EN_BUCK,
419 .enable_reg = LP8788_EN_BUCK,
Darizona-micsupp.c136 .enable_reg = ARIZONA_MIC_CHARGE_PUMP_1,
163 .enable_reg = ARIZONA_MIC_CHARGE_PUMP_1,
Dpfuze100-regulator.c172 .enable_reg = (base), \
207 .enable_reg = (base), \
225 .enable_reg = (base), \
244 .enable_reg = (base), \
Dsky81452-regulator.c64 .enable_reg = SKY81452_REG1,
Dstw481x-vmmc.c49 .enable_reg = STW_CONF1,
Drn5t618-regulator.c43 .enable_reg = RN5T618_##ereg, \
Dpcf50633-regulator.c40 .enable_reg = PCF50633_REG_##_id##OUT + 1, \
Dpalmas-regulator.c902 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, in palmas_ldo_registration()
927 desc->enable_reg = in palmas_ldo_registration()
1014 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, in tps65917_ldo_registration()
1028 desc->enable_reg = in tps65917_ldo_registration()
1162 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, in palmas_smps_registration()
1211 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, in palmas_smps_registration()
1318 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, in tps65917_smps_registration()
D88pm800.c108 .enable_reg = PM800_##ereg, \
134 .enable_reg = PM800_##ereg, \
Ds5m8767.c924 int enable_reg, enable_val; in s5m8767_pmic_probe() local
940 s5m8767_get_register(s5m8767, id, &enable_reg, in s5m8767_pmic_probe()
942 regulators[id].enable_reg = enable_reg; in s5m8767_pmic_probe()
Dwm831x-dcdc.c497 dcdc->desc.enable_reg = WM831X_DCDC_ENABLE; in wm831x_buckv_probe()
649 dcdc->desc.enable_reg = WM831X_DCDC_ENABLE; in wm831x_buckp_probe()
767 dcdc->desc.enable_reg = WM831X_DCDC_ENABLE; in wm831x_boostp_probe()
850 dcdc->desc.enable_reg = WM831X_DCDC_ENABLE; in wm831x_epe_probe()
Dwm831x-ldo.c265 ldo->desc.enable_reg = WM831X_LDO_ENABLE; in wm831x_gp_ldo_probe()
476 ldo->desc.enable_reg = WM831X_LDO_ENABLE; in wm831x_aldo_probe()
618 ldo->desc.enable_reg = WM831X_LDO_ENABLE; in wm831x_alive_ldo_probe()
Dda9052-regulator.c304 .enable_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
324 .enable_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
Dda9210-regulator.c79 .enable_reg = DA9210_REG_BUCK_CONT,
Drc5t583-regulator.c93 .enable_reg = RC5T583_REG_##_en_reg, \
Dpbias-regulator.c163 drvdata[data_idx].desc.enable_reg = res->start; in pbias_regulator_probe()
Dtps65217-regulator.c43 .enable_reg = TPS65217_REG_ENABLE, \
Dmax8649.c141 .enable_reg = MAX8649_CONTROL,
Dda9055-regulator.c375 .enable_reg = DA9055_REG_BCORE_CONT + DA9055_ID_##_id, \
403 .enable_reg = DA9055_REG_BCORE_CONT + DA9055_ID_##_id, \
Das3711-regulator.c144 .enable_reg = AS3711_ ## _en_reg, \
Dfan53555.c287 rdesc->enable_reg = di->vol_reg; in fan53555_regulator_register()
Dtps65023-regulator.c250 tps->desc[i].enable_reg = TPS65023_REG_REG_CTRL; in tps_65023_probe()
Dda9063-regulator.c66 .desc.enable_reg = DA9063_REG_##regl_name##_CONT, \
87 .desc.enable_reg = DA9063_REG_##regl_name##_CONT, \
Dmax8973-regulator.c404 max->desc.enable_reg = MAX8973_VOUT; in max8973_probe()
Dda9211-regulator.c229 .enable_reg = DA9211_REG_BUCKA_CONT + DA9211_ID_##_id,\
Dbcm590xx-regulator.c425 pmu->desc[i].enable_reg = bcm590xx_get_enable_register(i); in bcm590xx_probe()
Dlp8755.c312 .enable_reg = LP8755_REG_BUCK##_id,\
Dltc3589.c216 .enable_reg = (en_bit) ? LTC3589_OVEN : 0, \
Dtps65910-regulator.c1190 pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i); in tps65910_probe()
/linux-4.1.27/drivers/clk/shmobile/
Dclk-sh73a0.c93 void __iomem *enable_reg = cpg->reg; in sh73a0_cpg_register_clock() local
99 enable_reg += CPG_PLL0CR; in sh73a0_cpg_register_clock()
102 enable_reg += CPG_PLL1CR; in sh73a0_cpg_register_clock()
105 enable_reg += CPG_PLL2CR; in sh73a0_cpg_register_clock()
108 enable_reg += CPG_PLL3CR; in sh73a0_cpg_register_clock()
114 mult = ((clk_readl(enable_reg) >> 24) & 0x3f) + 1; in sh73a0_cpg_register_clock()
117 if (clk_readl(enable_reg) & BIT(20)) in sh73a0_cpg_register_clock()
/linux-4.1.27/drivers/input/misc/
Dsparcspkr.c22 void __iomem *enable_reg; member
126 sbus_writeb(sbus_readb(info->enable_reg) | 3, info->enable_reg); in grover_spkr_event()
134 sbus_writeb(sbus_readb(info->enable_reg) & 0xFC, info->enable_reg); in grover_spkr_event()
286 info->enable_reg = of_ioremap(&op->resource[3], 0, 1, "grover beep enable"); in grover_beep_probe()
287 if (!info->enable_reg) in grover_beep_probe()
299 of_iounmap(&op->resource[3], info->enable_reg, 1); in grover_beep_probe()
320 of_iounmap(&op->resource[3], info->enable_reg, 1); in grover_remove()
Dpm8941-pwrkey.c62 unsigned int enable_reg; in pm8941_reboot_notify() local
68 enable_reg = PON_PS_HOLD_RST_CTL; in pm8941_reboot_notify()
70 enable_reg = PON_PS_HOLD_RST_CTL2; in pm8941_reboot_notify()
73 pwrkey->baseaddr + enable_reg, in pm8941_reboot_notify()
107 pwrkey->baseaddr + enable_reg, in pm8941_reboot_notify()
/linux-4.1.27/arch/arm/mach-omap2/
Dclock.c336 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); in omap2_clk_dflt_find_companion()
361 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in omap2_clk_dflt_find_idlest()
403 if (unlikely(clk->enable_reg == NULL)) { in omap2_dflt_clk_enable()
411 v = omap2_clk_readl(clk, clk->enable_reg); in omap2_dflt_clk_enable()
416 omap2_clk_writel(v, clk, clk->enable_reg); in omap2_dflt_clk_enable()
417 v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ in omap2_dflt_clk_enable()
445 if (!clk->enable_reg) { in omap2_dflt_clk_disable()
455 v = omap2_clk_readl(clk, clk->enable_reg); in omap2_dflt_clk_disable()
460 omap2_clk_writel(v, clk, clk->enable_reg); in omap2_dflt_clk_disable()
492 if (unlikely(clk->enable_reg)) in omap2_clkops_enable_clkdm()
[all …]
Dclock3517.c55 *idlest_reg = (__force void __iomem *)(clk->enable_reg); in am35xx_clk_find_idlest()
78 *other_reg = (__force void __iomem *)(clk->enable_reg); in am35xx_clk_find_companion()
107 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in am35xx_clk_ipss_find_idlest()
Dclock34xx.c47 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in omap3430es2_clk_ssi_find_idlest()
85 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in omap3430es2_clk_dss_usbhost_find_idlest()
122 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in omap3430es2_clk_hsotgusb_find_idlest()
Dclkt_iclk.c32 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); in omap2_clkt_iclk_allow_idle()
46 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); in omap2_clkt_iclk_deny_idle()
Dclock.h101 .enable_reg = _enable_reg, \
/linux-4.1.27/include/linux/
Dsh_clk.h54 void __iomem *enable_reg; member
123 .enable_reg = (void __iomem *)_enable_reg, \
157 .enable_reg = (void __iomem *)_reg, \
181 .enable_reg = (void __iomem *)_reg, \
194 .enable_reg = (void __iomem *)_reg, \
210 .enable_reg = (void __iomem *)_reg, \
/linux-4.1.27/drivers/char/agp/
Dsworks-agp.c266 u8 enable_reg; in serverworks_configure() local
292 pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg); in serverworks_configure()
293 enable_reg |= 0x1; /* Agp Enable bit */ in serverworks_configure()
294 pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg); in serverworks_configure()
303 pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg); in serverworks_configure()
304 enable_reg &= ~0x3; in serverworks_configure()
305 pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg); in serverworks_configure()
307 pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg); in serverworks_configure()
308 enable_reg |= (1<<6); in serverworks_configure()
309 pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg); in serverworks_configure()
Damd-k7-agp.c210 u16 enable_reg; in amd_irongate_configure() local
233 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
234 enable_reg = (enable_reg | 0x0004); in amd_irongate_configure()
235 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
253 u16 enable_reg; in amd_irongate_cleanup() local
257 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_cleanup()
258 enable_reg = (enable_reg & ~(0x0004)); in amd_irongate_cleanup()
259 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_cleanup()
/linux-4.1.27/drivers/clk/ti/
Dgate.c114 clk_hw->enable_reg = reg; in _register_gate()
195 reg = (struct clk_omap_reg *)&gate->enable_reg; in ti_clk_build_component_gate()
266 gate->enable_reg = ti_clk_get_reg_addr(node, 0); in _of_ti_composite_gate_clk_setup()
267 if (IS_ERR(gate->enable_reg)) in _of_ti_composite_gate_clk_setup()
Dinterface.c51 clk_hw->enable_reg = reg; in _register_interface()
/linux-4.1.27/drivers/acpi/acpica/
Devgpe.c340 u32 enable_reg; in acpi_ev_gpe_detect() local
409 acpi_hw_read(&enable_reg, in acpi_ev_gpe_detect()
421 status_reg, enable_reg, in acpi_ev_gpe_detect()
427 enabled_status_byte = (u8)(status_reg & enable_reg); in acpi_ev_gpe_detect()
/linux-4.1.27/drivers/sh/clk/
Dcpg.c61 (phys_addr_t)clk->enable_reg + clk->mapped_reg; in sh_clk_mstp_enable()
76 clk->enable_reg, clk->enable_bit); in sh_clk_mstp_enable()
481 map->phys = (phys_addr_t)clks[i].enable_reg; in sh_clk_fsidiv_register()
484 clks[i].enable_reg = 0; /* remove .enable_reg */ in sh_clk_fsidiv_register()
Dcore.c383 clk->mapped_reg += (phys_addr_t)clk->enable_reg - clk->mapping->phys; in clk_establish_mapping()
/linux-4.1.27/arch/arm/mach-shmobile/
Dclock-sh73a0.c99 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1); in pll_recalc()
104 if (__raw_readl(clk->enable_reg) & (1 << 20)) in pll_recalc()
120 .enable_reg = (void __iomem *)PLL0CR,
128 .enable_reg = (void __iomem *)PLL1CR,
136 .enable_reg = (void __iomem *)PLL2CR,
144 .enable_reg = (void __iomem *)PLL3CR,
Dclock-r8a7740.c128 mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1; in pllc01_recalc()
141 .enable_reg = (void __iomem *)FRQCRC,
148 .enable_reg = (void __iomem *)FRQCRA,
/linux-4.1.27/Documentation/devicetree/bindings/interrupt-controller/
Dbrcm,bcm3380-l2-intc.txt17 <enable_reg 0x4 status_reg 0x4>...
/linux-4.1.27/drivers/clk/zynq/
Dclkc.c110 u32 enable_reg; in zynq_clk_register_fclk() local
153 enable_reg = clk_readl(fclk_gate_reg) & 1; in zynq_clk_register_fclk()
154 if (enable && !enable_reg) { in zynq_clk_register_fclk()
/linux-4.1.27/include/linux/regulator/
Ddriver.h293 unsigned int enable_reg; member
/linux-4.1.27/include/linux/clk/
Dti.h142 void __iomem *enable_reg; member
/linux-4.1.27/arch/arm/plat-omap/
Ddma.c1215 u32 val, enable_reg; in omap2_dma_irq_handler() local
1224 enable_reg = p->dma_read(IRQENABLE_L0, 0); in omap2_dma_irq_handler()
1225 val &= enable_reg; /* Dispatch only relevant interrupts */ in omap2_dma_irq_handler()
/linux-4.1.27/arch/sh/drivers/pci/
Dpcie-sh7786.c239 clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); in pcie_clk_init()
/linux-4.1.27/drivers/video/fbdev/omap2/dss/
Ddsi.c870 const struct dsi_reg enable_reg, in _omap_dsi_configure_irqs() argument
889 old_mask = dsi_read_reg(dsidev, enable_reg); in _omap_dsi_configure_irqs()
892 dsi_write_reg(dsidev, enable_reg, mask); in _omap_dsi_configure_irqs()
895 dsi_read_reg(dsidev, enable_reg); in _omap_dsi_configure_irqs()