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Searched refs:nv_wo32 (Results 1 – 47 of 47) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv25.c50 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); in nv25_gr_context_ctor()
51 nv_wo32(chan, 0x035c, 0xffff0000); in nv25_gr_context_ctor()
52 nv_wo32(chan, 0x03c0, 0x0fff0000); in nv25_gr_context_ctor()
53 nv_wo32(chan, 0x03c4, 0x0fff0000); in nv25_gr_context_ctor()
54 nv_wo32(chan, 0x049c, 0x00000101); in nv25_gr_context_ctor()
55 nv_wo32(chan, 0x04b0, 0x00000111); in nv25_gr_context_ctor()
56 nv_wo32(chan, 0x04c8, 0x00000080); in nv25_gr_context_ctor()
57 nv_wo32(chan, 0x04cc, 0xffff0000); in nv25_gr_context_ctor()
58 nv_wo32(chan, 0x04d0, 0x00000001); in nv25_gr_context_ctor()
59 nv_wo32(chan, 0x04e4, 0x44400000); in nv25_gr_context_ctor()
[all …]
Dnv35.c52 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); in nv35_gr_context_ctor()
53 nv_wo32(chan, 0x040c, 0x00000101); in nv35_gr_context_ctor()
54 nv_wo32(chan, 0x0420, 0x00000111); in nv35_gr_context_ctor()
55 nv_wo32(chan, 0x0424, 0x00000060); in nv35_gr_context_ctor()
56 nv_wo32(chan, 0x0440, 0x00000080); in nv35_gr_context_ctor()
57 nv_wo32(chan, 0x0444, 0xffff0000); in nv35_gr_context_ctor()
58 nv_wo32(chan, 0x0448, 0x00000001); in nv35_gr_context_ctor()
59 nv_wo32(chan, 0x045c, 0x44400000); in nv35_gr_context_ctor()
60 nv_wo32(chan, 0x0488, 0xffff0000); in nv35_gr_context_ctor()
62 nv_wo32(chan, i, 0x0fff0000); in nv35_gr_context_ctor()
[all …]
Dnv34.c52 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); in nv34_gr_context_ctor()
53 nv_wo32(chan, 0x040c, 0x01000101); in nv34_gr_context_ctor()
54 nv_wo32(chan, 0x0420, 0x00000111); in nv34_gr_context_ctor()
55 nv_wo32(chan, 0x0424, 0x00000060); in nv34_gr_context_ctor()
56 nv_wo32(chan, 0x0440, 0x00000080); in nv34_gr_context_ctor()
57 nv_wo32(chan, 0x0444, 0xffff0000); in nv34_gr_context_ctor()
58 nv_wo32(chan, 0x0448, 0x00000001); in nv34_gr_context_ctor()
59 nv_wo32(chan, 0x045c, 0x44400000); in nv34_gr_context_ctor()
60 nv_wo32(chan, 0x0480, 0xffff0000); in nv34_gr_context_ctor()
62 nv_wo32(chan, i, 0x0fff0000); in nv34_gr_context_ctor()
[all …]
Dnv2a.c26 nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); in nv2a_gr_context_ctor()
27 nv_wo32(chan, 0x033c, 0xffff0000); in nv2a_gr_context_ctor()
28 nv_wo32(chan, 0x03a0, 0x0fff0000); in nv2a_gr_context_ctor()
29 nv_wo32(chan, 0x03a4, 0x0fff0000); in nv2a_gr_context_ctor()
30 nv_wo32(chan, 0x047c, 0x00000101); in nv2a_gr_context_ctor()
31 nv_wo32(chan, 0x0490, 0x00000111); in nv2a_gr_context_ctor()
32 nv_wo32(chan, 0x04a8, 0x44400000); in nv2a_gr_context_ctor()
34 nv_wo32(chan, i, 0x00030303); in nv2a_gr_context_ctor()
36 nv_wo32(chan, i, 0x00080000); in nv2a_gr_context_ctor()
38 nv_wo32(chan, i, 0x01012000); in nv2a_gr_context_ctor()
[all …]
Dnv30.c54 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); in nv30_gr_context_ctor()
55 nv_wo32(chan, 0x0410, 0x00000101); in nv30_gr_context_ctor()
56 nv_wo32(chan, 0x0424, 0x00000111); in nv30_gr_context_ctor()
57 nv_wo32(chan, 0x0428, 0x00000060); in nv30_gr_context_ctor()
58 nv_wo32(chan, 0x0444, 0x00000080); in nv30_gr_context_ctor()
59 nv_wo32(chan, 0x0448, 0xffff0000); in nv30_gr_context_ctor()
60 nv_wo32(chan, 0x044c, 0x00000001); in nv30_gr_context_ctor()
61 nv_wo32(chan, 0x0460, 0x44400000); in nv30_gr_context_ctor()
62 nv_wo32(chan, 0x048c, 0xffff0000); in nv30_gr_context_ctor()
64 nv_wo32(chan, i, 0x0fff0000); in nv30_gr_context_ctor()
[all …]
Dnv20.c55 nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); in nv20_gr_context_ctor()
56 nv_wo32(chan, 0x033c, 0xffff0000); in nv20_gr_context_ctor()
57 nv_wo32(chan, 0x03a0, 0x0fff0000); in nv20_gr_context_ctor()
58 nv_wo32(chan, 0x03a4, 0x0fff0000); in nv20_gr_context_ctor()
59 nv_wo32(chan, 0x047c, 0x00000101); in nv20_gr_context_ctor()
60 nv_wo32(chan, 0x0490, 0x00000111); in nv20_gr_context_ctor()
61 nv_wo32(chan, 0x04a8, 0x44400000); in nv20_gr_context_ctor()
63 nv_wo32(chan, i, 0x00030303); in nv20_gr_context_ctor()
65 nv_wo32(chan, i, 0x00080000); in nv20_gr_context_ctor()
67 nv_wo32(chan, i, 0x01012000); in nv20_gr_context_ctor()
[all …]
Dctxgf100.c1283 nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000)); in gf100_grctx_generate()
1284 nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000)); in gf100_grctx_generate()
1285 nv_wo32(chan, 0x0208, 0xffffffff); in gf100_grctx_generate()
1286 nv_wo32(chan, 0x020c, 0x000000ff); in gf100_grctx_generate()
1289 nv_wo32(chan, 0x1000, 0x00000000); in gf100_grctx_generate()
1290 nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8); in gf100_grctx_generate()
1295 nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr)); in gf100_grctx_generate()
1296 nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr)); in gf100_grctx_generate()
1300 nv_wo32(chan, 0x0210, 0x00080004); in gf100_grctx_generate()
1301 nv_wo32(chan, 0x0214, 0x00000000); in gf100_grctx_generate()
[all …]
Dnv40.c68 nv_wo32(obj, 0x00, nv_mclass(obj)); in nv40_gr_object_ctor()
69 nv_wo32(obj, 0x04, 0x00000000); in nv40_gr_object_ctor()
70 nv_wo32(obj, 0x08, 0x00000000); in nv40_gr_object_ctor()
74 nv_wo32(obj, 0x0c, 0x00000000); in nv40_gr_object_ctor()
75 nv_wo32(obj, 0x10, 0x00000000); in nv40_gr_object_ctor()
151 nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4); in nv40_gr_context_ctor()
Dgf100.c334 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); in gf100_gr_context_ctor()
335 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data); in gf100_gr_context_ctor()
340 nv_wo32(chan, i, priv->data[i / 4]); in gf100_gr_context_ctor()
343 nv_wo32(chan, 0x00, chan->mmio_nr / 2); in gf100_gr_context_ctor()
344 nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8); in gf100_gr_context_ctor()
346 nv_wo32(chan, 0xf4, 0); in gf100_gr_context_ctor()
347 nv_wo32(chan, 0xf8, 0); in gf100_gr_context_ctor()
348 nv_wo32(chan, 0x10, chan->mmio_nr / 2); in gf100_gr_context_ctor()
349 nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset)); in gf100_gr_context_ctor()
350 nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset)); in gf100_gr_context_ctor()
[all …]
Dnv04.c456 nv_wo32(object, 0x00, tmp); in nv04_gr_set_ctx1()
475 nv_wo32(object, 0x0c, tmp); in nv04_gr_set_ctx_val()
964 nv_wo32(obj, 0x00, nv_mclass(obj)); in nv04_gr_object_ctor()
968 nv_wo32(obj, 0x04, 0x00000000); in nv04_gr_object_ctor()
969 nv_wo32(obj, 0x08, 0x00000000); in nv04_gr_object_ctor()
970 nv_wo32(obj, 0x0c, 0x00000000); in nv04_gr_object_ctor()
Dnv50.c68 nv_wo32(obj, 0x00, nv_mclass(obj)); in nv50_gr_object_ctor()
69 nv_wo32(obj, 0x04, 0x00000000); in nv50_gr_object_ctor()
70 nv_wo32(obj, 0x08, 0x00000000); in nv50_gr_object_ctor()
71 nv_wo32(obj, 0x0c, 0x00000000); in nv50_gr_object_ctor()
Dctxnv40.c586 nv_wo32(obj, offset * 4, 0x3f800000); in nv40_gr_construct_shader()
590 nv_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001); in nv40_gr_construct_shader()
592 nv_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000); in nv40_gr_construct_shader()
Dctxnv40.h127 nv_wo32(ctx->data, reg * 4, val); in gr_def()
Dctxnv50.c789 nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val); in dd_emit()
1161 nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val); in xf_emit()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/
Dfalcon.c36 nv_wo32(falcon, 0x004, 0x00000010); in nvkm_falcon_intr()
42 nv_wo32(falcon, 0x004, intr); in nvkm_falcon_intr()
110 nv_wo32(falcon, 0x004, 0x00000010); in _nvkm_falcon_init()
114 nv_wo32(falcon, 0x014, 0xffffffff); in _nvkm_falcon_init()
183 nv_wo32(falcon->core, i, falcon->code.data[i / 4]); in _nvkm_falcon_init()
189 nv_wo32(falcon, 0x618, 0x04000000); in _nvkm_falcon_init()
191 nv_wo32(falcon, 0x618, 0x00000114); in _nvkm_falcon_init()
192 nv_wo32(falcon, 0x11c, 0); in _nvkm_falcon_init()
193 nv_wo32(falcon, 0x110, falcon->core->addr >> 8); in _nvkm_falcon_init()
194 nv_wo32(falcon, 0x114, 0); in _nvkm_falcon_init()
[all …]
Dxtensa.c66 nv_wo32(xtensa, 0xc20, intr); in _nvkm_xtensa_intr()
135 nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i)); in _nvkm_xtensa_init()
139 nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */ in _nvkm_xtensa_init()
140 nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */ in _nvkm_xtensa_init()
142 nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */ in _nvkm_xtensa_init()
143 nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ in _nvkm_xtensa_init()
144 nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ in _nvkm_xtensa_init()
146 nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */ in _nvkm_xtensa_init()
147 nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */ in _nvkm_xtensa_init()
148 nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */ in _nvkm_xtensa_init()
[all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dg84.c68 nv_wo32(base->eng, addr + 0x00, 0x00190000); in g84_fifo_context_attach()
69 nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); in g84_fifo_context_attach()
70 nv_wo32(base->eng, addr + 0x08, lower_32_bits(start)); in g84_fifo_context_attach()
71 nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | in g84_fifo_context_attach()
73 nv_wo32(base->eng, addr + 0x10, 0x00000000); in g84_fifo_context_attach()
74 nv_wo32(base->eng, addr + 0x14, 0x00000000); in g84_fifo_context_attach()
117 nv_wo32(base->eng, addr + 0x00, 0x00000000); in g84_fifo_context_detach()
118 nv_wo32(base->eng, addr + 0x04, 0x00000000); in g84_fifo_context_detach()
119 nv_wo32(base->eng, addr + 0x08, 0x00000000); in g84_fifo_context_detach()
120 nv_wo32(base->eng, addr + 0x0c, 0x00000000); in g84_fifo_context_detach()
[all …]
Dnv50.c53 nv_wo32(cur, p++ * 4, i); in nv50_fifo_playlist_update_locked()
90 nv_wo32(base->eng, addr + 0x00, 0x00190000); in nv50_fifo_context_attach()
91 nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); in nv50_fifo_context_attach()
92 nv_wo32(base->eng, addr + 0x08, lower_32_bits(start)); in nv50_fifo_context_attach()
93 nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | in nv50_fifo_context_attach()
95 nv_wo32(base->eng, addr + 0x10, 0x00000000); in nv50_fifo_context_attach()
96 nv_wo32(base->eng, addr + 0x14, 0x00000000); in nv50_fifo_context_attach()
145 nv_wo32(base->eng, addr + 0x00, 0x00000000); in nv50_fifo_context_detach()
146 nv_wo32(base->eng, addr + 0x04, 0x00000000); in nv50_fifo_context_detach()
147 nv_wo32(base->eng, addr + 0x08, 0x00000000); in nv50_fifo_context_detach()
[all …]
Dgf100.c90 nv_wo32(cur, p + 0, i); in gf100_fifo_runlist_update()
91 nv_wo32(cur, p + 4, 0x00000004); in gf100_fifo_runlist_update()
138 nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); in gf100_fifo_context_attach()
139 nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset)); in gf100_fifo_context_attach()
174 nv_wo32(base, addr + 0x00, 0x00000000); in gf100_fifo_context_detach()
175 nv_wo32(base, addr + 0x04, 0x00000000); in gf100_fifo_context_detach()
228 nv_wo32(priv->user.mem, usermem + i, 0x00000000); in gf100_fifo_chan_ctor()
230 nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem)); in gf100_fifo_chan_ctor()
231 nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem)); in gf100_fifo_chan_ctor()
232 nv_wo32(base, 0x10, 0x0000face); in gf100_fifo_chan_ctor()
[all …]
Dgk104.c110 nv_wo32(cur, p + 0, i); in gk104_fifo_runlist_update()
111 nv_wo32(cur, p + 4, 0x00000000); in gk104_fifo_runlist_update()
162 nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); in gk104_fifo_context_attach()
163 nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset)); in gk104_fifo_context_attach()
200 nv_wo32(base, addr + 0x00, 0x00000000); in gk104_fifo_context_detach()
201 nv_wo32(base, addr + 0x04, 0x00000000); in gk104_fifo_context_detach()
265 nv_wo32(priv->user.mem, usermem + i, 0x00000000); in gk104_fifo_chan_ctor()
267 nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem)); in gk104_fifo_chan_ctor()
268 nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem)); in gk104_fifo_chan_ctor()
269 nv_wo32(base, 0x10, 0x0000face); in gk104_fifo_chan_ctor()
[all …]
Dnv40.c133 nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr); in nv40_fifo_context_attach()
169 nv_wo32(priv->ramfc, chan->ramfc + ctx, 0x00000000); in nv40_fifo_context_detach()
214 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv40_fifo_chan_ctor()
215 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv40_fifo_chan_ctor()
216 nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); in nv40_fifo_chan_ctor()
217 nv_wo32(priv->ramfc, chan->ramfc + 0x18, 0x30000000 | in nv40_fifo_chan_ctor()
224 nv_wo32(priv->ramfc, chan->ramfc + 0x3c, 0x0001ffff); in nv40_fifo_chan_ctor()
Dnv10.c89 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv10_fifo_chan_ctor()
90 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv10_fifo_chan_ctor()
91 nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); in nv10_fifo_chan_ctor()
92 nv_wo32(priv->ramfc, chan->ramfc + 0x14, in nv10_fifo_chan_ctor()
Dnv17.c96 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv17_fifo_chan_ctor()
97 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv17_fifo_chan_ctor()
98 nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); in nv17_fifo_chan_ctor()
99 nv_wo32(priv->ramfc, chan->ramfc + 0x14, in nv17_fifo_chan_ctor()
Dnv04.c146 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv04_fifo_chan_ctor()
147 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv04_fifo_chan_ctor()
148 nv_wo32(priv->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4); in nv04_fifo_chan_ctor()
149 nv_wo32(priv->ramfc, chan->ramfc + 0x10, in nv04_fifo_chan_ctor()
167 nv_wo32(priv->ramfc, chan->ramfc + c->ctxp, 0x00000000); in nv04_fifo_chan_dtor()
220 nv_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs)); in nv04_fifo_chan_fini()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dnv44.c78 nv_wo32(pgt, base + 0x0, tmp[0]); in nv44_vm_fill()
79 nv_wo32(pgt, base + 0x4, tmp[1]); in nv44_vm_fill()
80 nv_wo32(pgt, base + 0x8, tmp[2]); in nv44_vm_fill()
81 nv_wo32(pgt, base + 0xc, tmp[3] | 0x40000000); in nv44_vm_fill()
104 nv_wo32(pgt, pte++ * 4, tmp[0] >> 0 | tmp[1] << 27); in nv44_vm_map_sg()
105 nv_wo32(pgt, pte++ * 4, tmp[1] >> 5 | tmp[2] << 22); in nv44_vm_map_sg()
106 nv_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17); in nv44_vm_map_sg()
107 nv_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000); in nv44_vm_map_sg()
129 nv_wo32(pgt, pte++ * 4, 0x00000000); in nv44_vm_unmap()
130 nv_wo32(pgt, pte++ * 4, 0x00000000); in nv44_vm_unmap()
[all …]
Dgf100.c87 nv_wo32(pgd, (index * 8) + 0, pde[0]); in gf100_vm_map_pgt()
88 nv_wo32(pgd, (index * 8) + 4, pde[1]); in gf100_vm_map_pgt()
123 nv_wo32(pgt, pte + 0, lower_32_bits(phys)); in gf100_vm_map()
124 nv_wo32(pgt, pte + 4, upper_32_bits(phys)); in gf100_vm_map()
141 nv_wo32(pgt, pte + 0, lower_32_bits(phys)); in gf100_vm_map_sg()
142 nv_wo32(pgt, pte + 4, upper_32_bits(phys)); in gf100_vm_map_sg()
152 nv_wo32(pgt, pte + 0, 0x00000000); in gf100_vm_unmap()
153 nv_wo32(pgt, pte + 4, 0x00000000); in gf100_vm_unmap()
Dnv50.c60 nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys)); in nv50_vm_map_pgt()
61 nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys)); in nv50_vm_map_pgt()
116 nv_wo32(pgt, pte + 0, offset_l); in nv50_vm_map()
117 nv_wo32(pgt, pte + 4, offset_h); in nv50_vm_map()
132 nv_wo32(pgt, pte + 0, lower_32_bits(phys)); in nv50_vm_map_sg()
133 nv_wo32(pgt, pte + 4, upper_32_bits(phys)); in nv50_vm_map_sg()
143 nv_wo32(pgt, pte + 0, 0x00000000); in nv50_vm_unmap()
144 nv_wo32(pgt, pte + 4, 0x00000000); in nv50_vm_unmap()
Dnv04.c45 nv_wo32(pgt, pte, phys | 3); in nv04_vm_map_sg()
58 nv_wo32(pgt, pte, 0x00000000); in nv04_vm_unmap()
122 nv_wo32(dma, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */ in nv04_mmu_ctor()
123 nv_wo32(dma, 0x00004, NV04_PDMA_SIZE - 1); in nv04_mmu_ctor()
Dnv41.c47 nv_wo32(pgt, pte, (phys >> 7) | 1); in nv41_vm_map_sg()
60 nv_wo32(pgt, pte, 0x00000000); in nv41_vm_unmap()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
Dnv50.c164 nv_wo32(priv->bar3, 0x00, 0x7fc00000); in nv50_bar_ctor()
165 nv_wo32(priv->bar3, 0x04, lower_32_bits(limit)); in nv50_bar_ctor()
166 nv_wo32(priv->bar3, 0x08, lower_32_bits(start)); in nv50_bar_ctor()
167 nv_wo32(priv->bar3, 0x0c, upper_32_bits(limit) << 24 | in nv50_bar_ctor()
169 nv_wo32(priv->bar3, 0x10, 0x00000000); in nv50_bar_ctor()
170 nv_wo32(priv->bar3, 0x14, 0x00000000); in nv50_bar_ctor()
191 nv_wo32(priv->bar1, 0x00, 0x7fc00000); in nv50_bar_ctor()
192 nv_wo32(priv->bar1, 0x04, lower_32_bits(limit)); in nv50_bar_ctor()
193 nv_wo32(priv->bar1, 0x08, lower_32_bits(start)); in nv50_bar_ctor()
194 nv_wo32(priv->bar1, 0x0c, upper_32_bits(limit) << 24 | in nv50_bar_ctor()
[all …]
Dgf100.c126 nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr)); in gf100_bar_ctor_vm()
127 nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr)); in gf100_bar_ctor_vm()
128 nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1)); in gf100_bar_ctor_vm()
129 nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1)); in gf100_bar_ctor_vm()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/
Dgf110.c66 nv_wo32(*pgpuobj, 0x00, priv->flags0); in gf110_dmaobj_bind()
67 nv_wo32(*pgpuobj, 0x04, priv->base.start >> 8); in gf110_dmaobj_bind()
68 nv_wo32(*pgpuobj, 0x08, priv->base.limit >> 8); in gf110_dmaobj_bind()
69 nv_wo32(*pgpuobj, 0x0c, 0x00000000); in gf110_dmaobj_bind()
70 nv_wo32(*pgpuobj, 0x10, 0x00000000); in gf110_dmaobj_bind()
71 nv_wo32(*pgpuobj, 0x14, 0x00000000); in gf110_dmaobj_bind()
Dgf100.c60 nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj)); in gf100_dmaobj_bind()
61 nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit)); in gf100_dmaobj_bind()
62 nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start)); in gf100_dmaobj_bind()
63 nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 | in gf100_dmaobj_bind()
65 nv_wo32(*pgpuobj, 0x10, 0x00000000); in gf100_dmaobj_bind()
66 nv_wo32(*pgpuobj, 0x14, priv->flags5); in gf100_dmaobj_bind()
Dnv50.c72 nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj)); in nv50_dmaobj_bind()
73 nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit)); in nv50_dmaobj_bind()
74 nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start)); in nv50_dmaobj_bind()
75 nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 | in nv50_dmaobj_bind()
77 nv_wo32(*pgpuobj, 0x10, 0x00000000); in nv50_dmaobj_bind()
78 nv_wo32(*pgpuobj, 0x14, priv->flags5); in nv50_dmaobj_bind()
Dnv04.c74 nv_wo32(*pgpuobj, 0x00, priv->flags0 | (adjust << 20)); in nv04_dmaobj_bind()
75 nv_wo32(*pgpuobj, 0x04, length); in nv04_dmaobj_bind()
76 nv_wo32(*pgpuobj, 0x08, priv->flags2 | offset); in nv04_dmaobj_bind()
77 nv_wo32(*pgpuobj, 0x0c, priv->flags2 | offset); in nv04_dmaobj_bind()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv50.c56 nv_wo32(obj, 0x00, nv_mclass(obj)); in nv50_mpeg_object_ctor()
57 nv_wo32(obj, 0x04, 0x00000000); in nv50_mpeg_object_ctor()
58 nv_wo32(obj, 0x08, 0x00000000); in nv50_mpeg_object_ctor()
59 nv_wo32(obj, 0x0c, 0x00000000); in nv50_mpeg_object_ctor()
99 nv_wo32(chan, 0x0070, 0x00801ec1); in nv50_mpeg_context_ctor()
100 nv_wo32(chan, 0x007c, 0x0000037c); in nv50_mpeg_context_ctor()
Dnv31.c52 nv_wo32(obj, 0x00, nv_mclass(obj)); in nv31_mpeg_object_ctor()
53 nv_wo32(obj, 0x04, 0x00000000); in nv31_mpeg_object_ctor()
54 nv_wo32(obj, 0x08, 0x00000000); in nv31_mpeg_object_ctor()
55 nv_wo32(obj, 0x0c, 0x00000000); in nv31_mpeg_object_ctor()
Dnv44.c57 nv_wo32(&chan->base.base, 0x78, 0x02001ec1); in nv44_mpeg_context_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/core/
Dramht.c51 nv_wo32(ramht, co + 0, handle); in nvkm_ramht_insert()
52 nv_wo32(ramht, co + 4, context); in nvkm_ramht_insert()
70 nv_wo32(ramht, cookie + 0, 0x00000000); in nvkm_ramht_remove()
71 nv_wo32(ramht, cookie + 4, 0x00000000); in nvkm_ramht_remove()
Dgpuobj.c38 nv_wo32(gpuobj, i, 0x00000000); in nvkm_gpuobj_destroy()
129 nv_wo32(gpuobj, i, 0x00000000); in nvkm_gpuobj_create_()
Dioctl.c295 nv_wo32(object, args->v0.addr, args->v0.data); in nvkm_ioctl_wr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
Dg84.c54 nv_wo32(obj, 0x00, nv_mclass(obj)); in g84_cipher_object_ctor()
55 nv_wo32(obj, 0x04, 0x00000000); in g84_cipher_object_ctor()
56 nv_wo32(obj, 0x08, 0x00000000); in g84_cipher_object_ctor()
57 nv_wo32(obj, 0x0c, 0x00000000); in g84_cipher_object_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/ce/
Dgt215.c103 nv_wo32(falcon, 0x004, 0x00000040); in gt215_ce_intr()
109 nv_wo32(falcon, 0x004, stat); in gt215_ce_intr()
Dgf100.c88 nv_wo32(priv, 0x084, nv_engidx(&priv->base.base) - NVDEV_ENGINE_CE0); in gf100_ce_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/
Dobject.h176 nv_wo32(void *obj, u64 addr, u32 data) in nv_wo32() function
186 nv_wo32(obj, addr, (temp & ~mask) | data); in nv_mo32()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dbase.c121 nv_wo32(iobj, i, iobj->suspend[i / 4]); in _nvkm_instmem_init()
Dnv04.c45 nv_wo32(priv, node->mem->offset + addr, data); in nv04_instobj_wr32()