Home
last modified time | relevance | path

Searched refs:pll1 (Results 1 – 50 of 50) sorted by relevance

/linux-4.1.27/arch/powerpc/boot/dts/fsl/
Dqoriq-clockgen1.dtsi55 pll1: pll1@820 { label
60 clock-output-names = "pll1", "pll1-div2";
66 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
67 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
74 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
75 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dt1040si-post.dtsi355 <&pll1 0>, <&pll1 1>, <&pll1 2>;
356 clock-names = "pll0", "pll0-div2", "pll1-div4",
357 "pll1", "pll1-div2", "pll1-div4";
366 <&pll1 0>, <&pll1 1>, <&pll1 2>;
367 clock-names = "pll0", "pll0-div2", "pll1-div4",
368 "pll1", "pll1-div2", "pll1-div4";
377 <&pll1 0>, <&pll1 1>, <&pll1 2>;
378 clock-names = "pll0", "pll0-div2", "pll1-div4",
379 "pll1", "pll1-div2", "pll1-div4";
388 <&pll1 0>, <&pll1 1>, <&pll1 2>;
Db4420si-post.dtsi92 <&pll1 0>, <&pll1 1>, <&pll1 2>;
94 "pll1", "pll1-div2", "pll1-div4";
Dqoriq-clockgen2.dtsi54 pll1: pll1@820 { label
59 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
Dt2081si-post.dtsi419 <&pll1 0>, <&pll1 1>, <&pll1 2>;
420 clock-names = "pll0", "pll0-div2", "pll1-div4",
421 "pll1", "pll1-div2", "pll1-div4";
430 <&pll1 0>, <&pll1 1>, <&pll1 2>;
431 clock-names = "pll0", "pll0-div2", "pll1-div4",
432 "pll1", "pll1-div2", "pll1-div4";
Db4860si-post.dtsi194 <&pll1 0>, <&pll1 1>, <&pll1 2>;
196 "pll1", "pll1-div2", "pll1-div4";
Dp3041si-post.dtsi350 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
351 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
359 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
360 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp5040si-post.dtsi315 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
316 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
324 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
325 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp2041si-post.dtsi323 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
324 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
332 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
333 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dt4240si-post.dtsi666 <&pll1 0>, <&pll1 1>, <&pll1 2>,
669 "pll1", "pll1-div2", "pll1-div4",
679 <&pll1 0>, <&pll1 1>, <&pll1 2>,
682 "pll1", "pll1-div2", "pll1-div4",
Dp4080si-post.dtsi386 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
387 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
395 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
396 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
/linux-4.1.27/arch/avr32/boards/favr-32/
Dsetup.c277 struct clk *pll1; in set_abdac_rate() local
289 pll1 = clk_get(NULL, "pll1"); in set_abdac_rate()
290 if (IS_ERR(pll1)) { in set_abdac_rate()
291 retval = PTR_ERR(pll1); in set_abdac_rate()
301 retval = clk_set_parent(pll1, osc1); in set_abdac_rate()
311 retval = clk_round_rate(pll1, in set_abdac_rate()
318 retval = clk_set_rate(pll1, retval); in set_abdac_rate()
322 retval = clk_set_parent(abdac, pll1); in set_abdac_rate()
329 clk_put(pll1); in set_abdac_rate()
/linux-4.1.27/Documentation/devicetree/bindings/clock/
Dqoriq-clock.txt109 pll1: pll1@820 {
114 clock-output-names = "pll1", "pll1-div2";
121 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
122 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
130 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
131 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Drenesas,r8a73a4-cpg-clocks.txt17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
Drenesas,sh73a0-cpg-clocks.txt19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
Drenesas,rcar-gen2-cpg-clocks.txt21 "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
34 clock-output-names = "main", "pll0, "pll1", "pll3",
Dsunxi.txt10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
127 pll1: clk@01c20000 {
129 compatible = "allwinner,sun4i-a10-pll1-clk";
132 clock-output-names = "pll1";
155 clocks = <&osc32k>, <&osc24M>, <&pll1>;
Dsilabs,si5351.txt77 /* connect xtal input as source of pll0 and pll1 */
100 * - pll1 as clock source of multisynth1
102 * - multisynth1 can change pll1
Dprima2-clock.txt17 pll1 2
Dimx28-clock.txt16 pll1 2
/linux-4.1.27/arch/arm/boot/dts/
Dstih415-clock.dtsi40 "clk-s-a0-pll1";
98 "clk-s-a1-pll1";
165 clk_m_a0_pll1: clk-m-a0-pll1 {
171 clock-output-names = "clk-m-a0-pll1-phi0",
172 "clk-m-a0-pll1-phi1",
173 "clk-m-a0-pll1-phi2",
174 "clk-m-a0-pll1-phi3";
279 clk_m_a1_pll1: clk-m-a1-pll1 {
285 clock-output-names = "clk-m-a1-pll1-phi0",
286 "clk-m-a1-pll1-phi1",
[all …]
Dstih416-clock.dtsi41 "clk-s-a0-pll1";
99 "clk-s-a1-pll1";
167 clk_m_a0_pll1: clk-m-a0-pll1 {
173 clock-output-names = "clk-m-a0-pll1-phi0",
174 "clk-m-a0-pll1-phi1",
175 "clk-m-a0-pll1-phi2",
176 "clk-m-a0-pll1-phi3";
281 clk_m_a1_pll1: clk-m-a1-pll1 {
287 clock-output-names = "clk-m-a1-pll1-phi0",
288 "clk-m-a1-pll1-phi1",
[all …]
Dsun5i-a13.dtsi131 pll1: clk@01c20000 { label
133 compatible = "allwinner,sun4i-a10-pll1-clk";
136 clock-output-names = "pll1";
141 compatible = "allwinner,sun4i-a10-pll1-clk";
168 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
Dsun5i-a10s.dtsi90 pll1: clk@01c20000 { label
92 compatible = "allwinner,sun4i-a10-pll1-clk";
95 clock-output-names = "pll1";
100 compatible = "allwinner,sun4i-a10-pll1-clk";
127 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
Dsun8i-a23.dtsi113 pll1: clk@01c20000 { label
115 compatible = "allwinner,sun8i-a23-pll1-clk";
118 clock-output-names = "pll1";
148 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
Dls1021a.dtsi164 clock-output-names = "cga-pll1", "cga-pll1-div2",
165 "cga-pll1-div4";
Ddove-cubox.dts92 /* connect xtal input as source of pll0 and pll1 */
Dsun4i-a10.dtsi157 pll1: clk@01c20000 { label
159 compatible = "allwinner,sun4i-a10-pll1-clk";
162 clock-output-names = "pll1";
167 compatible = "allwinner,sun4i-a10-pll1-clk";
194 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
Dstih407-clock.dtsi144 clk_s_c0_pll1: clk-s-c0-pll1 {
150 clock-output-names = "clk-s-c0-pll1-odf-0";
Dstih410-clock.dtsi147 clk_s_c0_pll1: clk-s-c0-pll1 {
153 clock-output-names = "clk-s-c0-pll1-odf-0";
Dstih418-clock.dtsi147 clk_s_c0_pll1: clk-s-c0-pll1 {
153 clock-output-names = "clk-s-c0-pll1-odf-0";
Dsun6i-a31.dtsi154 pll1: clk@01c20000 { label
156 compatible = "allwinner,sun6i-a31-pll1-clk";
159 clock-output-names = "pll1";
181 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
Dste-nomadik-stn8815.dtsi195 pll1: pll1@0 { label
206 clocks = <&pll1>;
Dsun7i-a20.dtsi198 pll1: clk@01c20000 { label
200 compatible = "allwinner,sun4i-a10-pll1-clk";
203 clock-output-names = "pll1";
242 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
Dr8a7794.dtsi388 clock-output-names = "main", "pll0", "pll1", "pll3",
Dr8a73a4.dtsi502 clock-output-names = "main", "pll0", "pll1", "pll2",
Dsh73a0.dtsi585 clock-output-names = "main", "pll0", "pll1", "pll2",
Dr8a7790.dtsi888 clock-output-names = "main", "pll0", "pll1", "pll3",
Dr8a7791.dtsi909 clock-output-names = "main", "pll0", "pll1", "pll3",
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c204 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
213 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
228 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
230 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
264 nv_wr32(devinit, reg1, pll1); in setPLL_double_highregs()
/linux-4.1.27/drivers/gpu/drm/tegra/
Dhdmi.c28 u32 pll1; member
173 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
188 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
206 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
220 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
234 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
251 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
269 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
288 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
307 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
[all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/dispnv04/
Dhw.c132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/clock/st/
Dst,clkgen.txt72 "clk-s-a0-pll1";
92 <&clk-s_a0_pll 2>; /* pll1 */
Dst,clkgen-pll.txt49 "clk-s-a0-pll1";
/linux-4.1.27/drivers/clk/sirf/
Dclk-prima2.c62 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
138 for (i = pll1; i < maxclk; i++) { in prima2_clk_init()
Dclk-atlas6.c63 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
139 for (i = pll1; i < maxclk; i++) { in atlas6_clk_init()
/linux-4.1.27/drivers/clk/mxs/
Dclk-imx28.c139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
175 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
/linux-4.1.27/Documentation/devicetree/bindings/video/
Dti,dra7-dss.txt24 'pll1', 'pll2_clkctrl', 'pll2'
/linux-4.1.27/arch/avr32/mach-at32ap/
Dat32ap700x.c316 static struct clk pll1 = { variable
572 if (parent == &osc1 || parent == &pll1) in genclk_set_parent()
579 if (parent == &pll0 || parent == &pll1) in genclk_set_parent()
599 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1; in genclk_init_parent()
2224 &pll1,
2300 pll1.parent = &osc1; in setup_platform()
/linux-4.1.27/Documentation/
Dprintk-formats.txt266 %pC pll1
267 %pCn pll1