Home
last modified time | relevance | path

Searched refs:write_aux_reg (Results 1 – 9 of 9) sorted by relevance

/linux-4.1.27/arch/arc/mm/
Dtlb.c111 write_aux_reg(ARC_REG_TLBPD1, 0); in __tlb_entry_erase()
112 write_aux_reg(ARC_REG_TLBPD0, 0); in __tlb_entry_erase()
113 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); in __tlb_entry_erase()
120 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid); in tlb_entry_lkup()
122 write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe); in tlb_entry_lkup()
175 write_aux_reg(ARC_REG_TLBINDEX, 0xa); in utlb_invalidate()
178 write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB); in utlb_invalidate()
200 write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex); in tlb_entry_insert()
203 write_aux_reg(ARC_REG_TLBPD1, pd1); in tlb_entry_insert()
210 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); in tlb_entry_insert()
[all …]
Dcache_arc700.c243 write_aux_reg(aux_tag, paddr); in __cache_line_loop()
250 write_aux_reg(aux_tag, paddr); in __cache_line_loop()
254 write_aux_reg(aux_cmd, vaddr); in __cache_line_loop()
257 write_aux_reg(aux_cmd, paddr); in __cache_line_loop()
280 write_aux_reg(ARC_REG_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH) in __before_dc_op()
294 write_aux_reg(ARC_REG_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH); in __after_dc_op()
315 write_aux_reg(aux, 0x1); in __dc_entire_op()
402 write_aux_reg(ARC_REG_IC_IVIC, 1); in __ic_entire_inv()
/linux-4.1.27/arch/arc/kernel/
Dtime.c122 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX); in arc_counter_setup()
123 write_aux_reg(ARC_REG_TIMER1_CNT, 0); in arc_counter_setup()
124 write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); in arc_counter_setup()
152 write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); in arc_timer_event_setup()
153 write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ in arc_timer_event_setup()
155 write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); in arc_timer_event_setup()
210 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); in timer_irq_handler()
Dperf_event.c79 write_aux_reg(ARC_REG_PCT_INDEX, idx); in arc_pmu_read_counter()
81 write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN); in arc_pmu_read_counter()
172 write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1); in arc_pmu_enable()
180 write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0); in arc_pmu_disable()
202 write_aux_reg(ARC_REG_PCT_INDEX, idx); in arc_pmu_start()
203 write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config); in arc_pmu_start()
213 write_aux_reg(ARC_REG_PCT_INDEX, idx); in arc_pmu_stop()
216 write_aux_reg(ARC_REG_PCT_CONFIG, 0); in arc_pmu_stop()
252 write_aux_reg(ARC_REG_PCT_INDEX, idx); in arc_pmu_add()
253 write_aux_reg(ARC_REG_PCT_CONFIG, 0); in arc_pmu_add()
[all …]
Dirq.c41 write_aux_reg(AUX_IRQ_LEV, level_mask); in arc_init_IRQ()
64 write_aux_reg(AUX_IENABLE, ienb); in arc_irq_mask()
73 write_aux_reg(AUX_IENABLE, ienb); in arc_irq_unmask()
/linux-4.1.27/arch/arc/plat-arcfpga/
Dsmp.c34 write_aux_reg(ARC_AUX_XTL_REG_PARAM, pc); in iss_model_smp_wakeup_cpu()
37 write_aux_reg(ARC_AUX_XTL_REG_CMD, in iss_model_smp_wakeup_cpu()
41 write_aux_reg(ARC_AUX_XTL_REG_CMD, in iss_model_smp_wakeup_cpu()
/linux-4.1.27/arch/arc/plat-arcfpga/include/plat/
Dsmp.h57 write_aux_reg(ARC_AUX_IDU_REG_CMD, __val); \
60 #define IDU_SET_PARAM(par) write_aux_reg(ARC_AUX_IDU_REG_PARAM, par)
/linux-4.1.27/arch/arc/include/asm/
Dmmu_context.h98 write_aux_reg(ARC_REG_PID, hw_pid(mm, cpu) | MMU_ENABLE); in get_new_mmu_context()
151 write_aux_reg(ARC_REG_SCRATCH_DATA0, next->pgd); in switch_mm()
Darcregs.h112 #define write_aux_reg(reg_immed, val) \ macro
133 #define write_aux_reg(reg_imm, val) \ macro
179 write_aux_reg(reg, tmp); \