Searched refs:DMA0_REGISTER_OFFSET (Results 1 – 5 of 5) sorted by relevance
62 reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET; in cayman_dma_get_rptr()86 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; in cayman_dma_get_wptr()107 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; in cayman_dma_set_wptr()166 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()168 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()198 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
875 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): in cayman_get_allowed_info_register()1137 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()1775 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in cayman_gpu_check_soft_reset()1856 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_gpu_soft_reset()1858 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
1287 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): in si_get_allowed_info_register()3279 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()3799 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in si_gpu_check_soft_reset()3881 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset()3883 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()4048 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset()4050 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()5526 offset = DMA0_REGISTER_OFFSET; in si_enable_dma_mgcg()5538 offset = DMA0_REGISTER_OFFSET; in si_enable_dma_mgcg()5944 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()[all …]
1300 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
1810 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro