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Searched refs:SDMA0_REGISTER_OFFSET (Results 1 – 12 of 12) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Dcik_sdma.c72 reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_get_rptr()
96 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_get_wptr()
117 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_set_wptr()
261 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_stop()
311 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
343 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_enable()
376 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_resume()
484 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_sdma_load_microcode()
486 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++)); in cik_sdma_load_microcode()
487 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); in cik_sdma_load_microcode()
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Dcik.c166 case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET): in cik_get_allowed_info_register()
3742 WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
5225 RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
5279 tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); in cik_gpu_check_soft_reset()
5367 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_soft_reset()
5369 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5570 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
5572 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5941 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5942 WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
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Dcikd.h1954 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dcik_sdma.c47 SDMA0_REGISTER_OFFSET,
889 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
892 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
895 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
910 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
913 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
920 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
923 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
1122 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_soft_reset()
1124 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
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Dvi.c402 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false},
559 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); in vi_print_gpu_status_regs()
653 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); in vi_gpu_check_soft_reset()
735 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in vi_gpu_soft_reset()
737 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in vi_gpu_soft_reset()
885 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in vi_gpu_pci_config_reset()
887 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in vi_gpu_pci_config_reset()
Dsdma_v2_4.c57 SDMA0_REGISTER_OFFSET,
1136 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
1138 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
1184 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1186 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1189 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1191 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
Dsdma_v3_0.c62 SDMA0_REGISTER_OFFSET,
1298 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_soft_reset()
1300 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in sdma_v3_0_soft_reset()
1346 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1348 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1351 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1353 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
Dcik.c1048 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
1102 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); in amdgpu_cik_gpu_check_soft_reset()
1188 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_soft_reset()
1190 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
1394 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
1396 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
Dvid.h26 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
Dcikd.h481 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
Dgfx_v8_0.c2902 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, in gfx_v8_0_gpu_init()
4167 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET)); in gfx_v8_0_print_status()
Dgfx_v7_0.c2232 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); in gfx_v7_0_gpu_init()
5014 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET)); in gfx_v7_0_print_status()