Searched refs:gb_tile_config (Results 1 – 2 of 2) sorted by relevance
219 unsigned gb_tile_config; in r300_ring_start() local223 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); in r300_ring_start()226 gb_tile_config |= R300_PIPE_COUNT_R300; in r300_ring_start()229 gb_tile_config |= R300_PIPE_COUNT_R420_3P; in r300_ring_start()232 gb_tile_config |= R300_PIPE_COUNT_R420; in r300_ring_start()236 gb_tile_config |= R300_PIPE_COUNT_RV350; in r300_ring_start()251 radeon_ring_write(ring, gb_tile_config); in r300_ring_start()335 uint32_t gb_tile_config, tmp; in r300_gpu_init() local346 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); in r300_gpu_init()349 gb_tile_config |= R300_PIPE_COUNT_R300; in r300_gpu_init()[all …]
411 uint32_t gb_tile_config, gb_pipe_sel = 0; in radeon_init_pipes() local444 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/); in radeon_init_pipes()447 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; in radeon_init_pipes()448 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; in radeon_init_pipes()449 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; in radeon_init_pipes()451 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; in radeon_init_pipes()458 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); in radeon_init_pipes()