1Samsung Exynos SoC USB controller
2
3The USB devices interface with USB controllers on Exynos SOCs.
4The device node has following properties.
5
6EHCI
7Required properties:
8 - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
9   EHCI controller in host mode.
10 - reg: physical base address of the controller and length of memory mapped
11   region.
12 - interrupts: interrupt number to the cpu.
13 - clocks: from common clock binding: handle to usb clock.
14 - clock-names: from common clock binding: Shall be "usbhost".
15 - port: if in the SoC there are EHCI phys, they should be listed here.
16   One phy per port. Each port should have following entries:
17	- reg: port number on EHCI controller, e.g
18	       On Exynos5250, port 0 is USB2.0 otg phy
19			      port 1 is HSIC phy0
20			      port 2 is HSIC phy1
21	- phys: from the *Generic PHY* bindings; specifying phy used by port.
22
23Optional properties:
24 - samsung,vbus-gpio:  if present, specifies the GPIO that
25   needs to be pulled up for the bus to be powered.
26
27Example:
28
29	usb@12110000 {
30		compatible = "samsung,exynos4210-ehci";
31		reg = <0x12110000 0x100>;
32		interrupts = <0 71 0>;
33		samsung,vbus-gpio = <&gpx2 6 1 3 3>;
34
35		clocks = <&clock 285>;
36		clock-names = "usbhost";
37
38		#address-cells = <1>;
39		#size-cells = <0>;
40		port@0 {
41		    reg = <0>;
42		    phys = <&usb2phy 1>;
43		    status = "disabled";
44		};
45	};
46
47OHCI
48Required properties:
49 - compatible: should be "samsung,exynos4210-ohci" for USB 2.0
50   OHCI companion controller in host mode.
51 - reg: physical base address of the controller and length of memory mapped
52   region.
53 - interrupts: interrupt number to the cpu.
54 - clocks: from common clock binding: handle to usb clock.
55 - clock-names: from common clock binding: Shall be "usbhost".
56 - port: if in the SoC there are OHCI phys, they should be listed here.
57   One phy per port. Each port should have following entries:
58	- reg: port number on OHCI controller, e.g
59	       On Exynos5250, port 0 is USB2.0 otg phy
60			      port 1 is HSIC phy0
61			      port 2 is HSIC phy1
62	- phys: from the *Generic PHY* bindings, specifying phy used by port.
63
64Example:
65	usb@12120000 {
66		compatible = "samsung,exynos4210-ohci";
67		reg = <0x12120000 0x100>;
68		interrupts = <0 71 0>;
69
70		clocks = <&clock 285>;
71		clock-names = "usbhost";
72
73		#address-cells = <1>;
74		#size-cells = <0>;
75		port@0 {
76		    reg = <0>;
77		    phys = <&usb2phy 1>;
78		    status = "disabled";
79		};
80
81	};
82
83DWC3
84Required properties:
85 - compatible: should be one of the following -
86	       "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
87					    Exynos5250/5420.
88	       "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
89 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
90				 with 'reg' property.
91 - ranges: allows valid 1:1 translation between child's address space and
92	   parent's address space
93 - clocks: Clock IDs array as required by the controller.
94 - clock-names: names of clocks correseponding to IDs in the clock property
95
96Sub-nodes:
97The dwc3 core should be added as subnode to Exynos dwc3 glue.
98- dwc3 :
99   The binding details of dwc3 can be found in:
100   Documentation/devicetree/bindings/usb/dwc3.txt
101
102Example:
103	usb@12000000 {
104		compatible = "samsung,exynos5250-dwusb3";
105		clocks = <&clock 286>;
106		clock-names = "usbdrd30";
107		#address-cells = <1>;
108		#size-cells = <1>;
109		ranges;
110
111		dwc3 {
112			compatible = "synopsys,dwc3";
113			reg = <0x12000000 0x10000>;
114			interrupts = <0 72 0>;
115			usb-phy = <&usb2_phy &usb3_phy>;
116		};
117	};
118