1 /*
2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #ifndef _ASM_ARC_IO_H
10 #define _ASM_ARC_IO_H
11
12 #include <linux/types.h>
13 #include <asm/byteorder.h>
14 #include <asm/page.h>
15
16 #ifdef CONFIG_ISA_ARCV2
17 #include <asm/barrier.h>
18 #define __iormb() rmb()
19 #define __iowmb() wmb()
20 #else
21 #define __iormb() do { } while (0)
22 #define __iowmb() do { } while (0)
23 #endif
24
25 extern void __iomem *ioremap(unsigned long physaddr, unsigned long size);
26 extern void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
27 unsigned long flags);
28 extern void iounmap(const void __iomem *addr);
29
30 #define ioremap_nocache(phy, sz) ioremap(phy, sz)
31 #define ioremap_wc(phy, sz) ioremap(phy, sz)
32 #define ioremap_wt(phy, sz) ioremap(phy, sz)
33
34 /*
35 * io{read,write}{16,32}be() macros
36 */
37 #define ioread16be(p) ({ u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
38 #define ioread32be(p) ({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
39
40 #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force u16)cpu_to_be16(v), p); })
41 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force u32)cpu_to_be32(v), p); })
42
43 /* Change struct page to physical address */
44 #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
45
46 #define __raw_readb __raw_readb
__raw_readb(const volatile void __iomem * addr)47 static inline u8 __raw_readb(const volatile void __iomem *addr)
48 {
49 u8 b;
50
51 __asm__ __volatile__(
52 " ldb%U1 %0, %1 \n"
53 : "=r" (b)
54 : "m" (*(volatile u8 __force *)addr)
55 : "memory");
56
57 return b;
58 }
59
60 #define __raw_readw __raw_readw
__raw_readw(const volatile void __iomem * addr)61 static inline u16 __raw_readw(const volatile void __iomem *addr)
62 {
63 u16 s;
64
65 __asm__ __volatile__(
66 " ldw%U1 %0, %1 \n"
67 : "=r" (s)
68 : "m" (*(volatile u16 __force *)addr)
69 : "memory");
70
71 return s;
72 }
73
74 #define __raw_readl __raw_readl
__raw_readl(const volatile void __iomem * addr)75 static inline u32 __raw_readl(const volatile void __iomem *addr)
76 {
77 u32 w;
78
79 __asm__ __volatile__(
80 " ld%U1 %0, %1 \n"
81 : "=r" (w)
82 : "m" (*(volatile u32 __force *)addr)
83 : "memory");
84
85 return w;
86 }
87
88 #define __raw_writeb __raw_writeb
__raw_writeb(u8 b,volatile void __iomem * addr)89 static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
90 {
91 __asm__ __volatile__(
92 " stb%U1 %0, %1 \n"
93 :
94 : "r" (b), "m" (*(volatile u8 __force *)addr)
95 : "memory");
96 }
97
98 #define __raw_writew __raw_writew
__raw_writew(u16 s,volatile void __iomem * addr)99 static inline void __raw_writew(u16 s, volatile void __iomem *addr)
100 {
101 __asm__ __volatile__(
102 " stw%U1 %0, %1 \n"
103 :
104 : "r" (s), "m" (*(volatile u16 __force *)addr)
105 : "memory");
106
107 }
108
109 #define __raw_writel __raw_writel
__raw_writel(u32 w,volatile void __iomem * addr)110 static inline void __raw_writel(u32 w, volatile void __iomem *addr)
111 {
112 __asm__ __volatile__(
113 " st%U1 %0, %1 \n"
114 :
115 : "r" (w), "m" (*(volatile u32 __force *)addr)
116 : "memory");
117
118 }
119
120 /*
121 * MMIO can also get buffered/optimized in micro-arch, so barriers needed
122 * Based on ARM model for the typical use case
123 *
124 * <ST [DMA buffer]>
125 * <writel MMIO "go" reg>
126 * or:
127 * <readl MMIO "status" reg>
128 * <LD [DMA buffer]>
129 *
130 * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
131 */
132 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
133 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
134 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
135
136 #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
137 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
138 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
139
140 /*
141 * Relaxed API for drivers which can handle barrier ordering themselves
142 *
143 * Also these are defined to perform little endian accesses.
144 * To provide the typical device register semantics of fixed endian,
145 * swap the byte order for Big Endian
146 *
147 * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
148 */
149 #define readb_relaxed(c) __raw_readb(c)
150 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
151 __raw_readw(c)); __r; })
152 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
153 __raw_readl(c)); __r; })
154
155 #define writeb_relaxed(v,c) __raw_writeb(v,c)
156 #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
157 #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
158
159 #include <asm-generic/io.h>
160
161 #endif /* _ASM_ARC_IO_H */
162