1 /*
2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9 #include <linux/device.h>
10 #include <linux/export.h>
11 #include <linux/platform_device.h>
12 #include <linux/mtd/mtd.h>
13 #include <linux/mtd/partitions.h>
14 #include <linux/mtd/physmap.h>
15 #include <linux/spi/spi.h>
16 #include <linux/spi/flash.h>
17
18 #include <linux/i2c.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/usb/musb.h>
22 #include <asm/dma.h>
23 #include <asm/bfin5xx_spi.h>
24 #include <asm/reboot.h>
25 #include <asm/nand.h>
26 #include <asm/portmux.h>
27 #include <asm/dpmc.h>
28 #include <linux/spi/ad7877.h>
29
30 /*
31 * Name the Board for the /proc/cpuinfo
32 */
33 const char bfin_board_name[] = "ADI BF526-EZBRD";
34
35 /*
36 * Driver needs to know address, irq and flag pin.
37 */
38
39 #if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
40 static struct resource musb_resources[] = {
41 [0] = {
42 .start = 0xffc03800,
43 .end = 0xffc03cff,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = { /* general IRQ */
47 .start = IRQ_USB_INT0,
48 .end = IRQ_USB_INT0,
49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
50 .name = "mc"
51 },
52 [2] = { /* DMA IRQ */
53 .start = IRQ_USB_DMA,
54 .end = IRQ_USB_DMA,
55 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
56 .name = "dma"
57 },
58 };
59
60 static struct musb_hdrc_config musb_config = {
61 .multipoint = 0,
62 .dyn_fifo = 0,
63 .soft_con = 1,
64 .dma = 1,
65 .num_eps = 8,
66 .dma_channels = 8,
67 .gpio_vrsel = GPIO_PG13,
68 /* Some custom boards need to be active low, just set it to "0"
69 * if it is the case.
70 */
71 .gpio_vrsel_active = 1,
72 .clkin = 24, /* musb CLKIN in MHZ */
73 };
74
75 static struct musb_hdrc_platform_data musb_plat = {
76 #if defined(CONFIG_USB_MUSB_OTG)
77 .mode = MUSB_OTG,
78 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
79 .mode = MUSB_HOST,
80 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
81 .mode = MUSB_PERIPHERAL,
82 #endif
83 .config = &musb_config,
84 };
85
86 static u64 musb_dmamask = ~(u32)0;
87
88 static struct platform_device musb_device = {
89 .name = "musb-blackfin",
90 .id = 0,
91 .dev = {
92 .dma_mask = &musb_dmamask,
93 .coherent_dma_mask = 0xffffffff,
94 .platform_data = &musb_plat,
95 },
96 .num_resources = ARRAY_SIZE(musb_resources),
97 .resource = musb_resources,
98 };
99 #endif
100
101 #if IS_ENABLED(CONFIG_MTD_PHYSMAP)
102 static struct mtd_partition ezbrd_partitions[] = {
103 {
104 .name = "bootloader(nor)",
105 .size = 0x40000,
106 .offset = 0,
107 }, {
108 .name = "linux kernel(nor)",
109 .size = 0x1C0000,
110 .offset = MTDPART_OFS_APPEND,
111 }, {
112 .name = "file system(nor)",
113 .size = MTDPART_SIZ_FULL,
114 .offset = MTDPART_OFS_APPEND,
115 }
116 };
117
118 static struct physmap_flash_data ezbrd_flash_data = {
119 .width = 2,
120 .parts = ezbrd_partitions,
121 .nr_parts = ARRAY_SIZE(ezbrd_partitions),
122 };
123
124 static struct resource ezbrd_flash_resource = {
125 .start = 0x20000000,
126 .end = 0x203fffff,
127 .flags = IORESOURCE_MEM,
128 };
129
130 static struct platform_device ezbrd_flash_device = {
131 .name = "physmap-flash",
132 .id = 0,
133 .dev = {
134 .platform_data = &ezbrd_flash_data,
135 },
136 .num_resources = 1,
137 .resource = &ezbrd_flash_resource,
138 };
139 #endif
140
141 #if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
142 static struct mtd_partition partition_info[] = {
143 {
144 .name = "bootloader(nand)",
145 .offset = 0,
146 .size = 0x40000,
147 }, {
148 .name = "linux kernel(nand)",
149 .offset = MTDPART_OFS_APPEND,
150 .size = 4 * 1024 * 1024,
151 },
152 {
153 .name = "file system(nand)",
154 .offset = MTDPART_OFS_APPEND,
155 .size = MTDPART_SIZ_FULL,
156 },
157 };
158
159 static struct bf5xx_nand_platform bf5xx_nand_platform = {
160 .data_width = NFC_NWIDTH_8,
161 .partitions = partition_info,
162 .nr_partitions = ARRAY_SIZE(partition_info),
163 .rd_dly = 3,
164 .wr_dly = 3,
165 };
166
167 static struct resource bf5xx_nand_resources[] = {
168 {
169 .start = NFC_CTL,
170 .end = NFC_DATA_RD + 2,
171 .flags = IORESOURCE_MEM,
172 },
173 {
174 .start = CH_NFC,
175 .end = CH_NFC,
176 .flags = IORESOURCE_IRQ,
177 },
178 };
179
180 static struct platform_device bf5xx_nand_device = {
181 .name = "bf5xx-nand",
182 .id = 0,
183 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
184 .resource = bf5xx_nand_resources,
185 .dev = {
186 .platform_data = &bf5xx_nand_platform,
187 },
188 };
189 #endif
190
191 #if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
192 static struct platform_device rtc_device = {
193 .name = "rtc-bfin",
194 .id = -1,
195 };
196 #endif
197
198
199 #if IS_ENABLED(CONFIG_BFIN_MAC)
200 #include <linux/bfin_mac.h>
201 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
202
203 static struct bfin_phydev_platform_data bfin_phydev_data[] = {
204 {
205 .addr = 1,
206 .irq = IRQ_MAC_PHYINT,
207 },
208 };
209
210 static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
211 .phydev_number = 1,
212 .phydev_data = bfin_phydev_data,
213 .phy_mode = PHY_INTERFACE_MODE_RMII,
214 .mac_peripherals = bfin_mac_peripherals,
215 };
216
217 static struct platform_device bfin_mii_bus = {
218 .name = "bfin_mii_bus",
219 .dev = {
220 .platform_data = &bfin_mii_bus_data,
221 }
222 };
223
224 static struct platform_device bfin_mac_device = {
225 .name = "bfin_mac",
226 .dev = {
227 .platform_data = &bfin_mii_bus,
228 }
229 };
230 #endif
231
232 #if IS_ENABLED(CONFIG_MTD_M25P80)
233 static struct mtd_partition bfin_spi_flash_partitions[] = {
234 {
235 .name = "bootloader(spi)",
236 .size = 0x00040000,
237 .offset = 0,
238 .mask_flags = MTD_CAP_ROM
239 }, {
240 .name = "linux kernel(spi)",
241 .size = MTDPART_SIZ_FULL,
242 .offset = MTDPART_OFS_APPEND,
243 }
244 };
245
246 static struct flash_platform_data bfin_spi_flash_data = {
247 .name = "m25p80",
248 .parts = bfin_spi_flash_partitions,
249 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
250 .type = "sst25wf040",
251 };
252
253 /* SPI flash chip (sst25wf040) */
254 static struct bfin5xx_spi_chip spi_flash_chip_info = {
255 .enable_dma = 0, /* use dma transfer with this chip*/
256 };
257 #endif
258
259 #if IS_ENABLED(CONFIG_MMC_SPI)
260 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
261 .enable_dma = 0,
262 };
263 #endif
264
265 #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
266 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
267 .model = 7877,
268 .vref_delay_usecs = 50, /* internal, no capacitor */
269 .x_plate_ohms = 419,
270 .y_plate_ohms = 486,
271 .pressure_max = 1000,
272 .pressure_min = 0,
273 .stopacq_polarity = 1,
274 .first_conversion_delay = 3,
275 .acquisition_time = 1,
276 .averaging = 1,
277 .pen_down_acc_interval = 1,
278 };
279 #endif
280
281 #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
282 #include <linux/spi/ad7879.h>
283 static const struct ad7879_platform_data bfin_ad7879_ts_info = {
284 .model = 7879, /* Model = AD7879 */
285 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
286 .pressure_max = 10000,
287 .pressure_min = 0,
288 .first_conversion_delay = 3, /* wait 512us before do a first conversion */
289 .acquisition_time = 1, /* 4us acquisition time per sample */
290 .median = 2, /* do 8 measurements */
291 .averaging = 1, /* take the average of 4 middle samples */
292 .pen_down_acc_interval = 255, /* 9.4 ms */
293 .gpio_export = 1, /* Export GPIO to gpiolib */
294 .gpio_base = -1, /* Dynamic allocation */
295 };
296 #endif
297
298 static struct spi_board_info bfin_spi_board_info[] __initdata = {
299 #if IS_ENABLED(CONFIG_MTD_M25P80)
300 {
301 /* the modalias must be the same as spi device driver name */
302 .modalias = "m25p80", /* Name of spi_driver for this device */
303 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
304 .bus_num = 0, /* Framework bus number */
305 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
306 .platform_data = &bfin_spi_flash_data,
307 .controller_data = &spi_flash_chip_info,
308 .mode = SPI_MODE_3,
309 },
310 #endif
311
312 #if IS_ENABLED(CONFIG_MMC_SPI)
313 {
314 .modalias = "mmc_spi",
315 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
316 .bus_num = 0,
317 .chip_select = 5,
318 .controller_data = &mmc_spi_chip_info,
319 .mode = SPI_MODE_3,
320 },
321 #endif
322 #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
323 {
324 .modalias = "ad7877",
325 .platform_data = &bfin_ad7877_ts_info,
326 .irq = IRQ_PF8,
327 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
328 .bus_num = 0,
329 .chip_select = 2,
330 },
331 #endif
332 #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
333 {
334 .modalias = "ad7879",
335 .platform_data = &bfin_ad7879_ts_info,
336 .irq = IRQ_PG0,
337 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
338 .bus_num = 0,
339 .chip_select = 5,
340 .mode = SPI_CPHA | SPI_CPOL,
341 },
342 #endif
343 #if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
344 && defined(CONFIG_SND_SOC_WM8731_SPI)
345 {
346 .modalias = "wm8731",
347 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
348 .bus_num = 0,
349 .chip_select = 5,
350 .mode = SPI_MODE_0,
351 },
352 #endif
353 #if IS_ENABLED(CONFIG_SPI_SPIDEV)
354 {
355 .modalias = "spidev",
356 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
357 .bus_num = 0,
358 .chip_select = 1,
359 },
360 #endif
361 #if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
362 {
363 .modalias = "bfin-lq035q1-spi",
364 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
365 .bus_num = 0,
366 .chip_select = 1,
367 .mode = SPI_CPHA | SPI_CPOL,
368 },
369 #endif
370 };
371
372 #if IS_ENABLED(CONFIG_SPI_BFIN5XX)
373 /* SPI controller data */
374 static struct bfin5xx_spi_master bfin_spi0_info = {
375 .num_chipselect = 8,
376 .enable_dma = 1, /* master has the ability to do dma transfer */
377 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
378 };
379
380 /* SPI (0) */
381 static struct resource bfin_spi0_resource[] = {
382 [0] = {
383 .start = SPI0_REGBASE,
384 .end = SPI0_REGBASE + 0xFF,
385 .flags = IORESOURCE_MEM,
386 },
387 [1] = {
388 .start = CH_SPI,
389 .end = CH_SPI,
390 .flags = IORESOURCE_DMA,
391 },
392 [2] = {
393 .start = IRQ_SPI,
394 .end = IRQ_SPI,
395 .flags = IORESOURCE_IRQ,
396 },
397 };
398
399 static struct platform_device bfin_spi0_device = {
400 .name = "bfin-spi",
401 .id = 0, /* Bus number */
402 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
403 .resource = bfin_spi0_resource,
404 .dev = {
405 .platform_data = &bfin_spi0_info, /* Passed to driver */
406 },
407 };
408 #endif /* spi master and devices */
409
410 #if IS_ENABLED(CONFIG_SERIAL_BFIN)
411 #ifdef CONFIG_SERIAL_BFIN_UART0
412 static struct resource bfin_uart0_resources[] = {
413 {
414 .start = UART0_THR,
415 .end = UART0_GCTL+2,
416 .flags = IORESOURCE_MEM,
417 },
418 {
419 .start = IRQ_UART0_TX,
420 .end = IRQ_UART0_TX,
421 .flags = IORESOURCE_IRQ,
422 },
423 {
424 .start = IRQ_UART0_RX,
425 .end = IRQ_UART0_RX,
426 .flags = IORESOURCE_IRQ,
427 },
428 {
429 .start = IRQ_UART0_ERROR,
430 .end = IRQ_UART0_ERROR,
431 .flags = IORESOURCE_IRQ,
432 },
433 {
434 .start = CH_UART0_TX,
435 .end = CH_UART0_TX,
436 .flags = IORESOURCE_DMA,
437 },
438 {
439 .start = CH_UART0_RX,
440 .end = CH_UART0_RX,
441 .flags = IORESOURCE_DMA,
442 },
443 };
444
445 static unsigned short bfin_uart0_peripherals[] = {
446 P_UART0_TX, P_UART0_RX, 0
447 };
448
449 static struct platform_device bfin_uart0_device = {
450 .name = "bfin-uart",
451 .id = 0,
452 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
453 .resource = bfin_uart0_resources,
454 .dev = {
455 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
456 },
457 };
458 #endif
459 #ifdef CONFIG_SERIAL_BFIN_UART1
460 static struct resource bfin_uart1_resources[] = {
461 {
462 .start = UART1_THR,
463 .end = UART1_GCTL+2,
464 .flags = IORESOURCE_MEM,
465 },
466 {
467 .start = IRQ_UART1_TX,
468 .end = IRQ_UART1_TX,
469 .flags = IORESOURCE_IRQ,
470 },
471 {
472 .start = IRQ_UART1_RX,
473 .end = IRQ_UART1_RX,
474 .flags = IORESOURCE_IRQ,
475 },
476 {
477 .start = IRQ_UART1_ERROR,
478 .end = IRQ_UART1_ERROR,
479 .flags = IORESOURCE_IRQ,
480 },
481 {
482 .start = CH_UART1_TX,
483 .end = CH_UART1_TX,
484 .flags = IORESOURCE_DMA,
485 },
486 {
487 .start = CH_UART1_RX,
488 .end = CH_UART1_RX,
489 .flags = IORESOURCE_DMA,
490 },
491 #ifdef CONFIG_BFIN_UART1_CTSRTS
492 { /* CTS pin */
493 .start = GPIO_PG0,
494 .end = GPIO_PG0,
495 .flags = IORESOURCE_IO,
496 },
497 { /* RTS pin */
498 .start = GPIO_PF10,
499 .end = GPIO_PF10,
500 .flags = IORESOURCE_IO,
501 },
502 #endif
503 };
504
505 static unsigned short bfin_uart1_peripherals[] = {
506 P_UART1_TX, P_UART1_RX, 0
507 };
508
509 static struct platform_device bfin_uart1_device = {
510 .name = "bfin-uart",
511 .id = 1,
512 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
513 .resource = bfin_uart1_resources,
514 .dev = {
515 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
516 },
517 };
518 #endif
519 #endif
520
521 #if IS_ENABLED(CONFIG_BFIN_SIR)
522 #ifdef CONFIG_BFIN_SIR0
523 static struct resource bfin_sir0_resources[] = {
524 {
525 .start = 0xFFC00400,
526 .end = 0xFFC004FF,
527 .flags = IORESOURCE_MEM,
528 },
529 {
530 .start = IRQ_UART0_RX,
531 .end = IRQ_UART0_RX+1,
532 .flags = IORESOURCE_IRQ,
533 },
534 {
535 .start = CH_UART0_RX,
536 .end = CH_UART0_RX+1,
537 .flags = IORESOURCE_DMA,
538 },
539 };
540
541 static struct platform_device bfin_sir0_device = {
542 .name = "bfin_sir",
543 .id = 0,
544 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
545 .resource = bfin_sir0_resources,
546 };
547 #endif
548 #ifdef CONFIG_BFIN_SIR1
549 static struct resource bfin_sir1_resources[] = {
550 {
551 .start = 0xFFC02000,
552 .end = 0xFFC020FF,
553 .flags = IORESOURCE_MEM,
554 },
555 {
556 .start = IRQ_UART1_RX,
557 .end = IRQ_UART1_RX+1,
558 .flags = IORESOURCE_IRQ,
559 },
560 {
561 .start = CH_UART1_RX,
562 .end = CH_UART1_RX+1,
563 .flags = IORESOURCE_DMA,
564 },
565 };
566
567 static struct platform_device bfin_sir1_device = {
568 .name = "bfin_sir",
569 .id = 1,
570 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
571 .resource = bfin_sir1_resources,
572 };
573 #endif
574 #endif
575
576 #if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
577 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
578
579 static struct resource bfin_twi0_resource[] = {
580 [0] = {
581 .start = TWI0_REGBASE,
582 .end = TWI0_REGBASE,
583 .flags = IORESOURCE_MEM,
584 },
585 [1] = {
586 .start = IRQ_TWI,
587 .end = IRQ_TWI,
588 .flags = IORESOURCE_IRQ,
589 },
590 };
591
592 static struct platform_device i2c_bfin_twi_device = {
593 .name = "i2c-bfin-twi",
594 .id = 0,
595 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
596 .resource = bfin_twi0_resource,
597 .dev = {
598 .platform_data = &bfin_twi0_pins,
599 },
600 };
601 #endif
602
603 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
604 #if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
605 {
606 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
607 },
608 #endif
609 #if IS_ENABLED(CONFIG_INPUT_PCF8574)
610 {
611 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
612 .irq = IRQ_PF8,
613 },
614 #endif
615 };
616
617 #if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
618 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
619 static struct resource bfin_sport0_uart_resources[] = {
620 {
621 .start = SPORT0_TCR1,
622 .end = SPORT0_MRCS3+4,
623 .flags = IORESOURCE_MEM,
624 },
625 {
626 .start = IRQ_SPORT0_RX,
627 .end = IRQ_SPORT0_RX+1,
628 .flags = IORESOURCE_IRQ,
629 },
630 {
631 .start = IRQ_SPORT0_ERROR,
632 .end = IRQ_SPORT0_ERROR,
633 .flags = IORESOURCE_IRQ,
634 },
635 };
636
637 static unsigned short bfin_sport0_peripherals[] = {
638 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
639 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
640 };
641
642 static struct platform_device bfin_sport0_uart_device = {
643 .name = "bfin-sport-uart",
644 .id = 0,
645 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
646 .resource = bfin_sport0_uart_resources,
647 .dev = {
648 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
649 },
650 };
651 #endif
652 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
653 static struct resource bfin_sport1_uart_resources[] = {
654 {
655 .start = SPORT1_TCR1,
656 .end = SPORT1_MRCS3+4,
657 .flags = IORESOURCE_MEM,
658 },
659 {
660 .start = IRQ_SPORT1_RX,
661 .end = IRQ_SPORT1_RX+1,
662 .flags = IORESOURCE_IRQ,
663 },
664 {
665 .start = IRQ_SPORT1_ERROR,
666 .end = IRQ_SPORT1_ERROR,
667 .flags = IORESOURCE_IRQ,
668 },
669 };
670
671 static unsigned short bfin_sport1_peripherals[] = {
672 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
673 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
674 };
675
676 static struct platform_device bfin_sport1_uart_device = {
677 .name = "bfin-sport-uart",
678 .id = 1,
679 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
680 .resource = bfin_sport1_uart_resources,
681 .dev = {
682 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
683 },
684 };
685 #endif
686 #endif
687
688 #if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
689 #include <linux/input.h>
690 #include <linux/gpio_keys.h>
691
692 static struct gpio_keys_button bfin_gpio_keys_table[] = {
693 {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
694 {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
695 };
696
697 static struct gpio_keys_platform_data bfin_gpio_keys_data = {
698 .buttons = bfin_gpio_keys_table,
699 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
700 };
701
702 static struct platform_device bfin_device_gpiokeys = {
703 .name = "gpio-keys",
704 .dev = {
705 .platform_data = &bfin_gpio_keys_data,
706 },
707 };
708 #endif
709
710 static const unsigned int cclk_vlev_datasheet[] =
711 {
712 VRPAIR(VLEV_100, 400000000),
713 VRPAIR(VLEV_105, 426000000),
714 VRPAIR(VLEV_110, 500000000),
715 VRPAIR(VLEV_115, 533000000),
716 VRPAIR(VLEV_120, 600000000),
717 };
718
719 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
720 .tuple_tab = cclk_vlev_datasheet,
721 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
722 .vr_settling_time = 25 /* us */,
723 };
724
725 static struct platform_device bfin_dpmc = {
726 .name = "bfin dpmc",
727 .dev = {
728 .platform_data = &bfin_dmpc_vreg_data,
729 },
730 };
731
732 #if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
733 #include <asm/bfin-lq035q1.h>
734
735 static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
736 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
737 .ppi_mode = USE_RGB565_16_BIT_PPI,
738 .use_bl = 1,
739 .gpio_bl = GPIO_PG12,
740 };
741
742 static struct resource bfin_lq035q1_resources[] = {
743 {
744 .start = IRQ_PPI_ERROR,
745 .end = IRQ_PPI_ERROR,
746 .flags = IORESOURCE_IRQ,
747 },
748 };
749
750 static struct platform_device bfin_lq035q1_device = {
751 .name = "bfin-lq035q1",
752 .id = -1,
753 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
754 .resource = bfin_lq035q1_resources,
755 .dev = {
756 .platform_data = &bfin_lq035q1_data,
757 },
758 };
759 #endif
760
761 static struct platform_device *stamp_devices[] __initdata = {
762
763 &bfin_dpmc,
764
765 #if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
766 &bf5xx_nand_device,
767 #endif
768
769 #if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
770 &rtc_device,
771 #endif
772
773 #if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
774 &musb_device,
775 #endif
776
777 #if IS_ENABLED(CONFIG_BFIN_MAC)
778 &bfin_mii_bus,
779 &bfin_mac_device,
780 #endif
781
782 #if IS_ENABLED(CONFIG_SPI_BFIN5XX)
783 &bfin_spi0_device,
784 #endif
785
786 #if IS_ENABLED(CONFIG_SERIAL_BFIN)
787 #ifdef CONFIG_SERIAL_BFIN_UART0
788 &bfin_uart0_device,
789 #endif
790 #ifdef CONFIG_SERIAL_BFIN_UART1
791 &bfin_uart1_device,
792 #endif
793 #endif
794
795 #if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
796 &bfin_lq035q1_device,
797 #endif
798
799 #if IS_ENABLED(CONFIG_BFIN_SIR)
800 #ifdef CONFIG_BFIN_SIR0
801 &bfin_sir0_device,
802 #endif
803 #ifdef CONFIG_BFIN_SIR1
804 &bfin_sir1_device,
805 #endif
806 #endif
807
808 #if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
809 &i2c_bfin_twi_device,
810 #endif
811
812 #if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
813 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
814 &bfin_sport0_uart_device,
815 #endif
816 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
817 &bfin_sport1_uart_device,
818 #endif
819 #endif
820
821 #if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
822 &bfin_device_gpiokeys,
823 #endif
824
825 #if IS_ENABLED(CONFIG_MTD_PHYSMAP)
826 &ezbrd_flash_device,
827 #endif
828 };
829
ezbrd_init(void)830 static int __init ezbrd_init(void)
831 {
832 printk(KERN_INFO "%s(): registering device resources\n", __func__);
833 i2c_register_board_info(0, bfin_i2c_board_info,
834 ARRAY_SIZE(bfin_i2c_board_info));
835 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
836 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
837 return 0;
838 }
839
840 arch_initcall(ezbrd_init);
841
842 static struct platform_device *ezbrd_early_devices[] __initdata = {
843 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
844 #ifdef CONFIG_SERIAL_BFIN_UART0
845 &bfin_uart0_device,
846 #endif
847 #ifdef CONFIG_SERIAL_BFIN_UART1
848 &bfin_uart1_device,
849 #endif
850 #endif
851
852 #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
853 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
854 &bfin_sport0_uart_device,
855 #endif
856 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
857 &bfin_sport1_uart_device,
858 #endif
859 #endif
860 };
861
native_machine_early_platform_add_devices(void)862 void __init native_machine_early_platform_add_devices(void)
863 {
864 printk(KERN_INFO "register early platform devices\n");
865 early_platform_add_devices(ezbrd_early_devices,
866 ARRAY_SIZE(ezbrd_early_devices));
867 }
868
native_machine_restart(char * cmd)869 void native_machine_restart(char *cmd)
870 {
871 /* workaround reboot hang when booting from SPI */
872 if ((bfin_read_SYSCR() & 0x7) == 0x3)
873 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
874 }
875
bfin_get_ether_addr(char * addr)876 int bfin_get_ether_addr(char *addr)
877 {
878 /* the MAC is stored in OTP memory page 0xDF */
879 u32 ret;
880 u64 otp_mac;
881 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
882
883 ret = otp_read(0xDF, 0x00, &otp_mac);
884 if (!(ret & 0x1)) {
885 char *otp_mac_p = (char *)&otp_mac;
886 for (ret = 0; ret < 6; ++ret)
887 addr[ret] = otp_mac_p[5 - ret];
888 }
889 return 0;
890 }
891 EXPORT_SYMBOL(bfin_get_ether_addr);
892