1 /*
2  * mmp2 clock framework source file
3  *
4  * Copyright (C) 2012 Marvell
5  * Chao Xie <xiechao.mail@gmail.com>
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2. This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11 
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/spinlock.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 
20 #include <mach/addr-map.h>
21 
22 #include "clk.h"
23 
24 #define APBC_RTC	0x0
25 #define APBC_TWSI0	0x4
26 #define APBC_TWSI1	0x8
27 #define APBC_TWSI2	0xc
28 #define APBC_TWSI3	0x10
29 #define APBC_TWSI4	0x7c
30 #define APBC_TWSI5	0x80
31 #define APBC_KPC	0x18
32 #define APBC_UART0	0x2c
33 #define APBC_UART1	0x30
34 #define APBC_UART2	0x34
35 #define APBC_UART3	0x88
36 #define APBC_GPIO	0x38
37 #define APBC_PWM0	0x3c
38 #define APBC_PWM1	0x40
39 #define APBC_PWM2	0x44
40 #define APBC_PWM3	0x48
41 #define APBC_SSP0	0x50
42 #define APBC_SSP1	0x54
43 #define APBC_SSP2	0x58
44 #define APBC_SSP3	0x5c
45 #define APMU_SDH0	0x54
46 #define APMU_SDH1	0x58
47 #define APMU_SDH2	0xe8
48 #define APMU_SDH3	0xec
49 #define APMU_USB	0x5c
50 #define APMU_DISP0	0x4c
51 #define APMU_DISP1	0x110
52 #define APMU_CCIC0	0x50
53 #define APMU_CCIC1	0xf4
54 #define MPMU_UART_PLL	0x14
55 
56 static DEFINE_SPINLOCK(clk_lock);
57 
58 static struct mmp_clk_factor_masks uart_factor_masks = {
59 	.factor = 2,
60 	.num_mask = 0x1fff,
61 	.den_mask = 0x1fff,
62 	.num_shift = 16,
63 	.den_shift = 0,
64 };
65 
66 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
67 	{.num = 8125, .den = 1536},	/*14.745MHZ */
68 	{.num = 3521, .den = 689},	/*19.23MHZ */
69 };
70 
71 static const char *uart_parent[] = {"uart_pll", "vctcxo"};
72 static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
73 static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
74 static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
75 static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
76 
mmp2_clk_init(void)77 void __init mmp2_clk_init(void)
78 {
79 	struct clk *clk;
80 	struct clk *vctcxo;
81 	void __iomem *mpmu_base;
82 	void __iomem *apmu_base;
83 	void __iomem *apbc_base;
84 
85 	mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
86 	if (mpmu_base == NULL) {
87 		pr_err("error to ioremap MPMU base\n");
88 		return;
89 	}
90 
91 	apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
92 	if (apmu_base == NULL) {
93 		pr_err("error to ioremap APMU base\n");
94 		return;
95 	}
96 
97 	apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
98 	if (apbc_base == NULL) {
99 		pr_err("error to ioremap APBC base\n");
100 		return;
101 	}
102 
103 	clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
104 	clk_register_clkdev(clk, "clk32", NULL);
105 
106 	vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
107 				26000000);
108 	clk_register_clkdev(vctcxo, "vctcxo", NULL);
109 
110 	clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
111 				800000000);
112 	clk_register_clkdev(clk, "pll1", NULL);
113 
114 	clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT,
115 				480000000);
116 	clk_register_clkdev(clk, "usb_pll", NULL);
117 
118 	clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT,
119 				960000000);
120 	clk_register_clkdev(clk, "pll2", NULL);
121 
122 	clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
123 				CLK_SET_RATE_PARENT, 1, 2);
124 	clk_register_clkdev(clk, "pll1_2", NULL);
125 
126 	clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
127 				CLK_SET_RATE_PARENT, 1, 2);
128 	clk_register_clkdev(clk, "pll1_4", NULL);
129 
130 	clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
131 				CLK_SET_RATE_PARENT, 1, 2);
132 	clk_register_clkdev(clk, "pll1_8", NULL);
133 
134 	clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
135 				CLK_SET_RATE_PARENT, 1, 2);
136 	clk_register_clkdev(clk, "pll1_16", NULL);
137 
138 	clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
139 				CLK_SET_RATE_PARENT, 1, 5);
140 	clk_register_clkdev(clk, "pll1_20", NULL);
141 
142 	clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
143 				CLK_SET_RATE_PARENT, 1, 3);
144 	clk_register_clkdev(clk, "pll1_3", NULL);
145 
146 	clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
147 				CLK_SET_RATE_PARENT, 1, 2);
148 	clk_register_clkdev(clk, "pll1_6", NULL);
149 
150 	clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
151 				CLK_SET_RATE_PARENT, 1, 2);
152 	clk_register_clkdev(clk, "pll1_12", NULL);
153 
154 	clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
155 				CLK_SET_RATE_PARENT, 1, 2);
156 	clk_register_clkdev(clk, "pll2_2", NULL);
157 
158 	clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
159 				CLK_SET_RATE_PARENT, 1, 2);
160 	clk_register_clkdev(clk, "pll2_4", NULL);
161 
162 	clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
163 				CLK_SET_RATE_PARENT, 1, 2);
164 	clk_register_clkdev(clk, "pll2_8", NULL);
165 
166 	clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
167 				CLK_SET_RATE_PARENT, 1, 2);
168 	clk_register_clkdev(clk, "pll2_16", NULL);
169 
170 	clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
171 				CLK_SET_RATE_PARENT, 1, 3);
172 	clk_register_clkdev(clk, "pll2_3", NULL);
173 
174 	clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
175 				CLK_SET_RATE_PARENT, 1, 2);
176 	clk_register_clkdev(clk, "pll2_6", NULL);
177 
178 	clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
179 				CLK_SET_RATE_PARENT, 1, 2);
180 	clk_register_clkdev(clk, "pll2_12", NULL);
181 
182 	clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
183 				CLK_SET_RATE_PARENT, 1, 2);
184 	clk_register_clkdev(clk, "vctcxo_2", NULL);
185 
186 	clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
187 				CLK_SET_RATE_PARENT, 1, 2);
188 	clk_register_clkdev(clk, "vctcxo_4", NULL);
189 
190 	clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
191 				mpmu_base + MPMU_UART_PLL,
192 				&uart_factor_masks, uart_factor_tbl,
193 				ARRAY_SIZE(uart_factor_tbl), &clk_lock);
194 	clk_set_rate(clk, 14745600);
195 	clk_register_clkdev(clk, "uart_pll", NULL);
196 
197 	clk = mmp_clk_register_apbc("twsi0", "vctcxo",
198 				apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
199 	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
200 
201 	clk = mmp_clk_register_apbc("twsi1", "vctcxo",
202 				apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
203 	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
204 
205 	clk = mmp_clk_register_apbc("twsi2", "vctcxo",
206 				apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
207 	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
208 
209 	clk = mmp_clk_register_apbc("twsi3", "vctcxo",
210 				apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
211 	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
212 
213 	clk = mmp_clk_register_apbc("twsi4", "vctcxo",
214 				apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
215 	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
216 
217 	clk = mmp_clk_register_apbc("twsi5", "vctcxo",
218 				apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
219 	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
220 
221 	clk = mmp_clk_register_apbc("gpio", "vctcxo",
222 				apbc_base + APBC_GPIO, 10, 0, &clk_lock);
223 	clk_register_clkdev(clk, NULL, "mmp2-gpio");
224 
225 	clk = mmp_clk_register_apbc("kpc", "clk32",
226 				apbc_base + APBC_KPC, 10, 0, &clk_lock);
227 	clk_register_clkdev(clk, NULL, "pxa27x-keypad");
228 
229 	clk = mmp_clk_register_apbc("rtc", "clk32",
230 				apbc_base + APBC_RTC, 10, 0, &clk_lock);
231 	clk_register_clkdev(clk, NULL, "mmp-rtc");
232 
233 	clk = mmp_clk_register_apbc("pwm0", "vctcxo",
234 				apbc_base + APBC_PWM0, 10, 0, &clk_lock);
235 	clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
236 
237 	clk = mmp_clk_register_apbc("pwm1", "vctcxo",
238 				apbc_base + APBC_PWM1, 10, 0, &clk_lock);
239 	clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
240 
241 	clk = mmp_clk_register_apbc("pwm2", "vctcxo",
242 				apbc_base + APBC_PWM2, 10, 0, &clk_lock);
243 	clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
244 
245 	clk = mmp_clk_register_apbc("pwm3", "vctcxo",
246 				apbc_base + APBC_PWM3, 10, 0, &clk_lock);
247 	clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
248 
249 	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
250 				ARRAY_SIZE(uart_parent),
251 				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
252 				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
253 	clk_set_parent(clk, vctcxo);
254 	clk_register_clkdev(clk, "uart_mux.0", NULL);
255 
256 	clk = mmp_clk_register_apbc("uart0", "uart0_mux",
257 				apbc_base + APBC_UART0, 10, 0, &clk_lock);
258 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
259 
260 	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
261 				ARRAY_SIZE(uart_parent),
262 				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
263 				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
264 	clk_set_parent(clk, vctcxo);
265 	clk_register_clkdev(clk, "uart_mux.1", NULL);
266 
267 	clk = mmp_clk_register_apbc("uart1", "uart1_mux",
268 				apbc_base + APBC_UART1, 10, 0, &clk_lock);
269 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
270 
271 	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
272 				ARRAY_SIZE(uart_parent),
273 				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
274 				apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
275 	clk_set_parent(clk, vctcxo);
276 	clk_register_clkdev(clk, "uart_mux.2", NULL);
277 
278 	clk = mmp_clk_register_apbc("uart2", "uart2_mux",
279 				apbc_base + APBC_UART2, 10, 0, &clk_lock);
280 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
281 
282 	clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
283 				ARRAY_SIZE(uart_parent),
284 				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
285 				apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
286 	clk_set_parent(clk, vctcxo);
287 	clk_register_clkdev(clk, "uart_mux.3", NULL);
288 
289 	clk = mmp_clk_register_apbc("uart3", "uart3_mux",
290 				apbc_base + APBC_UART3, 10, 0, &clk_lock);
291 	clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
292 
293 	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
294 				ARRAY_SIZE(ssp_parent),
295 				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
296 				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
297 	clk_register_clkdev(clk, "uart_mux.0", NULL);
298 
299 	clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
300 				apbc_base + APBC_SSP0, 10, 0, &clk_lock);
301 	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
302 
303 	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
304 				ARRAY_SIZE(ssp_parent),
305 				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
306 				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
307 	clk_register_clkdev(clk, "ssp_mux.1", NULL);
308 
309 	clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
310 				apbc_base + APBC_SSP1, 10, 0, &clk_lock);
311 	clk_register_clkdev(clk, NULL, "mmp-ssp.1");
312 
313 	clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
314 				ARRAY_SIZE(ssp_parent),
315 				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
316 				apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
317 	clk_register_clkdev(clk, "ssp_mux.2", NULL);
318 
319 	clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
320 				apbc_base + APBC_SSP2, 10, 0, &clk_lock);
321 	clk_register_clkdev(clk, NULL, "mmp-ssp.2");
322 
323 	clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
324 				ARRAY_SIZE(ssp_parent),
325 				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
326 				apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
327 	clk_register_clkdev(clk, "ssp_mux.3", NULL);
328 
329 	clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
330 				apbc_base + APBC_SSP3, 10, 0, &clk_lock);
331 	clk_register_clkdev(clk, NULL, "mmp-ssp.3");
332 
333 	clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
334 				ARRAY_SIZE(sdh_parent),
335 				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
336 				apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
337 	clk_register_clkdev(clk, "sdh_mux", NULL);
338 
339 	clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
340 				CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
341 				10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
342 	clk_register_clkdev(clk, "sdh_div", NULL);
343 
344 	clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
345 				0x1b, &clk_lock);
346 	clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
347 
348 	clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
349 				0x1b, &clk_lock);
350 	clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
351 
352 	clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
353 				0x1b, &clk_lock);
354 	clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
355 
356 	clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
357 				0x1b, &clk_lock);
358 	clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
359 
360 	clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
361 				0x9, &clk_lock);
362 	clk_register_clkdev(clk, "usb_clk", NULL);
363 
364 	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
365 				ARRAY_SIZE(disp_parent),
366 				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
367 				apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
368 	clk_register_clkdev(clk, "disp_mux.0", NULL);
369 
370 	clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
371 				CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
372 				8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
373 	clk_register_clkdev(clk, "disp_div.0", NULL);
374 
375 	clk = mmp_clk_register_apmu("disp0", "disp0_div",
376 				apmu_base + APMU_DISP0, 0x1b, &clk_lock);
377 	clk_register_clkdev(clk, NULL, "mmp-disp.0");
378 
379 	clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
380 				apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
381 	clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
382 
383 	clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
384 				apmu_base + APMU_DISP0, 0x1024, &clk_lock);
385 	clk_register_clkdev(clk, "disp_sphy.0", NULL);
386 
387 	clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
388 				ARRAY_SIZE(disp_parent),
389 				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
390 				apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
391 	clk_register_clkdev(clk, "disp_mux.1", NULL);
392 
393 	clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
394 				CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
395 				8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
396 	clk_register_clkdev(clk, "disp_div.1", NULL);
397 
398 	clk = mmp_clk_register_apmu("disp1", "disp1_div",
399 				apmu_base + APMU_DISP1, 0x1b, &clk_lock);
400 	clk_register_clkdev(clk, NULL, "mmp-disp.1");
401 
402 	clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
403 				apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
404 	clk_register_clkdev(clk, "ccic_arbiter", NULL);
405 
406 	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
407 				ARRAY_SIZE(ccic_parent),
408 				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
409 				apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
410 	clk_register_clkdev(clk, "ccic_mux.0", NULL);
411 
412 	clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
413 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
414 				17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
415 	clk_register_clkdev(clk, "ccic_div.0", NULL);
416 
417 	clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
418 				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
419 	clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
420 
421 	clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
422 				apmu_base + APMU_CCIC0, 0x24, &clk_lock);
423 	clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
424 
425 	clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
426 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
427 				10, 5, 0, &clk_lock);
428 	clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
429 
430 	clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
431 				apmu_base + APMU_CCIC0, 0x300, &clk_lock);
432 	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
433 
434 	clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
435 				ARRAY_SIZE(ccic_parent),
436 				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
437 				apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
438 	clk_register_clkdev(clk, "ccic_mux.1", NULL);
439 
440 	clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
441 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
442 				16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
443 	clk_register_clkdev(clk, "ccic_div.1", NULL);
444 
445 	clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
446 				apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
447 	clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
448 
449 	clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
450 				apmu_base + APMU_CCIC1, 0x24, &clk_lock);
451 	clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
452 
453 	clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
454 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
455 				10, 5, 0, &clk_lock);
456 	clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
457 
458 	clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
459 				apmu_base + APMU_CCIC1, 0x300, &clk_lock);
460 	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
461 }
462