1 /*
2 * Mediatek SoCs General-Purpose Timer handling.
3 *
4 * Copyright (C) 2014 Matthias Brugger
5 *
6 * Matthias Brugger <matthias.bgg@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqreturn.h>
24 #include <linux/of.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/sched_clock.h>
28 #include <linux/slab.h>
29
30 #define GPT_IRQ_EN_REG 0x00
31 #define GPT_IRQ_ENABLE(val) BIT((val) - 1)
32 #define GPT_IRQ_ACK_REG 0x08
33 #define GPT_IRQ_ACK(val) BIT((val) - 1)
34
35 #define TIMER_CTRL_REG(val) (0x10 * (val))
36 #define TIMER_CTRL_OP(val) (((val) & 0x3) << 4)
37 #define TIMER_CTRL_OP_ONESHOT (0)
38 #define TIMER_CTRL_OP_REPEAT (1)
39 #define TIMER_CTRL_OP_FREERUN (3)
40 #define TIMER_CTRL_CLEAR (2)
41 #define TIMER_CTRL_ENABLE (1)
42 #define TIMER_CTRL_DISABLE (0)
43
44 #define TIMER_CLK_REG(val) (0x04 + (0x10 * (val)))
45 #define TIMER_CLK_SRC(val) (((val) & 0x1) << 4)
46 #define TIMER_CLK_SRC_SYS13M (0)
47 #define TIMER_CLK_SRC_RTC32K (1)
48 #define TIMER_CLK_DIV1 (0x0)
49 #define TIMER_CLK_DIV2 (0x1)
50
51 #define TIMER_CNT_REG(val) (0x08 + (0x10 * (val)))
52 #define TIMER_CMP_REG(val) (0x0C + (0x10 * (val)))
53
54 #define GPT_CLK_EVT 1
55 #define GPT_CLK_SRC 2
56
57 struct mtk_clock_event_device {
58 void __iomem *gpt_base;
59 u32 ticks_per_jiffy;
60 struct clock_event_device dev;
61 };
62
63 static void __iomem *gpt_sched_reg __read_mostly;
64
mtk_read_sched_clock(void)65 static u64 notrace mtk_read_sched_clock(void)
66 {
67 return readl_relaxed(gpt_sched_reg);
68 }
69
to_mtk_clk(struct clock_event_device * c)70 static inline struct mtk_clock_event_device *to_mtk_clk(
71 struct clock_event_device *c)
72 {
73 return container_of(c, struct mtk_clock_event_device, dev);
74 }
75
mtk_clkevt_time_stop(struct mtk_clock_event_device * evt,u8 timer)76 static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
77 {
78 u32 val;
79
80 val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
81 writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base +
82 TIMER_CTRL_REG(timer));
83 }
84
mtk_clkevt_time_setup(struct mtk_clock_event_device * evt,unsigned long delay,u8 timer)85 static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt,
86 unsigned long delay, u8 timer)
87 {
88 writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
89 }
90
mtk_clkevt_time_start(struct mtk_clock_event_device * evt,bool periodic,u8 timer)91 static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt,
92 bool periodic, u8 timer)
93 {
94 u32 val;
95
96 /* Acknowledge interrupt */
97 writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);
98
99 val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
100
101 /* Clear 2 bit timer operation mode field */
102 val &= ~TIMER_CTRL_OP(0x3);
103
104 if (periodic)
105 val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT);
106 else
107 val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);
108
109 writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
110 evt->gpt_base + TIMER_CTRL_REG(timer));
111 }
112
mtk_clkevt_shutdown(struct clock_event_device * clk)113 static int mtk_clkevt_shutdown(struct clock_event_device *clk)
114 {
115 mtk_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT);
116 return 0;
117 }
118
mtk_clkevt_set_periodic(struct clock_event_device * clk)119 static int mtk_clkevt_set_periodic(struct clock_event_device *clk)
120 {
121 struct mtk_clock_event_device *evt = to_mtk_clk(clk);
122
123 mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
124 mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
125 mtk_clkevt_time_start(evt, true, GPT_CLK_EVT);
126 return 0;
127 }
128
mtk_clkevt_next_event(unsigned long event,struct clock_event_device * clk)129 static int mtk_clkevt_next_event(unsigned long event,
130 struct clock_event_device *clk)
131 {
132 struct mtk_clock_event_device *evt = to_mtk_clk(clk);
133
134 mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
135 mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT);
136 mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
137
138 return 0;
139 }
140
mtk_timer_interrupt(int irq,void * dev_id)141 static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
142 {
143 struct mtk_clock_event_device *evt = dev_id;
144
145 /* Acknowledge timer0 irq */
146 writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
147 evt->dev.event_handler(&evt->dev);
148
149 return IRQ_HANDLED;
150 }
151
152 static void
mtk_timer_setup(struct mtk_clock_event_device * evt,u8 timer,u8 option)153 mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
154 {
155 writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
156 evt->gpt_base + TIMER_CTRL_REG(timer));
157
158 writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1,
159 evt->gpt_base + TIMER_CLK_REG(timer));
160
161 writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
162
163 writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE,
164 evt->gpt_base + TIMER_CTRL_REG(timer));
165 }
166
mtk_timer_enable_irq(struct mtk_clock_event_device * evt,u8 timer)167 static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
168 {
169 u32 val;
170
171 /* Disable all interrupts */
172 writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
173
174 /* Acknowledge all spurious pending interrupts */
175 writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
176
177 val = readl(evt->gpt_base + GPT_IRQ_EN_REG);
178 writel(val | GPT_IRQ_ENABLE(timer),
179 evt->gpt_base + GPT_IRQ_EN_REG);
180 }
181
mtk_timer_init(struct device_node * node)182 static void __init mtk_timer_init(struct device_node *node)
183 {
184 struct mtk_clock_event_device *evt;
185 struct resource res;
186 unsigned long rate = 0;
187 struct clk *clk;
188
189 evt = kzalloc(sizeof(*evt), GFP_KERNEL);
190 if (!evt) {
191 pr_warn("Can't allocate mtk clock event driver struct");
192 return;
193 }
194
195 evt->dev.name = "mtk_tick";
196 evt->dev.rating = 300;
197 evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
198 evt->dev.set_state_shutdown = mtk_clkevt_shutdown;
199 evt->dev.set_state_periodic = mtk_clkevt_set_periodic;
200 evt->dev.set_state_oneshot = mtk_clkevt_shutdown;
201 evt->dev.tick_resume = mtk_clkevt_shutdown;
202 evt->dev.set_next_event = mtk_clkevt_next_event;
203 evt->dev.cpumask = cpu_possible_mask;
204
205 evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer");
206 if (IS_ERR(evt->gpt_base)) {
207 pr_warn("Can't get resource\n");
208 return;
209 }
210
211 evt->dev.irq = irq_of_parse_and_map(node, 0);
212 if (evt->dev.irq <= 0) {
213 pr_warn("Can't parse IRQ");
214 goto err_mem;
215 }
216
217 clk = of_clk_get(node, 0);
218 if (IS_ERR(clk)) {
219 pr_warn("Can't get timer clock");
220 goto err_irq;
221 }
222
223 if (clk_prepare_enable(clk)) {
224 pr_warn("Can't prepare clock");
225 goto err_clk_put;
226 }
227 rate = clk_get_rate(clk);
228
229 if (request_irq(evt->dev.irq, mtk_timer_interrupt,
230 IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) {
231 pr_warn("failed to setup irq %d\n", evt->dev.irq);
232 goto err_clk_disable;
233 }
234
235 evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
236
237 /* Configure clock source */
238 mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
239 clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
240 node->name, rate, 300, 32, clocksource_mmio_readl_up);
241 gpt_sched_reg = evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC);
242 sched_clock_register(mtk_read_sched_clock, 32, rate);
243
244 /* Configure clock event */
245 mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
246 clockevents_config_and_register(&evt->dev, rate, 0x3,
247 0xffffffff);
248
249 mtk_timer_enable_irq(evt, GPT_CLK_EVT);
250
251 return;
252
253 err_clk_disable:
254 clk_disable_unprepare(clk);
255 err_clk_put:
256 clk_put(clk);
257 err_irq:
258 irq_dispose_mapping(evt->dev.irq);
259 err_mem:
260 iounmap(evt->gpt_base);
261 of_address_to_resource(node, 0, &res);
262 release_mem_region(res.start, resource_size(&res));
263 }
264 CLOCKSOURCE_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init);
265