1 /*
2 * Copyright (C) 2015 Linaro Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/bitops.h>
9 #include <linux/device.h>
10 #include <linux/errno.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/irqchip/chained_irq.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20
21 #define ZX_GPIO_DIR 0x00
22 #define ZX_GPIO_IVE 0x04
23 #define ZX_GPIO_IV 0x08
24 #define ZX_GPIO_IEP 0x0C
25 #define ZX_GPIO_IEN 0x10
26 #define ZX_GPIO_DI 0x14
27 #define ZX_GPIO_DO1 0x18
28 #define ZX_GPIO_DO0 0x1C
29 #define ZX_GPIO_DO 0x20
30
31 #define ZX_GPIO_IM 0x28
32 #define ZX_GPIO_IE 0x2C
33
34 #define ZX_GPIO_MIS 0x30
35 #define ZX_GPIO_IC 0x34
36
37 #define ZX_GPIO_NR 16
38
39 struct zx_gpio {
40 spinlock_t lock;
41
42 void __iomem *base;
43 struct gpio_chip gc;
44 };
45
to_zx(struct gpio_chip * gc)46 static inline struct zx_gpio *to_zx(struct gpio_chip *gc)
47 {
48 return container_of(gc, struct zx_gpio, gc);
49 }
50
zx_direction_input(struct gpio_chip * gc,unsigned offset)51 static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
52 {
53 struct zx_gpio *chip = to_zx(gc);
54 unsigned long flags;
55 u16 gpiodir;
56
57 if (offset >= gc->ngpio)
58 return -EINVAL;
59
60 spin_lock_irqsave(&chip->lock, flags);
61 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
62 gpiodir &= ~BIT(offset);
63 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
64 spin_unlock_irqrestore(&chip->lock, flags);
65
66 return 0;
67 }
68
zx_direction_output(struct gpio_chip * gc,unsigned offset,int value)69 static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
70 int value)
71 {
72 struct zx_gpio *chip = to_zx(gc);
73 unsigned long flags;
74 u16 gpiodir;
75
76 if (offset >= gc->ngpio)
77 return -EINVAL;
78
79 spin_lock_irqsave(&chip->lock, flags);
80 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
81 gpiodir |= BIT(offset);
82 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
83
84 if (value)
85 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
86 else
87 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
88 spin_unlock_irqrestore(&chip->lock, flags);
89
90 return 0;
91 }
92
zx_get_value(struct gpio_chip * gc,unsigned offset)93 static int zx_get_value(struct gpio_chip *gc, unsigned offset)
94 {
95 struct zx_gpio *chip = to_zx(gc);
96
97 return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
98 }
99
zx_set_value(struct gpio_chip * gc,unsigned offset,int value)100 static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
101 {
102 struct zx_gpio *chip = to_zx(gc);
103
104 if (value)
105 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
106 else
107 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
108 }
109
zx_irq_type(struct irq_data * d,unsigned trigger)110 static int zx_irq_type(struct irq_data *d, unsigned trigger)
111 {
112 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
113 struct zx_gpio *chip = to_zx(gc);
114 int offset = irqd_to_hwirq(d);
115 unsigned long flags;
116 u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
117 u16 bit = BIT(offset);
118
119 if (offset < 0 || offset >= ZX_GPIO_NR)
120 return -EINVAL;
121
122 spin_lock_irqsave(&chip->lock, flags);
123
124 gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
125 gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
126 gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
127 gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
128
129 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
130 gpiois |= bit;
131 if (trigger & IRQ_TYPE_LEVEL_HIGH)
132 gpioiev |= bit;
133 else
134 gpioiev &= ~bit;
135 } else
136 gpiois &= ~bit;
137
138 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
139 gpioi_epos |= bit;
140 gpioi_eneg |= bit;
141 } else {
142 if (trigger & IRQ_TYPE_EDGE_RISING) {
143 gpioi_epos |= bit;
144 gpioi_eneg &= ~bit;
145 } else if (trigger & IRQ_TYPE_EDGE_FALLING) {
146 gpioi_eneg |= bit;
147 gpioi_epos &= ~bit;
148 }
149 }
150
151 writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
152 writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
153 writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
154 writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
155 spin_unlock_irqrestore(&chip->lock, flags);
156
157 return 0;
158 }
159
zx_irq_handler(struct irq_desc * desc)160 static void zx_irq_handler(struct irq_desc *desc)
161 {
162 unsigned long pending;
163 int offset;
164 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
165 struct zx_gpio *chip = to_zx(gc);
166 struct irq_chip *irqchip = irq_desc_get_chip(desc);
167
168 chained_irq_enter(irqchip, desc);
169
170 pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
171 writew_relaxed(pending, chip->base + ZX_GPIO_IC);
172 if (pending) {
173 for_each_set_bit(offset, &pending, ZX_GPIO_NR)
174 generic_handle_irq(irq_find_mapping(gc->irqdomain,
175 offset));
176 }
177
178 chained_irq_exit(irqchip, desc);
179 }
180
zx_irq_mask(struct irq_data * d)181 static void zx_irq_mask(struct irq_data *d)
182 {
183 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
184 struct zx_gpio *chip = to_zx(gc);
185 u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
186 u16 gpioie;
187
188 spin_lock(&chip->lock);
189 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
190 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
191 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
192 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
193 spin_unlock(&chip->lock);
194 }
195
zx_irq_unmask(struct irq_data * d)196 static void zx_irq_unmask(struct irq_data *d)
197 {
198 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
199 struct zx_gpio *chip = to_zx(gc);
200 u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
201 u16 gpioie;
202
203 spin_lock(&chip->lock);
204 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
205 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
206 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
207 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
208 spin_unlock(&chip->lock);
209 }
210
211 static struct irq_chip zx_irqchip = {
212 .name = "zx-gpio",
213 .irq_mask = zx_irq_mask,
214 .irq_unmask = zx_irq_unmask,
215 .irq_set_type = zx_irq_type,
216 };
217
zx_gpio_probe(struct platform_device * pdev)218 static int zx_gpio_probe(struct platform_device *pdev)
219 {
220 struct device *dev = &pdev->dev;
221 struct zx_gpio *chip;
222 struct resource *res;
223 int irq, id, ret;
224
225 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
226 if (!chip)
227 return -ENOMEM;
228
229 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
230 chip->base = devm_ioremap_resource(dev, res);
231 if (IS_ERR(chip->base))
232 return PTR_ERR(chip->base);
233
234 spin_lock_init(&chip->lock);
235 if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
236 chip->gc.request = gpiochip_generic_request;
237 chip->gc.free = gpiochip_generic_free;
238 }
239
240 id = of_alias_get_id(dev->of_node, "gpio");
241 chip->gc.direction_input = zx_direction_input;
242 chip->gc.direction_output = zx_direction_output;
243 chip->gc.get = zx_get_value;
244 chip->gc.set = zx_set_value;
245 chip->gc.base = ZX_GPIO_NR * id;
246 chip->gc.ngpio = ZX_GPIO_NR;
247 chip->gc.label = dev_name(dev);
248 chip->gc.dev = dev;
249 chip->gc.owner = THIS_MODULE;
250
251 ret = gpiochip_add(&chip->gc);
252 if (ret)
253 return ret;
254
255 /*
256 * irq_chip support
257 */
258 writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
259 writew_relaxed(0, chip->base + ZX_GPIO_IE);
260 irq = platform_get_irq(pdev, 0);
261 if (irq < 0) {
262 dev_err(dev, "invalid IRQ\n");
263 gpiochip_remove(&chip->gc);
264 return -ENODEV;
265 }
266
267 ret = gpiochip_irqchip_add(&chip->gc, &zx_irqchip,
268 0, handle_simple_irq,
269 IRQ_TYPE_NONE);
270 if (ret) {
271 dev_err(dev, "could not add irqchip\n");
272 gpiochip_remove(&chip->gc);
273 return ret;
274 }
275 gpiochip_set_chained_irqchip(&chip->gc, &zx_irqchip,
276 irq, zx_irq_handler);
277
278 platform_set_drvdata(pdev, chip);
279 dev_info(dev, "ZX GPIO chip registered\n");
280
281 return 0;
282 }
283
284 static const struct of_device_id zx_gpio_match[] = {
285 {
286 .compatible = "zte,zx296702-gpio",
287 },
288 { },
289 };
290 MODULE_DEVICE_TABLE(of, zx_gpio_match);
291
292 static struct platform_driver zx_gpio_driver = {
293 .probe = zx_gpio_probe,
294 .driver = {
295 .name = "zx_gpio",
296 .of_match_table = of_match_ptr(zx_gpio_match),
297 },
298 };
299
300 module_platform_driver(zx_gpio_driver)
301
302 MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
303 MODULE_DESCRIPTION("ZTE ZX296702 GPIO driver");
304 MODULE_LICENSE("GPL");
305