1 /*
2 * (C) Copyright 2009-2010
3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
4 *
5 * Portions Copyright (C) 2010, 2011 Cavium Networks, Inc.
6 *
7 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/platform_device.h>
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/delay.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/i2c.h>
22 #include <linux/io.h>
23 #include <linux/of.h>
24
25 #include <asm/octeon/octeon.h>
26
27 #define DRV_NAME "i2c-octeon"
28
29 /* The previous out-of-tree version was implicitly version 1.0. */
30 #define DRV_VERSION "2.0"
31
32 /* register offsets */
33 #define SW_TWSI 0x00
34 #define TWSI_INT 0x10
35
36 /* Controller command patterns */
37 #define SW_TWSI_V 0x8000000000000000ull
38 #define SW_TWSI_EOP_TWSI_DATA 0x0C00000100000000ull
39 #define SW_TWSI_EOP_TWSI_CTL 0x0C00000200000000ull
40 #define SW_TWSI_EOP_TWSI_CLKCTL 0x0C00000300000000ull
41 #define SW_TWSI_EOP_TWSI_STAT 0x0C00000300000000ull
42 #define SW_TWSI_EOP_TWSI_RST 0x0C00000700000000ull
43 #define SW_TWSI_OP_TWSI_CLK 0x0800000000000000ull
44 #define SW_TWSI_R 0x0100000000000000ull
45
46 /* Controller command and status bits */
47 #define TWSI_CTL_CE 0x80
48 #define TWSI_CTL_ENAB 0x40
49 #define TWSI_CTL_STA 0x20
50 #define TWSI_CTL_STP 0x10
51 #define TWSI_CTL_IFLG 0x08
52 #define TWSI_CTL_AAK 0x04
53
54 /* Some status values */
55 #define STAT_START 0x08
56 #define STAT_RSTART 0x10
57 #define STAT_TXADDR_ACK 0x18
58 #define STAT_TXDATA_ACK 0x28
59 #define STAT_RXADDR_ACK 0x40
60 #define STAT_RXDATA_ACK 0x50
61 #define STAT_IDLE 0xF8
62
63 struct octeon_i2c {
64 wait_queue_head_t queue;
65 struct i2c_adapter adap;
66 int irq;
67 u32 twsi_freq;
68 int sys_freq;
69 resource_size_t twsi_phys;
70 void __iomem *twsi_base;
71 resource_size_t regsize;
72 struct device *dev;
73 };
74
75 /**
76 * octeon_i2c_write_sw - write an I2C core register.
77 * @i2c: The struct octeon_i2c.
78 * @eop_reg: Register selector.
79 * @data: Value to be written.
80 *
81 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
82 */
octeon_i2c_write_sw(struct octeon_i2c * i2c,u64 eop_reg,u8 data)83 static void octeon_i2c_write_sw(struct octeon_i2c *i2c,
84 u64 eop_reg,
85 u8 data)
86 {
87 u64 tmp;
88
89 __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
90 do {
91 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
92 } while ((tmp & SW_TWSI_V) != 0);
93 }
94
95 /**
96 * octeon_i2c_read_sw - write an I2C core register.
97 * @i2c: The struct octeon_i2c.
98 * @eop_reg: Register selector.
99 *
100 * Returns the data.
101 *
102 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
103 */
octeon_i2c_read_sw(struct octeon_i2c * i2c,u64 eop_reg)104 static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
105 {
106 u64 tmp;
107
108 __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
109 do {
110 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
111 } while ((tmp & SW_TWSI_V) != 0);
112
113 return tmp & 0xFF;
114 }
115
116 /**
117 * octeon_i2c_write_int - write the TWSI_INT register
118 * @i2c: The struct octeon_i2c.
119 * @data: Value to be written.
120 */
octeon_i2c_write_int(struct octeon_i2c * i2c,u64 data)121 static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
122 {
123 __raw_writeq(data, i2c->twsi_base + TWSI_INT);
124 __raw_readq(i2c->twsi_base + TWSI_INT);
125 }
126
127 /**
128 * octeon_i2c_int_enable - enable the TS interrupt.
129 * @i2c: The struct octeon_i2c.
130 *
131 * The interrupt will be asserted when there is non-STAT_IDLE state in
132 * the SW_TWSI_EOP_TWSI_STAT register.
133 */
octeon_i2c_int_enable(struct octeon_i2c * i2c)134 static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
135 {
136 octeon_i2c_write_int(i2c, 0x40);
137 }
138
139 /**
140 * octeon_i2c_int_disable - disable the TS interrupt.
141 * @i2c: The struct octeon_i2c.
142 */
octeon_i2c_int_disable(struct octeon_i2c * i2c)143 static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
144 {
145 octeon_i2c_write_int(i2c, 0);
146 }
147
148 /**
149 * octeon_i2c_unblock - unblock the bus.
150 * @i2c: The struct octeon_i2c.
151 *
152 * If there was a reset while a device was driving 0 to bus,
153 * bus is blocked. We toggle it free manually by some clock
154 * cycles and send a stop.
155 */
octeon_i2c_unblock(struct octeon_i2c * i2c)156 static void octeon_i2c_unblock(struct octeon_i2c *i2c)
157 {
158 int i;
159
160 dev_dbg(i2c->dev, "%s\n", __func__);
161 for (i = 0; i < 9; i++) {
162 octeon_i2c_write_int(i2c, 0x0);
163 udelay(5);
164 octeon_i2c_write_int(i2c, 0x200);
165 udelay(5);
166 }
167 octeon_i2c_write_int(i2c, 0x300);
168 udelay(5);
169 octeon_i2c_write_int(i2c, 0x100);
170 udelay(5);
171 octeon_i2c_write_int(i2c, 0x0);
172 }
173
174 /**
175 * octeon_i2c_isr - the interrupt service routine.
176 * @int: The irq, unused.
177 * @dev_id: Our struct octeon_i2c.
178 */
octeon_i2c_isr(int irq,void * dev_id)179 static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
180 {
181 struct octeon_i2c *i2c = dev_id;
182
183 octeon_i2c_int_disable(i2c);
184 wake_up(&i2c->queue);
185
186 return IRQ_HANDLED;
187 }
188
189
octeon_i2c_test_iflg(struct octeon_i2c * i2c)190 static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
191 {
192 return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
193 }
194
195 /**
196 * octeon_i2c_wait - wait for the IFLG to be set.
197 * @i2c: The struct octeon_i2c.
198 *
199 * Returns 0 on success, otherwise a negative errno.
200 */
octeon_i2c_wait(struct octeon_i2c * i2c)201 static int octeon_i2c_wait(struct octeon_i2c *i2c)
202 {
203 long result;
204
205 octeon_i2c_int_enable(i2c);
206
207 result = wait_event_timeout(i2c->queue,
208 octeon_i2c_test_iflg(i2c),
209 i2c->adap.timeout);
210
211 octeon_i2c_int_disable(i2c);
212
213 if (result == 0) {
214 dev_dbg(i2c->dev, "%s: timeout\n", __func__);
215 return -ETIMEDOUT;
216 }
217
218 return 0;
219 }
220
221 /**
222 * octeon_i2c_start - send START to the bus.
223 * @i2c: The struct octeon_i2c.
224 *
225 * Returns 0 on success, otherwise a negative errno.
226 */
octeon_i2c_start(struct octeon_i2c * i2c)227 static int octeon_i2c_start(struct octeon_i2c *i2c)
228 {
229 u8 data;
230 int result;
231
232 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
233 TWSI_CTL_ENAB | TWSI_CTL_STA);
234
235 result = octeon_i2c_wait(i2c);
236 if (result) {
237 if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
238 /*
239 * Controller refused to send start flag May
240 * be a client is holding SDA low - let's try
241 * to free it.
242 */
243 octeon_i2c_unblock(i2c);
244 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
245 TWSI_CTL_ENAB | TWSI_CTL_STA);
246
247 result = octeon_i2c_wait(i2c);
248 }
249 if (result)
250 return result;
251 }
252
253 data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
254 if ((data != STAT_START) && (data != STAT_RSTART)) {
255 dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
256 return -EIO;
257 }
258
259 return 0;
260 }
261
262 /**
263 * octeon_i2c_stop - send STOP to the bus.
264 * @i2c: The struct octeon_i2c.
265 *
266 * Returns 0 on success, otherwise a negative errno.
267 */
octeon_i2c_stop(struct octeon_i2c * i2c)268 static int octeon_i2c_stop(struct octeon_i2c *i2c)
269 {
270 u8 data;
271
272 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
273 TWSI_CTL_ENAB | TWSI_CTL_STP);
274
275 data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
276
277 if (data != STAT_IDLE) {
278 dev_err(i2c->dev, "%s: bad status(0x%x)\n", __func__, data);
279 return -EIO;
280 }
281 return 0;
282 }
283
284 /**
285 * octeon_i2c_write - send data to the bus.
286 * @i2c: The struct octeon_i2c.
287 * @target: Target address.
288 * @data: Pointer to the data to be sent.
289 * @length: Length of the data.
290 *
291 * The address is sent over the bus, then the data.
292 *
293 * Returns 0 on success, otherwise a negative errno.
294 */
octeon_i2c_write(struct octeon_i2c * i2c,int target,const u8 * data,int length)295 static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
296 const u8 *data, int length)
297 {
298 int i, result;
299 u8 tmp;
300
301 result = octeon_i2c_start(i2c);
302 if (result)
303 return result;
304
305 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
306 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
307
308 result = octeon_i2c_wait(i2c);
309 if (result)
310 return result;
311
312 for (i = 0; i < length; i++) {
313 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
314 if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
315 dev_err(i2c->dev,
316 "%s: bad status before write (0x%x)\n",
317 __func__, tmp);
318 return -EIO;
319 }
320
321 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
322 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
323
324 result = octeon_i2c_wait(i2c);
325 if (result)
326 return result;
327 }
328
329 return 0;
330 }
331
332 /**
333 * octeon_i2c_read - receive data from the bus.
334 * @i2c: The struct octeon_i2c.
335 * @target: Target address.
336 * @data: Pointer to the location to store the datae .
337 * @length: Length of the data.
338 *
339 * The address is sent over the bus, then the data is read.
340 *
341 * Returns 0 on success, otherwise a negative errno.
342 */
octeon_i2c_read(struct octeon_i2c * i2c,int target,u8 * data,int length)343 static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
344 u8 *data, int length)
345 {
346 int i, result;
347 u8 tmp;
348
349 if (length < 1)
350 return -EINVAL;
351
352 result = octeon_i2c_start(i2c);
353 if (result)
354 return result;
355
356 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target<<1) | 1);
357 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
358
359 result = octeon_i2c_wait(i2c);
360 if (result)
361 return result;
362
363 for (i = 0; i < length; i++) {
364 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
365 if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
366 dev_err(i2c->dev,
367 "%s: bad status before read (0x%x)\n",
368 __func__, tmp);
369 return -EIO;
370 }
371
372 if (i+1 < length)
373 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
374 TWSI_CTL_ENAB | TWSI_CTL_AAK);
375 else
376 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
377 TWSI_CTL_ENAB);
378
379 result = octeon_i2c_wait(i2c);
380 if (result)
381 return result;
382
383 data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
384 }
385 return 0;
386 }
387
388 /**
389 * octeon_i2c_xfer - The driver's master_xfer function.
390 * @adap: Pointer to the i2c_adapter structure.
391 * @msgs: Pointer to the messages to be processed.
392 * @num: Length of the MSGS array.
393 *
394 * Returns the number of messages processed, or a negative errno on
395 * failure.
396 */
octeon_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)397 static int octeon_i2c_xfer(struct i2c_adapter *adap,
398 struct i2c_msg *msgs,
399 int num)
400 {
401 struct i2c_msg *pmsg;
402 int i;
403 int ret = 0;
404 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
405
406 for (i = 0; ret == 0 && i < num; i++) {
407 pmsg = &msgs[i];
408 dev_dbg(i2c->dev,
409 "Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
410 pmsg->flags & I2C_M_RD ? "read" : "write",
411 pmsg->len, pmsg->addr, i + 1, num);
412 if (pmsg->flags & I2C_M_RD)
413 ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
414 pmsg->len);
415 else
416 ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
417 pmsg->len);
418 }
419 octeon_i2c_stop(i2c);
420
421 return (ret != 0) ? ret : num;
422 }
423
octeon_i2c_functionality(struct i2c_adapter * adap)424 static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
425 {
426 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
427 }
428
429 static const struct i2c_algorithm octeon_i2c_algo = {
430 .master_xfer = octeon_i2c_xfer,
431 .functionality = octeon_i2c_functionality,
432 };
433
434 static struct i2c_adapter octeon_i2c_ops = {
435 .owner = THIS_MODULE,
436 .name = "OCTEON adapter",
437 .algo = &octeon_i2c_algo,
438 .timeout = HZ / 50,
439 };
440
441 /**
442 * octeon_i2c_setclock - Calculate and set clock divisors.
443 */
octeon_i2c_setclock(struct octeon_i2c * i2c)444 static int octeon_i2c_setclock(struct octeon_i2c *i2c)
445 {
446 int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
447 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
448
449 for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
450 /*
451 * An mdiv value of less than 2 seems to not work well
452 * with ds1337 RTCs, so we constrain it to larger
453 * values.
454 */
455 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
456 /*
457 * For given ndiv and mdiv values check the
458 * two closest thp values.
459 */
460 tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
461 tclk *= (1 << ndiv_idx);
462 thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
463 for (inc = 0; inc <= 1; inc++) {
464 thp_idx = thp_base + inc;
465 if (thp_idx < 5 || thp_idx > 0xff)
466 continue;
467
468 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
469 foscl = foscl / (1 << ndiv_idx);
470 foscl = foscl / (mdiv_idx + 1) / 10;
471 diff = abs(foscl - i2c->twsi_freq);
472 if (diff < delta_hz) {
473 delta_hz = diff;
474 thp = thp_idx;
475 mdiv = mdiv_idx;
476 ndiv = ndiv_idx;
477 }
478 }
479 }
480 }
481 octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
482 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
483
484 return 0;
485 }
486
octeon_i2c_initlowlevel(struct octeon_i2c * i2c)487 static int octeon_i2c_initlowlevel(struct octeon_i2c *i2c)
488 {
489 u8 status;
490 int tries;
491
492 /* disable high level controller, enable bus access */
493 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
494
495 /* reset controller */
496 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
497
498 for (tries = 10; tries; tries--) {
499 udelay(1);
500 status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
501 if (status == STAT_IDLE)
502 return 0;
503 }
504 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
505 return -EIO;
506 }
507
octeon_i2c_probe(struct platform_device * pdev)508 static int octeon_i2c_probe(struct platform_device *pdev)
509 {
510 int irq, result = 0;
511 struct octeon_i2c *i2c;
512 struct resource *res_mem;
513
514 /* All adaptors have an irq. */
515 irq = platform_get_irq(pdev, 0);
516 if (irq < 0)
517 return irq;
518
519 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
520 if (!i2c) {
521 dev_err(&pdev->dev, "kzalloc failed\n");
522 result = -ENOMEM;
523 goto out;
524 }
525 i2c->dev = &pdev->dev;
526
527 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
528
529 if (res_mem == NULL) {
530 dev_err(i2c->dev, "found no memory resource\n");
531 result = -ENXIO;
532 goto out;
533 }
534 i2c->twsi_phys = res_mem->start;
535 i2c->regsize = resource_size(res_mem);
536
537 /*
538 * "clock-rate" is a legacy binding, the official binding is
539 * "clock-frequency". Try the official one first and then
540 * fall back if it doesn't exist.
541 */
542 if (of_property_read_u32(pdev->dev.of_node,
543 "clock-frequency", &i2c->twsi_freq) &&
544 of_property_read_u32(pdev->dev.of_node,
545 "clock-rate", &i2c->twsi_freq)) {
546 dev_err(i2c->dev,
547 "no I2C 'clock-rate' or 'clock-frequency' property\n");
548 result = -ENXIO;
549 goto out;
550 }
551
552 i2c->sys_freq = octeon_get_io_clock_rate();
553
554 if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize,
555 res_mem->name)) {
556 dev_err(i2c->dev, "request_mem_region failed\n");
557 goto out;
558 }
559 i2c->twsi_base = devm_ioremap(&pdev->dev, i2c->twsi_phys, i2c->regsize);
560
561 init_waitqueue_head(&i2c->queue);
562
563 i2c->irq = irq;
564
565 result = devm_request_irq(&pdev->dev, i2c->irq,
566 octeon_i2c_isr, 0, DRV_NAME, i2c);
567 if (result < 0) {
568 dev_err(i2c->dev, "failed to attach interrupt\n");
569 goto out;
570 }
571
572 result = octeon_i2c_initlowlevel(i2c);
573 if (result) {
574 dev_err(i2c->dev, "init low level failed\n");
575 goto out;
576 }
577
578 result = octeon_i2c_setclock(i2c);
579 if (result) {
580 dev_err(i2c->dev, "clock init failed\n");
581 goto out;
582 }
583
584 i2c->adap = octeon_i2c_ops;
585 i2c->adap.dev.parent = &pdev->dev;
586 i2c->adap.dev.of_node = pdev->dev.of_node;
587 i2c_set_adapdata(&i2c->adap, i2c);
588 platform_set_drvdata(pdev, i2c);
589
590 result = i2c_add_adapter(&i2c->adap);
591 if (result < 0) {
592 dev_err(i2c->dev, "failed to add adapter\n");
593 goto out;
594 }
595 dev_info(i2c->dev, "version %s\n", DRV_VERSION);
596
597 return 0;
598
599 out:
600 return result;
601 };
602
octeon_i2c_remove(struct platform_device * pdev)603 static int octeon_i2c_remove(struct platform_device *pdev)
604 {
605 struct octeon_i2c *i2c = platform_get_drvdata(pdev);
606
607 i2c_del_adapter(&i2c->adap);
608 return 0;
609 };
610
611 static struct of_device_id octeon_i2c_match[] = {
612 {
613 .compatible = "cavium,octeon-3860-twsi",
614 },
615 {},
616 };
617 MODULE_DEVICE_TABLE(of, octeon_i2c_match);
618
619 static struct platform_driver octeon_i2c_driver = {
620 .probe = octeon_i2c_probe,
621 .remove = octeon_i2c_remove,
622 .driver = {
623 .name = DRV_NAME,
624 .of_match_table = octeon_i2c_match,
625 },
626 };
627
628 module_platform_driver(octeon_i2c_driver);
629
630 MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
631 MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
632 MODULE_LICENSE("GPL");
633 MODULE_VERSION(DRV_VERSION);
634