1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_ADMINQ_CMD_H_ 28 #define _I40E_ADMINQ_CMD_H_ 29 30 /* This header file defines the i40e Admin Queue commands and is shared between 31 * i40e Firmware and Software. 32 * 33 * This file needs to comply with the Linux Kernel coding style. 34 */ 35 36 #define I40E_FW_API_VERSION_MAJOR 0x0001 37 #define I40E_FW_API_VERSION_MINOR 0x0004 38 39 struct i40e_aq_desc { 40 __le16 flags; 41 __le16 opcode; 42 __le16 datalen; 43 __le16 retval; 44 __le32 cookie_high; 45 __le32 cookie_low; 46 union { 47 struct { 48 __le32 param0; 49 __le32 param1; 50 __le32 param2; 51 __le32 param3; 52 } internal; 53 struct { 54 __le32 param0; 55 __le32 param1; 56 __le32 addr_high; 57 __le32 addr_low; 58 } external; 59 u8 raw[16]; 60 } params; 61 }; 62 63 /* Flags sub-structure 64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 66 */ 67 68 /* command flags and offsets*/ 69 #define I40E_AQ_FLAG_DD_SHIFT 0 70 #define I40E_AQ_FLAG_CMP_SHIFT 1 71 #define I40E_AQ_FLAG_ERR_SHIFT 2 72 #define I40E_AQ_FLAG_VFE_SHIFT 3 73 #define I40E_AQ_FLAG_LB_SHIFT 9 74 #define I40E_AQ_FLAG_RD_SHIFT 10 75 #define I40E_AQ_FLAG_VFC_SHIFT 11 76 #define I40E_AQ_FLAG_BUF_SHIFT 12 77 #define I40E_AQ_FLAG_SI_SHIFT 13 78 #define I40E_AQ_FLAG_EI_SHIFT 14 79 #define I40E_AQ_FLAG_FE_SHIFT 15 80 81 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 82 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 83 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 84 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 85 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 86 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 87 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 88 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 89 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 90 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 91 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 92 93 /* error codes */ 94 enum i40e_admin_queue_err { 95 I40E_AQ_RC_OK = 0, /* success */ 96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 97 I40E_AQ_RC_ENOENT = 2, /* No such element */ 98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 100 I40E_AQ_RC_EIO = 5, /* I/O error */ 101 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 103 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 105 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 106 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 108 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 117 I40E_AQ_RC_EFBIG = 22, /* File too large */ 118 }; 119 120 /* Admin Queue command opcodes */ 121 enum i40e_admin_queue_opc { 122 /* aq commands */ 123 i40e_aqc_opc_get_version = 0x0001, 124 i40e_aqc_opc_driver_version = 0x0002, 125 i40e_aqc_opc_queue_shutdown = 0x0003, 126 i40e_aqc_opc_set_pf_context = 0x0004, 127 128 /* resource ownership */ 129 i40e_aqc_opc_request_resource = 0x0008, 130 i40e_aqc_opc_release_resource = 0x0009, 131 132 i40e_aqc_opc_list_func_capabilities = 0x000A, 133 i40e_aqc_opc_list_dev_capabilities = 0x000B, 134 135 /* LAA */ 136 i40e_aqc_opc_mac_address_read = 0x0107, 137 i40e_aqc_opc_mac_address_write = 0x0108, 138 139 /* PXE */ 140 i40e_aqc_opc_clear_pxe_mode = 0x0110, 141 142 /* internal switch commands */ 143 i40e_aqc_opc_get_switch_config = 0x0200, 144 i40e_aqc_opc_add_statistics = 0x0201, 145 i40e_aqc_opc_remove_statistics = 0x0202, 146 i40e_aqc_opc_set_port_parameters = 0x0203, 147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 148 149 i40e_aqc_opc_add_vsi = 0x0210, 150 i40e_aqc_opc_update_vsi_parameters = 0x0211, 151 i40e_aqc_opc_get_vsi_parameters = 0x0212, 152 153 i40e_aqc_opc_add_pv = 0x0220, 154 i40e_aqc_opc_update_pv_parameters = 0x0221, 155 i40e_aqc_opc_get_pv_parameters = 0x0222, 156 157 i40e_aqc_opc_add_veb = 0x0230, 158 i40e_aqc_opc_update_veb_parameters = 0x0231, 159 i40e_aqc_opc_get_veb_parameters = 0x0232, 160 161 i40e_aqc_opc_delete_element = 0x0243, 162 163 i40e_aqc_opc_add_macvlan = 0x0250, 164 i40e_aqc_opc_remove_macvlan = 0x0251, 165 i40e_aqc_opc_add_vlan = 0x0252, 166 i40e_aqc_opc_remove_vlan = 0x0253, 167 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 168 i40e_aqc_opc_add_tag = 0x0255, 169 i40e_aqc_opc_remove_tag = 0x0256, 170 i40e_aqc_opc_add_multicast_etag = 0x0257, 171 i40e_aqc_opc_remove_multicast_etag = 0x0258, 172 i40e_aqc_opc_update_tag = 0x0259, 173 i40e_aqc_opc_add_control_packet_filter = 0x025A, 174 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 175 i40e_aqc_opc_add_cloud_filters = 0x025C, 176 i40e_aqc_opc_remove_cloud_filters = 0x025D, 177 178 i40e_aqc_opc_add_mirror_rule = 0x0260, 179 i40e_aqc_opc_delete_mirror_rule = 0x0261, 180 181 /* DCB commands */ 182 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 183 i40e_aqc_opc_dcb_updated = 0x0302, 184 185 /* TX scheduler */ 186 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 187 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 188 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 189 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 190 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 191 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 192 193 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 194 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 195 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 196 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 197 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 198 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 199 i40e_aqc_opc_query_port_ets_config = 0x0419, 200 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 201 i40e_aqc_opc_suspend_port_tx = 0x041B, 202 i40e_aqc_opc_resume_port_tx = 0x041C, 203 i40e_aqc_opc_configure_partition_bw = 0x041D, 204 205 /* hmc */ 206 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 207 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 208 209 /* phy commands*/ 210 i40e_aqc_opc_get_phy_abilities = 0x0600, 211 i40e_aqc_opc_set_phy_config = 0x0601, 212 i40e_aqc_opc_set_mac_config = 0x0603, 213 i40e_aqc_opc_set_link_restart_an = 0x0605, 214 i40e_aqc_opc_get_link_status = 0x0607, 215 i40e_aqc_opc_set_phy_int_mask = 0x0613, 216 i40e_aqc_opc_get_local_advt_reg = 0x0614, 217 i40e_aqc_opc_set_local_advt_reg = 0x0615, 218 i40e_aqc_opc_get_partner_advt = 0x0616, 219 i40e_aqc_opc_set_lb_modes = 0x0618, 220 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 221 i40e_aqc_opc_set_phy_debug = 0x0622, 222 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 223 224 /* NVM commands */ 225 i40e_aqc_opc_nvm_read = 0x0701, 226 i40e_aqc_opc_nvm_erase = 0x0702, 227 i40e_aqc_opc_nvm_update = 0x0703, 228 i40e_aqc_opc_nvm_config_read = 0x0704, 229 i40e_aqc_opc_nvm_config_write = 0x0705, 230 231 /* virtualization commands */ 232 i40e_aqc_opc_send_msg_to_pf = 0x0801, 233 i40e_aqc_opc_send_msg_to_vf = 0x0802, 234 i40e_aqc_opc_send_msg_to_peer = 0x0803, 235 236 /* alternate structure */ 237 i40e_aqc_opc_alternate_write = 0x0900, 238 i40e_aqc_opc_alternate_write_indirect = 0x0901, 239 i40e_aqc_opc_alternate_read = 0x0902, 240 i40e_aqc_opc_alternate_read_indirect = 0x0903, 241 i40e_aqc_opc_alternate_write_done = 0x0904, 242 i40e_aqc_opc_alternate_set_mode = 0x0905, 243 i40e_aqc_opc_alternate_clear_port = 0x0906, 244 245 /* LLDP commands */ 246 i40e_aqc_opc_lldp_get_mib = 0x0A00, 247 i40e_aqc_opc_lldp_update_mib = 0x0A01, 248 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 249 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 250 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 251 i40e_aqc_opc_lldp_stop = 0x0A05, 252 i40e_aqc_opc_lldp_start = 0x0A06, 253 254 /* Tunnel commands */ 255 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 256 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 257 i40e_aqc_opc_set_rss_key = 0x0B02, 258 i40e_aqc_opc_set_rss_lut = 0x0B03, 259 i40e_aqc_opc_get_rss_key = 0x0B04, 260 i40e_aqc_opc_get_rss_lut = 0x0B05, 261 262 /* Async Events */ 263 i40e_aqc_opc_event_lan_overflow = 0x1001, 264 265 /* OEM commands */ 266 i40e_aqc_opc_oem_parameter_change = 0xFE00, 267 i40e_aqc_opc_oem_device_status_change = 0xFE01, 268 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 269 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 270 271 /* debug commands */ 272 i40e_aqc_opc_debug_read_reg = 0xFF03, 273 i40e_aqc_opc_debug_write_reg = 0xFF04, 274 i40e_aqc_opc_debug_modify_reg = 0xFF07, 275 i40e_aqc_opc_debug_dump_internals = 0xFF08, 276 }; 277 278 /* command structures and indirect data structures */ 279 280 /* Structure naming conventions: 281 * - no suffix for direct command descriptor structures 282 * - _data for indirect sent data 283 * - _resp for indirect return data (data which is both will use _data) 284 * - _completion for direct return data 285 * - _element_ for repeated elements (may also be _data or _resp) 286 * 287 * Command structures are expected to overlay the params.raw member of the basic 288 * descriptor, and as such cannot exceed 16 bytes in length. 289 */ 290 291 /* This macro is used to generate a compilation error if a structure 292 * is not exactly the correct length. It gives a divide by zero error if the 293 * structure is not of the correct size, otherwise it creates an enum that is 294 * never used. 295 */ 296 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 297 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 298 299 /* This macro is used extensively to ensure that command structures are 16 300 * bytes in length as they have to map to the raw array of that size. 301 */ 302 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 303 304 /* internal (0x00XX) commands */ 305 306 /* Get version (direct 0x0001) */ 307 struct i40e_aqc_get_version { 308 __le32 rom_ver; 309 __le32 fw_build; 310 __le16 fw_major; 311 __le16 fw_minor; 312 __le16 api_major; 313 __le16 api_minor; 314 }; 315 316 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 317 318 /* Send driver version (indirect 0x0002) */ 319 struct i40e_aqc_driver_version { 320 u8 driver_major_ver; 321 u8 driver_minor_ver; 322 u8 driver_build_ver; 323 u8 driver_subbuild_ver; 324 u8 reserved[4]; 325 __le32 address_high; 326 __le32 address_low; 327 }; 328 329 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 330 331 /* Queue Shutdown (direct 0x0003) */ 332 struct i40e_aqc_queue_shutdown { 333 __le32 driver_unloading; 334 #define I40E_AQ_DRIVER_UNLOADING 0x1 335 u8 reserved[12]; 336 }; 337 338 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 339 340 /* Set PF context (0x0004, direct) */ 341 struct i40e_aqc_set_pf_context { 342 u8 pf_id; 343 u8 reserved[15]; 344 }; 345 346 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 347 348 /* Request resource ownership (direct 0x0008) 349 * Release resource ownership (direct 0x0009) 350 */ 351 #define I40E_AQ_RESOURCE_NVM 1 352 #define I40E_AQ_RESOURCE_SDP 2 353 #define I40E_AQ_RESOURCE_ACCESS_READ 1 354 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 355 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 356 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 357 358 struct i40e_aqc_request_resource { 359 __le16 resource_id; 360 __le16 access_type; 361 __le32 timeout; 362 __le32 resource_number; 363 u8 reserved[4]; 364 }; 365 366 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 367 368 /* Get function capabilities (indirect 0x000A) 369 * Get device capabilities (indirect 0x000B) 370 */ 371 struct i40e_aqc_list_capabilites { 372 u8 command_flags; 373 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 374 u8 pf_index; 375 u8 reserved[2]; 376 __le32 count; 377 __le32 addr_high; 378 __le32 addr_low; 379 }; 380 381 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 382 383 struct i40e_aqc_list_capabilities_element_resp { 384 __le16 id; 385 u8 major_rev; 386 u8 minor_rev; 387 __le32 number; 388 __le32 logical_id; 389 __le32 phys_id; 390 u8 reserved[16]; 391 }; 392 393 /* list of caps */ 394 395 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 396 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 397 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 398 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 399 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 400 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 401 #define I40E_AQ_CAP_ID_SRIOV 0x0012 402 #define I40E_AQ_CAP_ID_VF 0x0013 403 #define I40E_AQ_CAP_ID_VMDQ 0x0014 404 #define I40E_AQ_CAP_ID_8021QBG 0x0015 405 #define I40E_AQ_CAP_ID_8021QBR 0x0016 406 #define I40E_AQ_CAP_ID_VSI 0x0017 407 #define I40E_AQ_CAP_ID_DCB 0x0018 408 #define I40E_AQ_CAP_ID_FCOE 0x0021 409 #define I40E_AQ_CAP_ID_ISCSI 0x0022 410 #define I40E_AQ_CAP_ID_RSS 0x0040 411 #define I40E_AQ_CAP_ID_RXQ 0x0041 412 #define I40E_AQ_CAP_ID_TXQ 0x0042 413 #define I40E_AQ_CAP_ID_MSIX 0x0043 414 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 415 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 416 #define I40E_AQ_CAP_ID_1588 0x0046 417 #define I40E_AQ_CAP_ID_IWARP 0x0051 418 #define I40E_AQ_CAP_ID_LED 0x0061 419 #define I40E_AQ_CAP_ID_SDP 0x0062 420 #define I40E_AQ_CAP_ID_MDIO 0x0063 421 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 422 #define I40E_AQ_CAP_ID_CEM 0x00F2 423 424 /* Set CPPM Configuration (direct 0x0103) */ 425 struct i40e_aqc_cppm_configuration { 426 __le16 command_flags; 427 #define I40E_AQ_CPPM_EN_LTRC 0x0800 428 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 429 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 430 #define I40E_AQ_CPPM_EN_HPTC 0x4000 431 #define I40E_AQ_CPPM_EN_DMARC 0x8000 432 __le16 ttlx; 433 __le32 dmacr; 434 __le16 dmcth; 435 u8 hptc; 436 u8 reserved; 437 __le32 pfltrc; 438 }; 439 440 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 441 442 /* Set ARP Proxy command / response (indirect 0x0104) */ 443 struct i40e_aqc_arp_proxy_data { 444 __le16 command_flags; 445 #define I40E_AQ_ARP_INIT_IPV4 0x0008 446 #define I40E_AQ_ARP_UNSUP_CTL 0x0010 447 #define I40E_AQ_ARP_ENA 0x0020 448 #define I40E_AQ_ARP_ADD_IPV4 0x0040 449 #define I40E_AQ_ARP_DEL_IPV4 0x0080 450 __le16 table_id; 451 __le32 pfpm_proxyfc; 452 __le32 ip_addr; 453 u8 mac_addr[6]; 454 u8 reserved[2]; 455 }; 456 457 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 458 459 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 460 struct i40e_aqc_ns_proxy_data { 461 __le16 table_idx_mac_addr_0; 462 __le16 table_idx_mac_addr_1; 463 __le16 table_idx_ipv6_0; 464 __le16 table_idx_ipv6_1; 465 __le16 control; 466 #define I40E_AQ_NS_PROXY_ADD_0 0x0100 467 #define I40E_AQ_NS_PROXY_DEL_0 0x0200 468 #define I40E_AQ_NS_PROXY_ADD_1 0x0400 469 #define I40E_AQ_NS_PROXY_DEL_1 0x0800 470 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 471 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 472 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 473 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 474 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 475 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 476 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 477 u8 mac_addr_0[6]; 478 u8 mac_addr_1[6]; 479 u8 local_mac_addr[6]; 480 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 481 u8 ipv6_addr_1[16]; 482 }; 483 484 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 485 486 /* Manage LAA Command (0x0106) - obsolete */ 487 struct i40e_aqc_mng_laa { 488 __le16 command_flags; 489 #define I40E_AQ_LAA_FLAG_WR 0x8000 490 u8 reserved[2]; 491 __le32 sal; 492 __le16 sah; 493 u8 reserved2[6]; 494 }; 495 496 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 497 498 /* Manage MAC Address Read Command (indirect 0x0107) */ 499 struct i40e_aqc_mac_address_read { 500 __le16 command_flags; 501 #define I40E_AQC_LAN_ADDR_VALID 0x10 502 #define I40E_AQC_SAN_ADDR_VALID 0x20 503 #define I40E_AQC_PORT_ADDR_VALID 0x40 504 #define I40E_AQC_WOL_ADDR_VALID 0x80 505 #define I40E_AQC_MC_MAG_EN_VALID 0x100 506 #define I40E_AQC_ADDR_VALID_MASK 0x1F0 507 u8 reserved[6]; 508 __le32 addr_high; 509 __le32 addr_low; 510 }; 511 512 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 513 514 struct i40e_aqc_mac_address_read_data { 515 u8 pf_lan_mac[6]; 516 u8 pf_san_mac[6]; 517 u8 port_mac[6]; 518 u8 pf_wol_mac[6]; 519 }; 520 521 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 522 523 /* Manage MAC Address Write Command (0x0108) */ 524 struct i40e_aqc_mac_address_write { 525 __le16 command_flags; 526 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 527 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 528 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 529 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 530 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 531 532 __le16 mac_sah; 533 __le32 mac_sal; 534 u8 reserved[8]; 535 }; 536 537 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 538 539 /* PXE commands (0x011x) */ 540 541 /* Clear PXE Command and response (direct 0x0110) */ 542 struct i40e_aqc_clear_pxe { 543 u8 rx_cnt; 544 u8 reserved[15]; 545 }; 546 547 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 548 549 /* Switch configuration commands (0x02xx) */ 550 551 /* Used by many indirect commands that only pass an seid and a buffer in the 552 * command 553 */ 554 struct i40e_aqc_switch_seid { 555 __le16 seid; 556 u8 reserved[6]; 557 __le32 addr_high; 558 __le32 addr_low; 559 }; 560 561 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 562 563 /* Get Switch Configuration command (indirect 0x0200) 564 * uses i40e_aqc_switch_seid for the descriptor 565 */ 566 struct i40e_aqc_get_switch_config_header_resp { 567 __le16 num_reported; 568 __le16 num_total; 569 u8 reserved[12]; 570 }; 571 572 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 573 574 struct i40e_aqc_switch_config_element_resp { 575 u8 element_type; 576 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 577 #define I40E_AQ_SW_ELEM_TYPE_PF 2 578 #define I40E_AQ_SW_ELEM_TYPE_VF 3 579 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 580 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 581 #define I40E_AQ_SW_ELEM_TYPE_PV 16 582 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 583 #define I40E_AQ_SW_ELEM_TYPE_PA 18 584 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 585 u8 revision; 586 #define I40E_AQ_SW_ELEM_REV_1 1 587 __le16 seid; 588 __le16 uplink_seid; 589 __le16 downlink_seid; 590 u8 reserved[3]; 591 u8 connection_type; 592 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 593 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 594 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 595 __le16 scheduler_id; 596 __le16 element_info; 597 }; 598 599 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 600 601 /* Get Switch Configuration (indirect 0x0200) 602 * an array of elements are returned in the response buffer 603 * the first in the array is the header, remainder are elements 604 */ 605 struct i40e_aqc_get_switch_config_resp { 606 struct i40e_aqc_get_switch_config_header_resp header; 607 struct i40e_aqc_switch_config_element_resp element[1]; 608 }; 609 610 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 611 612 /* Add Statistics (direct 0x0201) 613 * Remove Statistics (direct 0x0202) 614 */ 615 struct i40e_aqc_add_remove_statistics { 616 __le16 seid; 617 __le16 vlan; 618 __le16 stat_index; 619 u8 reserved[10]; 620 }; 621 622 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 623 624 /* Set Port Parameters command (direct 0x0203) */ 625 struct i40e_aqc_set_port_parameters { 626 __le16 command_flags; 627 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 628 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 629 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 630 __le16 bad_frame_vsi; 631 __le16 default_seid; /* reserved for command */ 632 u8 reserved[10]; 633 }; 634 635 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 636 637 /* Get Switch Resource Allocation (indirect 0x0204) */ 638 struct i40e_aqc_get_switch_resource_alloc { 639 u8 num_entries; /* reserved for command */ 640 u8 reserved[7]; 641 __le32 addr_high; 642 __le32 addr_low; 643 }; 644 645 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 646 647 /* expect an array of these structs in the response buffer */ 648 struct i40e_aqc_switch_resource_alloc_element_resp { 649 u8 resource_type; 650 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 651 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 652 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 653 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 654 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 655 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 656 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 657 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 658 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 659 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 660 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 661 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 662 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 663 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 664 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 665 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 666 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 667 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 668 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 669 u8 reserved1; 670 __le16 guaranteed; 671 __le16 total; 672 __le16 used; 673 __le16 total_unalloced; 674 u8 reserved2[6]; 675 }; 676 677 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 678 679 /* Add VSI (indirect 0x0210) 680 * this indirect command uses struct i40e_aqc_vsi_properties_data 681 * as the indirect buffer (128 bytes) 682 * 683 * Update VSI (indirect 0x211) 684 * uses the same data structure as Add VSI 685 * 686 * Get VSI (indirect 0x0212) 687 * uses the same completion and data structure as Add VSI 688 */ 689 struct i40e_aqc_add_get_update_vsi { 690 __le16 uplink_seid; 691 u8 connection_type; 692 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 693 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 694 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 695 u8 reserved1; 696 u8 vf_id; 697 u8 reserved2; 698 __le16 vsi_flags; 699 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 700 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 701 #define I40E_AQ_VSI_TYPE_VF 0x0 702 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 703 #define I40E_AQ_VSI_TYPE_PF 0x2 704 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 705 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 706 __le32 addr_high; 707 __le32 addr_low; 708 }; 709 710 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 711 712 struct i40e_aqc_add_get_update_vsi_completion { 713 __le16 seid; 714 __le16 vsi_number; 715 __le16 vsi_used; 716 __le16 vsi_free; 717 __le32 addr_high; 718 __le32 addr_low; 719 }; 720 721 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 722 723 struct i40e_aqc_vsi_properties_data { 724 /* first 96 byte are written by SW */ 725 __le16 valid_sections; 726 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 727 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 728 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 729 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 730 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 731 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 732 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 733 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 734 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 735 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 736 /* switch section */ 737 __le16 switch_id; /* 12bit id combined with flags below */ 738 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 739 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 740 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 741 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 742 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 743 u8 sw_reserved[2]; 744 /* security section */ 745 u8 sec_flags; 746 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 747 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 748 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 749 u8 sec_reserved; 750 /* VLAN section */ 751 __le16 pvid; /* VLANS include priority bits */ 752 __le16 fcoe_pvid; 753 u8 port_vlan_flags; 754 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 755 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 756 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 757 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 758 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 759 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 760 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 761 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 762 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 763 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 764 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 765 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 766 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 767 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 768 u8 pvlan_reserved[3]; 769 /* ingress egress up sections */ 770 __le32 ingress_table; /* bitmap, 3 bits per up */ 771 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 772 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 773 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 774 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 775 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 776 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 777 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 778 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 779 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 780 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 781 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 782 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 783 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 784 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 785 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 786 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 787 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 788 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 789 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 790 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 791 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 792 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 793 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 794 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 795 __le32 egress_table; /* same defines as for ingress table */ 796 /* cascaded PV section */ 797 __le16 cas_pv_tag; 798 u8 cas_pv_flags; 799 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 800 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 801 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 802 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 803 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 804 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 805 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 806 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 807 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 808 u8 cas_pv_reserved; 809 /* queue mapping section */ 810 __le16 mapping_flags; 811 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 812 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 813 __le16 queue_mapping[16]; 814 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 815 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 816 __le16 tc_mapping[8]; 817 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 818 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 819 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 820 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 821 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 822 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 823 /* queueing option section */ 824 u8 queueing_opt_flags; 825 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 826 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 827 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 828 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 829 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 830 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 831 u8 queueing_opt_reserved[3]; 832 /* scheduler section */ 833 u8 up_enable_bits; 834 u8 sched_reserved; 835 /* outer up section */ 836 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 837 u8 cmd_reserved[8]; 838 /* last 32 bytes are written by FW */ 839 __le16 qs_handle[8]; 840 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 841 __le16 stat_counter_idx; 842 __le16 sched_id; 843 u8 resp_reserved[12]; 844 }; 845 846 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 847 848 /* Add Port Virtualizer (direct 0x0220) 849 * also used for update PV (direct 0x0221) but only flags are used 850 * (IS_CTRL_PORT only works on add PV) 851 */ 852 struct i40e_aqc_add_update_pv { 853 __le16 command_flags; 854 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 855 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 856 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 857 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 858 __le16 uplink_seid; 859 __le16 connected_seid; 860 u8 reserved[10]; 861 }; 862 863 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 864 865 struct i40e_aqc_add_update_pv_completion { 866 /* reserved for update; for add also encodes error if rc == ENOSPC */ 867 __le16 pv_seid; 868 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 869 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 870 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 871 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 872 u8 reserved[14]; 873 }; 874 875 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 876 877 /* Get PV Params (direct 0x0222) 878 * uses i40e_aqc_switch_seid for the descriptor 879 */ 880 881 struct i40e_aqc_get_pv_params_completion { 882 __le16 seid; 883 __le16 default_stag; 884 __le16 pv_flags; /* same flags as add_pv */ 885 #define I40E_AQC_GET_PV_PV_TYPE 0x1 886 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 887 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 888 u8 reserved[8]; 889 __le16 default_port_seid; 890 }; 891 892 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 893 894 /* Add VEB (direct 0x0230) */ 895 struct i40e_aqc_add_veb { 896 __le16 uplink_seid; 897 __le16 downlink_seid; 898 __le16 veb_flags; 899 #define I40E_AQC_ADD_VEB_FLOATING 0x1 900 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 901 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 902 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 903 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 904 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 905 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 906 u8 enable_tcs; 907 u8 reserved[9]; 908 }; 909 910 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 911 912 struct i40e_aqc_add_veb_completion { 913 u8 reserved[6]; 914 __le16 switch_seid; 915 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 916 __le16 veb_seid; 917 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 918 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 919 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 920 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 921 __le16 statistic_index; 922 __le16 vebs_used; 923 __le16 vebs_free; 924 }; 925 926 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 927 928 /* Get VEB Parameters (direct 0x0232) 929 * uses i40e_aqc_switch_seid for the descriptor 930 */ 931 struct i40e_aqc_get_veb_parameters_completion { 932 __le16 seid; 933 __le16 switch_id; 934 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 935 __le16 statistic_index; 936 __le16 vebs_used; 937 __le16 vebs_free; 938 u8 reserved[4]; 939 }; 940 941 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 942 943 /* Delete Element (direct 0x0243) 944 * uses the generic i40e_aqc_switch_seid 945 */ 946 947 /* Add MAC-VLAN (indirect 0x0250) */ 948 949 /* used for the command for most vlan commands */ 950 struct i40e_aqc_macvlan { 951 __le16 num_addresses; 952 __le16 seid[3]; 953 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 954 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 955 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 956 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 957 __le32 addr_high; 958 __le32 addr_low; 959 }; 960 961 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 962 963 /* indirect data for command and response */ 964 struct i40e_aqc_add_macvlan_element_data { 965 u8 mac_addr[6]; 966 __le16 vlan_tag; 967 __le16 flags; 968 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 969 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 970 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 971 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 972 __le16 queue_number; 973 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 974 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 975 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 976 /* response section */ 977 u8 match_method; 978 #define I40E_AQC_MM_PERFECT_MATCH 0x01 979 #define I40E_AQC_MM_HASH_MATCH 0x02 980 #define I40E_AQC_MM_ERR_NO_RES 0xFF 981 u8 reserved1[3]; 982 }; 983 984 struct i40e_aqc_add_remove_macvlan_completion { 985 __le16 perfect_mac_used; 986 __le16 perfect_mac_free; 987 __le16 unicast_hash_free; 988 __le16 multicast_hash_free; 989 __le32 addr_high; 990 __le32 addr_low; 991 }; 992 993 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 994 995 /* Remove MAC-VLAN (indirect 0x0251) 996 * uses i40e_aqc_macvlan for the descriptor 997 * data points to an array of num_addresses of elements 998 */ 999 1000 struct i40e_aqc_remove_macvlan_element_data { 1001 u8 mac_addr[6]; 1002 __le16 vlan_tag; 1003 u8 flags; 1004 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1005 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1006 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1007 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1008 u8 reserved[3]; 1009 /* reply section */ 1010 u8 error_code; 1011 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1012 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1013 u8 reply_reserved[3]; 1014 }; 1015 1016 /* Add VLAN (indirect 0x0252) 1017 * Remove VLAN (indirect 0x0253) 1018 * use the generic i40e_aqc_macvlan for the command 1019 */ 1020 struct i40e_aqc_add_remove_vlan_element_data { 1021 __le16 vlan_tag; 1022 u8 vlan_flags; 1023 /* flags for add VLAN */ 1024 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1025 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1026 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1027 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1028 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1029 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1030 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1031 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1032 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1033 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1034 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1035 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1036 /* flags for remove VLAN */ 1037 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1038 u8 reserved; 1039 u8 result; 1040 /* flags for add VLAN */ 1041 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1042 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1043 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1044 /* flags for remove VLAN */ 1045 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1046 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1047 u8 reserved1[3]; 1048 }; 1049 1050 struct i40e_aqc_add_remove_vlan_completion { 1051 u8 reserved[4]; 1052 __le16 vlans_used; 1053 __le16 vlans_free; 1054 __le32 addr_high; 1055 __le32 addr_low; 1056 }; 1057 1058 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1059 struct i40e_aqc_set_vsi_promiscuous_modes { 1060 __le16 promiscuous_flags; 1061 __le16 valid_flags; 1062 /* flags used for both fields above */ 1063 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1064 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1065 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1066 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1067 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1068 __le16 seid; 1069 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1070 __le16 vlan_tag; 1071 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1072 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1073 u8 reserved[8]; 1074 }; 1075 1076 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1077 1078 /* Add S/E-tag command (direct 0x0255) 1079 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1080 */ 1081 struct i40e_aqc_add_tag { 1082 __le16 flags; 1083 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1084 __le16 seid; 1085 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1086 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1087 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1088 __le16 tag; 1089 __le16 queue_number; 1090 u8 reserved[8]; 1091 }; 1092 1093 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1094 1095 struct i40e_aqc_add_remove_tag_completion { 1096 u8 reserved[12]; 1097 __le16 tags_used; 1098 __le16 tags_free; 1099 }; 1100 1101 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1102 1103 /* Remove S/E-tag command (direct 0x0256) 1104 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1105 */ 1106 struct i40e_aqc_remove_tag { 1107 __le16 seid; 1108 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1109 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1110 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1111 __le16 tag; 1112 u8 reserved[12]; 1113 }; 1114 1115 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1116 1117 /* Add multicast E-Tag (direct 0x0257) 1118 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1119 * and no external data 1120 */ 1121 struct i40e_aqc_add_remove_mcast_etag { 1122 __le16 pv_seid; 1123 __le16 etag; 1124 u8 num_unicast_etags; 1125 u8 reserved[3]; 1126 __le32 addr_high; /* address of array of 2-byte s-tags */ 1127 __le32 addr_low; 1128 }; 1129 1130 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1131 1132 struct i40e_aqc_add_remove_mcast_etag_completion { 1133 u8 reserved[4]; 1134 __le16 mcast_etags_used; 1135 __le16 mcast_etags_free; 1136 __le32 addr_high; 1137 __le32 addr_low; 1138 1139 }; 1140 1141 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1142 1143 /* Update S/E-Tag (direct 0x0259) */ 1144 struct i40e_aqc_update_tag { 1145 __le16 seid; 1146 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1147 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1148 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1149 __le16 old_tag; 1150 __le16 new_tag; 1151 u8 reserved[10]; 1152 }; 1153 1154 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1155 1156 struct i40e_aqc_update_tag_completion { 1157 u8 reserved[12]; 1158 __le16 tags_used; 1159 __le16 tags_free; 1160 }; 1161 1162 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1163 1164 /* Add Control Packet filter (direct 0x025A) 1165 * Remove Control Packet filter (direct 0x025B) 1166 * uses the i40e_aqc_add_oveb_cloud, 1167 * and the generic direct completion structure 1168 */ 1169 struct i40e_aqc_add_remove_control_packet_filter { 1170 u8 mac[6]; 1171 __le16 etype; 1172 __le16 flags; 1173 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1174 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1175 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1176 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1177 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1178 __le16 seid; 1179 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1180 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1181 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1182 __le16 queue; 1183 u8 reserved[2]; 1184 }; 1185 1186 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1187 1188 struct i40e_aqc_add_remove_control_packet_filter_completion { 1189 __le16 mac_etype_used; 1190 __le16 etype_used; 1191 __le16 mac_etype_free; 1192 __le16 etype_free; 1193 u8 reserved[8]; 1194 }; 1195 1196 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1197 1198 /* Add Cloud filters (indirect 0x025C) 1199 * Remove Cloud filters (indirect 0x025D) 1200 * uses the i40e_aqc_add_remove_cloud_filters, 1201 * and the generic indirect completion structure 1202 */ 1203 struct i40e_aqc_add_remove_cloud_filters { 1204 u8 num_filters; 1205 u8 reserved; 1206 __le16 seid; 1207 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1208 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1209 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1210 u8 reserved2[4]; 1211 __le32 addr_high; 1212 __le32 addr_low; 1213 }; 1214 1215 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1216 1217 struct i40e_aqc_add_remove_cloud_filters_element_data { 1218 u8 outer_mac[6]; 1219 u8 inner_mac[6]; 1220 __le16 inner_vlan; 1221 union { 1222 struct { 1223 u8 reserved[12]; 1224 u8 data[4]; 1225 } v4; 1226 struct { 1227 u8 data[16]; 1228 } v6; 1229 } ipaddr; 1230 __le16 flags; 1231 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1232 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1233 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1234 /* 0x0000 reserved */ 1235 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1236 /* 0x0002 reserved */ 1237 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1238 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1239 /* 0x0005 reserved */ 1240 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1241 /* 0x0007 reserved */ 1242 /* 0x0008 reserved */ 1243 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1244 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1245 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1246 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1247 1248 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1249 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1250 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1251 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1252 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1253 1254 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1255 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1256 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1257 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1258 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1259 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1260 1261 __le32 tenant_id; 1262 u8 reserved[4]; 1263 __le16 queue_number; 1264 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1265 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1266 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1267 u8 reserved2[14]; 1268 /* response section */ 1269 u8 allocation_result; 1270 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1271 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1272 u8 response_reserved[7]; 1273 }; 1274 1275 struct i40e_aqc_remove_cloud_filters_completion { 1276 __le16 perfect_ovlan_used; 1277 __le16 perfect_ovlan_free; 1278 __le16 vlan_used; 1279 __le16 vlan_free; 1280 __le32 addr_high; 1281 __le32 addr_low; 1282 }; 1283 1284 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1285 1286 /* Add Mirror Rule (indirect or direct 0x0260) 1287 * Delete Mirror Rule (indirect or direct 0x0261) 1288 * note: some rule types (4,5) do not use an external buffer. 1289 * take care to set the flags correctly. 1290 */ 1291 struct i40e_aqc_add_delete_mirror_rule { 1292 __le16 seid; 1293 __le16 rule_type; 1294 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1295 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1296 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1297 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1298 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1299 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1300 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1301 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1302 __le16 num_entries; 1303 __le16 destination; /* VSI for add, rule id for delete */ 1304 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1305 __le32 addr_low; 1306 }; 1307 1308 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1309 1310 struct i40e_aqc_add_delete_mirror_rule_completion { 1311 u8 reserved[2]; 1312 __le16 rule_id; /* only used on add */ 1313 __le16 mirror_rules_used; 1314 __le16 mirror_rules_free; 1315 __le32 addr_high; 1316 __le32 addr_low; 1317 }; 1318 1319 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1320 1321 /* DCB 0x03xx*/ 1322 1323 /* PFC Ignore (direct 0x0301) 1324 * the command and response use the same descriptor structure 1325 */ 1326 struct i40e_aqc_pfc_ignore { 1327 u8 tc_bitmap; 1328 u8 command_flags; /* unused on response */ 1329 #define I40E_AQC_PFC_IGNORE_SET 0x80 1330 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1331 u8 reserved[14]; 1332 }; 1333 1334 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1335 1336 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1337 * with no parameters 1338 */ 1339 1340 /* TX scheduler 0x04xx */ 1341 1342 /* Almost all the indirect commands use 1343 * this generic struct to pass the SEID in param0 1344 */ 1345 struct i40e_aqc_tx_sched_ind { 1346 __le16 vsi_seid; 1347 u8 reserved[6]; 1348 __le32 addr_high; 1349 __le32 addr_low; 1350 }; 1351 1352 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1353 1354 /* Several commands respond with a set of queue set handles */ 1355 struct i40e_aqc_qs_handles_resp { 1356 __le16 qs_handles[8]; 1357 }; 1358 1359 /* Configure VSI BW limits (direct 0x0400) */ 1360 struct i40e_aqc_configure_vsi_bw_limit { 1361 __le16 vsi_seid; 1362 u8 reserved[2]; 1363 __le16 credit; 1364 u8 reserved1[2]; 1365 u8 max_credit; /* 0-3, limit = 2^max */ 1366 u8 reserved2[7]; 1367 }; 1368 1369 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1370 1371 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1372 * responds with i40e_aqc_qs_handles_resp 1373 */ 1374 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1375 u8 tc_valid_bits; 1376 u8 reserved[15]; 1377 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1378 1379 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1380 __le16 tc_bw_max[2]; 1381 u8 reserved1[28]; 1382 }; 1383 1384 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1385 1386 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1387 * responds with i40e_aqc_qs_handles_resp 1388 */ 1389 struct i40e_aqc_configure_vsi_tc_bw_data { 1390 u8 tc_valid_bits; 1391 u8 reserved[3]; 1392 u8 tc_bw_credits[8]; 1393 u8 reserved1[4]; 1394 __le16 qs_handles[8]; 1395 }; 1396 1397 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1398 1399 /* Query vsi bw configuration (indirect 0x0408) */ 1400 struct i40e_aqc_query_vsi_bw_config_resp { 1401 u8 tc_valid_bits; 1402 u8 tc_suspended_bits; 1403 u8 reserved[14]; 1404 __le16 qs_handles[8]; 1405 u8 reserved1[4]; 1406 __le16 port_bw_limit; 1407 u8 reserved2[2]; 1408 u8 max_bw; /* 0-3, limit = 2^max */ 1409 u8 reserved3[23]; 1410 }; 1411 1412 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1413 1414 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1415 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1416 u8 tc_valid_bits; 1417 u8 reserved[3]; 1418 u8 share_credits[8]; 1419 __le16 credits[8]; 1420 1421 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1422 __le16 tc_bw_max[2]; 1423 }; 1424 1425 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1426 1427 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1428 struct i40e_aqc_configure_switching_comp_bw_limit { 1429 __le16 seid; 1430 u8 reserved[2]; 1431 __le16 credit; 1432 u8 reserved1[2]; 1433 u8 max_bw; /* 0-3, limit = 2^max */ 1434 u8 reserved2[7]; 1435 }; 1436 1437 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1438 1439 /* Enable Physical Port ETS (indirect 0x0413) 1440 * Modify Physical Port ETS (indirect 0x0414) 1441 * Disable Physical Port ETS (indirect 0x0415) 1442 */ 1443 struct i40e_aqc_configure_switching_comp_ets_data { 1444 u8 reserved[4]; 1445 u8 tc_valid_bits; 1446 u8 seepage; 1447 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1448 u8 tc_strict_priority_flags; 1449 u8 reserved1[17]; 1450 u8 tc_bw_share_credits[8]; 1451 u8 reserved2[96]; 1452 }; 1453 1454 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1455 1456 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1457 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1458 u8 tc_valid_bits; 1459 u8 reserved[15]; 1460 __le16 tc_bw_credit[8]; 1461 1462 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1463 __le16 tc_bw_max[2]; 1464 u8 reserved1[28]; 1465 }; 1466 1467 I40E_CHECK_STRUCT_LEN(0x40, 1468 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1469 1470 /* Configure Switching Component Bandwidth Allocation per Tc 1471 * (indirect 0x0417) 1472 */ 1473 struct i40e_aqc_configure_switching_comp_bw_config_data { 1474 u8 tc_valid_bits; 1475 u8 reserved[2]; 1476 u8 absolute_credits; /* bool */ 1477 u8 tc_bw_share_credits[8]; 1478 u8 reserved1[20]; 1479 }; 1480 1481 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1482 1483 /* Query Switching Component Configuration (indirect 0x0418) */ 1484 struct i40e_aqc_query_switching_comp_ets_config_resp { 1485 u8 tc_valid_bits; 1486 u8 reserved[35]; 1487 __le16 port_bw_limit; 1488 u8 reserved1[2]; 1489 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1490 u8 reserved2[23]; 1491 }; 1492 1493 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1494 1495 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1496 struct i40e_aqc_query_port_ets_config_resp { 1497 u8 reserved[4]; 1498 u8 tc_valid_bits; 1499 u8 reserved1; 1500 u8 tc_strict_priority_bits; 1501 u8 reserved2; 1502 u8 tc_bw_share_credits[8]; 1503 __le16 tc_bw_limits[8]; 1504 1505 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1506 __le16 tc_bw_max[2]; 1507 u8 reserved3[32]; 1508 }; 1509 1510 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1511 1512 /* Query Switching Component Bandwidth Allocation per Traffic Type 1513 * (indirect 0x041A) 1514 */ 1515 struct i40e_aqc_query_switching_comp_bw_config_resp { 1516 u8 tc_valid_bits; 1517 u8 reserved[2]; 1518 u8 absolute_credits_enable; /* bool */ 1519 u8 tc_bw_share_credits[8]; 1520 __le16 tc_bw_limits[8]; 1521 1522 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1523 __le16 tc_bw_max[2]; 1524 }; 1525 1526 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1527 1528 /* Suspend/resume port TX traffic 1529 * (direct 0x041B and 0x041C) uses the generic SEID struct 1530 */ 1531 1532 /* Configure partition BW 1533 * (indirect 0x041D) 1534 */ 1535 struct i40e_aqc_configure_partition_bw_data { 1536 __le16 pf_valid_bits; 1537 u8 min_bw[16]; /* guaranteed bandwidth */ 1538 u8 max_bw[16]; /* bandwidth limit */ 1539 }; 1540 1541 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1542 1543 /* Get and set the active HMC resource profile and status. 1544 * (direct 0x0500) and (direct 0x0501) 1545 */ 1546 struct i40e_aq_get_set_hmc_resource_profile { 1547 u8 pm_profile; 1548 u8 pe_vf_enabled; 1549 u8 reserved[14]; 1550 }; 1551 1552 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1553 1554 enum i40e_aq_hmc_profile { 1555 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1556 I40E_HMC_PROFILE_DEFAULT = 1, 1557 I40E_HMC_PROFILE_FAVOR_VF = 2, 1558 I40E_HMC_PROFILE_EQUAL = 3, 1559 }; 1560 1561 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1562 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1563 1564 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1565 1566 /* set in param0 for get phy abilities to report qualified modules */ 1567 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1568 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1569 1570 enum i40e_aq_phy_type { 1571 I40E_PHY_TYPE_SGMII = 0x0, 1572 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1573 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1574 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1575 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1576 I40E_PHY_TYPE_XAUI = 0x5, 1577 I40E_PHY_TYPE_XFI = 0x6, 1578 I40E_PHY_TYPE_SFI = 0x7, 1579 I40E_PHY_TYPE_XLAUI = 0x8, 1580 I40E_PHY_TYPE_XLPPI = 0x9, 1581 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1582 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1583 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1584 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1585 I40E_PHY_TYPE_100BASE_TX = 0x11, 1586 I40E_PHY_TYPE_1000BASE_T = 0x12, 1587 I40E_PHY_TYPE_10GBASE_T = 0x13, 1588 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1589 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1590 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1591 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1592 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1593 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1594 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1595 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1596 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1597 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1598 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1599 I40E_PHY_TYPE_MAX 1600 }; 1601 1602 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1603 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1604 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1605 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1606 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1607 1608 enum i40e_aq_link_speed { 1609 I40E_LINK_SPEED_UNKNOWN = 0, 1610 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1611 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1612 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1613 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1614 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1615 }; 1616 1617 struct i40e_aqc_module_desc { 1618 u8 oui[3]; 1619 u8 reserved1; 1620 u8 part_number[16]; 1621 u8 revision[4]; 1622 u8 reserved2[8]; 1623 }; 1624 1625 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1626 1627 struct i40e_aq_get_phy_abilities_resp { 1628 __le32 phy_type; /* bitmap using the above enum for offsets */ 1629 u8 link_speed; /* bitmap using the above enum bit patterns */ 1630 u8 abilities; 1631 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1632 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1633 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1634 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1635 #define I40E_AQ_PHY_AN_ENABLED 0x10 1636 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1637 __le16 eee_capability; 1638 #define I40E_AQ_EEE_100BASE_TX 0x0002 1639 #define I40E_AQ_EEE_1000BASE_T 0x0004 1640 #define I40E_AQ_EEE_10GBASE_T 0x0008 1641 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1642 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1643 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1644 __le32 eeer_val; 1645 u8 d3_lpan; 1646 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1647 u8 reserved[3]; 1648 u8 phy_id[4]; 1649 u8 module_type[3]; 1650 u8 qualified_module_count; 1651 #define I40E_AQ_PHY_MAX_QMS 16 1652 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1653 }; 1654 1655 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1656 1657 /* Set PHY Config (direct 0x0601) */ 1658 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1659 __le32 phy_type; 1660 u8 link_speed; 1661 u8 abilities; 1662 /* bits 0-2 use the values from get_phy_abilities_resp */ 1663 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1664 #define I40E_AQ_PHY_ENABLE_AN 0x10 1665 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1666 __le16 eee_capability; 1667 __le32 eeer; 1668 u8 low_power_ctrl; 1669 u8 reserved[3]; 1670 }; 1671 1672 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1673 1674 /* Set MAC Config command data structure (direct 0x0603) */ 1675 struct i40e_aq_set_mac_config { 1676 __le16 max_frame_size; 1677 u8 params; 1678 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1679 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1680 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1681 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1682 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1683 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1684 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1685 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1687 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1688 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1689 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1690 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1691 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1692 u8 tx_timer_priority; /* bitmap */ 1693 __le16 tx_timer_value; 1694 __le16 fc_refresh_threshold; 1695 u8 reserved[8]; 1696 }; 1697 1698 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1699 1700 /* Restart Auto-Negotiation (direct 0x605) */ 1701 struct i40e_aqc_set_link_restart_an { 1702 u8 command; 1703 #define I40E_AQ_PHY_RESTART_AN 0x02 1704 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1705 u8 reserved[15]; 1706 }; 1707 1708 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1709 1710 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1711 struct i40e_aqc_get_link_status { 1712 __le16 command_flags; /* only field set on command */ 1713 #define I40E_AQ_LSE_MASK 0x3 1714 #define I40E_AQ_LSE_NOP 0x0 1715 #define I40E_AQ_LSE_DISABLE 0x2 1716 #define I40E_AQ_LSE_ENABLE 0x3 1717 /* only response uses this flag */ 1718 #define I40E_AQ_LSE_IS_ENABLED 0x1 1719 u8 phy_type; /* i40e_aq_phy_type */ 1720 u8 link_speed; /* i40e_aq_link_speed */ 1721 u8 link_info; 1722 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1723 #define I40E_AQ_LINK_UP_FUNCTION 0x01 1724 #define I40E_AQ_LINK_FAULT 0x02 1725 #define I40E_AQ_LINK_FAULT_TX 0x04 1726 #define I40E_AQ_LINK_FAULT_RX 0x08 1727 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1728 #define I40E_AQ_LINK_UP_PORT 0x20 1729 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1730 #define I40E_AQ_SIGNAL_DETECT 0x80 1731 u8 an_info; 1732 #define I40E_AQ_AN_COMPLETED 0x01 1733 #define I40E_AQ_LP_AN_ABILITY 0x02 1734 #define I40E_AQ_PD_FAULT 0x04 1735 #define I40E_AQ_FEC_EN 0x08 1736 #define I40E_AQ_PHY_LOW_POWER 0x10 1737 #define I40E_AQ_LINK_PAUSE_TX 0x20 1738 #define I40E_AQ_LINK_PAUSE_RX 0x40 1739 #define I40E_AQ_QUALIFIED_MODULE 0x80 1740 u8 ext_info; 1741 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1742 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1743 #define I40E_AQ_LINK_TX_SHIFT 0x02 1744 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1745 #define I40E_AQ_LINK_TX_ACTIVE 0x00 1746 #define I40E_AQ_LINK_TX_DRAINED 0x01 1747 #define I40E_AQ_LINK_TX_FLUSHED 0x03 1748 #define I40E_AQ_LINK_FORCED_40G 0x10 1749 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1750 __le16 max_frame_size; 1751 u8 config; 1752 #define I40E_AQ_CONFIG_CRC_ENA 0x04 1753 #define I40E_AQ_CONFIG_PACING_MASK 0x78 1754 u8 reserved[5]; 1755 }; 1756 1757 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1758 1759 /* Set event mask command (direct 0x613) */ 1760 struct i40e_aqc_set_phy_int_mask { 1761 u8 reserved[8]; 1762 __le16 event_mask; 1763 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1764 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1765 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1766 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1767 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1768 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1769 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1770 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1771 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1772 u8 reserved1[6]; 1773 }; 1774 1775 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1776 1777 /* Get Local AN advt register (direct 0x0614) 1778 * Set Local AN advt register (direct 0x0615) 1779 * Get Link Partner AN advt register (direct 0x0616) 1780 */ 1781 struct i40e_aqc_an_advt_reg { 1782 __le32 local_an_reg0; 1783 __le16 local_an_reg1; 1784 u8 reserved[10]; 1785 }; 1786 1787 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1788 1789 /* Set Loopback mode (0x0618) */ 1790 struct i40e_aqc_set_lb_mode { 1791 __le16 lb_mode; 1792 #define I40E_AQ_LB_PHY_LOCAL 0x01 1793 #define I40E_AQ_LB_PHY_REMOTE 0x02 1794 #define I40E_AQ_LB_MAC_LOCAL 0x04 1795 u8 reserved[14]; 1796 }; 1797 1798 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1799 1800 /* Set PHY Debug command (0x0622) */ 1801 struct i40e_aqc_set_phy_debug { 1802 u8 command_flags; 1803 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1804 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1805 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1806 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1807 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1808 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1809 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1810 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1811 u8 reserved[15]; 1812 }; 1813 1814 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1815 1816 enum i40e_aq_phy_reg_type { 1817 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1818 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1819 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1820 }; 1821 1822 /* NVM Read command (indirect 0x0701) 1823 * NVM Erase commands (direct 0x0702) 1824 * NVM Update commands (indirect 0x0703) 1825 */ 1826 struct i40e_aqc_nvm_update { 1827 u8 command_flags; 1828 #define I40E_AQ_NVM_LAST_CMD 0x01 1829 #define I40E_AQ_NVM_FLASH_ONLY 0x80 1830 u8 module_pointer; 1831 __le16 length; 1832 __le32 offset; 1833 __le32 addr_high; 1834 __le32 addr_low; 1835 }; 1836 1837 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1838 1839 /* NVM Config Read (indirect 0x0704) */ 1840 struct i40e_aqc_nvm_config_read { 1841 __le16 cmd_flags; 1842 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1843 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1844 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1845 __le16 element_count; 1846 __le16 element_id; /* Feature/field ID */ 1847 __le16 element_id_msw; /* MSWord of field ID */ 1848 __le32 address_high; 1849 __le32 address_low; 1850 }; 1851 1852 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1853 1854 /* NVM Config Write (indirect 0x0705) */ 1855 struct i40e_aqc_nvm_config_write { 1856 __le16 cmd_flags; 1857 __le16 element_count; 1858 u8 reserved[4]; 1859 __le32 address_high; 1860 __le32 address_low; 1861 }; 1862 1863 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1864 1865 /* Used for 0x0704 as well as for 0x0705 commands */ 1866 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1867 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 1868 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1869 #define I40E_AQ_ANVM_FEATURE 0 1870 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1871 struct i40e_aqc_nvm_config_data_feature { 1872 __le16 feature_id; 1873 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1874 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1875 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1876 __le16 feature_options; 1877 __le16 feature_selection; 1878 }; 1879 1880 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1881 1882 struct i40e_aqc_nvm_config_data_immediate_field { 1883 __le32 field_id; 1884 __le32 field_value; 1885 __le16 field_options; 1886 __le16 reserved; 1887 }; 1888 1889 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1890 1891 /* Send to PF command (indirect 0x0801) id is only used by PF 1892 * Send to VF command (indirect 0x0802) id is only used by PF 1893 * Send to Peer PF command (indirect 0x0803) 1894 */ 1895 struct i40e_aqc_pf_vf_message { 1896 __le32 id; 1897 u8 reserved[4]; 1898 __le32 addr_high; 1899 __le32 addr_low; 1900 }; 1901 1902 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1903 1904 /* Alternate structure */ 1905 1906 /* Direct write (direct 0x0900) 1907 * Direct read (direct 0x0902) 1908 */ 1909 struct i40e_aqc_alternate_write { 1910 __le32 address0; 1911 __le32 data0; 1912 __le32 address1; 1913 __le32 data1; 1914 }; 1915 1916 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1917 1918 /* Indirect write (indirect 0x0901) 1919 * Indirect read (indirect 0x0903) 1920 */ 1921 1922 struct i40e_aqc_alternate_ind_write { 1923 __le32 address; 1924 __le32 length; 1925 __le32 addr_high; 1926 __le32 addr_low; 1927 }; 1928 1929 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1930 1931 /* Done alternate write (direct 0x0904) 1932 * uses i40e_aq_desc 1933 */ 1934 struct i40e_aqc_alternate_write_done { 1935 __le16 cmd_flags; 1936 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1937 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1938 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1939 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1940 u8 reserved[14]; 1941 }; 1942 1943 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1944 1945 /* Set OEM mode (direct 0x0905) */ 1946 struct i40e_aqc_alternate_set_mode { 1947 __le32 mode; 1948 #define I40E_AQ_ALTERNATE_MODE_NONE 0 1949 #define I40E_AQ_ALTERNATE_MODE_OEM 1 1950 u8 reserved[12]; 1951 }; 1952 1953 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1954 1955 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1956 1957 /* async events 0x10xx */ 1958 1959 /* Lan Queue Overflow Event (direct, 0x1001) */ 1960 struct i40e_aqc_lan_overflow { 1961 __le32 prtdcb_rupto; 1962 __le32 otx_ctl; 1963 u8 reserved[8]; 1964 }; 1965 1966 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1967 1968 /* Get LLDP MIB (indirect 0x0A00) */ 1969 struct i40e_aqc_lldp_get_mib { 1970 u8 type; 1971 u8 reserved1; 1972 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1973 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 1974 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 1975 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1976 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1977 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 1978 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 1979 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 1980 #define I40E_AQ_LLDP_TX_SHIFT 0x4 1981 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 1982 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 1983 __le16 local_len; 1984 __le16 remote_len; 1985 u8 reserved2[2]; 1986 __le32 addr_high; 1987 __le32 addr_low; 1988 }; 1989 1990 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 1991 1992 /* Configure LLDP MIB Change Event (direct 0x0A01) 1993 * also used for the event (with type in the command field) 1994 */ 1995 struct i40e_aqc_lldp_update_mib { 1996 u8 command; 1997 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1998 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 1999 u8 reserved[7]; 2000 __le32 addr_high; 2001 __le32 addr_low; 2002 }; 2003 2004 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2005 2006 /* Add LLDP TLV (indirect 0x0A02) 2007 * Delete LLDP TLV (indirect 0x0A04) 2008 */ 2009 struct i40e_aqc_lldp_add_tlv { 2010 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2011 u8 reserved1[1]; 2012 __le16 len; 2013 u8 reserved2[4]; 2014 __le32 addr_high; 2015 __le32 addr_low; 2016 }; 2017 2018 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2019 2020 /* Update LLDP TLV (indirect 0x0A03) */ 2021 struct i40e_aqc_lldp_update_tlv { 2022 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2023 u8 reserved; 2024 __le16 old_len; 2025 __le16 new_offset; 2026 __le16 new_len; 2027 __le32 addr_high; 2028 __le32 addr_low; 2029 }; 2030 2031 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2032 2033 /* Stop LLDP (direct 0x0A05) */ 2034 struct i40e_aqc_lldp_stop { 2035 u8 command; 2036 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2037 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2038 u8 reserved[15]; 2039 }; 2040 2041 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2042 2043 /* Start LLDP (direct 0x0A06) */ 2044 2045 struct i40e_aqc_lldp_start { 2046 u8 command; 2047 #define I40E_AQ_LLDP_AGENT_START 0x1 2048 u8 reserved[15]; 2049 }; 2050 2051 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2052 2053 /* Apply MIB changes (0x0A07) 2054 * uses the generic struc as it contains no data 2055 */ 2056 2057 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2058 struct i40e_aqc_add_udp_tunnel { 2059 __le16 udp_port; 2060 u8 reserved0[3]; 2061 u8 protocol_type; 2062 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2063 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2064 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2065 u8 reserved1[10]; 2066 }; 2067 2068 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2069 2070 struct i40e_aqc_add_udp_tunnel_completion { 2071 __le16 udp_port; 2072 u8 filter_entry_index; 2073 u8 multiple_pfs; 2074 #define I40E_AQC_SINGLE_PF 0x0 2075 #define I40E_AQC_MULTIPLE_PFS 0x1 2076 u8 total_filters; 2077 u8 reserved[11]; 2078 }; 2079 2080 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2081 2082 /* remove UDP Tunnel command (0x0B01) */ 2083 struct i40e_aqc_remove_udp_tunnel { 2084 u8 reserved[2]; 2085 u8 index; /* 0 to 15 */ 2086 u8 reserved2[13]; 2087 }; 2088 2089 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2090 2091 struct i40e_aqc_del_udp_tunnel_completion { 2092 __le16 udp_port; 2093 u8 index; /* 0 to 15 */ 2094 u8 multiple_pfs; 2095 u8 total_filters_used; 2096 u8 reserved1[11]; 2097 }; 2098 2099 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2100 2101 struct i40e_aqc_get_set_rss_key { 2102 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2103 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2104 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2105 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2106 __le16 vsi_id; 2107 u8 reserved[6]; 2108 __le32 addr_high; 2109 __le32 addr_low; 2110 }; 2111 2112 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2113 2114 struct i40e_aqc_get_set_rss_key_data { 2115 u8 standard_rss_key[0x28]; 2116 u8 extended_hash_key[0xc]; 2117 }; 2118 2119 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2120 2121 struct i40e_aqc_get_set_rss_lut { 2122 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2123 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2124 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2125 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2126 __le16 vsi_id; 2127 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2128 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2129 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2130 2131 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2132 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2133 __le16 flags; 2134 u8 reserved[4]; 2135 __le32 addr_high; 2136 __le32 addr_low; 2137 }; 2138 2139 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2140 2141 /* tunnel key structure 0x0B10 */ 2142 2143 struct i40e_aqc_tunnel_key_structure_A0 { 2144 __le16 key1_off; 2145 __le16 key1_len; 2146 __le16 key2_off; 2147 __le16 key2_len; 2148 __le16 flags; 2149 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2150 /* response flags */ 2151 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2152 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2153 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2154 u8 resreved[6]; 2155 }; 2156 2157 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0); 2158 2159 struct i40e_aqc_tunnel_key_structure { 2160 u8 key1_off; 2161 u8 key2_off; 2162 u8 key1_len; /* 0 to 15 */ 2163 u8 key2_len; /* 0 to 15 */ 2164 u8 flags; 2165 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2166 /* response flags */ 2167 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2168 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2169 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2170 u8 network_key_index; 2171 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2172 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2173 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2174 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2175 u8 reserved[10]; 2176 }; 2177 2178 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2179 2180 /* OEM mode commands (direct 0xFE0x) */ 2181 struct i40e_aqc_oem_param_change { 2182 __le32 param_type; 2183 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2184 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2185 #define I40E_AQ_OEM_PARAM_MAC 2 2186 __le32 param_value1; 2187 __le16 param_value2; 2188 u8 reserved[6]; 2189 }; 2190 2191 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2192 2193 struct i40e_aqc_oem_state_change { 2194 __le32 state; 2195 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2196 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2197 u8 reserved[12]; 2198 }; 2199 2200 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2201 2202 /* Initialize OCSD (0xFE02, direct) */ 2203 struct i40e_aqc_opc_oem_ocsd_initialize { 2204 u8 type_status; 2205 u8 reserved1[3]; 2206 __le32 ocsd_memory_block_addr_high; 2207 __le32 ocsd_memory_block_addr_low; 2208 __le32 requested_update_interval; 2209 }; 2210 2211 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2212 2213 /* Initialize OCBB (0xFE03, direct) */ 2214 struct i40e_aqc_opc_oem_ocbb_initialize { 2215 u8 type_status; 2216 u8 reserved1[3]; 2217 __le32 ocbb_memory_block_addr_high; 2218 __le32 ocbb_memory_block_addr_low; 2219 u8 reserved2[4]; 2220 }; 2221 2222 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2223 2224 /* debug commands */ 2225 2226 /* get device id (0xFF00) uses the generic structure */ 2227 2228 /* set test more (0xFF01, internal) */ 2229 2230 struct i40e_acq_set_test_mode { 2231 u8 mode; 2232 #define I40E_AQ_TEST_PARTIAL 0 2233 #define I40E_AQ_TEST_FULL 1 2234 #define I40E_AQ_TEST_NVM 2 2235 u8 reserved[3]; 2236 u8 command; 2237 #define I40E_AQ_TEST_OPEN 0 2238 #define I40E_AQ_TEST_CLOSE 1 2239 #define I40E_AQ_TEST_INC 2 2240 u8 reserved2[3]; 2241 __le32 address_high; 2242 __le32 address_low; 2243 }; 2244 2245 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2246 2247 /* Debug Read Register command (0xFF03) 2248 * Debug Write Register command (0xFF04) 2249 */ 2250 struct i40e_aqc_debug_reg_read_write { 2251 __le32 reserved; 2252 __le32 address; 2253 __le32 value_high; 2254 __le32 value_low; 2255 }; 2256 2257 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2258 2259 /* Scatter/gather Reg Read (indirect 0xFF05) 2260 * Scatter/gather Reg Write (indirect 0xFF06) 2261 */ 2262 2263 /* i40e_aq_desc is used for the command */ 2264 struct i40e_aqc_debug_reg_sg_element_data { 2265 __le32 address; 2266 __le32 value; 2267 }; 2268 2269 /* Debug Modify register (direct 0xFF07) */ 2270 struct i40e_aqc_debug_modify_reg { 2271 __le32 address; 2272 __le32 value; 2273 __le32 clear_mask; 2274 __le32 set_mask; 2275 }; 2276 2277 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2278 2279 /* dump internal data (0xFF08, indirect) */ 2280 2281 #define I40E_AQ_CLUSTER_ID_AUX 0 2282 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2283 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2284 #define I40E_AQ_CLUSTER_ID_HMC 3 2285 #define I40E_AQ_CLUSTER_ID_MAC0 4 2286 #define I40E_AQ_CLUSTER_ID_MAC1 5 2287 #define I40E_AQ_CLUSTER_ID_MAC2 6 2288 #define I40E_AQ_CLUSTER_ID_MAC3 7 2289 #define I40E_AQ_CLUSTER_ID_DCB 8 2290 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2291 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2292 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2293 2294 struct i40e_aqc_debug_dump_internals { 2295 u8 cluster_id; 2296 u8 table_id; 2297 __le16 data_size; 2298 __le32 idx; 2299 __le32 address_high; 2300 __le32 address_low; 2301 }; 2302 2303 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2304 2305 struct i40e_aqc_debug_modify_internals { 2306 u8 cluster_id; 2307 u8 cluster_specific_params[7]; 2308 __le32 address_high; 2309 __le32 address_low; 2310 }; 2311 2312 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2313 2314 #endif 2315