1 /*
2 * Broadcom SATA3 AHCI Controller PHY Driver
3 *
4 * Copyright © 2009-2015 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/device.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/phy/phy.h>
25 #include <linux/platform_device.h>
26
27 #define SATA_MDIO_BANK_OFFSET 0x23c
28 #define SATA_MDIO_REG_OFFSET(ofs) ((ofs) * 4)
29 #define SATA_MDIO_REG_SPACE_SIZE 0x1000
30 #define SATA_MDIO_REG_LENGTH 0x1f00
31
32 #define MAX_PORTS 2
33
34 /* Register offset between PHYs in PCB space */
35 #define SATA_MDIO_REG_SPACE_SIZE 0x1000
36
37 struct brcm_sata_port {
38 int portnum;
39 struct phy *phy;
40 struct brcm_sata_phy *phy_priv;
41 bool ssc_en;
42 };
43
44 struct brcm_sata_phy {
45 struct device *dev;
46 void __iomem *phy_base;
47
48 struct brcm_sata_port phys[MAX_PORTS];
49 };
50
51 enum sata_mdio_phy_regs_28nm {
52 PLL_REG_BANK_0 = 0x50,
53 PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
54
55 TXPMD_REG_BANK = 0x1a0,
56 TXPMD_CONTROL1 = 0x81,
57 TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0),
58 TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = BIT(1),
59 TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82,
60 TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83,
61 TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff,
62 TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84,
63 TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff,
64 };
65
brcm_sata_phy_base(struct brcm_sata_port * port)66 static inline void __iomem *brcm_sata_phy_base(struct brcm_sata_port *port)
67 {
68 struct brcm_sata_phy *priv = port->phy_priv;
69
70 return priv->phy_base + (port->portnum * SATA_MDIO_REG_SPACE_SIZE);
71 }
72
brcm_sata_mdio_wr(void __iomem * addr,u32 bank,u32 ofs,u32 msk,u32 value)73 static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
74 u32 msk, u32 value)
75 {
76 u32 tmp;
77
78 writel(bank, addr + SATA_MDIO_BANK_OFFSET);
79 tmp = readl(addr + SATA_MDIO_REG_OFFSET(ofs));
80 tmp = (tmp & msk) | value;
81 writel(tmp, addr + SATA_MDIO_REG_OFFSET(ofs));
82 }
83
84 /* These defaults were characterized by H/W group */
85 #define FMIN_VAL_DEFAULT 0x3df
86 #define FMAX_VAL_DEFAULT 0x3df
87 #define FMAX_VAL_SSC 0x83
88
brcm_sata_cfg_ssc_28nm(struct brcm_sata_port * port)89 static void brcm_sata_cfg_ssc_28nm(struct brcm_sata_port *port)
90 {
91 void __iomem *base = brcm_sata_phy_base(port);
92 struct brcm_sata_phy *priv = port->phy_priv;
93 u32 tmp;
94
95 /* override the TX spread spectrum setting */
96 tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
97 brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
98
99 /* set fixed min freq */
100 brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
101 ~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
102 FMIN_VAL_DEFAULT);
103
104 /* set fixed max freq depending on SSC config */
105 if (port->ssc_en) {
106 dev_info(priv->dev, "enabling SSC on port %d\n", port->portnum);
107 tmp = FMAX_VAL_SSC;
108 } else {
109 tmp = FMAX_VAL_DEFAULT;
110 }
111
112 brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
113 ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
114 }
115
brcm_sata_phy_init(struct phy * phy)116 static int brcm_sata_phy_init(struct phy *phy)
117 {
118 struct brcm_sata_port *port = phy_get_drvdata(phy);
119
120 brcm_sata_cfg_ssc_28nm(port);
121
122 return 0;
123 }
124
125 static const struct phy_ops phy_ops_28nm = {
126 .init = brcm_sata_phy_init,
127 .owner = THIS_MODULE,
128 };
129
130 static const struct of_device_id brcm_sata_phy_of_match[] = {
131 { .compatible = "brcm,bcm7445-sata-phy" },
132 {},
133 };
134 MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
135
brcm_sata_phy_probe(struct platform_device * pdev)136 static int brcm_sata_phy_probe(struct platform_device *pdev)
137 {
138 struct device *dev = &pdev->dev;
139 struct device_node *dn = dev->of_node, *child;
140 struct brcm_sata_phy *priv;
141 struct resource *res;
142 struct phy_provider *provider;
143 int ret, count = 0;
144
145 if (of_get_child_count(dn) == 0)
146 return -ENODEV;
147
148 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
149 if (!priv)
150 return -ENOMEM;
151 dev_set_drvdata(dev, priv);
152 priv->dev = dev;
153
154 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
155 priv->phy_base = devm_ioremap_resource(dev, res);
156 if (IS_ERR(priv->phy_base))
157 return PTR_ERR(priv->phy_base);
158
159 for_each_available_child_of_node(dn, child) {
160 unsigned int id;
161 struct brcm_sata_port *port;
162
163 if (of_property_read_u32(child, "reg", &id)) {
164 dev_err(dev, "missing reg property in node %s\n",
165 child->name);
166 ret = -EINVAL;
167 goto put_child;
168 }
169
170 if (id >= MAX_PORTS) {
171 dev_err(dev, "invalid reg: %u\n", id);
172 ret = -EINVAL;
173 goto put_child;
174 }
175 if (priv->phys[id].phy) {
176 dev_err(dev, "already registered port %u\n", id);
177 ret = -EINVAL;
178 goto put_child;
179 }
180
181 port = &priv->phys[id];
182 port->portnum = id;
183 port->phy_priv = priv;
184 port->phy = devm_phy_create(dev, child, &phy_ops_28nm);
185 port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
186 if (IS_ERR(port->phy)) {
187 dev_err(dev, "failed to create PHY\n");
188 ret = PTR_ERR(port->phy);
189 goto put_child;
190 }
191
192 phy_set_drvdata(port->phy, port);
193 count++;
194 }
195
196 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
197 if (IS_ERR(provider)) {
198 dev_err(dev, "could not register PHY provider\n");
199 return PTR_ERR(provider);
200 }
201
202 dev_info(dev, "registered %d port(s)\n", count);
203
204 return 0;
205 put_child:
206 of_node_put(child);
207 return ret;
208 }
209
210 static struct platform_driver brcm_sata_phy_driver = {
211 .probe = brcm_sata_phy_probe,
212 .driver = {
213 .of_match_table = brcm_sata_phy_of_match,
214 .name = "brcmstb-sata-phy",
215 }
216 };
217 module_platform_driver(brcm_sata_phy_driver);
218
219 MODULE_DESCRIPTION("Broadcom STB SATA PHY driver");
220 MODULE_LICENSE("GPL");
221 MODULE_AUTHOR("Marc Carino");
222 MODULE_AUTHOR("Brian Norris");
223 MODULE_ALIAS("platform:phy-brcmstb-sata");
224