1 /*
2  * Allwinner A13 SoCs pinctrl driver.
3  *
4  * Copyright (C) 2014 Maxime Ripard
5  *
6  * Maxime Ripard <maxime.ripard@free-electrons.com>
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2.  This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  */
12 
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/pinctrl/pinctrl.h>
18 
19 #include "pinctrl-sunxi.h"
20 
21 static const struct sunxi_desc_pin sun5i_a13_pins[] = {
22 	/* Hole */
23 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
24 		  SUNXI_FUNCTION(0x0, "gpio_in"),
25 		  SUNXI_FUNCTION(0x1, "gpio_out"),
26 		  SUNXI_FUNCTION(0x2, "i2c0")),		/* SCK */
27 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
28 		  SUNXI_FUNCTION(0x0, "gpio_in"),
29 		  SUNXI_FUNCTION(0x1, "gpio_out"),
30 		  SUNXI_FUNCTION(0x2, "i2c0")),		/* SDA */
31 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
32 		  SUNXI_FUNCTION(0x0, "gpio_in"),
33 		  SUNXI_FUNCTION(0x1, "gpio_out"),
34 		  SUNXI_FUNCTION(0x2, "pwm"),
35 		  SUNXI_FUNCTION_IRQ(0x6, 16)),		/* EINT16 */
36 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
37 		  SUNXI_FUNCTION(0x0, "gpio_in"),
38 		  SUNXI_FUNCTION(0x1, "gpio_out"),
39 		  SUNXI_FUNCTION(0x2, "ir0"),		/* TX */
40 		  SUNXI_FUNCTION_IRQ(0x6, 17)),		/* EINT17 */
41 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
42 		  SUNXI_FUNCTION(0x0, "gpio_in"),
43 		  SUNXI_FUNCTION(0x1, "gpio_out"),
44 		  SUNXI_FUNCTION(0x2, "ir0"),		/* RX */
45 		  SUNXI_FUNCTION_IRQ(0x6, 18)),		/* EINT18 */
46 	/* Hole */
47 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
48 		  SUNXI_FUNCTION(0x0, "gpio_in"),
49 		  SUNXI_FUNCTION(0x1, "gpio_out"),
50 		  SUNXI_FUNCTION(0x2, "spi2"),		/* CS1 */
51 		  SUNXI_FUNCTION_IRQ(0x6, 24)),		/* EINT24 */
52 	/* Hole */
53 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
54 		  SUNXI_FUNCTION(0x0, "gpio_in"),
55 		  SUNXI_FUNCTION(0x1, "gpio_out"),
56 		  SUNXI_FUNCTION(0x2, "i2c1")),		/* SCK */
57 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
58 		  SUNXI_FUNCTION(0x0, "gpio_in"),
59 		  SUNXI_FUNCTION(0x1, "gpio_out"),
60 		  SUNXI_FUNCTION(0x2, "i2c1")),		/* SDA */
61 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
62 		  SUNXI_FUNCTION(0x0, "gpio_in"),
63 		  SUNXI_FUNCTION(0x1, "gpio_out"),
64 		  SUNXI_FUNCTION(0x2, "i2c2")),		/* SCK */
65 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
66 		  SUNXI_FUNCTION(0x0, "gpio_in"),
67 		  SUNXI_FUNCTION(0x1, "gpio_out"),
68 		  SUNXI_FUNCTION(0x2, "i2c2")),		/* SDA */
69 	/* Hole */
70 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
71 		  SUNXI_FUNCTION(0x0, "gpio_in"),
72 		  SUNXI_FUNCTION(0x1, "gpio_out"),
73 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NWE */
74 		  SUNXI_FUNCTION(0x3, "spi0")),		/* MOSI */
75 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
76 		  SUNXI_FUNCTION(0x0, "gpio_in"),
77 		  SUNXI_FUNCTION(0x1, "gpio_out"),
78 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NALE */
79 		  SUNXI_FUNCTION(0x3, "spi0")),		/* MISO */
80 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
81 		  SUNXI_FUNCTION(0x0, "gpio_in"),
82 		  SUNXI_FUNCTION(0x1, "gpio_out"),
83 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCLE */
84 		  SUNXI_FUNCTION(0x3, "spi0")),		/* CLK */
85 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
86 		  SUNXI_FUNCTION(0x0, "gpio_in"),
87 		  SUNXI_FUNCTION(0x1, "gpio_out"),
88 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE1 */
89 		  SUNXI_FUNCTION(0x3, "spi0")),		/* CS0 */
90 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
91 		  SUNXI_FUNCTION(0x0, "gpio_in"),
92 		  SUNXI_FUNCTION(0x1, "gpio_out"),
93 		  SUNXI_FUNCTION(0x2, "nand0")),	/* NCE0 */
94 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
95 		  SUNXI_FUNCTION(0x0, "gpio_in"),
96 		  SUNXI_FUNCTION(0x1, "gpio_out"),
97 		  SUNXI_FUNCTION(0x2, "nand0")),	/* NRE */
98 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
99 		  SUNXI_FUNCTION(0x0, "gpio_in"),
100 		  SUNXI_FUNCTION(0x1, "gpio_out"),
101 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NRB0 */
102 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CMD */
103 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
104 		  SUNXI_FUNCTION(0x0, "gpio_in"),
105 		  SUNXI_FUNCTION(0x1, "gpio_out"),
106 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NRB1 */
107 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CLK */
108 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
109 		  SUNXI_FUNCTION(0x0, "gpio_in"),
110 		  SUNXI_FUNCTION(0x1, "gpio_out"),
111 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ0 */
112 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D0 */
113 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
114 		  SUNXI_FUNCTION(0x0, "gpio_in"),
115 		  SUNXI_FUNCTION(0x1, "gpio_out"),
116 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ1 */
117 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D1 */
118 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
119 		  SUNXI_FUNCTION(0x0, "gpio_in"),
120 		  SUNXI_FUNCTION(0x1, "gpio_out"),
121 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ2 */
122 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D2 */
123 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
124 		  SUNXI_FUNCTION(0x0, "gpio_in"),
125 		  SUNXI_FUNCTION(0x1, "gpio_out"),
126 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ3 */
127 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D3 */
128 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
129 		  SUNXI_FUNCTION(0x0, "gpio_in"),
130 		  SUNXI_FUNCTION(0x1, "gpio_out"),
131 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ4 */
132 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D4 */
133 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
134 		  SUNXI_FUNCTION(0x0, "gpio_in"),
135 		  SUNXI_FUNCTION(0x1, "gpio_out"),
136 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ5 */
137 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D5 */
138 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
139 		  SUNXI_FUNCTION(0x0, "gpio_in"),
140 		  SUNXI_FUNCTION(0x1, "gpio_out"),
141 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ6 */
142 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D6 */
143 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
144 		  SUNXI_FUNCTION(0x0, "gpio_in"),
145 		  SUNXI_FUNCTION(0x1, "gpio_out"),
146 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ7 */
147 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D7 */
148 	/* Hole */
149 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
150 		  SUNXI_FUNCTION(0x0, "gpio_in"),
151 		  SUNXI_FUNCTION(0x1, "gpio_out"),
152 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQS */
153 		  SUNXI_FUNCTION(0x4, "uart3")),	/* RTS */
154 	/* Hole */
155 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
156 		  SUNXI_FUNCTION(0x0, "gpio_in"),
157 		  SUNXI_FUNCTION(0x1, "gpio_out"),
158 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D2 */
159 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
160 		  SUNXI_FUNCTION(0x0, "gpio_in"),
161 		  SUNXI_FUNCTION(0x1, "gpio_out"),
162 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D3 */
163 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
164 		  SUNXI_FUNCTION(0x0, "gpio_in"),
165 		  SUNXI_FUNCTION(0x1, "gpio_out"),
166 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D4 */
167 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
168 		  SUNXI_FUNCTION(0x0, "gpio_in"),
169 		  SUNXI_FUNCTION(0x1, "gpio_out"),
170 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D5 */
171 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
172 		  SUNXI_FUNCTION(0x0, "gpio_in"),
173 		  SUNXI_FUNCTION(0x1, "gpio_out"),
174 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D6 */
175 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
176 		  SUNXI_FUNCTION(0x0, "gpio_in"),
177 		  SUNXI_FUNCTION(0x1, "gpio_out"),
178 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D7 */
179 	/* Hole */
180 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
181 		  SUNXI_FUNCTION(0x0, "gpio_in"),
182 		  SUNXI_FUNCTION(0x1, "gpio_out"),
183 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D10 */
184 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
185 		  SUNXI_FUNCTION(0x0, "gpio_in"),
186 		  SUNXI_FUNCTION(0x1, "gpio_out"),
187 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D11 */
188 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
189 		  SUNXI_FUNCTION(0x0, "gpio_in"),
190 		  SUNXI_FUNCTION(0x1, "gpio_out"),
191 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D12 */
192 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
193 		  SUNXI_FUNCTION(0x0, "gpio_in"),
194 		  SUNXI_FUNCTION(0x1, "gpio_out"),
195 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D13 */
196 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
197 		  SUNXI_FUNCTION(0x0, "gpio_in"),
198 		  SUNXI_FUNCTION(0x1, "gpio_out"),
199 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D14 */
200 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
201 		  SUNXI_FUNCTION(0x0, "gpio_in"),
202 		  SUNXI_FUNCTION(0x1, "gpio_out"),
203 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D15 */
204 	/* Hole */
205 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
206 		  SUNXI_FUNCTION(0x0, "gpio_in"),
207 		  SUNXI_FUNCTION(0x1, "gpio_out"),
208 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D18 */
209 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
210 		  SUNXI_FUNCTION(0x0, "gpio_in"),
211 		  SUNXI_FUNCTION(0x1, "gpio_out"),
212 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D19 */
213 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
214 		  SUNXI_FUNCTION(0x0, "gpio_in"),
215 		  SUNXI_FUNCTION(0x1, "gpio_out"),
216 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D20 */
217 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
218 		  SUNXI_FUNCTION(0x0, "gpio_in"),
219 		  SUNXI_FUNCTION(0x1, "gpio_out"),
220 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D21 */
221 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
222 		  SUNXI_FUNCTION(0x0, "gpio_in"),
223 		  SUNXI_FUNCTION(0x1, "gpio_out"),
224 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D22 */
225 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
226 		  SUNXI_FUNCTION(0x0, "gpio_in"),
227 		  SUNXI_FUNCTION(0x1, "gpio_out"),
228 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* D23 */
229 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
230 		  SUNXI_FUNCTION(0x0, "gpio_in"),
231 		  SUNXI_FUNCTION(0x1, "gpio_out"),
232 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* CLK */
233 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
234 		  SUNXI_FUNCTION(0x0, "gpio_in"),
235 		  SUNXI_FUNCTION(0x1, "gpio_out"),
236 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* DE */
237 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
238 		  SUNXI_FUNCTION(0x0, "gpio_in"),
239 		  SUNXI_FUNCTION(0x1, "gpio_out"),
240 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* HSYNC */
241 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
242 		  SUNXI_FUNCTION(0x0, "gpio_in"),
243 		  SUNXI_FUNCTION(0x1, "gpio_out"),
244 		  SUNXI_FUNCTION(0x2, "lcd0")),		/* VSYNC */
245 	/* Hole */
246 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
247 		  SUNXI_FUNCTION(0x0, "gpio_in"),
248 		  SUNXI_FUNCTION(0x3, "csi0"),		/* PCLK */
249 		  SUNXI_FUNCTION(0x4, "spi2"),		/* CS0 */
250 		  SUNXI_FUNCTION_IRQ(0x6, 14)),		/* EINT14 */
251 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
252 		  SUNXI_FUNCTION(0x0, "gpio_in"),
253 		  SUNXI_FUNCTION(0x3, "csi0"),		/* MCLK */
254 		  SUNXI_FUNCTION(0x4, "spi2"),		/* CLK */
255 		  SUNXI_FUNCTION_IRQ(0x6, 15)),		/* EINT15 */
256 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
257 		  SUNXI_FUNCTION(0x0, "gpio_in"),
258 		  SUNXI_FUNCTION(0x3, "csi0"),		/* HSYNC */
259 		  SUNXI_FUNCTION(0x4, "spi2")),		/* MOSI */
260 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
261 		  SUNXI_FUNCTION(0x0, "gpio_in"),
262 		  SUNXI_FUNCTION(0x1, "gpio_out"),
263 		  SUNXI_FUNCTION(0x3, "csi0"),		/* VSYNC */
264 		  SUNXI_FUNCTION(0x4, "spi2")),		/* MISO */
265 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
266 		  SUNXI_FUNCTION(0x0, "gpio_in"),
267 		  SUNXI_FUNCTION(0x1, "gpio_out"),
268 		  SUNXI_FUNCTION(0x3, "csi0"),		/* D0 */
269 		  SUNXI_FUNCTION(0x4, "mmc2")),		/* D0 */
270 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
271 		  SUNXI_FUNCTION(0x0, "gpio_in"),
272 		  SUNXI_FUNCTION(0x1, "gpio_out"),
273 		  SUNXI_FUNCTION(0x3, "csi0"),		/* D1 */
274 		  SUNXI_FUNCTION(0x4, "mmc2")),		/* D1 */
275 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
276 		  SUNXI_FUNCTION(0x0, "gpio_in"),
277 		  SUNXI_FUNCTION(0x1, "gpio_out"),
278 		  SUNXI_FUNCTION(0x3, "csi0"),		/* D2 */
279 		  SUNXI_FUNCTION(0x4, "mmc2")),		/* D2 */
280 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
281 		  SUNXI_FUNCTION(0x0, "gpio_in"),
282 		  SUNXI_FUNCTION(0x1, "gpio_out"),
283 		  SUNXI_FUNCTION(0x3, "csi0"),		/* D3 */
284 		  SUNXI_FUNCTION(0x4, "mmc2")),		/* D3 */
285 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
286 		  SUNXI_FUNCTION(0x0, "gpio_in"),
287 		  SUNXI_FUNCTION(0x1, "gpio_out"),
288 		  SUNXI_FUNCTION(0x3, "csi0"),		/* D4 */
289 		  SUNXI_FUNCTION(0x4, "mmc2")),		/* CMD */
290 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
291 		  SUNXI_FUNCTION(0x0, "gpio_in"),
292 		  SUNXI_FUNCTION(0x1, "gpio_out"),
293 		  SUNXI_FUNCTION(0x3, "csi0"),		/* D5 */
294 		  SUNXI_FUNCTION(0x4, "mmc2")),		/* CLK */
295 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
296 		  SUNXI_FUNCTION(0x0, "gpio_in"),
297 		  SUNXI_FUNCTION(0x1, "gpio_out"),
298 		  SUNXI_FUNCTION(0x3, "csi0"),		/* D6 */
299 		  SUNXI_FUNCTION(0x4, "uart1")),	/* TX */
300 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
301 		  SUNXI_FUNCTION(0x0, "gpio_in"),
302 		  SUNXI_FUNCTION(0x1, "gpio_out"),
303 		  SUNXI_FUNCTION(0x3, "csi0"),		/* D7 */
304 		  SUNXI_FUNCTION(0x4, "uart1")),	/* RX */
305 	/* Hole */
306 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
307 		  SUNXI_FUNCTION(0x0, "gpio_in"),
308 		  SUNXI_FUNCTION(0x1, "gpio_out"),
309 		  SUNXI_FUNCTION(0x2, "mmc0")),		/* D1 */
310 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
311 		  SUNXI_FUNCTION(0x0, "gpio_in"),
312 		  SUNXI_FUNCTION(0x1, "gpio_out"),
313 		  SUNXI_FUNCTION(0x2, "mmc0")),		/* D0 */
314 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
315 		  SUNXI_FUNCTION(0x0, "gpio_in"),
316 		  SUNXI_FUNCTION(0x1, "gpio_out"),
317 		  SUNXI_FUNCTION(0x2, "mmc0")),		/* CLK */
318 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
319 		  SUNXI_FUNCTION(0x0, "gpio_in"),
320 		  SUNXI_FUNCTION(0x1, "gpio_out"),
321 		  SUNXI_FUNCTION(0x2, "mmc0")),		/* CMD */
322 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
323 		  SUNXI_FUNCTION(0x0, "gpio_in"),
324 		  SUNXI_FUNCTION(0x1, "gpio_out"),
325 		  SUNXI_FUNCTION(0x2, "mmc0")),		/* D3 */
326 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
327 		  SUNXI_FUNCTION(0x0, "gpio_in"),
328 		  SUNXI_FUNCTION(0x1, "gpio_out"),
329 		  SUNXI_FUNCTION(0x2, "mmc0")),		/* D2 */
330 	/* Hole */
331 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
332 		  SUNXI_FUNCTION(0x0, "gpio_in"),
333 		  SUNXI_FUNCTION_IRQ(0x6, 0)),		/* EINT0 */
334 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
335 		  SUNXI_FUNCTION(0x0, "gpio_in"),
336 		  SUNXI_FUNCTION_IRQ(0x6, 1)),		/* EINT1 */
337 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
338 		  SUNXI_FUNCTION(0x0, "gpio_in"),
339 		  SUNXI_FUNCTION_IRQ(0x6, 2)),		/* EINT2 */
340 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
341 		  SUNXI_FUNCTION(0x0, "gpio_in"),
342 		  SUNXI_FUNCTION(0x1, "gpio_out"),
343 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CMD */
344 		  SUNXI_FUNCTION(0x4, "uart1"),		/* TX */
345 		  SUNXI_FUNCTION_IRQ(0x6, 3)),		/* EINT3 */
346 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
347 		  SUNXI_FUNCTION(0x0, "gpio_in"),
348 		  SUNXI_FUNCTION(0x1, "gpio_out"),
349 		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CLK */
350 		  SUNXI_FUNCTION(0x4, "uart1"),		/* RX */
351 		  SUNXI_FUNCTION_IRQ(0x6, 4)),		/* EINT4 */
352 	/* Hole */
353 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
354 		  SUNXI_FUNCTION(0x0, "gpio_in"),
355 		  SUNXI_FUNCTION(0x1, "gpio_out"),
356 		  SUNXI_FUNCTION(0x2, "spi1"),		/* CS0 */
357 		  SUNXI_FUNCTION(0x3, "uart3"),		/* TX */
358 		  SUNXI_FUNCTION_IRQ(0x6, 9)),		/* EINT9 */
359 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
360 		  SUNXI_FUNCTION(0x0, "gpio_in"),
361 		  SUNXI_FUNCTION(0x1, "gpio_out"),
362 		  SUNXI_FUNCTION(0x2, "spi1"),		/* CLK */
363 		  SUNXI_FUNCTION(0x3, "uart3"),		/* RX */
364 		  SUNXI_FUNCTION_IRQ(0x6, 10)),		/* EINT10 */
365 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
366 		  SUNXI_FUNCTION(0x0, "gpio_in"),
367 		  SUNXI_FUNCTION(0x1, "gpio_out"),
368 		  SUNXI_FUNCTION(0x2, "spi1"),		/* MOSI */
369 		  SUNXI_FUNCTION(0x3, "uart3"),		/* CTS */
370 		  SUNXI_FUNCTION_IRQ(0x6, 11)),		/* EINT11 */
371 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
372 		  SUNXI_FUNCTION(0x0, "gpio_in"),
373 		  SUNXI_FUNCTION(0x1, "gpio_out"),
374 		  SUNXI_FUNCTION(0x2, "spi1"),		/* MISO */
375 		  SUNXI_FUNCTION(0x3, "uart3"),		/* RTS */
376 		  SUNXI_FUNCTION_IRQ(0x6, 12)),		/* EINT12 */
377 };
378 
379 static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
380 	.pins = sun5i_a13_pins,
381 	.npins = ARRAY_SIZE(sun5i_a13_pins),
382 	.irq_banks = 1,
383 };
384 
sun5i_a13_pinctrl_probe(struct platform_device * pdev)385 static int sun5i_a13_pinctrl_probe(struct platform_device *pdev)
386 {
387 	return sunxi_pinctrl_init(pdev,
388 				  &sun5i_a13_pinctrl_data);
389 }
390 
391 static const struct of_device_id sun5i_a13_pinctrl_match[] = {
392 	{ .compatible = "allwinner,sun5i-a13-pinctrl", },
393 	{}
394 };
395 MODULE_DEVICE_TABLE(of, sun5i_a13_pinctrl_match);
396 
397 static struct platform_driver sun5i_a13_pinctrl_driver = {
398 	.probe	= sun5i_a13_pinctrl_probe,
399 	.driver	= {
400 		.name		= "sun5i-a13-pinctrl",
401 		.of_match_table	= sun5i_a13_pinctrl_match,
402 	},
403 };
404 module_platform_driver(sun5i_a13_pinctrl_driver);
405 
406 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
407 MODULE_DESCRIPTION("Allwinner A13 pinctrl driver");
408 MODULE_LICENSE("GPL");
409