1 /*
2 * TI QSPI driver
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sourav Poddar <sourav.poddar@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GPLv2.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/omap-dma.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
28 #include <linux/io.h>
29 #include <linux/slab.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/of.h>
32 #include <linux/of_device.h>
33 #include <linux/pinctrl/consumer.h>
34
35 #include <linux/spi/spi.h>
36
37 struct ti_qspi_regs {
38 u32 clkctrl;
39 };
40
41 struct ti_qspi {
42 /* list synchronization */
43 struct mutex list_lock;
44
45 struct spi_master *master;
46 void __iomem *base;
47 void __iomem *ctrl_base;
48 void __iomem *mmap_base;
49 struct clk *fclk;
50 struct device *dev;
51
52 struct ti_qspi_regs ctx_reg;
53
54 u32 spi_max_frequency;
55 u32 cmd;
56 u32 dc;
57
58 bool ctrl_mod;
59 };
60
61 #define QSPI_PID (0x0)
62 #define QSPI_SYSCONFIG (0x10)
63 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
64 #define QSPI_SPI_DC_REG (0x44)
65 #define QSPI_SPI_CMD_REG (0x48)
66 #define QSPI_SPI_STATUS_REG (0x4c)
67 #define QSPI_SPI_DATA_REG (0x50)
68 #define QSPI_SPI_SETUP0_REG (0x54)
69 #define QSPI_SPI_SWITCH_REG (0x64)
70 #define QSPI_SPI_SETUP1_REG (0x58)
71 #define QSPI_SPI_SETUP2_REG (0x5c)
72 #define QSPI_SPI_SETUP3_REG (0x60)
73 #define QSPI_SPI_DATA_REG_1 (0x68)
74 #define QSPI_SPI_DATA_REG_2 (0x6c)
75 #define QSPI_SPI_DATA_REG_3 (0x70)
76
77 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
78
79 #define QSPI_FCLK 192000000
80
81 /* Clock Control */
82 #define QSPI_CLK_EN (1 << 31)
83 #define QSPI_CLK_DIV_MAX 0xffff
84
85 /* Command */
86 #define QSPI_EN_CS(n) (n << 28)
87 #define QSPI_WLEN(n) ((n - 1) << 19)
88 #define QSPI_3_PIN (1 << 18)
89 #define QSPI_RD_SNGL (1 << 16)
90 #define QSPI_WR_SNGL (2 << 16)
91 #define QSPI_RD_DUAL (3 << 16)
92 #define QSPI_RD_QUAD (7 << 16)
93 #define QSPI_INVAL (4 << 16)
94 #define QSPI_FLEN(n) ((n - 1) << 0)
95 #define QSPI_WLEN_MAX_BITS 128
96 #define QSPI_WLEN_MAX_BYTES 16
97 #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
98
99 /* STATUS REGISTER */
100 #define BUSY 0x01
101 #define WC 0x02
102
103 /* Device Control */
104 #define QSPI_DD(m, n) (m << (3 + n * 8))
105 #define QSPI_CKPHA(n) (1 << (2 + n * 8))
106 #define QSPI_CSPOL(n) (1 << (1 + n * 8))
107 #define QSPI_CKPOL(n) (1 << (n * 8))
108
109 #define QSPI_FRAME 4096
110
111 #define QSPI_AUTOSUSPEND_TIMEOUT 2000
112
ti_qspi_read(struct ti_qspi * qspi,unsigned long reg)113 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
114 unsigned long reg)
115 {
116 return readl(qspi->base + reg);
117 }
118
ti_qspi_write(struct ti_qspi * qspi,unsigned long val,unsigned long reg)119 static inline void ti_qspi_write(struct ti_qspi *qspi,
120 unsigned long val, unsigned long reg)
121 {
122 writel(val, qspi->base + reg);
123 }
124
ti_qspi_setup(struct spi_device * spi)125 static int ti_qspi_setup(struct spi_device *spi)
126 {
127 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
128 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
129 int clk_div = 0, ret;
130 u32 clk_ctrl_reg, clk_rate, clk_mask;
131
132 if (spi->master->busy) {
133 dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
134 return -EBUSY;
135 }
136
137 if (!qspi->spi_max_frequency) {
138 dev_err(qspi->dev, "spi max frequency not defined\n");
139 return -EINVAL;
140 }
141
142 clk_rate = clk_get_rate(qspi->fclk);
143
144 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
145
146 if (clk_div < 0) {
147 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
148 return -EINVAL;
149 }
150
151 if (clk_div > QSPI_CLK_DIV_MAX) {
152 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
153 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
154 return -EINVAL;
155 }
156
157 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
158 qspi->spi_max_frequency, clk_div);
159
160 ret = pm_runtime_get_sync(qspi->dev);
161 if (ret < 0) {
162 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
163 return ret;
164 }
165
166 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
167
168 clk_ctrl_reg &= ~QSPI_CLK_EN;
169
170 /* disable SCLK */
171 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
172
173 /* enable SCLK */
174 clk_mask = QSPI_CLK_EN | clk_div;
175 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
176 ctx_reg->clkctrl = clk_mask;
177
178 pm_runtime_mark_last_busy(qspi->dev);
179 ret = pm_runtime_put_autosuspend(qspi->dev);
180 if (ret < 0) {
181 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
182 return ret;
183 }
184
185 return 0;
186 }
187
ti_qspi_restore_ctx(struct ti_qspi * qspi)188 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
189 {
190 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
191
192 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
193 }
194
qspi_is_busy(struct ti_qspi * qspi)195 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
196 {
197 u32 stat;
198 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
199
200 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
201 while ((stat & BUSY) && time_after(timeout, jiffies)) {
202 cpu_relax();
203 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
204 }
205
206 WARN(stat & BUSY, "qspi busy\n");
207 return stat & BUSY;
208 }
209
ti_qspi_poll_wc(struct ti_qspi * qspi)210 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
211 {
212 u32 stat;
213 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
214
215 do {
216 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
217 if (stat & WC)
218 return 0;
219 cpu_relax();
220 } while (time_after(timeout, jiffies));
221
222 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
223 if (stat & WC)
224 return 0;
225 return -ETIMEDOUT;
226 }
227
qspi_write_msg(struct ti_qspi * qspi,struct spi_transfer * t,int count)228 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
229 int count)
230 {
231 int wlen, xfer_len;
232 unsigned int cmd;
233 const u8 *txbuf;
234 u32 data;
235
236 txbuf = t->tx_buf;
237 cmd = qspi->cmd | QSPI_WR_SNGL;
238 wlen = t->bits_per_word >> 3; /* in bytes */
239 xfer_len = wlen;
240
241 while (count) {
242 if (qspi_is_busy(qspi))
243 return -EBUSY;
244
245 switch (wlen) {
246 case 1:
247 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
248 cmd, qspi->dc, *txbuf);
249 if (count >= QSPI_WLEN_MAX_BYTES) {
250 u32 *txp = (u32 *)txbuf;
251
252 data = cpu_to_be32(*txp++);
253 writel(data, qspi->base +
254 QSPI_SPI_DATA_REG_3);
255 data = cpu_to_be32(*txp++);
256 writel(data, qspi->base +
257 QSPI_SPI_DATA_REG_2);
258 data = cpu_to_be32(*txp++);
259 writel(data, qspi->base +
260 QSPI_SPI_DATA_REG_1);
261 data = cpu_to_be32(*txp++);
262 writel(data, qspi->base +
263 QSPI_SPI_DATA_REG);
264 xfer_len = QSPI_WLEN_MAX_BYTES;
265 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
266 } else {
267 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
268 cmd = qspi->cmd | QSPI_WR_SNGL;
269 xfer_len = wlen;
270 cmd |= QSPI_WLEN(wlen);
271 }
272 break;
273 case 2:
274 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
275 cmd, qspi->dc, *txbuf);
276 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
277 break;
278 case 4:
279 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
280 cmd, qspi->dc, *txbuf);
281 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
282 break;
283 }
284
285 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
286 if (ti_qspi_poll_wc(qspi)) {
287 dev_err(qspi->dev, "write timed out\n");
288 return -ETIMEDOUT;
289 }
290 txbuf += xfer_len;
291 count -= xfer_len;
292 }
293
294 return 0;
295 }
296
qspi_read_msg(struct ti_qspi * qspi,struct spi_transfer * t,int count)297 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
298 int count)
299 {
300 int wlen;
301 unsigned int cmd;
302 u8 *rxbuf;
303
304 rxbuf = t->rx_buf;
305 cmd = qspi->cmd;
306 switch (t->rx_nbits) {
307 case SPI_NBITS_DUAL:
308 cmd |= QSPI_RD_DUAL;
309 break;
310 case SPI_NBITS_QUAD:
311 cmd |= QSPI_RD_QUAD;
312 break;
313 default:
314 cmd |= QSPI_RD_SNGL;
315 break;
316 }
317 wlen = t->bits_per_word >> 3; /* in bytes */
318
319 while (count) {
320 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
321 if (qspi_is_busy(qspi))
322 return -EBUSY;
323
324 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
325 if (ti_qspi_poll_wc(qspi)) {
326 dev_err(qspi->dev, "read timed out\n");
327 return -ETIMEDOUT;
328 }
329 switch (wlen) {
330 case 1:
331 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
332 break;
333 case 2:
334 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
335 break;
336 case 4:
337 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
338 break;
339 }
340 rxbuf += wlen;
341 count -= wlen;
342 }
343
344 return 0;
345 }
346
qspi_transfer_msg(struct ti_qspi * qspi,struct spi_transfer * t,int count)347 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
348 int count)
349 {
350 int ret;
351
352 if (t->tx_buf) {
353 ret = qspi_write_msg(qspi, t, count);
354 if (ret) {
355 dev_dbg(qspi->dev, "Error while writing\n");
356 return ret;
357 }
358 }
359
360 if (t->rx_buf) {
361 ret = qspi_read_msg(qspi, t, count);
362 if (ret) {
363 dev_dbg(qspi->dev, "Error while reading\n");
364 return ret;
365 }
366 }
367
368 return 0;
369 }
370
ti_qspi_start_transfer_one(struct spi_master * master,struct spi_message * m)371 static int ti_qspi_start_transfer_one(struct spi_master *master,
372 struct spi_message *m)
373 {
374 struct ti_qspi *qspi = spi_master_get_devdata(master);
375 struct spi_device *spi = m->spi;
376 struct spi_transfer *t;
377 int status = 0, ret;
378 unsigned int frame_len_words, transfer_len_words;
379 int wlen;
380
381 /* setup device control reg */
382 qspi->dc = 0;
383
384 if (spi->mode & SPI_CPHA)
385 qspi->dc |= QSPI_CKPHA(spi->chip_select);
386 if (spi->mode & SPI_CPOL)
387 qspi->dc |= QSPI_CKPOL(spi->chip_select);
388 if (spi->mode & SPI_CS_HIGH)
389 qspi->dc |= QSPI_CSPOL(spi->chip_select);
390
391 frame_len_words = 0;
392 list_for_each_entry(t, &m->transfers, transfer_list)
393 frame_len_words += t->len / (t->bits_per_word >> 3);
394 frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
395
396 /* setup command reg */
397 qspi->cmd = 0;
398 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
399 qspi->cmd |= QSPI_FLEN(frame_len_words);
400
401 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
402
403 mutex_lock(&qspi->list_lock);
404
405 list_for_each_entry(t, &m->transfers, transfer_list) {
406 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
407 QSPI_WLEN(t->bits_per_word));
408
409 wlen = t->bits_per_word >> 3;
410 transfer_len_words = min(t->len / wlen, frame_len_words);
411
412 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
413 if (ret) {
414 dev_dbg(qspi->dev, "transfer message failed\n");
415 mutex_unlock(&qspi->list_lock);
416 return -EINVAL;
417 }
418
419 m->actual_length += transfer_len_words * wlen;
420 frame_len_words -= transfer_len_words;
421 if (frame_len_words == 0)
422 break;
423 }
424
425 mutex_unlock(&qspi->list_lock);
426
427 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
428 m->status = status;
429 spi_finalize_current_message(master);
430
431 return status;
432 }
433
ti_qspi_runtime_resume(struct device * dev)434 static int ti_qspi_runtime_resume(struct device *dev)
435 {
436 struct ti_qspi *qspi;
437
438 qspi = dev_get_drvdata(dev);
439 ti_qspi_restore_ctx(qspi);
440
441 return 0;
442 }
443
444 static const struct of_device_id ti_qspi_match[] = {
445 {.compatible = "ti,dra7xxx-qspi" },
446 {.compatible = "ti,am4372-qspi" },
447 {},
448 };
449 MODULE_DEVICE_TABLE(of, ti_qspi_match);
450
ti_qspi_probe(struct platform_device * pdev)451 static int ti_qspi_probe(struct platform_device *pdev)
452 {
453 struct ti_qspi *qspi;
454 struct spi_master *master;
455 struct resource *r, *res_ctrl, *res_mmap;
456 struct device_node *np = pdev->dev.of_node;
457 u32 max_freq;
458 int ret = 0, num_cs, irq;
459
460 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
461 if (!master)
462 return -ENOMEM;
463
464 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
465
466 master->flags = SPI_MASTER_HALF_DUPLEX;
467 master->setup = ti_qspi_setup;
468 master->auto_runtime_pm = true;
469 master->transfer_one_message = ti_qspi_start_transfer_one;
470 master->dev.of_node = pdev->dev.of_node;
471 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
472 SPI_BPW_MASK(8);
473
474 if (!of_property_read_u32(np, "num-cs", &num_cs))
475 master->num_chipselect = num_cs;
476
477 qspi = spi_master_get_devdata(master);
478 qspi->master = master;
479 qspi->dev = &pdev->dev;
480 platform_set_drvdata(pdev, qspi);
481
482 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
483 if (r == NULL) {
484 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
485 if (r == NULL) {
486 dev_err(&pdev->dev, "missing platform data\n");
487 return -ENODEV;
488 }
489 }
490
491 res_mmap = platform_get_resource_byname(pdev,
492 IORESOURCE_MEM, "qspi_mmap");
493 if (res_mmap == NULL) {
494 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
495 if (res_mmap == NULL) {
496 dev_err(&pdev->dev,
497 "memory mapped resource not required\n");
498 }
499 }
500
501 res_ctrl = platform_get_resource_byname(pdev,
502 IORESOURCE_MEM, "qspi_ctrlmod");
503 if (res_ctrl == NULL) {
504 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
505 if (res_ctrl == NULL) {
506 dev_dbg(&pdev->dev,
507 "control module resources not required\n");
508 }
509 }
510
511 irq = platform_get_irq(pdev, 0);
512 if (irq < 0) {
513 dev_err(&pdev->dev, "no irq resource?\n");
514 return irq;
515 }
516
517 mutex_init(&qspi->list_lock);
518
519 qspi->base = devm_ioremap_resource(&pdev->dev, r);
520 if (IS_ERR(qspi->base)) {
521 ret = PTR_ERR(qspi->base);
522 goto free_master;
523 }
524
525 if (res_ctrl) {
526 qspi->ctrl_mod = true;
527 qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
528 if (IS_ERR(qspi->ctrl_base)) {
529 ret = PTR_ERR(qspi->ctrl_base);
530 goto free_master;
531 }
532 }
533
534 if (res_mmap) {
535 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
536 if (IS_ERR(qspi->mmap_base)) {
537 ret = PTR_ERR(qspi->mmap_base);
538 goto free_master;
539 }
540 }
541
542 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
543 if (IS_ERR(qspi->fclk)) {
544 ret = PTR_ERR(qspi->fclk);
545 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
546 }
547
548 pm_runtime_use_autosuspend(&pdev->dev);
549 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
550 pm_runtime_enable(&pdev->dev);
551
552 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
553 qspi->spi_max_frequency = max_freq;
554
555 ret = devm_spi_register_master(&pdev->dev, master);
556 if (ret)
557 goto free_master;
558
559 return 0;
560
561 free_master:
562 spi_master_put(master);
563 return ret;
564 }
565
ti_qspi_remove(struct platform_device * pdev)566 static int ti_qspi_remove(struct platform_device *pdev)
567 {
568 pm_runtime_put_sync(&pdev->dev);
569 pm_runtime_disable(&pdev->dev);
570
571 return 0;
572 }
573
574 static const struct dev_pm_ops ti_qspi_pm_ops = {
575 .runtime_resume = ti_qspi_runtime_resume,
576 };
577
578 static struct platform_driver ti_qspi_driver = {
579 .probe = ti_qspi_probe,
580 .remove = ti_qspi_remove,
581 .driver = {
582 .name = "ti-qspi",
583 .pm = &ti_qspi_pm_ops,
584 .of_match_table = ti_qspi_match,
585 }
586 };
587
588 module_platform_driver(ti_qspi_driver);
589
590 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
591 MODULE_LICENSE("GPL v2");
592 MODULE_DESCRIPTION("TI QSPI controller driver");
593 MODULE_ALIAS("platform:ti-qspi");
594