| /linux-4.1.27/arch/mips/mm/ |
| H A D | page.c | 102 static int cache_line_size; variable
103 #define cache_line_mask() (cache_line_size - 1)
149 cache_line_size = cpu_dcache_line_size(); set_prefetch_parameters()
209 cache_line_size = cpu_scache_line_size(); set_prefetch_parameters()
211 cache_line_size = cpu_dcache_line_size(); set_prefetch_parameters()
218 max(cache_line_size >> 1, set_prefetch_parameters()
221 max(cache_line_size >> 1, set_prefetch_parameters()
242 } else if (cache_line_size == (half_clear_loop_size << 1)) { build_clear_pref()
301 off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size) build_clear_page()
302 * cache_line_size : 0; build_clear_page()
305 off -= cache_line_size; build_clear_page()
394 } else if (cache_line_size == (half_copy_loop_size << 1)) { build_copy_store_pref()
452 off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) * build_copy_page()
453 cache_line_size : 0; build_copy_page()
456 off -= cache_line_size; build_copy_page()
458 off = cache_line_size ? min(8, pref_bias_copy_store / cache_line_size) * build_copy_page()
459 cache_line_size : 0; build_copy_page()
462 off -= cache_line_size; build_copy_page()
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| /linux-4.1.27/include/linux/ |
| H A D | cache.h | 64 #define cache_line_size() L1_CACHE_BYTES macro
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| H A D | pci_hotplug.h | 132 u8 cache_line_size; member in struct:hpp_type0
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| /linux-4.1.27/arch/arm64/include/asm/ |
| H A D | cache.h | 37 static inline int cache_line_size(void) cache_line_size() function
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| /linux-4.1.27/drivers/infiniband/hw/mlx5/ |
| H A D | user.h | 76 __u32 cache_line_size; member in struct:mlx5_ib_alloc_ucontext_resp
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| H A D | main.c | 441 resp.cache_line_size = L1_CACHE_BYTES; mlx5_ib_alloc_ucontext()
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| /linux-4.1.27/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_crat.h | 161 uint16_t cache_line_size; member in struct:crat_subtype_cache
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| H A D | kfd_topology.c | 241 props->cacheline_size = cache->cache_line_size; kfd_parse_subtype_cache()
607 sysfs_show_32bit_prop(buffer, "cache_line_size", cache->cacheline_size); kfd_cache_show()
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| /linux-4.1.27/drivers/pci/ |
| H A D | pci-acpi.c | 60 hpx->t0->cache_line_size = fields[2].integer.value; decode_type0_hpx_record()
239 hpp->t0->cache_line_size = fields[0].integer.value; acpi_run_hpp()
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| H A D | probe.c | 1276 .cache_line_size = 8,
1296 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size); program_hpp_type0()
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| /linux-4.1.27/drivers/block/ |
| H A D | cpqarray.c | 608 unchar cache_line_size, latency_timer; cpqarray_pci_init() local
636 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line_size); cpqarray_pci_init()
656 printk("cache_line_size = %x\n", cache_line_size); cpqarray_pci_init()
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| /linux-4.1.27/drivers/pci/host/ |
| H A D | pci-mvebu.c | 74 u8 cache_line_size; member in struct:mvebu_sw_pci_bridge
441 bridge->cache_line_size = 0x10; mvebu_sw_pci_bridge_init()
473 bridge->latency_timer << 8 | bridge->cache_line_size; mvebu_sw_pci_bridge_read()
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| /linux-4.1.27/drivers/edac/ |
| H A D | i7core_edac.c | 2046 const int cache_line_size = 64; set_sdram_scrub_rate() local
2054 cache_line_size * 1000000; set_sdram_scrub_rate()
2086 const u32 cache_line_size = 64; get_sdram_scrub_rate() local
2106 1000000 * cache_line_size; get_sdram_scrub_rate()
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| /linux-4.1.27/block/ |
| H A D | blk-flush.c | 502 rq_sz = round_up(rq_sz + cmd_size, cache_line_size()); blk_alloc_flush_queue()
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| H A D | blk-mq.c | 1462 cache_line_size()); blk_mq_init_rq_map()
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| /linux-4.1.27/arch/arm64/kernel/ |
| H A D | setup.c | 255 cls = cache_line_size(); setup_processor()
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| /linux-4.1.27/arch/powerpc/kernel/ |
| H A D | eeh_pe.c | 66 alloc_size = ALIGN(alloc_size, cache_line_size()); eeh_pe_alloc()
82 cache_line_size()); eeh_pe_alloc()
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| H A D | cacheinfo.c | 231 /* not cache_line_size() because that's a macro in include/linux/cache.h */ cache_get_line_size()
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| /linux-4.1.27/drivers/net/ethernet/mellanox/mlx4/ |
| H A D | main.c | 245 if (cache_line_size() == 128 || cache_line_size() == 256) { mlx4_enable_cqe_eqe_stride()
254 if (cache_line_size() != 32 && cache_line_size() != 64) mlx4_enable_cqe_eqe_stride()
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| H A D | fw.c | 1723 (ilog2(cache_line_size()) - 4) << 5; mlx4_INIT_HCA()
1772 dev->caps.eqe_size = cache_line_size(); mlx4_INIT_HCA()
1773 dev->caps.cqe_size = cache_line_size(); mlx4_INIT_HCA()
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| /linux-4.1.27/kernel/trace/ |
| H A D | ring_buffer.c | 1176 bpage = kzalloc_node(ALIGN(sizeof(*bpage), cache_line_size()), __rb_allocate_pages()
1236 cpu_buffer = kzalloc_node(ALIGN(sizeof(*cpu_buffer), cache_line_size()), rb_allocate_cpu_buffer()
1252 bpage = kzalloc_node(ALIGN(sizeof(*bpage), cache_line_size()), rb_allocate_cpu_buffer()
1334 buffer = kzalloc(ALIGN(sizeof(*buffer), cache_line_size()), __ring_buffer_alloc()
1368 buffer->buffers = kzalloc(ALIGN(bsize, cache_line_size()), __ring_buffer_alloc()
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| /linux-4.1.27/drivers/staging/unisys/common-spar/include/channels/ |
| H A D | iochannel.h | 495 /* RCVPOST_BUF_SIZe must be at most page_size(4096) - cache_line_size (64) The
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| /linux-4.1.27/arch/x86/include/asm/ |
| H A D | processor.h | 166 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) macro
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| /linux-4.1.27/mm/ |
| H A D | slab_common.c | 285 unsigned long ralign = cache_line_size(); calculate_alignment()
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| H A D | slab.c | 2200 size >= 256 && cachep->object_size > cache_line_size() && __kmem_cache_create()
2260 cachep->colour_off = cache_line_size(); __kmem_cache_create()
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| H A D | slub.c | 3710 cache_line_size(), kmem_cache_init()
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| /linux-4.1.27/drivers/net/ethernet/chelsio/cxgb4/ |
| H A D | t4_hw.c | 4201 * @cache_line_size: the host's Cache Line Size
4208 unsigned int cache_line_size) t4_fixup_host_params()
4212 unsigned int stat_len = cache_line_size > 64 ? 128 : 64; t4_fixup_host_params()
4213 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size; t4_fixup_host_params()
4207 t4_fixup_host_params(struct adapter *adap, unsigned int page_size, unsigned int cache_line_size) t4_fixup_host_params() argument
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| H A D | cxgb4.h | 1257 unsigned int cache_line_size);
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| /linux-4.1.27/drivers/scsi/ |
| H A D | ipr.h | 1385 u8 cache_line_size; member in struct:ipr_chip_cfg_t
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| H A D | ipr.c | 110 .cache_line_size = 0x20,
135 .cache_line_size = 0x20,
160 .cache_line_size = 0x20,
9942 ioa_cfg->chip_cfg->cache_line_size); ipr_probe_ioa()
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| /linux-4.1.27/drivers/staging/fwserial/ |
| H A D | fwserial.c | 999 cache_line_size(), fwtty_port_activate()
|