Searched refs:inb (Results 1 - 200 of 638) sorted by relevance

1234

/linux-4.1.27/arch/alpha/kernel/
H A Des1888.c15 inb(0x0229); es1888_init()
16 inb(0x0229); es1888_init()
17 inb(0x0229); es1888_init()
18 inb(0x022b); es1888_init()
19 inb(0x0229); es1888_init()
20 inb(0x022b); es1888_init()
21 inb(0x0229); es1888_init()
22 inb(0x0229); es1888_init()
23 inb(0x022b); es1888_init()
24 inb(0x0229); es1888_init()
25 inb(0x0220); /* This sets the base address to 0x220 */ es1888_init()
29 inb(0x0226); /* pause */ es1888_init()
31 while (!(inb(0x022e) & 0x80)) /* wait for bit 7 to assert*/ es1888_init()
33 inb(0x022a); /* pause */ es1888_init()
35 inb(0x022a); /* pause, also forces the write */ es1888_init()
36 while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ es1888_init()
39 while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ es1888_init()
42 while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ es1888_init()
45 while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ es1888_init()
48 inb(0x022c); /* force the write */ es1888_init()
H A Dsys_jensen.c103 printk("61=%02x, 461=%02x\n", inb(0x61), inb(0x461)); jensen_device_interrupt()
130 inb(0x64); jensen_device_interrupt()
131 inb(0x60); jensen_device_interrupt()
133 inb(0x3fa); jensen_device_interrupt()
134 inb(0x2fa); jensen_device_interrupt()
H A Dsmc37c93x.c99 devId = inb(dataPort); SMCConfigState()
102 /* unsigned char devRev = */ inb(dataPort); SMCConfigState()
193 oldValue = inb(dataPort); SMCEnableFDC()
219 currentControl = inb(dataPort); SMCReportDeviceStatus()
H A Dirq_i8259.c157 pic = inb(0x20) | (inb(0xA0) << 8); /* read isr */ isa_no_iack_sc_device_interrupt()
H A Dpc873xx.c28 return inb(base + 1); pc873xx_read()
H A Dsys_sio.c139 old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8); sio_fixup_irq_levels()
264 ctest4 = inb(io_port+0x21); alphabook1_init_pci()
277 outb(0x0f, 0x3ce); orig = inb(0x3cf); /* read PR5 */ alphabook1_init_pci()
279 outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */ alphabook1_init_pci()
H A Dsys_eb64p.c71 pld = inb(0x26) | (inb(0x27) << 8); eb64p_device_interrupt()
H A Dsys_mikasa.c72 | (((unsigned long) inb(0xa0)) << 8) mikasa_device_interrupt()
73 | inb(0x20)); mikasa_device_interrupt()
/linux-4.1.27/drivers/scsi/
H A Datp870u.c65 j = inb(tmport); atp870u_intr_handle()
78 cmdp = inb(dev->ioport[c] + 0x10); atp870u_intr_handle()
83 if ((inb(tmport1) & 0x80) == 0) atp870u_intr_handle()
84 outb((inb(tmport1) | 0x80), tmport1); atp870u_intr_handle()
87 if ((inb(tmpcip) & 0x08) != 0) atp870u_intr_handle()
91 if ((inb(tmpcip) & 0x08) == 0) { atp870u_intr_handle()
94 if ((inb(tmpcip) & 0x01) == 0) { atp870u_intr_handle()
104 i = inb(tmport); atp870u_intr_handle()
113 target_id = inb(tmport); atp870u_intr_handle()
144 ((unsigned char *) &adrcnt)[2] = inb(tmport++); atp870u_intr_handle()
145 ((unsigned char *) &adrcnt)[1] = inb(tmport++); atp870u_intr_handle()
146 ((unsigned char *) &adrcnt)[0] = inb(tmport); atp870u_intr_handle()
165 while ((inb(tmport) & 0x01) != 0x01) { atp870u_intr_handle()
203 ((unsigned char *) &adrcnt)[2] = inb(tmport++); atp870u_intr_handle()
204 ((unsigned char *) &adrcnt)[1] = inb(tmport++); atp870u_intr_handle()
205 ((unsigned char *) &adrcnt)[0] = inb(tmport); atp870u_intr_handle()
235 lun = inb(tmport) & 0x07; atp870u_intr_handle()
246 ((unsigned char *) &adrcnt)[2] = inb(tmport++); atp870u_intr_handle()
247 ((unsigned char *) &adrcnt)[1] = inb(tmport++); atp870u_intr_handle()
248 ((unsigned char *) &adrcnt)[0] = inb(tmport); atp870u_intr_handle()
277 j = inb(dev->baseport + 0x29) & 0xfe; atp870u_intr_handle()
286 target_id = inb(tmport); atp870u_intr_handle()
318 printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k, inb(tmport-1), inb(tmport-2), inb(tmport-3)); atp870u_intr_handle()
333 i=inb(tmpcip) & 0xf3; atp870u_intr_handle()
343 outb((unsigned char) ((inb(tmport) & 0x3f) | 0xc0), tmport); atp870u_intr_handle()
345 outb((unsigned char) (inb(tmport) & 0x3f), tmport); atp870u_intr_handle()
350 outb((unsigned char) ((inb(tmport) & 0xf3) | 0x08), tmport); atp870u_intr_handle()
352 outb((unsigned char) (inb(tmport) & 0xf3), tmport); atp870u_intr_handle()
366 while ((inb(tmport) & 0x01) != j) { atp870u_intr_handle()
460 errstus = inb(tmport); atp870u_intr_handle()
468 j = inb(dev->baseport + 0x29) | 0x01; atp870u_intr_handle()
493 while ((inb(tmport) & 0x01) != 0x01) { atp870u_intr_handle()
563 outb((unsigned char) (inb(tmport) | 0x20), tmport); atp870u_intr_handle()
588 // inb(tmport); atp870u_intr_handle()
682 printk("dev->ioport[c] = %x inb(tmport) = %x dev->in_int[%d] = %d dev->in_snd[%d] = %d\n",dev->ioport[c],inb(tmport),c,dev->in_int[c],c,dev->in_snd[c]); atp870u_queuecommand_lck()
684 if ((inb(tmport) == 0) && (dev->in_int[c] == 0) && (dev->in_snd[c] == 0)) { atp870u_queuecommand_lck()
764 if ((inb(tmport) & 0xb0) != 0) { send_s870()
768 if (inb(tmport) == 0) { send_s870()
790 j = inb(dev->baseport + 0x29) & 0xfe; send_s870()
816 while ((inb(tmport) & 0x01) != j) { send_s870()
875 outb((unsigned char) (inb(tmport) | 0x80), tmport); send_s870()
880 if (inb(tmport) == 0) { send_s870()
940 j=inb(tmpcip) & 0xf3;
952 outb((unsigned char) ((inb(tmport) & 0x3f) | 0xc0), tmport);
954 outb((unsigned char) (inb(tmport) & 0x3f), tmport);
960 outb((inb(tmport) & 0xf3) | 0x08, tmport);
962 outb(inb(tmport) & 0xf3, tmport);
969 if (inb(tmport) == 0) {
982 if (inb(tmport) == 0) {
1113 while ((inb(tmport) & 0x80) == 0x00) tscam()
1116 k = inb(tmport); tscam()
1142 inb(0x80); /* 2 deskew delay(45ns*2=90ns) */ tscam()
1149 if ((inb(tmport) & 0x04) != 0) { tscam()
1155 if ((inb(tmport) & 0x80) != 0) { /* bsy ? */ tscam()
1162 if ((inb(tmport) & 0x81) == 0x0081) { tscam()
1168 inb(0x80); tscam()
1171 inb(0x80); tscam()
1186 if ((inb(tmport) & 0x80) == 0x00) { /* bsy ? */ tscam()
1194 while ((inb(tmport) & 0x80) == 0) tscam()
1197 inb(tmport); tscam()
1305 outb((unsigned char) (inb(tmport) | 0x10), tmport); is870()
1351 while ((inb(tmport) & 0x80) == 0x00) is870()
1355 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e) is870()
1358 while (inb(tmport) != 0x8e) is870()
1372 while ((inb(tmport) & 0x80) == 0x00) is870()
1375 j = inb(tmport); is870()
1400 while ((inb(tmport) & 0x80) == 0x00) is870()
1404 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e) is870()
1407 while (inb(tmport) != 0x8e) is870()
1419 k = inb(tmport); is870()
1422 mbuf[j++] = inb(tmport); is870()
1430 j = inb(tmport); is870()
1444 while ((inb(tmport) & 0x80) == 0x00) is870()
1448 if (inb(tmport) != 0x16) { is870()
1486 while ((inb(tmport) & 0x80) == 0x00) is870()
1490 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e) is870()
1493 while (inb(tmport) != 0x8e) is870()
1504 while ((inb(tmport) & 0x80) == 0) { is870()
1505 if ((inb(tmport) & 0x01) != 0) { is870()
1513 while ((inb(tmport) & 0x80) == 0x00) is870()
1516 j = inb(tmport) & 0x0f; is870()
1531 while ((inb(tmport) & 0x80) == 0) { is870()
1532 if ((inb(tmport) & 0x01) != 0) { is870()
1539 j = inb(tmport) & 0x0f; is870()
1558 j = inb(tmport); is870()
1561 mbuf[k++] = inb(tmport); is870()
1569 j = inb(tmport) & 0x0f; is870()
1589 while ((inb(tmport) & 0x80) == 0x00) is870()
1593 j = inb(tmport); is870()
1645 while ((inb(tmport) & 0x80) == 0x00) is870()
1649 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e) is870()
1652 while (inb(tmport) != 0x8e) is870()
1663 while ((inb(tmport) & 0x80) == 0) { is870()
1664 if ((inb(tmport) & 0x01) != 0) { is870()
1680 while ((inb(tmport) & 0x80) == 0x00) is870()
1683 j = inb(tmport) & 0x0f; is870()
1698 while ((inb(tmport) & 0x80) == 0x00) { is870()
1699 if ((inb(tmport) & 0x01) != 0x00) { is870()
1706 j = inb(tmport); is870()
1729 j = inb(tmport); is870()
1732 mbuf[k++] = inb(tmport); is870()
1741 while ((inb(tmport) & 0x80) == 0x00) is870()
1744 j = inb(tmport); is870()
1769 while ((inb(tmport) & 0x80) == 0x00) is870()
1773 j = inb(tmport); is870()
1814 outb((unsigned char) (inb(tmport) & 0xef), tmport); is870()
1832 lvdmode = inb(wkport + 0x3f) & 0x40; is880()
1871 while ((inb(tmport) & 0x80) == 0x00) is880()
1875 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e) is880()
1878 while (inb(tmport) != 0x8e) is880()
1893 while ((inb(tmport) & 0x80) == 0x00) is880()
1897 j = inb(tmport); is880()
1922 while ((inb(tmport) & 0x80) == 0x00) is880()
1926 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e) is880()
1929 while (inb(tmport) != 0x8e) is880()
1939 k = inb(tmport); is880()
1942 mbuf[j++] = inb(tmport); is880()
1950 j = inb(tmport); is880()
1963 while ((inb(tmport) & 0x80) == 0x00) is880()
1967 if (inb(tmport) != 0x16) is880()
2010 while ((inb(tmport) & 0x80) == 0x00) is880()
2015 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e) is880()
2018 while (inb(tmport) != 0x8e) is880()
2029 while ((inb(tmport) & 0x80) == 0) { is880()
2030 if ((inb(tmport) & 0x01) != 0) { is880()
2038 while ((inb(tmport) & 0x80) == 0x00) is880()
2041 j = inb(tmport) & 0x0f; is880()
2056 while ((inb(tmport) & 0x80) == 0) { is880()
2057 if ((inb(tmport) & 0x01) != 0) { is880()
2064 j = inb(tmport) & 0x0f; is880()
2083 j = inb(tmport); is880()
2086 mbuf[k++] = inb(tmport); is880()
2094 j = inb(tmport) & 0x0f; is880()
2114 while ((inb(tmport) & 0x80) == 0x00) is880()
2118 j = inb(tmport); is880()
2162 while ((inb(tmport) & 0x80) == 0x00) is880()
2166 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e) is880()
2169 while (inb(tmport) != 0x8e) is880()
2180 while ((inb(tmport) & 0x80) == 0) { is880()
2181 if ((inb(tmport) & 0x01) != 0) { is880()
2188 while ((inb(tmport) & 0x80) == 0x00) is880()
2191 j = inb(tmport) & 0x0f; is880()
2206 while ((inb(tmport) & 0x80) == 0) { is880()
2207 if ((inb(tmport) & 0x01) != 0) { is880()
2214 j = inb(tmport) & 0x0f; is880()
2233 j = inb(tmport); is880()
2236 mbuf[k++] = inb(tmport); is880()
2244 j = inb(tmport) & 0x0f; is880()
2264 while ((inb(tmport) & 0x80) == 0x00) is880()
2268 j = inb(tmport); is880()
2333 while ((inb(tmport) & 0x80) == 0x00) is880()
2337 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) { is880()
2340 while (inb(tmport) != 0x8e) is880()
2351 while ((inb(tmport) & 0x80) == 0) { is880()
2352 if ((inb(tmport) & 0x01) != 0) { is880()
2372 while ((inb(tmport) & 0x80) == 0x00) is880()
2375 j = inb(tmport) & 0x0f; is880()
2390 while ((inb(tmport) & 0x80) == 0x00) { is880()
2391 if ((inb(tmport) & 0x01) != 0x00) { is880()
2398 j = inb(tmport); is880()
2421 j = inb(tmport); is880()
2424 mbuf[k++] = inb(tmport); is880()
2433 while ((inb(tmport) & 0x80) == 0x00) is880()
2436 j = inb(tmport); is880()
2461 while ((inb(tmport) & 0x80) == 0x00) is880()
2465 j = inb(tmport); is880()
2616 host_id = inb(base_io + 0x39); atp870u_probe()
2627 atpdev->scam_on = inb(tmport); atp870u_probe()
2629 atpdev->global_map[0] = inb(tmport); atp870u_probe()
2641 if (inb(base_io + 0x30) == 0xff) atp870u_probe()
2644 atpdev->sp[0][m++] = inb(base_io + 0x30); atp870u_probe()
2645 atpdev->sp[0][m++] = inb(base_io + 0x31); atp870u_probe()
2646 atpdev->sp[0][m++] = inb(base_io + 0x32); atp870u_probe()
2647 atpdev->sp[0][m++] = inb(base_io + 0x33); atp870u_probe()
2650 atpdev->sp[0][m++] = inb(base_io + 0x30); atp870u_probe()
2651 atpdev->sp[0][m++] = inb(base_io + 0x31); atp870u_probe()
2652 atpdev->sp[0][m++] = inb(base_io + 0x32); atp870u_probe()
2653 atpdev->sp[0][m++] = inb(base_io + 0x33); atp870u_probe()
2656 atpdev->sp[0][m++] = inb(base_io + 0x30); atp870u_probe()
2657 atpdev->sp[0][m++] = inb(base_io + 0x31); atp870u_probe()
2658 atpdev->sp[0][m++] = inb(base_io + 0x32); atp870u_probe()
2659 atpdev->sp[0][m++] = inb(base_io + 0x33); atp870u_probe()
2662 atpdev->sp[0][m++] = inb(base_io + 0x30); atp870u_probe()
2663 atpdev->sp[0][m++] = inb(base_io + 0x31); atp870u_probe()
2664 atpdev->sp[0][m++] = inb(base_io + 0x32); atp870u_probe()
2665 atpdev->sp[0][m++] = inb(base_io + 0x33); atp870u_probe()
2707 k = inb(tmport) & 0x80; atp870u_probe()
2715 inb(tmport); atp870u_probe()
2717 inb(tmport); atp870u_probe()
2723 while ((inb(tmport) & 0x80) == 0) atp870u_probe()
2726 inb(tmport); atp870u_probe()
2778 c=inb(base_io + 0x29); atp870u_probe()
2807 c=inb(base_io + 0x29); atp870u_probe()
2837 k = inb(base_io + 0x28) & 0x8f; atp870u_probe()
2846 inb(base_io + 0x9b); atp870u_probe()
2847 inb(base_io + 0x97); atp870u_probe()
2848 inb(base_io + 0xdb); atp870u_probe()
2849 inb(base_io + 0xd7); atp870u_probe()
2860 while ((inb(tmport) & 0x80) == 0) atp870u_probe()
2864 inb(tmport); atp870u_probe()
2881 while ((inb(tmport) & 0x80) == 0) atp870u_probe()
2885 inb(tmport); atp870u_probe()
2898 k = inb(base_io + 0x28) & 0xcf; atp870u_probe()
2901 k = inb(base_io + 0x1f) | 0x80; atp870u_probe()
2903 k = inb(base_io + 0x29) | 0x01; atp870u_probe()
2929 atpdev->scam_on = inb(tmport); atp870u_probe()
2931 atpdev->global_map[0] = inb(tmport++); atp870u_probe()
2965 k = (inb(tmport) & 0xf3) | 0x10; atp870u_probe()
2976 while ((inb(tmport) & 0x80) == 0) atp870u_probe()
2980 inb(tmport); atp870u_probe()
2990 outb((inb(tmport) & 0xef), tmport); atp870u_probe()
2992 outb((inb(tmport) | 0x20), tmport); atp870u_probe()
3070 printk(" r%2x=%2x", j, inb(tmport++)); atp870u_abort()
3073 printk(" r1c=%2x", inb(tmport)); atp870u_abort()
3075 printk(" r1f=%2x in_snd=%2x ", inb(tmport), dev->in_snd[c]); atp870u_abort()
3077 printk(" d00=%2x", inb(tmport)); atp870u_abort()
3079 printk(" d02=%2x", inb(tmport)); atp870u_abort()
3232 lvdmode=inb(wkport + 0x1b) >> 7; is885()
3272 while ((inb(tmport) & 0x80) == 0x00) is885()
3275 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) { is885()
3278 while (inb(tmport) != 0x8e) is885()
3291 while ((inb(tmport) & 0x80) == 0x00) is885()
3294 j = inb(tmport); is885()
3318 while ((inb(tmport) & 0x80) == 0x00) is885()
3321 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) { is885()
3324 while (inb(tmport) != 0x8e) is885()
3333 k = inb(tmport); is885()
3336 mbuf[j++] = inb(tmport); is885()
3344 j = inb(tmport); is885()
3357 while ((inb(tmport) & 0x80) == 0x00) is885()
3360 if (inb(tmport) != 0x16) { is885()
3402 while ((inb(tmport) & 0x80) == 0x00) is885()
3405 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) { is885()
3408 while (inb(tmport) != 0x8e) is885()
3418 while ((inb(tmport) & 0x80) == 0) { is885()
3419 if ((inb(tmport) & 0x01) != 0) { is885()
3427 while ((inb(tmport) & 0x80) == 0x00) is885()
3429 j = inb(tmport) & 0x0f; is885()
3444 while ((inb(tmport) & 0x80) == 0) { is885()
3445 if ((inb(tmport) & 0x01) != 0) { is885()
3453 j = inb(tmport) & 0x0f; is885()
3472 j = inb(tmport); is885()
3475 mbuf[k++] = inb(tmport); is885()
3483 j = inb(tmport) & 0x0f; is885()
3502 while ((inb(tmport) & 0x80) == 0x00); is885()
3504 j = inb(tmport); is885()
3551 while ((inb(tmport) & 0x80) == 0x00) is885()
3554 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) { is885()
3557 while (inb(tmport) != 0x8e) is885()
3567 while ((inb(tmport) & 0x80) == 0) { is885()
3568 if ((inb(tmport) & 0x01) != 0) { is885()
3576 while ((inb(tmport) & 0x80) == 0x00) is885()
3578 j = inb(tmport) & 0x0f; is885()
3593 while ((inb(tmport) & 0x80) == 0) { is885()
3594 if ((inb(tmport) & 0x01) != 0) { is885()
3602 j = inb(tmport) & 0x0f; is885()
3621 j = inb(tmport); is885()
3624 mbuf[k++] = inb(tmport); is885()
3632 j = inb(tmport) & 0x0f; is885()
3651 while ((inb(tmport) & 0x80) == 0x00) is885()
3654 j = inb(tmport); is885()
3720 while ((inb(tmport) & 0x80) == 0x00) is885()
3723 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) { is885()
3726 while (inb(tmport) != 0x8e) is885()
3736 while ((inb(tmport) & 0x80) == 0) { is885()
3737 if ((inb(tmport) & 0x01) != 0) { is885()
3756 while ((inb(tmport) & 0x80) == 0x00) is885()
3758 j = inb(tmport) & 0x0f; is885()
3773 while ((inb(tmport) & 0x80) == 0x00) { is885()
3774 if ((inb(tmport) & 0x01) != 0x00) { is885()
3782 j = inb(tmport); is885()
3805 j = inb(tmport); is885()
3808 mbuf[k++] = inb(tmport); is885()
3816 while ((inb(tmport) & 0x80) == 0x00); is885()
3817 j = inb(tmport); is885()
3841 while ((inb(tmport) & 0x80) == 0x00) is885()
3844 j = inb(tmport); is885()
H A Dqlogicfas408.c84 x = inb(qbase + 0xd); ql_zap()
105 if (reqlen >= 128 && (inb(qbase + 8) & 2)) { /* full */ ql_pdma()
111 if ((j = inb(qbase + 8)) & 4) ql_pdma()
117 if (reqlen >= 44 && (inb(qbase + 8) & 8)) { /* 1/3 */ ql_pdma()
130 while (reqlen && !((j = inb(qbase + 8)) & 0x10)) ql_pdma()
132 *request++ = inb(qbase + 4); ql_pdma()
136 j = inb(qbase + 8); ql_pdma()
142 if (reqlen >= 128 && inb(qbase + 8) & 0x10) { /* empty */ ql_pdma()
148 if (!((j = inb(qbase + 8)) & 8)) { ql_pdma()
153 if (reqlen >= 40 && !(inb(qbase + 8) & 4)) { /* 2/3 */ ql_pdma()
164 while (reqlen && !((j = inb(qbase + 8)) & 2)) ql_pdma()
170 j = inb(qbase + 8); ql_pdma()
174 return inb(qbase + 8) & 0xc0; ql_pdma()
190 !((k = inb(qbase + 4)) & 0xe0)) { ql_wai()
224 inb(qbase + 5); /* clear interrupts */ ql_icmd()
225 if (inb(qbase + 5)) /* if still interrupting */ ql_icmd()
227 else if (inb(qbase + 7) & 0x1f) ql_icmd()
229 while (inb(qbase + 5)); /* clear ints */ ql_icmd()
233 inb(qbase + 8); /* clear int bits */ ql_icmd()
274 j = inb(qbase + 6); ql_pcmd()
275 i = inb(qbase + 5); ql_pcmd()
279 i |= inb(qbase + 5); /* the 0x10 bit can be set after the 0x08 */ ql_pcmd()
285 j &= 7; /* j = inb( qbase + 7 ) >> 5; */ ql_pcmd()
294 j, i, inb(qbase + 7) & 0x1f); ql_pcmd()
299 if (inb(qbase + 7) & 0x1f) /* if some bytes in fifo */ ql_pcmd()
304 if (reqlen && !((phase = inb(qbase + 4)) & 6)) { /* data phase */ ql_pcmd()
332 k = inb(qbase + 5); /* should be 0x10, bus service */
342 !(inb(qbase + 4) & 6))
351 while (inb(qbase + 5))
360 i = inb(qbase + 5); /* get chip irq stat */
361 j = inb(qbase + 7) & 0x1f; /* and bytes rec'd */
362 status = inb(qbase + 2);
363 message = inb(qbase + 2);
382 i = inb(qbase + 5); /* should be bus service */
386 i |= inb(qbase + 5);
408 if (!(inb(qbase + 4) & 0x80)) /* false alarm? */ ql_ihandl()
414 while (i-- && inb(qbase + 5)); /* maybe also ql_zap() */ ql_ihandl()
536 return inb(qbase + 0xe) & 0xf8; qlogicfas408_get_chip_type()
556 while (inb(qbase + 0xf) & 4) qlogicfas408_setup()
570 return (((inb(qbase + 0xe) ^ inb(qbase + 0xe)) == 7) && qlogicfas408_detect()
571 ((inb(qbase + 0xe) ^ inb(qbase + 0xe)) == 7)); qlogicfas408_detect()
H A Dppa.h128 #define r_dtr(x) (unsigned char)inb((x))
129 #define r_str(x) (unsigned char)inb((x)+1)
130 #define r_ctr(x) (unsigned char)inb((x)+2)
131 #define r_epp(x) (unsigned char)inb((x)+4)
132 #define r_fifo(x) (unsigned char)inb((x)) /* x must be base_hi */
134 #define r_ecr(x) (unsigned char)inb((x)+0x2) /* x must be base_hi */
H A Dimm.h121 #define r_dtr(x) (unsigned char)inb((x))
122 #define r_str(x) (unsigned char)inb((x)+1)
123 #define r_ctr(x) (unsigned char)inb((x)+2)
124 #define r_epp(x) (unsigned char)inb((x)+4)
125 #define r_fifo(x) (unsigned char)inb((x)) /* x must be base_hi */
127 #define r_ecr(x) (unsigned char)inb((x)+2) /* x must be base_hi */
H A Dsym53c416.c255 bytes_left = inb(base + PIO_FIFO_CNT); /* Number of bytes in the PIO FIFO */ sym53c416_read()
266 *(buffer++) = inb(base + PIO_FIFO_1); sym53c416_read()
272 while(time_before(jiffies, i) && (inb(base + PIO_INT_REG) & EMPTY) && timeout) sym53c416_read()
273 if(inb(base + PIO_INT_REG) & SCI) sym53c416_read()
276 if(inb(base + PIO_INT_REG) & EMPTY) sym53c416_read()
297 bufferfree = PIO_SIZE - inb(base + PIO_FIFO_CNT); sym53c416_write()
316 while(time_before(jiffies, i) && (inb(base + PIO_INT_REG) & FULL) && timeout) sym53c416_write()
319 if(inb(base + PIO_INT_REG) & FULL) sym53c416_write()
338 status_reg = inb(base + STATUS_REG); sym53c416_intr_handle()
339 pio_int_reg = inb(base + PIO_INT_REG); sym53c416_intr_handle()
340 int_reg = inb(base + INT_REG); sym53c416_intr_handle()
356 printk(KERN_WARNING "sym53c416: Illegal Command: 0x%02x.\n", inb(base + COMMAND_REG)); sym53c416_intr_handle()
488 current_command->SCp.Status = inb(base + SCSI_FIFO);
489 current_command->SCp.Message = inb(base + SCSI_FIFO);
521 inb(base + INT_REG); sym53c416_probeirq()
533 while(time_before(jiffies, i) && !(inb(base + STATUS_REG) & SCI)) sym53c416_probeirq()
574 if(inb(base + COMMAND_REG) != NOOP) sym53c416_test()
576 if(!inb(base + TC_HIGH) || inb(base + TC_HIGH) == 0xFF) sym53c416_test()
578 if((inb(base + PIO_INT_REG) & (FULL | EMPTY | CE | OUE | FIE | EIE)) != EMPTY) sym53c416_test()
727 int rev = inb(base + TC_HIGH); sym53c416_info()
H A Daha1740.c199 if ( inb(PORTADR(base)) & PORTADDR_ENH ) aha1740_test_port()
228 while(inb(G2STAT(base)) & G2STAT_INTPEND) { aha1740_intr_handle()
231 adapstat = inb(G2INTST(base)); aha1740_intr_handle()
243 inb(G2STAT(base)),adapstat, aha1740_intr_handle()
244 inb(G2INTST(base)), number_serviced++); aha1740_intr_handle()
250 inb(G2STAT(base)),adapstat, aha1740_intr_handle()
251 inb(G2INTST(base)), number_serviced++); aha1740_intr_handle()
291 inb(MBOXIN0(base)), aha1740_intr_handle()
292 inb(MBOXIN1(base)), aha1740_intr_handle()
293 inb(MBOXIN2(base)), aha1740_intr_handle()
294 inb(MBOXIN3(base))); /* Say What? */ aha1740_intr_handle()
461 if (inb(G2STAT(base)) & G2STAT_MBXOUT) break;
471 if (! (inb(G2STAT(base)) & G2STAT_BUSY)) break;
497 *irq_level = intab[inb(INTDEF(base)) & 0x7]; aha1740_getconfig()
498 *irq_type = (inb(INTDEF(base)) & 0x8) >> 3; aha1740_getconfig()
499 *translation = inb(RESV1(base)) & 0x1; aha1740_getconfig()
500 outb(inb(INTDEF(base)) | 0x10, INTDEF(base)); aha1740_getconfig()
568 if ((inb(G2STAT(slotbase)) & aha1740_probe()
H A Deata_pio.c175 if (inb(sh->base + HA_RSTATUS) & HA_SBUSY) eata_pio_int_handler()
188 stat = inb(base + HA_RSTATUS); eata_pio_int_handler()
257 if (!(inb(base + HA_RSTATUS) & HA_SERROR)) { eata_pio_int_handler()
267 eata_stat = inb(base + HA_RSTATUS); eata_pio_int_handler()
288 while (inb(base + HA_RSTATUS) & HA_SBUSY) eata_pio_send_command()
390 while (!(inb(base + HA_RSTATUS) & HA_SDRQ)) eata_pio_queue_lck()
413 while (inb(cmd->device->host->base + HA_RAUXSTAT) & HA_ABUSY) eata_pio_abort()
540 while (!(inb(base + HA_RSTATUS) & HA_SDRQ)) get_pio_board_data()
548 while (inb(base + HA_RSTATUS) & HA_SBUSY) get_pio_board_data()
551 if (inb(base + HA_RSTATUS) & HA_SERROR) get_pio_board_data()
553 else if (!(inb(base + HA_RSTATUS) & HA_SDRQ)) get_pio_board_data()
557 while (inb(base + HA_RSTATUS) & HA_SDRQ) get_pio_board_data()
574 while (inb(base + HA_RSTATUS) & HA_SBUSY) get_pio_conf_PIO()
583 while (!(inb(base + HA_RSTATUS) & HA_SDRQ)) get_pio_conf_PIO()
590 if (inb(base + HA_RSTATUS) & HA_SERROR) { get_pio_conf_PIO()
603 while (inb(base + HA_RSTATUS) & HA_SDRQ) get_pio_conf_PIO()
637 while (inb(base + HA_RSTATUS) & HA_SBUSY); print_selftest()
640 while (inb(base + HA_RSTATUS) & HA_SBUSY) print_selftest()
642 if (inb(base + HA_RSTATUS) & HA_SDRQ) { print_selftest()
651 } while (inb(base + HA_RSTATUS) & (HA_SBUSY | HA_SDRQ)); print_selftest()
653 return (!(inb(base + HA_RSTATUS) & HA_SERROR)); print_selftest()
822 pal1 = inb((u16) base - 8); find_pio_EISA()
823 pal2 = inb((u16) base - 7); find_pio_EISA()
824 pal3 = inb((u16) base - 6); find_pio_EISA()
869 if ((inb(base) == 0x12) && (inb(base + 1) == 0x14)) find_pio_PCI()
H A DNCR_Q720.c177 i = inb(io_base) | (inb(io_base+1)<<8); NCR_Q720_probe()
185 pos4 = inb(io_base + 4); NCR_Q720_probe()
191 asr10 = inb(io_base + 0x12); NCR_Q720_probe()
197 asr9 = inb(io_base + 0x11); NCR_Q720_probe()
236 asr2 = inb(io_base + 0x0a); NCR_Q720_probe()
H A Dultrastor.c394 in_byte = inb(U14F_PRODUCT_ID(config.port_address)); ultrastor_14f_detect()
410 in_byte = inb(U14F_PRODUCT_ID(config.port_address) + 1); ultrastor_14f_detect()
454 *(char *)&config_1 = inb(CONFIG(config.port_address + 0)); ultrastor_14f_detect()
455 *(char *)&config_2 = inb(CONFIG(config.port_address + 1)); ultrastor_14f_detect()
550 if (inb(addr) != US24F_PRODUCT_ID_0 &&
551 inb(addr+1) != US24F_PRODUCT_ID_1 &&
552 inb(addr+2) != US24F_PRODUCT_ID_2)
555 config.revision = inb(addr+3);
557 if (! (inb(addr+4) & 1))
567 config_1 = inb(addr + 5);
594 config_2 = inb(addr + 7);
769 while (inb(config.ogm_address - 1) != 0 && config.aborted[mscp_index] == 0xff)
774 while ((inb(LCL_DOORBELL_INTR(config.doorbell_address)) & (config.slot ? 2 : 1)) && config.aborted[mscp_index] == 0xff)
782 if (inb(LCL_DOORBELL_INTR(config.doorbell_address)) & (config.slot ? 2 : 1))
880 unsigned char p = inb(port0 + i);
887 ogm_status = inb(port0 + 22);
889 icm_status = inb(port0 + 27);
897 if (config.slot ? inb(config.icm_address - 1) == 2 :
898 (inb(SYS_DOORBELL_INTR(config.doorbell_address)) & 1))
919 if (config.slot && inb(config.ogm_address - 1) == 0)
1076 unsigned char icm_status = inb(config.icm_address - 1);
1169 if (config.slot ? inb(config.icm_address - 1) :
1170 (inb(SYS_DOORBELL_INTR(config.doorbell_address)) & 1))
H A Dpas16.c161 #define rtrc(i) {inb(0x3da); outb(0x31, 0x3c0); outb((i), 0x3c0);}
214 tmp = inb( io_port + IO_CONFIG_3 ); init_board()
261 board_rev = inb( io_port + PCB_CONFIG ); pas16_hw_detect()
269 tmp = inb( io_port + PCB_CONFIG ); pas16_hw_detect()
275 if( ( inb( io_port + OPERATION_MODE_1 ) & 0x03 ) != 0x03 ) pas16_hw_detect()
431 outb( (inb(io_port + IO_CONFIG_3) & 0x0f), io_port + IO_CONFIG_3 ); pas16_detect()
504 while ( !(inb(instance->io_port + P_STATUS_REG_OFFSET) & P_ST_RDY) ) NCR5380_pread()
509 if ( inb(instance->io_port + P_TIMEOUT_STATUS_REG_OFFSET) & P_TS_TIM) { NCR5380_pread()
541 while ( !((inb(instance->io_port + P_STATUS_REG_OFFSET)) & P_ST_RDY) ) NCR5380_pwrite()
546 if (inb(instance->io_port + P_TIMEOUT_STATUS_REG_OFFSET) & P_TS_TIM) { NCR5380_pwrite()
H A Dinitio.c382 rb = inb(base + TUL_NVRAM); initio_se2_rd()
433 if ((rb = inb(base + TUL_NVRAM)) & SE2DI) initio_se2_wr()
519 gctrl = inb(base + TUL_GCTRL); initio_read_eeprom()
526 gctrl = inb(base + TUL_GCTRL); initio_read_eeprom()
540 if (inb(host->addr + TUL_XStatus) & XPEND) { /* if DMA xfer is pending, abort DMA xfer */ initio_stop_bm()
543 while ((inb(host->addr + TUL_Int) & XABT) == 0) initio_stop_bm()
561 while (!((host->jsint = inb(host->addr + TUL_SInt)) & TSS_SCSIRST_INT)) initio_reset_scsi()
572 inb(host->addr + TUL_SInt); initio_reset_scsi()
609 outb(inb(host->addr + TUL_PCMD) | 0x40, host->addr + TUL_PCMD); initio_init()
642 (inb(host->addr + TUL_GCTRL1) & 0xFE), initio_init()
1085 if (inb(host->addr + TUL_Int) & TSS_INT_PENDING) { initio_isr()
1162 if (inb(host->addr + TUL_SStatus0) & TSS_INT_PENDING) tulip_main()
1179 if ((host->jsstatus0 = inb(host->addr + TUL_SStatus0)) & TSS_INT_PENDING) { tulip_scsi()
1181 host->jsstatus1 = inb(host->addr + TUL_SStatus1); tulip_scsi()
1182 host->jsint = inb(host->addr + TUL_SInt); tulip_scsi()
1365 outb((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)), host->addr + TUL_SSignal); initio_state_1()
1396 outb((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)), host->addr + TUL_SSignal); initio_state_2()
1458 outb(inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7), host->addr + TUL_SSignal); initio_state_3()
1550 if (inb(host->addr + TUL_XCmd) & 0x20) { initio_state_5()
1555 if (inb(host->addr + TUL_XStatus) & XPEND) { /* DMA xfer pending, Send STOP */ initio_state_5()
1557 outb(inb(host->addr + TUL_XCtrl) | 0x80, host->addr + TUL_XCtrl); initio_state_5()
1559 while (inb(host->addr + TUL_XStatus) & XPEND) initio_state_5()
1564 if ((inb(host->addr + TUL_SStatus1) & TSS_XFER_CMP) == 0) { initio_state_5()
1566 cnt += (inb(host->addr + TUL_SFifoCnt) & 0x1F) << 1; initio_state_5()
1568 cnt += (inb(host->addr + TUL_SFifoCnt) & 0x1F); initio_state_5()
1570 if (inb(host->addr + TUL_XStatus) & XPEND) { /* if DMA xfer is pending, abort DMA xfer */ initio_state_5()
1573 while ((inb(host->addr + TUL_Int) & XABT) == 0) initio_state_5()
1582 if ((inb(host->addr + TUL_SStatus1) & TSS_XFER_CMP) == 0) initio_state_5()
1681 cnt = inb(host->addr + TUL_SFifoCnt) & 0x1F; initio_state_7()
1684 inb(host->addr + TUL_SFifo); initio_state_7()
1779 inb(host->addr + TUL_SFifo); initio_xpad_in()
1818 scb->tastat = inb(host->addr + TUL_SFifo); initio_status_msg()
1829 msg = inb(host->addr + TUL_SFifo); initio_status_msg()
1898 if (inb(host->addr + TUL_XStatus) & 0x01) { int_initio_scsi_rst()
1901 while ((inb(host->addr + TUL_Int) & 0x04) == 0) int_initio_scsi_rst()
1942 tar = inb(host->addr + TUL_SBusId); int_initio_resel()
1944 lun = inb(host->addr + TUL_SIdent) & 0x0F; int_initio_resel()
1961 msg = inb(host->addr + TUL_SFifo); /* Read Tag Message */ int_initio_resel()
1976 tag = inb(host->addr + TUL_SFifo); /* Read Tag ID */ int_initio_resel()
2037 outb(((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN), host->addr + TUL_SSignal); initio_msgout_abort_targ()
2060 outb(((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN), host->addr + TUL_SSignal); initio_msgout_abort_tag()
2091 switch (inb(host->addr + TUL_SFifo)) { initio_msgin()
2101 outb((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)), initio_msgin()
2105 outb(((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN), initio_msgin()
2131 outb(((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN), host->addr + TUL_SSignal); initio_msgout_reject()
2164 len = inb(host->addr + TUL_SFifo); initio_msgin_extend()
2174 host->msg[idx++] = inb(host->addr + TUL_SFifo); initio_msgin_extend()
2190 r = inb(host->addr + TUL_SSignal); initio_msgin_extend()
2222 outb(((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN), host->addr + TUL_SSignal); initio_msgin_extend()
2227 outb(((inb(host->addr + TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN), host->addr + TUL_SSignal); initio_msgin_extend()
2439 while (!((host->jsstatus0 = inb(host->addr + TUL_SStatus0)) wait_tulip()
2443 host->jsint = inb(host->addr + TUL_SInt); wait_tulip()
2445 host->jsstatus1 = inb(host->addr + TUL_SStatus1); wait_tulip()
2486 while (!((host->jsstatus0 = inb(host->addr + TUL_SStatus0)) & TSS_INT_PENDING)) initio_wait_disc()
2489 host->jsint = inb(host->addr + TUL_SInt); initio_wait_disc()
2505 while (!((host->jsstatus0 = inb(host->addr + TUL_SStatus0)) initio_wait_done_disc()
2509 host->jsint = inb(host->addr + TUL_SInt); initio_wait_done_disc()
H A Da100u2w.c144 if (inb(host->base + ORC_HCTRL) & HOSTSTOP) /* Wait HOSTSTOP set */ wait_chip_ready()
156 if (inb(host->base + ORC_HSTUS) & RREADY) /* Wait READY set */ wait_firmware_ready()
169 if (!(inb(host->base + ORC_HCTRL) & SCSIRST)) /* Wait SCSIRST done */ wait_scsi_reset_done()
182 if (!(inb(host->base + ORC_HCTRL) & HDO)) /* Wait HDO off */ wait_HDO_off()
195 if ((*data = inb(host->base + ORC_HSTUS)) & HDI) wait_hdi_set()
215 version = inb(host->base + ORC_HDATA); orc_read_fwrev()
220 version |= inb(host->base + ORC_HDATA) << 8; orc_read_fwrev()
264 *ptr = inb(host->base + ORC_HDATA); orc_nv_read()
375 data = inb(host->base + ORC_GCFG); orc_load_firmware()
379 if (inb(host->base + ORC_EBIOSDATA) != 0x55) { orc_load_firmware()
384 if (inb(host->base + ORC_EBIOSDATA) != 0xAA) { orc_load_firmware()
393 *data32_ptr = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ orc_load_firmware()
395 *(data32_ptr + 1) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ orc_load_firmware()
397 *(data32_ptr + 2) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ orc_load_firmware()
409 *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ orc_load_firmware()
424 *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ orc_load_firmware()
508 if (inb(host->base + ORC_HSTUS) & RREADY) { /* Orchid is ready */ init_orchid()
754 status = inb(host->base + ORC_HDATA); orchid_abort_scb()
817 if (inb(host->base + ORC_RQUEUECNT) == 0) orc_interrupt()
822 scb_index = inb(host->base + ORC_RQUEUE); orc_interrupt()
829 } while (inb(host->base + ORC_RQUEUECNT)); orc_interrupt()
H A DNCR53c406a.c153 #define rtrc(i) {inb(0x3da);outb(0x31,0x3c0);outb((i),0x3c0);}
353 i = inb(PIO_STATUS); NCR53c406a_pio_read()
391 *request++ = inb(PIO_FIFO); NCR53c406a_pio_read()
407 i = inb(PIO_STATUS); NCR53c406a_pio_write()
492 if ((inb(ports[i] + 0x0e) ^ inb(ports[i] + 0x0e)) == 7 && (inb(ports[i] + 0x0e) ^ inb(ports[i] + 0x0e)) == 7 && (inb(ports[i] + 0x0e) & 0xf8) == 0x58) { NCR53c406a_detect()
679 while (time_after(i, jiffies) && !(inb(STAT_REG) & 0xe0)) { /* wait for a pseudo-interrupt */
798 pio_status = inb(PIO_STATUS); NCR53c406a_intr()
801 status = inb(STAT_REG); NCR53c406a_intr()
802 DEB(seq_reg = inb(SEQ_REG)); NCR53c406a_intr()
803 int_reg = inb(INT_REG); NCR53c406a_intr()
804 DEB(fifo_size = inb(FIFO_FLAGS) & 0x1f); NCR53c406a_intr()
938 current_SC->SCp.Status = inb(SCSI_FIFO);
939 current_SC->SCp.Message = inb(SCSI_FIFO);
941 VDEB(printk("SCSI FIFO size=%d\n", inb(FIFO_FLAGS) & 0x1f));
959 inb(INT_REG); /* clear the interrupt register */ irq_probe()
968 while (time_after(i, jiffies) && !(inb(STAT_REG) & 0x80)) irq_probe()
H A Daha152x.h289 #define GETPORT(PORT) inb( PORT )
290 #define SETBITS(PORT, BITS) outb( (inb(PORT) | (BITS)), (PORT) )
291 #define CLRBITS(PORT, BITS) outb( (inb(PORT) & ~(BITS)), (PORT) )
292 #define TESTHI(PORT, BITS) ((inb(PORT) & (BITS)) == (BITS))
293 #define TESTLO(PORT, BITS) ((inb(PORT) & (BITS)) == 0)
H A Dfdomain.c598 inb( port + MSB_ID_Code ), inb( port + LSB_ID_Code ) ); fdomain_is_valid_port()
607 if (inb( port + LSB_ID_Code ) != 0xe9) { /* test for 0x6127 id */ fdomain_is_valid_port()
608 if (inb( port + LSB_ID_Code ) != 0x27) return 0; fdomain_is_valid_port()
609 if (inb( port + MSB_ID_Code ) != 0x61) return 0; fdomain_is_valid_port()
612 if (inb( port + MSB_ID_Code ) != 0x60) return 0; fdomain_is_valid_port()
621 if ((inb( port + Configuration2 ) & 0x80) == 0x80) { fdomain_is_valid_port()
623 if ((inb( port + Configuration2 ) & 0x80) == 0x00) { fdomain_is_valid_port()
641 result = inb( port_base + Read_Loopback ); fdomain_test_loopback()
666 int options = inb(base + Configuration1); fdomain_get_irq()
1050 status = inb(port_base + TMC_Status); /* Read adapter status */
1086 status = inb(port_base + SCSI_Status); /* Read adapter status */ fdomain_select()
1142 if ((inb(port_base + TMC_Status) & 0x01) == 0) do_fdomain_16x0_intr()
1171 status = inb(port_base + TMC_Status); /* Read adapter status */ do_fdomain_16x0_intr()
1195 status = inb(port_base + SCSI_Status); do_fdomain_16x0_intr()
1225 status = inb(port_base + SCSI_Status); do_fdomain_16x0_intr()
1252 current_SC->SCp.Status = inb(port_base + Read_SCSI_Data); do_fdomain_16x0_intr()
1271 current_SC->SCp.Message = inb(port_base + Read_SCSI_Data); do_fdomain_16x0_intr()
1346 *current_SC->SCp.ptr++ = inb(port_base + Read_FIFO); do_fdomain_16x0_intr()
1508 imr = (inb( 0x0a1 ) << 8) + inb( 0x21 ); print_info()
1510 irr = inb( 0xa0 ) << 8; print_info()
1512 irr += inb( 0x20 ); print_info()
1514 isr = inb( 0xa0 ) << 8; print_info()
1516 isr += inb( 0x20 ); print_info()
1524 printk( "SCSI Status = 0x%02x\n", inb(port_base + SCSI_Status)); print_info()
1525 printk( "TMC Status = 0x%02x", inb(port_base + TMC_Status)); print_info()
1526 if (inb((port_base + TMC_Status) & 1)) print_info()
1529 printk("Interrupt Status = 0x%02x", inb(port_base + Interrupt_Status)); print_info()
1530 if (inb(port_base + Interrupt_Status) & 0x08) print_info()
1534 printk("FIFO Status = 0x%02x\n", inb(port_base + FIFO_Status)); print_info()
1536 inb( port_base + Interrupt_Cond ) ); print_info()
1538 printk( "Configuration 1 = 0x%02x\n", inb( port_base + Configuration1 ) ); print_info()
1541 inb( port_base + Configuration2 ) ); print_info()
H A Dg_NCR5380.h52 #define NCR5380_read(reg) (inb(NCR5380_map_name + (reg)))
H A Daha1542.c80 u8 bits = inb(port) & mask; wait_mask()
122 *buf++ = inb(DATA(base)); aha1542_in()
191 if (inb(STATUS(sh->io_port)) == 0xff) aha1542_test_port()
208 if (inb(INTRFLAGS(sh->io_port)) & INTRMASK) aha1542_test_port()
219 inquiry_result[i] = inb(DATA(sh->io_port)); aha1542_test_port()
223 if (inb(STATUS(sh->io_port)) & DF) aha1542_test_port()
251 flag = inb(INTRFLAGS(sh->io_port)); aha1542_interrupt()
263 printk("status %02x\n", inb(STATUS(sh->io_port))); aha1542_interrupt()
270 flag = inb(INTRFLAGS(sh->io_port)); aha1542_interrupt()
514 i = inb(STATUS(sh->io_port)); aha1542_getconfig()
516 i = inb(DATA(sh->io_port)); aha1542_getconfig()
615 i = inb(STATUS(sh->io_port)); aha1542_query()
617 i = inb(DATA(sh->io_port)); aha1542_query()
H A Dnsp32_io.h22 return inb(base + index); nsp32_read1()
122 return inb(base + DATA_REG_LOW); nsp32_index_read1()
H A Dpas16.h124 #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) )
129 , instance->hostno, (reg), PAS16_io_port(reg))), inb( PAS16_io_port(reg)) )
H A Dqlogicfas408.h90 #define REG0 ( outb( inb( qbase + 0xd ) & 0x7f , qbase + 0xd ), outb( 4 , qbase + 0xd ))
91 #define REG1 ( outb( inb( qbase + 0xd ) | 0x80 , qbase + 0xd ), outb( 0xb4 | int_type, qbase + 0xd ))
/linux-4.1.27/arch/x86/include/asm/
H A Dmach_traps.h22 return inb(NMI_REASON_PORT); default_get_nmi_reason()
34 inb(0x71); /* dummy */ reassert_nmi()
36 inb(0x71); /* dummy */ reassert_nmi()
H A Dprocessor-cyrix.h13 * inb(0x23);
23 return inb(0x23); getCx86()
32 #define getCx86_old(reg) ({ outb((reg), 0x22); inb(0x23); })
H A Dmach_timer.h23 outb((inb(0x61) & ~0x02) | 0x01, 0x61); mach_prepare_counter()
H A Di8259.h32 unsigned char value = inb(port); inb_pic()
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-isch.c73 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT), sch_transaction()
74 inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0), sch_transaction()
75 inb(SMBHSTDAT1)); sch_transaction()
78 temp = inb(SMBHSTSTS) & 0x0f; sch_transaction()
90 temp = inb(SMBHSTSTS) & 0x0f; sch_transaction()
99 outb(inb(SMBHSTCNT) | 0x10, SMBHSTCNT); sch_transaction()
103 temp = inb(SMBHSTSTS) & 0x0f; sch_transaction()
122 temp = inb(SMBHSTSTS) & 0x07; sch_transaction()
133 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT), sch_transaction()
134 inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0), sch_transaction()
135 inb(SMBHSTDAT1)); sch_transaction()
153 temp = inb(SMBHSTSTS) & 0x0f; sch_access()
218 outb((inb(SMBHSTCNT) & 0xb0) | (size & 0x7), SMBHSTCNT); sch_access()
230 data->byte = inb(SMBHSTDAT0); sch_access()
233 data->word = inb(SMBHSTDAT0) + (inb(SMBHSTDAT1) << 8); sch_access()
236 data->block[0] = inb(SMBHSTDAT0); sch_access()
240 data->block[i] = inb(SMBBLKDAT+i-1); sch_access()
H A Di2c-via.c51 outb(state ? inb(I2C_DIR) & ~I2C_SCL : inb(I2C_DIR) | I2C_SCL, I2C_DIR); bit_via_setscl()
56 outb(state ? inb(I2C_DIR) & ~I2C_SDA : inb(I2C_DIR) | I2C_SDA, I2C_DIR); bit_via_setsda()
61 return (0 != (inb(I2C_IN) & I2C_SCL)); bit_via_getscl()
66 return (0 != (inb(I2C_IN) & I2C_SDA)); bit_via_getsda()
129 outb(inb(I2C_DIR) & ~(I2C_SDA | I2C_SCL), I2C_DIR); vt586b_probe()
130 outb(inb(I2C_OUT) & ~(I2C_SDA | I2C_SCL), I2C_OUT); vt586b_probe()
H A Dscx200_acb.c131 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1); scx200_acb_machine()
161 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1); scx200_acb_machine()
167 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1); scx200_acb_machine()
169 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1); scx200_acb_machine()
183 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1); scx200_acb_machine()
185 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1); scx200_acb_machine()
190 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1); scx200_acb_machine()
193 *iface->ptr++ = inb(ACBSDA); scx200_acb_machine()
202 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1); scx200_acb_machine()
232 status = inb(ACBST); scx200_acb_poll()
265 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2); scx200_acb_reset()
267 outb(inb(ACBCTL1) & ~(ACBCTL1_STASTRE | ACBCTL1_NMINTE), ACBCTL1); scx200_acb_reset()
269 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1); scx200_acb_reset()
273 outb(inb(ACBCST) | ACBCST_BB, ACBCST); scx200_acb_reset()
338 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1); scx200_acb_smbus_xfer()
396 if (inb(ACBCTL2) != 0x70) { scx200_acb_probe()
401 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1); scx200_acb_probe()
403 val = inb(ACBCTL1); scx200_acb_probe()
409 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2); scx200_acb_probe()
411 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1); scx200_acb_probe()
413 val = inb(ACBCTL1); scx200_acb_probe()
/linux-4.1.27/arch/mips/loongson/lemote-2f/
H A Dec_kb3310b.c30 value = inb(EC_IO_PORT_DATA); ec_read()
46 inb(EC_IO_PORT_DATA); ec_write()
70 status = inb(EC_STS_PORT); ec_query_seq()
72 status = inb(EC_STS_PORT); ec_query_seq()
112 status = inb(EC_STS_PORT); ec_get_event_num()
115 status = inb(EC_STS_PORT); ec_get_event_num()
123 value = inb(EC_DAT_PORT); ec_get_event_num()
H A Dirq.c41 isr = inb(PIC_MASTER_CMD) & mach_i8259_irq()
42 ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR); mach_i8259_irq()
44 isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8; mach_i8259_irq()
55 if (~inb(PIC_MASTER_ISR) & 0x80) mach_i8259_irq()
H A Dpm.c65 irq_mask = inb(PIC_MASTER_IMR); setup_wakeup_events()
72 inb(PIC_MASTER_IMR); setup_wakeup_events()
74 inb(PIC_SLAVE_IMR); setup_wakeup_events()
/linux-4.1.27/drivers/misc/c2port/
H A Dc2port-duramar2150.c38 v = inb(DIR_PORT); duramar2150_c2port_access()
57 v = inb(DIR_PORT); duramar2150_c2port_c2d_dir()
69 return inb(DATA_PORT) & C2D; duramar2150_c2port_c2d_get()
78 v = inb(DATA_PORT); duramar2150_c2port_c2d_set()
94 v = inb(DATA_PORT); duramar2150_c2port_c2ck_set()
/linux-4.1.27/scripts/dtc/
H A Dflattree.c584 static void inbuf_init(struct inbuf *inb, void *base, void *limit) inbuf_init() argument
586 inb->base = base; inbuf_init()
587 inb->limit = limit; inbuf_init()
588 inb->ptr = inb->base; inbuf_init()
591 static void flat_read_chunk(struct inbuf *inb, void *p, int len) flat_read_chunk() argument
593 if ((inb->ptr + len) > inb->limit) flat_read_chunk()
596 memcpy(p, inb->ptr, len); flat_read_chunk()
598 inb->ptr += len; flat_read_chunk()
601 static uint32_t flat_read_word(struct inbuf *inb) flat_read_word() argument
605 assert(((inb->ptr - inb->base) % sizeof(val)) == 0); flat_read_word()
607 flat_read_chunk(inb, &val, sizeof(val)); flat_read_word()
612 static void flat_realign(struct inbuf *inb, int align) flat_realign() argument
614 int off = inb->ptr - inb->base; flat_realign()
616 inb->ptr = inb->base + ALIGN(off, align); flat_realign()
617 if (inb->ptr > inb->limit) flat_realign()
621 static char *flat_read_string(struct inbuf *inb) flat_read_string() argument
624 const char *p = inb->ptr; flat_read_string()
628 if (p >= inb->limit) flat_read_string()
633 str = xstrdup(inb->ptr); flat_read_string()
635 inb->ptr += len; flat_read_string()
637 flat_realign(inb, sizeof(uint32_t)); flat_read_string()
642 static struct data flat_read_data(struct inbuf *inb, int len) flat_read_data() argument
652 flat_read_chunk(inb, d.val, len); flat_read_data()
654 flat_realign(inb, sizeof(uint32_t)); flat_read_data()
659 static char *flat_read_stringtable(struct inbuf *inb, int offset) flat_read_stringtable() argument
663 p = inb->base + offset; flat_read_stringtable()
665 if (p >= inb->limit || p < inb->base) flat_read_stringtable()
675 return xstrdup(inb->base + offset); flat_read_stringtable()
699 static struct reserve_info *flat_read_mem_reserve(struct inbuf *inb) flat_read_mem_reserve() argument
712 flat_read_chunk(inb, &re, sizeof(re)); flat_read_mem_reserve()
/linux-4.1.27/drivers/input/gameport/
H A Dlightning.c68 while ((inb(L4_PORT) & L4_BUSY) && t > 0) t--; l4_wait_ready()
85 if (inb(L4_PORT) & L4_BUSY) goto fail; l4_cooked_read()
89 status = inb(L4_PORT); l4_cooked_read()
94 axes[i] = inb(L4_PORT); l4_cooked_read()
100 *buttons = inb(L4_PORT) & 0x0f; l4_cooked_read()
129 if (inb(L4_PORT) & L4_BUSY) l4_getcal()
136 if (inb(L4_PORT) != L4_SELECT_DIGITAL + (port >> 2)) l4_getcal()
146 cal[i] = inb(L4_PORT); l4_getcal()
165 if (inb(L4_PORT) & L4_BUSY) l4_setcal()
172 if (inb(L4_PORT) != L4_SELECT_DIGITAL + (port >> 2)) l4_setcal()
264 if (inb(L4_PORT) & L4_BUSY) l4_add_card()
271 if (inb(L4_PORT) != L4_SELECT_DIGITAL + card_no) l4_add_card()
276 if (inb(L4_PORT) != L4_ID) l4_add_card()
281 rev = inb(L4_PORT); l4_add_card()
H A Dns558.c83 c = inb(io); ns558_isa_probe()
85 if (~(u = v = inb(io)) & 3) { ns558_isa_probe()
94 for (i = 0; i < 1000; i++) v &= inb(io); ns558_isa_probe()
106 u = inb(io); ns558_isa_probe()
108 if ((u ^ inb(io)) & 0xf) { ns558_isa_probe()
126 if (inb(io & (-1 << i)) != inb((io & (-1 << i)) + (1 << i) - 1)) b++; ns558_isa_probe()
/linux-4.1.27/arch/arm/mach-footbridge/
H A Dnetwinder-hw.c133 return inb(GP1_IO_BASE) | inb(GP2_IO_BASE) << 8; nw_gpio_read()
437 inb(0x203); rwa010_read_ident()
439 bit = inb(0x203); rwa010_read_ident()
453 dprintk("Card no = %d\n", inb(0x203)); rwa010_global_init()
476 i = inb(0x203); rwa010_game_port_init()
479 dprintk("%02X%02X (201)\n", inb(0x203), i); rwa010_game_port_init()
492 i = inb(0x203); rwa010_waveartist_init()
495 dprintk("%02X%02X (%X),", inb(0x203), i, base); rwa010_waveartist_init()
498 dprintk(" irq: %d (%d),", inb(0x203), irq); rwa010_waveartist_init()
501 dprintk(" dma: %d (%d)\n", inb(0x203), dma); rwa010_waveartist_init()
514 i = inb(0x203); rwa010_soundblaster_init()
517 dprintk("%02X%02X (%X),", inb(0x203), i, sb_base); rwa010_soundblaster_init()
521 dprintk("%d (%d),", inb(0x203), irq); rwa010_soundblaster_init()
525 dprintk("%d (%d)\n", inb(0x203), dma); rwa010_soundblaster_init()
529 i = inb(0x203); rwa010_soundblaster_init()
532 dprintk("%02X%02X (%X)\n", inb(0x203), i, al_base); rwa010_soundblaster_init()
546 if (inb(0x22e) & 0x80) rwa010_soundblaster_reset()
553 dprintk("SoundBlaster DSP reset: %02X (AA)\n", inb(0x22a)); rwa010_soundblaster_reset()
556 if ((inb(0x22c) & 0x80) == 0) rwa010_soundblaster_reset()
567 i = inb(0x22a); rwa010_soundblaster_reset()
569 i |= inb(0x22a) << 8; rwa010_soundblaster_reset()
573 if ((inb(0x22c) & 0x80) == 0) rwa010_soundblaster_reset()
H A Disa-irq.c37 outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO); isa_mask_pic_lo_irq()
44 outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO); isa_ack_pic_lo_irq()
52 outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO); isa_unmask_pic_lo_irq()
65 outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI); isa_mask_pic_hi_irq()
72 outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI); isa_ack_pic_hi_irq()
81 outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI); isa_unmask_pic_hi_irq()
144 if (inb(PIC_MASK_LO) == 0xf5 && inb(PIC_MASK_HI) == 0xfa) { isa_init_irq()
/linux-4.1.27/arch/sh/include/asm/
H A Dio_noioport.h4 static inline u8 inb(unsigned long addr) inb() function
48 #define inb_p(addr) inb(addr)
/linux-4.1.27/drivers/block/paride/
H A Dppc6lnx.c126 i = inb(ppc->lpt_addr + 1); ppc6_select()
131 ppc->org_data = inb(ppc->lpt_addr); ppc6_select()
133 ppc->org_ctrl = inb(ppc->lpt_addr + 2) & 0x5F; // readback ctrl ppc6_select()
176 k = inb(ppc->lpt_addr + 1) & 0xB8; ppc6_select()
184 k = (inb(ppc->lpt_addr + 1) & 0xB8) ^ 0xB8; ppc6_select()
303 data = inb(ppc->lpt_addr + 1); ppc6_rd_data_byte()
313 data |= inb(ppc->lpt_addr + 1) & 0xB8; ppc6_rd_data_byte()
329 data = inb(ppc->lpt_addr); ppc6_rd_data_byte()
348 data = inb(ppc->lpt_addr + 4); ppc6_rd_data_byte()
396 d = inb(ppc->lpt_addr + 1); ppc6_rd_data_blk()
406 d |= inb(ppc->lpt_addr + 1) & 0xB8; ppc6_rd_data_blk()
430 *data++ = inb(ppc->lpt_addr); ppc6_rd_data_blk()
453 *data++ = inb(ppc->lpt_addr + 4); ppc6_rd_data_blk()
477 *data++ = inb(ppc->lpt_addr + 4); ppc6_rd_data_blk()
501 *data++ = inb(ppc->lpt_addr + 4); ppc6_rd_data_blk()
522 inb(ppc->lpt_addr + 1); ppc6_wait_for_fifo()
/linux-4.1.27/arch/mips/loongson/common/
H A Dpm.c32 cached_slave_mask = inb(PIC_SLAVE_IMR); arch_suspend_disable_irqs()
33 cached_master_mask = inb(PIC_MASTER_IMR); arch_suspend_disable_irqs()
36 inb(PIC_SLAVE_IMR); arch_suspend_disable_irqs()
38 inb(PIC_MASTER_IMR); arch_suspend_disable_irqs()
/linux-4.1.27/arch/mips/include/asm/
H A Di8259.h58 irq = inb(PIC_MASTER_CMD) & 7; i8259_irq()
65 irq = (inb(PIC_SLAVE_CMD) & 7) + 8; i8259_irq()
77 if(~inb(PIC_MASTER_ISR) & 0x80) i8259_irq()
/linux-4.1.27/drivers/watchdog/
H A Dibmasr.c77 reg = inb(asr_read_addr); __asr_toggle()
80 reg = inb(asr_read_addr); __asr_toggle()
83 reg = inb(asr_read_addr); __asr_toggle()
86 reg = inb(asr_read_addr); __asr_toggle()
103 reg = inb(asr_read_addr); asr_enable()
113 reg = inb(asr_read_addr); asr_enable()
116 reg = inb(asr_read_addr); asr_enable()
125 reg = inb(asr_read_addr); asr_disable()
133 reg = inb(asr_read_addr); asr_disable()
137 reg = inb(asr_read_addr); asr_disable()
157 high = inb(0x2f); asr_get_base_address()
161 low = inb(0x2f); asr_get_base_address()
H A Dsp5100_tco.c136 val = inb(SB800_IO_PM_DATA_REG); tco_timer_enable()
142 val = inb(SB800_IO_PM_DATA_REG); tco_timer_enable()
161 val = inb(SP5100_IO_PM_DATA_REG); tco_timer_enable()
362 val = inb(data_reg);
364 val = val << 8 | inb(data_reg);
366 val = val << 8 | inb(data_reg);
369 val = val << 8 | (inb(data_reg) & 0xf8);
387 val = inb(SB800_IO_PM_DATA_REG);
389 val = val << 8 | inb(SB800_IO_PM_DATA_REG);
391 val = val << 8 | inb(SB800_IO_PM_DATA_REG);
393 val = val << 8 | inb(SB800_IO_PM_DATA_REG);
H A Dpc87413_wdt.c82 cr_data = inb(WDT_DATA_IO_PORT); pc87413_select_wdt_out()
108 cr_data = inb(WDT_DATA_IO_PORT); pc87413_enable_swc()
127 addr_h = inb(WDT_DATA_IO_PORT); pc87413_get_swc_base_addr()
131 addr_l = inb(WDT_DATA_IO_PORT); pc87413_get_swc_base_addr()
146 outb_p(inb(swc_base_addr + 0x0f) | 0x03, swc_base_addr + 0x0f); pc87413_swc_bank3()
168 outb_p(inb(swc_base_addr + WDCTL) | 0x01, swc_base_addr + WDCTL); pc87413_enable_wden()
178 outb_p(inb(swc_base_addr + WDCFG) | 0x80, swc_base_addr + WDCFG); pc87413_enable_sw_wd_tren()
189 outb_p(inb(swc_base_addr + WDCFG) & 0x7f, swc_base_addr + WDCFG); pc87413_disable_sw_wd_tren()
200 outb_p(inb(swc_base_addr + WDCTL) | 0x80, swc_base_addr + WDCTL); pc87413_enable_sw_wd_trg()
211 outb_p(inb(swc_base_addr + WDCTL) & 0x7f, swc_base_addr + WDCTL); pc87413_disable_sw_wd_trg()
H A Dwdt_pci.c135 inb(WDT_DC); /* Disable watchdog */ wdtpci_start()
141 inb(WDT_DC); /* Disable watchdog */ wdtpci_start()
145 inb(WDT_BUZZER); /* disable */ wdtpci_start()
147 inb(WDT_OPTONOTRST); /* disable */ wdtpci_start()
149 inb(WDT_OPTORST); /* disable */ wdtpci_start()
151 inb(WDT_PROGOUT); /* disable */ wdtpci_start()
181 inb(WDT_DC); /* Disable watchdog */ wdtpci_stop()
201 inb(WDT_DC); /* Disable watchdog */ wdtpci_ping()
248 new_status = inb(WDT_SR); wdtpci_get_status()
283 c = inb(WDT_RT); wdtpci_get_temperature()
310 status = inb(WDT_SR); wdtpci_interrupt()
317 pr_crit("Overheat alarm (%d)\n", inb(WDT_RT)); wdtpci_interrupt()
H A DiTCO_vendor_support.c34 #include <linux/io.h> /* For inb/outb/... */
188 val = inb(SM_DATAIO); supermicro_new_pre_start()
198 val = inb(SM_DATAIO); supermicro_new_pre_start()
204 val = inb(SM_DATAIO); supermicro_new_pre_start()
219 val = inb(SM_DATAIO); supermicro_new_pre_stop()
H A Dsch311x_wdt.c37 #include <linux/io.h> /* For inb/outb/... */
100 return inb(sio_config_port + 1); sch311x_sio_inb()
153 t = inb(sch311x_wdt_data.runtime_reg + GP60); sch311x_wdt_start()
167 t = inb(sch311x_wdt_data.runtime_reg + GP60); sch311x_wdt_stop()
214 new_status = inb(sch311x_wdt_data.runtime_reg + WDT_CTRL); sch311x_wdt_get_status()
/linux-4.1.27/drivers/staging/olpc_dcon/
H A Dolpc_dcon_xo_1_5.c55 tmp = inb(VX855_GPI_STATUS_CHG); dcon_was_irq()
68 outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI); dcon_init_xo_1_5()
93 tmp = inb(0x3c5); set_i2c_line()
134 outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI); dcon_wiggle_xo_1_5()
147 /* i believe this is the same as "inb(0x44b) & 3" */ dcon_read_status_xo_1_5()
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Ddt2814.c71 status = inb(dev->iobase + DT2814_CSR); dt2814_ai_eoc()
94 hi = inb(dev->iobase + DT2814_DATA); dt2814_ai_insn_read()
95 lo = inb(dev->iobase + DT2814_DATA); dt2814_ai_insn_read()
209 hi = inb(dev->iobase + DT2814_DATA); dt2814_interrupt()
210 lo = inb(dev->iobase + DT2814_DATA); dt2814_interrupt()
222 if (inb(dev->iobase + DT2814_CSR) & DT2814_FINISH) dt2814_interrupt()
225 inb(dev->iobase + DT2814_DATA); dt2814_interrupt()
226 inb(dev->iobase + DT2814_DATA); dt2814_interrupt()
247 if (inb(dev->iobase + DT2814_CSR) & DT2814_ERR) { dt2814_attach()
251 i = inb(dev->iobase + DT2814_DATA); dt2814_attach()
252 i = inb(dev->iobase + DT2814_DATA); dt2814_attach()
H A Dssv_dnp.c72 val = inb(CSCDR) & 0x0f; dnp_dio_insn_bits()
77 val = inb(CSCDR); dnp_dio_insn_bits()
79 val |= (inb(CSCDR) << 8); dnp_dio_insn_bits()
81 val |= ((inb(CSCDR) & 0xf0) << 12); dnp_dio_insn_bits()
122 val = inb(CSCDR); dnp_dio_insn_config()
161 outb((inb(CSCDR) & 0xAA), CSCDR); dnp_attach()
173 outb((inb(CSCDR) & 0xAA), CSCDR); dnp_detach()
H A Daio_iiro_16.c59 val = inb(dev->iobase + AIO_IIRO_16_INPUT_0_7); aio_iiro_16_read_inputs()
60 val |= inb(dev->iobase + AIO_IIRO_16_INPUT_8_15) << 8; aio_iiro_16_read_inputs()
72 status = inb(dev->iobase + AIO_IIRO_16_STATUS); aio_iiro_16_cos()
88 inb(dev->iobase + AIO_IIRO_16_IRQ); aio_iiro_enable_irq()
211 s->state = inb(dev->iobase + AIO_IIRO_16_RELAY_0_7) | aio_iiro_16_attach()
212 (inb(dev->iobase + AIO_IIRO_16_RELAY_8_15) << 8); aio_iiro_16_attach()
H A Dke_counter.c82 inb(dev->iobase + KE_LATCH_REG(chan)); ke_counter_insn_read()
84 val = inb(dev->iobase + KE_LSB_REG(chan)); ke_counter_insn_read()
85 val |= (inb(dev->iobase + KE_MID_REG(chan)) << 8); ke_counter_insn_read()
86 val |= (inb(dev->iobase + KE_MSB_REG(chan)) << 16); ke_counter_insn_read()
87 val |= (inb(dev->iobase + KE_SIGN_REG(chan)) << 24); ke_counter_insn_read()
128 src = inb(dev->iobase + KE_OSC_SEL_REG); ke_counter_insn_config()
H A Ddt2817.c100 val = inb(iobase + 0); dt2817_dio_insn_bits()
101 val |= (inb(iobase + 1) << 8); dt2817_dio_insn_bits()
102 val |= (inb(iobase + 2) << 16); dt2817_dio_insn_bits()
103 val |= (inb(iobase + 3) << 24); dt2817_dio_insn_bits()
H A Ddas08.c196 status = inb(dev->iobase + DAS08_STATUS); das08_ai_eoc()
217 inb(dev->iobase + DAS08_LSB); das08_ai_rinsn()
218 inb(dev->iobase + DAS08_MSB); das08_ai_rinsn()
238 if (inb(dev->iobase + DAS08_MSB) & 0x80) das08_ai_rinsn()
248 msb = inb(dev->iobase + DAS08_MSB); das08_ai_rinsn()
249 lsb = inb(dev->iobase + DAS08_LSB); das08_ai_rinsn()
273 data[1] = DAS08_IP(inb(dev->iobase + DAS08_STATUS)); das08_di_rbits()
304 data[1] = inb(dev->iobase + DAS08JR_DIO); das08jr_di_rbits()
335 inb(dev->iobase + DAS08JR_DIO); das08_ao_set_data()
340 inb(dev->iobase + DAS08AO_AO_UPDATE); das08_ao_set_data()
H A Ddmm32at.c190 val = inb(dev->iobase + DMM32AT_AI_LSB_REG); dmm32at_ai_get_sample()
191 val |= (inb(dev->iobase + DMM32AT_AI_MSB_REG) << 8); dmm32at_ai_get_sample()
204 status = inb(dev->iobase + context); dmm32at_ai_status()
422 intstat = inb(dev->iobase + DMM32AT_INTCLK_REG); dmm32at_isr()
452 status = inb(dev->iobase + DMM32AT_AUX_DI_REG); dmm32at_ao_eoc()
481 inb(dev->iobase + DMM32AT_AO_MSB_REG); dmm32at_ao_insn_write()
499 return inb(dev->iobase + regbase + port); dmm32at_8255_io()
530 ailo = inb(dev->iobase + DMM32AT_AI_LO_CHAN_REG); dmm32at_reset()
531 aihi = inb(dev->iobase + DMM32AT_AI_HI_CHAN_REG); dmm32at_reset()
532 fifostat = inb(dev->iobase + DMM32AT_FIFO_STATUS_REG); dmm32at_reset()
533 aistat = inb(dev->iobase + DMM32AT_AI_STATUS_REG); dmm32at_reset()
534 intstat = inb(dev->iobase + DMM32AT_INTCLK_REG); dmm32at_reset()
535 airback = inb(dev->iobase + DMM32AT_AI_READBACK_REG); dmm32at_reset()
H A Dcomedi_parport.c89 data[1] = inb(dev->iobase + PARPORT_DATA_REG); parport_data_reg_insn_bits()
106 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); parport_data_reg_insn_config()
121 data[1] = inb(dev->iobase + PARPORT_STATUS_REG) >> 3; parport_status_reg_insn_bits()
134 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); parport_ctrl_reg_insn_bits()
198 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); parport_intr_cmd()
210 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); parport_intr_cancel()
223 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); parport_interrupt()
H A Dfl512.c76 val = inb(dev->iobase + FL512_AI_LSB_REG); fl512_ai_insn_read()
77 val |= (inb(dev->iobase + FL512_AI_MSB_REG) << 8); fl512_ai_insn_read()
101 inb(dev->iobase + FL512_AO_TRIG_REG(chan)); fl512_ao_insn_write()
H A Dpcmad.c70 status = inb(dev->iobase + PCMAD_STATUS); pcmad_ai_eoc()
94 val = inb(dev->iobase + PCMAD_LSB) | pcmad_ai_insn_read()
95 (inb(dev->iobase + PCMAD_MSB) << 8); pcmad_ai_insn_read()
H A Damplc_pc263.c92 s->state = inb(dev->iobase) | (inb(dev->iobase + 1) << 8); pc263_attach()
H A Ddt2811.c230 status = inb(dev->iobase + DT2811_ADCSR); dt2811_ai_eoc()
250 data[i] = inb(dev->iobase + DT2811_ADDATLO); dt2811_ai_insn()
251 data[i] |= inb(dev->iobase + DT2811_ADDATHI) << 8; dt2811_ai_insn()
282 data[1] = inb(dev->iobase + DT2811_DIO); dt2811_di_insn_bits()
335 i = inb(dev->iobase + DT2811_ADDATLO); dt2811_attach()
336 i = inb(dev->iobase + DT2811_ADDATHI); dt2811_attach()
H A Drti800.c149 status = inb(dev->iobase + RTI800_CSR); rti800_ai_eoc()
171 inb(dev->iobase + RTI800_ADCHI); rti800_ai_insn_read()
198 data[i] = inb(dev->iobase + RTI800_ADCLO); rti800_ai_insn_read()
199 data[i] |= (inb(dev->iobase + RTI800_ADCHI) & 0xf) << 8; rti800_ai_insn_read()
239 data[1] = inb(dev->iobase + RTI800_DI); rti800_di_insn_bits()
270 inb(dev->iobase + RTI800_ADCHI); rti800_attach()
H A Dunioxx5.c151 *data = inb(usp->usp_iobase + channel_offset); __unioxx5_digital_read()
184 control = inb(usp->usp_iobase); /* get control register byte */ __unioxx5_analog_read()
187 while (!((control = inb(usp->usp_iobase + 0)) & Rx4CA)) __unioxx5_analog_read()
259 /* while(!((inb(usp->usp_iobase + 0)) & TxBE)); */ __unioxx5_analog_write()
266 while (!((inb(usp->usp_iobase + 0)) & TxBE)) __unioxx5_analog_write()
399 while (!(inb(iobase + 0) & TxBE)) __unioxx5_subdev_init()
404 while (!(inb(iobase + 0) & Rx2CA)) { __unioxx5_subdev_init()
415 usp->usp_module_type[i] = inb(iobase + 6); __unioxx5_subdev_init()
451 id = inb(ba + 0xE); unioxx5_attach()
452 num = inb(ba + 0xF); unioxx5_attach()
H A Dcb_pcimdas.c172 status = inb(devpriv->BADR3 + PCIMDAS_STATUS_REG); cb_pcimdas_ai_eoc()
193 d = inb(devpriv->BADR3 + PCIMDAS_PACER_REG); cb_pcimdas_ai_insn_read()
254 val = inb(devpriv->BADR3 + PCIMDAS_DI_DO_REG); cb_pcimdas_di_insn_bits()
299 ctrl = inb(devpriv->BADR3 + PCIMDAS_USER_CNTR_REG); cb_pcimdas_counter_insn_config()
321 status = inb(devpriv->BADR3 + PCIMDAS_STATUS_REG); cb_pcimdas_pacer_clk()
337 status = inb(devpriv->BADR3 + PCIMDAS_STATUS_REG); cb_pcimdas_is_ai_se()
351 status = inb(devpriv->BADR3 + PCIMDAS_STATUS_REG); cb_pcimdas_is_ai_uni()
H A Dpcmmio.c227 val = inb(iobase + PCMMIO_PORT_REG(port + 0)); pcmmio_dio_read()
228 val |= (inb(iobase + PCMMIO_PORT_REG(port + 1)) << 8); pcmmio_dio_read()
229 val |= (inb(iobase + PCMMIO_PORT_REG(port + 2)) << 16); pcmmio_dio_read()
232 val = inb(iobase + PCMMIO_PAGE_REG(0)); pcmmio_dio_read()
233 val |= (inb(iobase + PCMMIO_PAGE_REG(1)) << 8); pcmmio_dio_read()
234 val |= (inb(iobase + PCMMIO_PAGE_REG(2)) << 16); pcmmio_dio_read()
376 int_pend = inb(dev->iobase + PCMMIO_INT_PENDING_REG) & 0x07; interrupt_pcmmio()
533 status = inb(dev->iobase + PCMMIO_AI_STATUS_REG); pcmmio_ai_eoc()
586 val = inb(iobase + PCMMIO_AI_LSB_REG); pcmmio_ai_insn_read()
587 val |= inb(iobase + PCMMIO_AI_MSB_REG) << 8; pcmmio_ai_insn_read()
596 val = inb(iobase + PCMMIO_AI_LSB_REG); pcmmio_ai_insn_read()
597 val |= inb(iobase + PCMMIO_AI_MSB_REG) << 8; pcmmio_ai_insn_read()
616 status = inb(dev->iobase + PCMMIO_AO_STATUS_REG); pcmmio_ao_eoc()
H A Dadq12b.c125 status = inb(dev->iobase + ADQ12B_STINR); adq12b_ai_eoc()
151 val = inb(dev->iobase + ADQ12B_ADLOW); /* trigger A/D */ adq12b_ai_insn_read()
158 val = inb(dev->iobase + ADQ12B_ADHIG) << 8; adq12b_ai_insn_read()
159 val |= inb(dev->iobase + ADQ12B_ADLOW); /* retriggers A/D */ adq12b_ai_insn_read()
172 data[1] = (inb(dev->iobase + ADQ12B_STINR) & ADQ12B_STINR_IN_MASK); adq12b_di_insn_bits()
H A Dmultiq3.c117 hi = inb(dev->iobase + MULTIQ3_AD_CS); multiq3_ai_insn_read()
118 lo = inb(dev->iobase + MULTIQ3_AD_CS); multiq3_ai_insn_read()
182 value = inb(dev->iobase + MULTIQ3_ENC_DATA); multiq3_encoder_insn_read()
183 value |= (inb(dev->iobase + MULTIQ3_ENC_DATA) << 8); multiq3_encoder_insn_read()
184 value |= (inb(dev->iobase + MULTIQ3_ENC_DATA) << 16); multiq3_encoder_insn_read()
H A Dpcmda12.c88 inb(ioreg); pcmda12_ao_insn_write()
107 inb(dev->iobase); pcmda12_ao_insn_read()
122 inb(dev->iobase); pcmda12_ao_reset()
H A Damplc_pci263.c79 s->state = inb(dev->iobase) | (inb(dev->iobase + 1) << 8); pci263_auto_attach()
H A Dpcl730.c242 val = inb(dev->iobase + reg); pcl730_get_bits()
244 val |= (inb(dev->iobase + reg + 1) << 8); pcl730_get_bits()
246 val |= (inb(dev->iobase + reg + 2) << 16); pcl730_get_bits()
248 val |= (inb(dev->iobase + reg + 3) << 24); pcl730_get_bits()
H A Dpcl711.c176 val = inb(dev->iobase + PCL711_AI_MSB_REG) << 8; pcl711_ai_get_sample()
177 val |= inb(dev->iobase + PCL711_AI_LSB_REG); pcl711_ai_get_sample()
250 status = inb(dev->iobase + PCL711_AI_MSB_REG); pcl711_ai_eoc()
397 val = inb(dev->iobase + PCL711_DI_LSB_REG); pcl711_di_insn_bits()
398 val |= (inb(dev->iobase + PCL711_DI_MSB_REG) << 8); pcl711_di_insn_bits()
H A Daio_aio12_8.c107 status = inb(dev->iobase + AIO12_8_STATUS_REG); aio_aio12_8_ai_eoc()
131 inb(dev->iobase + AIO12_8_STATUS_REG); aio_aio12_8_ai_read()
H A Ddt2815.c74 status = inb(dev->iobase + DT2815_STATUS); dt2815_ao_status()
192 status = inb(dev->iobase + DT2815_STATUS); dt2815_attach()
H A Dquatech_daqp_cs.c202 while (!((status = inb(dev->iobase + DAQP_STATUS)) daqp_interrupt()
212 data = inb(dev->iobase + DAQP_FIFO); daqp_interrupt()
213 data |= inb(dev->iobase + DAQP_FIFO) << 8; daqp_interrupt()
305 && (inb(dev->iobase + DAQP_STATUS) & DAQP_STATUS_EVENTS)) daqp_ai_insn_read()
326 data[i] = inb(dev->iobase + DAQP_FIFO); daqp_ai_insn_read()
327 data[i] |= inb(dev->iobase + DAQP_FIFO) << 8; daqp_ai_insn_read()
612 && (inb(dev->iobase + DAQP_STATUS) & DAQP_STATUS_EVENTS)) daqp_ai_cmd()
669 data[0] = inb(dev->iobase + DAQP_DIGITAL_IO); daqp_di_insn_bits()
/linux-4.1.27/drivers/platform/chrome/
H A Dcros_ec_lpc.c41 if (!(inb(EC_LPC_ADDR_HOST_CMD) & EC_LPC_STATUS_BUSY_MASK)) ec_response_timed_out()
97 msg->result = inb(EC_LPC_ADDR_HOST_DATA); cros_ec_cmd_xfer_lpc()
113 args.flags = inb(EC_LPC_ADDR_HOST_ARGS); cros_ec_cmd_xfer_lpc()
114 args.command_version = inb(EC_LPC_ADDR_HOST_ARGS + 1); cros_ec_cmd_xfer_lpc()
115 args.data_size = inb(EC_LPC_ADDR_HOST_ARGS + 2); cros_ec_cmd_xfer_lpc()
116 args.checksum = inb(EC_LPC_ADDR_HOST_ARGS + 3); cros_ec_cmd_xfer_lpc()
132 msg->indata[i] = inb(EC_LPC_ADDR_HOST_PARAM + i); cros_ec_cmd_xfer_lpc()
165 *s = inb(EC_LPC_ADDR_MEMMAP + i); cros_ec_lpc_readmem()
171 *s = inb(EC_LPC_ADDR_MEMMAP + i); cros_ec_lpc_readmem()
192 if ((inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID) != 'E') || cros_ec_lpc_probe()
193 (inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID + 1) != 'C')) { cros_ec_lpc_probe()
/linux-4.1.27/drivers/ide/
H A Ddtc2278.c56 inb(0x3f6); sub22()
58 inb(0x3f6); sub22()
60 inb(0x3f6); sub22()
61 if(inb(0xb4) == c) { sub22()
63 inb(0x3f6); sub22()
117 inb(0x3f6); dtc2278_probe()
119 inb(0x3f6); dtc2278_probe()
H A Dpdc202xx_old.c89 u8 sc1d = inb(high_16 + 0x1d); pdc202xx_test_irq()
128 u8 clock = inb(clock_reg); pdc_old_enable_66MHz_clock()
136 u8 clock = inb(clock_reg); pdc_old_disable_66MHz_clock()
156 u8 clock = inb(high_16 + 0x11); pdc202xx_dma_start()
177 clock = inb(high_16 + 0x11); pdc202xx_dma_end()
193 udma_speed_flag = inb(dmabase | 0x1f); init_chipset_pdc202xx()
194 primary_mode = inb(dmabase | 0x1a); init_chipset_pdc202xx()
195 secondary_mode = inb(dmabase | 0x1b); init_chipset_pdc202xx()
208 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN"); init_chipset_pdc202xx()
H A Dns87415.c46 tmp = inb(port); superio_ide_inb()
70 tf->error = inb(io_ports->feature_addr); superio_tf_read()
72 tf->nsect = inb(io_ports->nsect_addr); superio_tf_read()
74 tf->lbal = inb(io_ports->lbal_addr); superio_tf_read()
76 tf->lbam = inb(io_ports->lbam_addr); superio_tf_read()
78 tf->lbah = inb(io_ports->lbah_addr); superio_tf_read()
191 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); ns87415_dma_end()
195 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); ns87415_dma_end()
H A Dht6560b.c138 (void)inb(HT_CONFIG_PORT); ht6560b_dev_select()
139 (void)inb(HT_CONFIG_PORT); ht6560b_dev_select()
140 (void)inb(HT_CONFIG_PORT); ht6560b_dev_select()
141 (void)inb(HT_CONFIG_PORT); ht6560b_dev_select()
147 (void)inb(hwif->io_ports.status_addr); ht6560b_dev_select()
167 if ((orig_value = inb(HT_CONFIG_PORT)) == 0xff) try_to_init_ht6560b()
172 if (!( (~inb(HT_CONFIG_PORT)) & 0x3f )) { try_to_init_ht6560b()
178 if ((~inb(HT_CONFIG_PORT))& 0x3f) { try_to_init_ht6560b()
187 (void)inb(0x1f7); /* Status register */ try_to_init_ht6560b()
H A Dpdc202xx_new.c76 value = inb(hwif->dma_base + 3); get_indexed_reg()
216 cnt0 = inb(pri_dma_base + 0x03); read_counter()
218 cnt1 = inb(pri_dma_base + 0x03); read_counter()
220 cnt2 = inb(sec_dma_base + 0x03); read_counter()
222 cnt3 = inb(sec_dma_base + 0x03); read_counter()
256 scr1 = inb(dma_base + 0x03); detect_pll_input_clock()
268 scr1 = inb(dma_base + 0x03); detect_pll_input_clock()
355 pll_ctl0 = inb(sec_dma_base + 0x03); init_chipset_pdcnew()
357 pll_ctl1 = inb(sec_dma_base + 0x03); init_chipset_pdcnew()
414 pll_ctl0 = inb(sec_dma_base + 0x03); init_chipset_pdcnew()
416 pll_ctl1 = inb(sec_dma_base + 0x03); init_chipset_pdcnew()
H A Dide-io-std.c19 return (u8) inb(port); ide_inb()
55 return inb(hwif->io_ports.status_addr); ide_read_status()
64 return inb(hwif->io_ports.ctl_addr); ide_read_altstatus()
152 (void)inb(port); ata_vlb_sync()
153 (void)inb(port); ata_vlb_sync()
154 (void)inb(port); ata_vlb_sync()
H A Dali14xx.c93 return inb(dataPort); inReg()
158 regOff = inb(basePort); findPort()
161 if (inb(basePort) == regOn) { findPort()
192 t = inb(regPort) & 0x01; initRegisters()
H A Dsc1200.c46 chip_id = inb (0x903c); sc1200_get_pci_clock()
47 silicon_revision = inb (0x903d); sc1200_get_pci_clock()
177 dma_stat = inb(dma_base+2); /* get DMA status */ sc1200_dma_end()
184 outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */ sc1200_dma_end()
H A Dopti621.c59 ret = inb(reg_base + reg); read_reg()
100 (void)inb(reg_base + CNTRL_REG); opti621_set_pio_mode()
/linux-4.1.27/drivers/char/tpm/
H A Dtpm_nsc.c75 *data = inb(chip->vendor.base + NSC_STATUS); wait_for_stat()
83 *data = inb(chip->vendor.base + 1); wait_for_stat()
98 status = inb(chip->vendor.base + NSC_STATUS); nsc_wait_for_ready()
100 status = inb(chip->vendor.base + NSC_DATA); nsc_wait_for_ready()
108 status = inb(chip->vendor.base + NSC_STATUS); nsc_wait_for_ready()
110 status = inb(chip->vendor.base + NSC_DATA); nsc_wait_for_ready()
136 inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_NORMAL) { tpm_nsc_recv()
152 *p = inb(chip->vendor.base + NSC_DATA); tpm_nsc_recv()
160 if ((data = inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_EOC) { tpm_nsc_recv()
227 return inb(chip->vendor.base + NSC_STATUS); tpm_nsc_status()
/linux-4.1.27/drivers/ata/
H A Dpata_legacy.c280 inb(0x1F5); pdc20230_set_piomode()
281 outb(inb(0x1F2) | 0x80, 0x1F2); pdc20230_set_piomode()
282 inb(0x1F2); pdc20230_set_piomode()
283 inb(0x3F6); pdc20230_set_piomode()
284 inb(0x3F6); pdc20230_set_piomode()
285 inb(0x1F2); pdc20230_set_piomode()
286 inb(0x1F2); pdc20230_set_piomode()
288 while ((inb(0x1F2) & 0x80) && --tries); pdc20230_set_piomode()
292 outb(inb(0x1F4) & 0x07, 0x1F4); pdc20230_set_piomode()
294 rt = inb(0x1F3); pdc20230_set_piomode()
300 outb(inb(0x1F2) | 0x01, 0x1F2); pdc20230_set_piomode()
302 inb(0x1F5); pdc20230_set_piomode()
372 inb(0x3E6); ht6560a_set_piomode()
373 inb(0x3E6); ht6560a_set_piomode()
374 inb(0x3E6); ht6560a_set_piomode()
375 inb(0x3E6); ht6560a_set_piomode()
406 inb(0x3E6); ht6560b_set_piomode()
407 inb(0x3E6); ht6560b_set_piomode()
408 inb(0x3E6); ht6560b_set_piomode()
409 inb(0x3E6); ht6560b_set_piomode()
414 u8 rconf = inb(0x3E6); ht6560b_set_piomode()
447 r = inb(0x24); opti_syscfg()
780 val = inb(port + 0x02); winbond_readcfg()
893 outb(inb(0x1F2) | 0x80, 0x1F2); probe_chip_type()
894 inb(0x1F5); probe_chip_type()
895 inb(0x1F2); probe_chip_type()
896 inb(0x3F6); probe_chip_type()
897 inb(0x3F6); probe_chip_type()
898 inb(0x1F2); probe_chip_type()
899 inb(0x1F2); probe_chip_type()
901 if ((inb(0x1F2) & 0x80) == 0) { probe_chip_type()
906 inb(0x1F5); probe_chip_type()
911 inb(0x1F2); probe_chip_type()
912 inb(0x1F2); probe_chip_type()
913 if (inb(0x1F2) == 0x00) probe_chip_type()
1110 res = inb(port + 3); qdi65_identify_port()
1144 r = inb(port); probe_qdi_vlb()
1148 res = inb(port); probe_qdi_vlb()
1160 r = inb(port + 1); probe_qdi_vlb()
/linux-4.1.27/drivers/input/mouse/
H A Dinport.c94 input_report_rel(inport_dev, REL_X, inb(INPORT_DATA_PORT)); inport_interrupt()
97 input_report_rel(inport_dev, REL_Y, inb(INPORT_DATA_PORT)); inport_interrupt()
100 buttons = inb(INPORT_DATA_PORT); inport_interrupt()
140 a = inb(INPORT_SIGNATURE_PORT); inport_init()
141 b = inb(INPORT_SIGNATURE_PORT); inport_init()
142 c = inb(INPORT_SIGNATURE_PORT); inport_init()
H A Dlogibm.c83 dx = (inb(LOGIBM_DATA_PORT) & 0xf); logibm_interrupt()
85 dx |= (inb(LOGIBM_DATA_PORT) & 0xf) << 4; logibm_interrupt()
87 dy = (inb(LOGIBM_DATA_PORT) & 0xf); logibm_interrupt()
89 buttons = inb(LOGIBM_DATA_PORT); logibm_interrupt()
133 if (inb(LOGIBM_SIGNATURE_PORT) != LOGIBM_SIGNATURE_BYTE) { logibm_init()
/linux-4.1.27/sound/oss/
H A Dsb_common.c103 if ((inb(DSP_STATUS) & 0x80) == 0) sb_dsp_command()
119 if (inb(DSP_DATA_AVAIL) & 0x80) sb_dsp_get_byte()
120 return inb(DSP_READ); sb_dsp_get_byte()
190 status = inb(DSP_DATA_AVAIL); sb_intr()
193 status = inb(DSP_DATA_AVL16); sb_intr()
198 int src = inb(devc->pcibase+0x1A); pci_intr()
239 for (loopc = 0; loopc < 1000 && !(inb(DSP_DATA_AVAIL) & 0x80); loopc++); sb_dsp_reset()
241 if (inb(DSP_READ) != 0xAA) sb_dsp_reset()
263 if (inb(DSP_DATA_AVAIL) & 0x80) dsp_get_vers()
266 devc->major = inb(DSP_READ); dsp_get_vers()
269 devc->minor = inb(DSP_READ); dsp_get_vers()
470 inb(0x229); relocate_ess1688()
471 inb(0x229); relocate_ess1688()
472 inb(0x229); relocate_ess1688()
475 inb(0x22b); relocate_ess1688()
476 inb(0x229); relocate_ess1688()
477 inb(0x22b); relocate_ess1688()
478 inb(0x229); relocate_ess1688()
479 inb(0x229); relocate_ess1688()
480 inb(0x22b); relocate_ess1688()
481 inb(0x229); relocate_ess1688()
484 inb(devc->base); relocate_ess1688()
553 inb(devc->base + 0x09); sb_dsp_detect()
554 inb(devc->base + 0x09); sb_dsp_detect()
555 inb(devc->base + 0x09); sb_dsp_detect()
556 inb(devc->base + 0x0b); sb_dsp_detect()
557 inb(devc->base + 0x09); sb_dsp_detect()
558 inb(devc->base + 0x0b); sb_dsp_detect()
559 inb(devc->base + 0x09); sb_dsp_detect()
560 inb(devc->base + 0x09); sb_dsp_detect()
561 inb(devc->base + 0x0b); sb_dsp_detect()
562 inb(devc->base + 0x09); sb_dsp_detect()
563 inb(devc->base + 0x00); sb_dsp_detect()
604 inb(DSP_DATA_AVAIL); sb_dsp_detect()
954 val = inb(MIXER_DATA); sb_getmixer()
998 val = inb(base); /* Data */ smw_getmem()
1016 control = inb(mpu_base + 7); smw_midi_init()
H A Dad1848.c209 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */ ad_read()
215 x = inb(io_Indexed_Data(devc)); ad_read()
225 x = inb(io_Indexed_Data(devc)); ad_read()
235 while (timeout > 0 && inb(devc->base) == 0x80) /* Are we initializing */ ad_write()
267 while (timeout > 0 && inb(devc->base) == 0x80) wait_for_calibration()
269 if (inb(devc->base) & 0x80) wait_for_calibration()
311 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */ ad_enter_MCE()
315 prev = inb(io_Index_Addr(devc)); ad_enter_MCE()
328 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */ ad_leave_MCE()
334 prev = inb(io_Index_Addr(devc)); ad_leave_MCE()
1165 while (timeout < 100 && inb(devc->base) != 0x80) ad1848_prepare_for_output()
1168 while (timeout < 10000 && inb(devc->base) == 0x80) ad1848_prepare_for_output()
1239 while (timeout < 100 && inb(devc->base) != 0x80) ad1848_prepare_for_input()
1243 while (timeout < 10000 && inb(devc->base) == 0x80) ad1848_prepare_for_input()
1260 while (timeout < 100 && inb(devc->base) != 0x80) ad1848_prepare_for_input()
1264 while (timeout < 10000 && inb(devc->base) == 0x80) ad1848_prepare_for_input()
1277 while (timeout < 100 && inb(devc->base) != 0x80) ad1848_prepare_for_input()
1280 while (timeout < 10000 && inb(devc->base) == 0x80) ad1848_prepare_for_input()
1596 if (inb(devc->base) == 0xff) ad1848_detect()
1609 unsigned char x = inb(devc->base); ad1848_detect()
1617 if (inb(devc->base) == 0x80) /* Not ready. Let's wait */ ad1848_detect()
1620 if ((inb(devc->base) & 0x80) != 0x00) /* Not a AD1848 */ ad1848_detect()
1622 DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base))); ad1848_detect()
1824 xid = inb(io_Indexed_Data(devc)); ad1848_detect()
2210 status = inb(io_Status(devc)); adintr()
2228 c930_stat = inb(0xe0f); adintr()
2267 if (inb(io_Status(devc)) & 0x01 && cnt++ < 4) adintr()
2283 if ((tmp = inb(0xc44)) == 0xff) init_deskpro_m()
2311 if ((tmp = inb(0xc44)) == 0xff) init_deskpro()
2317 if (inb(0xc44) != 0x04) init_deskpro()
2357 printk("%02x ", inb(0xc44)); init_deskpro()
2359 printk("%02x\n", inb(0xc44)); init_deskpro()
2389 printk("%02x ", inb(0xc44)); init_deskpro()
2391 printk("%02x\n", inb(0xc44)); init_deskpro()
2408 printk("%02x ", inb(0xc45)); init_deskpro()
2410 printk("%02x\n", inb(0xc45)); init_deskpro()
2422 printk("%02x ", inb(0xc45)); init_deskpro()
2424 printk("%02x\n", inb(0xc45)); init_deskpro()
2439 printk("%02x ", inb(0xc46)); init_deskpro()
2441 printk("%02x\n", inb(0xc46)); init_deskpro()
2453 printk("%02x ", inb(0xc46)); init_deskpro()
2455 printk("%02x\n", inb(0xc46)); init_deskpro()
2469 printk("%02x ", inb(0xc47)); init_deskpro()
2471 printk("%02x\n", inb(0xc47)); init_deskpro()
2483 printk("%02x ", inb(0xc47)); init_deskpro()
2485 printk("%02x\n", inb(0xc47)); init_deskpro()
2493 printk("Port 0xc6f (before) = %02x\n", inb(0xc6f)); init_deskpro()
2499 printk("Port 0xc6f (after) = %02x\n", inb(0xc6f)); init_deskpro()
2535 if ((tmp = inb(hw_config->io_base + 3)) == 0xff) /* Bus float */ probe_ms_sound()
2551 MDB(printk(KERN_ERR "No MSS signature detected on port 0x%x (0x%x)\n", hw_config->io_base, (int) inb(hw_config->io_base + 3))); probe_ms_sound()
2578 if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80) probe_ms_sound()
2583 if (hw_config->irq > 7 && hw_config->irq != 9 && inb(hw_config->io_base + 3) & 0x80) probe_ms_sound()
2633 if ((inb(version_port) & 0x40) == 0) attach_ms_sound()
H A Dwaveartist.c165 clear = ~clear & inb(ctlr_port); waveartist_set_ctlr()
178 old_ctlr = inb(ctlr_port) & ~IRQ_ACK; waveartist_iack()
205 if (inb(hw->io_base + STATR) & CMD_RF) { waveartist_reset()
244 if (inb(io_base + STATR) & CMD_RF) { waveartist_cmd()
262 if (inb(io_base + STATR) & CMD_WE) waveartist_cmd()
275 if (inb(io_base + STATR) & CMD_RF) waveartist_cmd()
613 inb(devc->hw.io_base + CTLR)); waveartist_prepare_for_input()
615 inb(devc->hw.io_base + STATR)); waveartist_prepare_for_input()
617 inb(devc->hw.io_base + IRQSTAT)); waveartist_prepare_for_input()
663 printk("WA CTLR reg: 0x%02X.\n",inb(devc->hw.io_base + CTLR)); waveartist_prepare_for_output()
664 printk("WA STAT reg: 0x%02X.\n",inb(devc->hw.io_base + STATR)); waveartist_prepare_for_output()
665 printk("WA IRQS reg: 0x%02X.\n",inb(devc->hw.io_base + IRQSTAT)); waveartist_prepare_for_output()
708 if (inb(devc->hw.io_base + STATR) & IRQ_REQ) waveartist_halt_input()
733 if (inb(devc->hw.io_base + STATR) & IRQ_REQ) waveartist_halt_output()
855 irqstatus = inb(devc->hw.io_base + IRQSTAT); waveartist_intr()
856 status = inb(devc->hw.io_base + STATR); waveartist_intr()
1544 while (volume && (inb(0x201) & 0x01)) vnc_volume_slider()
1763 temp = inb(0x201); vnc_slider()
/linux-4.1.27/drivers/net/irda/
H A Dw83977af.h43 return inb(efio+1); w977_read_reg()
H A Dnsc-ircc.c33 * bank = inb(iobase+BSR);
239 reg = inb(cfg_base); nsc_ircc_init()
248 id = inb(cfg_base+1); nsc_ircc_init()
615 reg = inb(cfg_base+1); nsc_ircc_probe_108()
637 reg = inb(cfg_base+1); nsc_ircc_probe_108()
686 reg = inb(cfg_base+1); nsc_ircc_probe_108()
723 reg = inb(cfg_base+1); nsc_ircc_probe_338()
729 reg = inb(cfg_base+1); nsc_ircc_probe_338()
735 reg = (inb(cfg_base+1) & 0xfe) << 2; nsc_ircc_probe_338()
738 reg |= ((inb(cfg_base+1) & 0xfc) << 8); nsc_ircc_probe_338()
744 reg = inb(cfg_base+1); nsc_ircc_probe_338()
794 reg = inb(cfg_base+1); nsc_ircc_probe_338()
800 reg = inb(cfg_base+1); nsc_ircc_probe_338()
806 reg = inb(cfg_base+1); nsc_ircc_probe_338()
848 enabled = inb(cfg_base+1) & 0x01; nsc_ircc_init_39x()
890 reg1 = inb(cfg_base+1); nsc_ircc_probe_39x()
892 reg2 = inb(cfg_base+1); nsc_ircc_probe_39x()
896 irq = inb(cfg_base+1); nsc_ircc_probe_39x()
898 irqt = inb(cfg_base+1); nsc_ircc_probe_39x()
902 dma1 = inb(cfg_base+1); nsc_ircc_probe_39x()
904 dma2 = inb(cfg_base+1); nsc_ircc_probe_39x()
908 info->enabled = enabled = inb(cfg_base+1) & 0x01; nsc_ircc_probe_39x()
911 susp = 1 - ((inb(cfg_base+1) & 0x02) >> 1); nsc_ircc_probe_39x()
920 enabled = inb(cfg_base+1) & 0x01; nsc_ircc_probe_39x()
992 version = inb(iobase+MID); nsc_ircc_setup()
1050 bank = inb(iobase+BSR); nsc_ircc_read_dongle_id()
1062 dongle_id = inb(iobase+4) & 0x0f; nsc_ircc_read_dongle_id()
1089 bank = inb(iobase+BSR); nsc_ircc_init_dongle_interface()
1174 bank = inb(iobase+BSR); nsc_ircc_change_dongle_speed()
1272 bank = inb(iobase+BSR); nsc_ircc_change_speed()
1292 outb(inb(iobase+4) | 0x04, iobase+4); nsc_ircc_change_speed()
1411 bank = inb(iobase+BSR); nsc_ircc_hard_xmit_sir()
1484 bank = inb(iobase+BSR); nsc_ircc_hard_xmit_fir()
1574 bsr = inb(iobase+BSR); nsc_ircc_dma_xmit()
1578 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR); nsc_ircc_dma_xmit()
1594 outb(inb(iobase+MCR)|MCR_TX_DFR|MCR_DMA_EN|MCR_IR_PLS, iobase+MCR); nsc_ircc_dma_xmit()
1613 bank = inb(iobase+BSR); nsc_ircc_pio_write()
1655 bank = inb(iobase+BSR); nsc_ircc_dma_xmit_complete()
1659 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR); nsc_ircc_dma_xmit_complete()
1662 if (inb(iobase+ASCR) & ASCR_TXUR) { nsc_ircc_dma_xmit_complete()
1721 bsr = inb(iobase+BSR); nsc_ircc_dma_receive()
1725 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR); nsc_ircc_dma_receive()
1746 outb(inb(iobase+MCR)|MCR_DMA_EN, iobase+MCR); nsc_ircc_dma_receive()
1772 bank = inb(iobase+BSR); nsc_ircc_dma_receive_complete()
1776 while ((status = inb(iobase+FRM_ST)) & FRM_ST_VLD) { nsc_ircc_dma_receive_complete()
1778 len = inb(iobase+RFLFL) | ((inb(iobase+RFLFH) & 0x1f) << 8); nsc_ircc_dma_receive_complete()
1836 if (inb(iobase+LSR) & LSR_RXDA) { nsc_ircc_dma_receive_complete()
1927 byte = inb(iobase+RXD); nsc_ircc_pio_receive()
1930 } while (inb(iobase+LSR) & LSR_RXDA); /* Data available */ nsc_ircc_pio_receive()
2009 bank = inb(iobase+BSR); nsc_ircc_fir_interrupt()
2097 bsr = inb(iobase+BSR); /* Save current bank */ nsc_ircc_interrupt()
2100 self->ier = inb(iobase+IER); nsc_ircc_interrupt()
2101 eir = inb(iobase+EIR) & self->ier; /* Mask out the interesting ones */ nsc_ircc_interrupt()
2141 bank = inb(iobase+BSR); nsc_ircc_is_receiving()
2143 if ((inb(iobase+RXFLV) & 0x3f) != 0) { nsc_ircc_is_receiving()
2194 bank = inb(iobase+BSR); nsc_ircc_net_open()
2249 bank = inb(iobase+BSR); nsc_ircc_net_close()
2329 bank = inb(iobase+BSR); nsc_ircc_suspend()
H A Dw83977af_ir.c34 * bank = inb( iobase+BSR);
344 outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1); w83977af_probe()
352 version = inb(iobase+AUID); w83977af_probe()
411 set = inb(iobase+SSR); w83977af_change_speed()
511 set = inb(iobase+SSR); w83977af_hard_xmit()
557 set = inb(iobase+SSR); w83977af_dma_write()
561 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); w83977af_dma_write()
572 outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR); w83977af_dma_write()
590 set = inb(iobase+SSR); w83977af_pio_write()
635 set = inb(iobase+SSR); w83977af_dma_xmit_complete()
639 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); w83977af_dma_xmit_complete()
642 if (inb(iobase+AUDR) & AUDR_UNDR) { w83977af_dma_xmit_complete()
689 set = inb(iobase+SSR); w83977af_dma_receive()
693 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); w83977af_dma_receive()
697 outb((inb(iobase+ADCR1) & ~ADCR1_D_CHSW)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL, w83977af_dma_receive()
727 hcr = inb(iobase+HCR); w83977af_dma_receive()
732 outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR); w83977af_dma_receive()
762 set = inb(iobase+SSR); w83977af_dma_receive_complete()
768 while ((status = inb(iobase+FS_FO)) & FS_FO_FSFDR) { w83977af_dma_receive_complete()
771 st_fifo->entries[st_fifo->tail].len = inb(iobase+RFLFL); w83977af_dma_receive_complete()
772 st_fifo->entries[st_fifo->tail].len |= inb(iobase+RFLFH) << 8; w83977af_dma_receive_complete()
815 if (inb(iobase+USR) & USR_RDR) { w83977af_dma_receive_complete()
878 byte = inb(iobase+RBR); w83977af_pio_receive()
881 } while (inb(iobase+USR) & USR_RDR); /* Data available */ w83977af_pio_receive()
917 set = inb(iobase+SSR); w83977af_sir_interrupt()
966 set = inb(iobase+SSR); w83977af_fir_interrupt()
1050 set = inb(iobase+SSR); w83977af_interrupt()
1053 icr = inb(iobase+ICR); w83977af_interrupt()
1054 isr = inb(iobase+ISR) & icr; /* Mask out the interesting ones */ w83977af_interrupt()
1089 set = inb(iobase+SSR); w83977af_is_receiving()
1091 if ((inb(iobase+RXFDTH) & 0x3f) != 0) { w83977af_is_receiving()
1137 set = inb(iobase+SSR); w83977af_net_open()
1196 set = inb(iobase+SSR); w83977af_net_close()
H A Dsmsc-ircc2.c362 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)), register_bank()
659 high = inb(fir_base + IRCC_ID_HIGH); smsc_ircc_present()
660 low = inb(fir_base + IRCC_ID_LOW); smsc_ircc_present()
661 chip = inb(fir_base + IRCC_CHIP_ID); smsc_ircc_present()
662 version = inb(fir_base + IRCC_VERSION); smsc_ircc_present()
663 config = inb(fir_base + IRCC_INTERFACE); smsc_ircc_present()
699 config = inb(fir_base + IRCC_INTERFACE); smsc_ircc_setup_io()
762 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A), smsc_ircc_init_chip()
766 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), smsc_ircc_init_chip()
769 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), smsc_ircc_init_chip()
772 (void) inb(iobase + IRCC_FIFO_THRESHOLD); smsc_ircc_init_chip()
776 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL); smsc_ircc_init_chip()
981 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A); smsc_ircc_set_fir_speed()
985 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA); smsc_ircc_set_fir_speed()
988 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL); smsc_ircc_set_fir_speed()
1013 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A); smsc_ircc_fir_start()
1022 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), smsc_ircc_fir_start()
1025 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), smsc_ircc_fir_start()
1028 (void) inb(fir_base + IRCC_FIFO_THRESHOLD); smsc_ircc_fir_start()
1054 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B); smsc_ircc_fir_stop()
1265 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, smsc_ircc_dma_xmit()
1273 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0; smsc_ircc_dma_xmit()
1284 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | smsc_ircc_dma_xmit()
1319 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, smsc_ircc_dma_xmit_complete()
1324 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) { smsc_ircc_dma_xmit_complete()
1359 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, smsc_ircc_dma_receive()
1369 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, smsc_ircc_dma_receive()
1386 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | smsc_ircc_dma_receive()
1423 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR); smsc_ircc_dma_receive_complete()
1424 lsr= inb(iobase + IRCC_LSR); smsc_ircc_dma_receive_complete()
1425 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08; smsc_ircc_dma_receive_complete()
1493 inb(iobase + UART_RX)); smsc_ircc_sir_receive()
1500 } while (inb(iobase + UART_LSR) & UART_LSR_DR); smsc_ircc_sir_receive()
1529 iir = inb(iobase + IRCC_IIR); smsc_ircc_interrupt()
1536 lcra = inb(iobase + IRCC_LCR_A); smsc_ircc_interrupt()
1537 lsr = inb(iobase + IRCC_LSR); smsc_ircc_interrupt()
1582 iir = inb(iobase + UART_IIR) & UART_IIR_ID; smsc_ircc_interrupt_sir()
1587 lsr = inb(iobase + UART_LSR); smsc_ircc_interrupt_sir()
1615 iir = inb(iobase + UART_IIR) & UART_IIR_ID; smsc_ircc_interrupt_sir()
1919 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA); smsc_ircc_sir_start()
2024 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) { smsc_ircc_sir_write()
2122 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT)) smsc_ircc_sir_wait_hw_transmitter_finish()
2193 mode = inb(cfgbase + 1); smsc_superio_flat()
2201 sirbase = inb(cfgbase + 1) << 2; smsc_superio_flat()
2205 firbase = inb(cfgbase + 1) << 3; smsc_superio_flat()
2209 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK; smsc_superio_flat()
2213 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; smsc_superio_flat()
2249 sir_io = inb(cfg_base + 1) << 8; smsc_superio_paged()
2251 sir_io |= inb(cfg_base + 1); smsc_superio_paged()
2255 fir_io = inb(cfg_base + 1) << 8; smsc_superio_paged()
2257 fir_io |= inb(cfg_base + 1); smsc_superio_paged()
2275 return inb(cfg_base) != reg ? -1 : 0; smsc_access()
2288 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */ smsc_ircc_probe()
2293 xdevid = inb(cfg_base + 1); smsc_ircc_probe()
2309 devid = inb(cfg_base + 1); smsc_ircc_probe()
2319 rev = inb(cfg_base + 1); smsc_ircc_probe()
2536 tmpbyte = inb(iobase +1); // Read device ID preconfigure_smsc_chip()
2545 tmpbyte = inb(iobase + 1); preconfigure_smsc_chip()
2554 tmpbyte = inb(iobase + 1); preconfigure_smsc_chip()
2558 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; preconfigure_smsc_chip()
2567 tmpbyte = inb(iobase + 1); preconfigure_smsc_chip()
2576 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK; preconfigure_smsc_chip()
2583 tmpbyte = inb(iobase + 1); preconfigure_smsc_chip()
2589 tmpbyte = inb(iobase + 1); preconfigure_smsc_chip()
2594 tmpbyte = inb(iobase + 1); preconfigure_smsc_chip()
2598 tmpbyte = inb(iobase + 1); preconfigure_smsc_chip()
2602 tmpbyte = inb(iobase + 1); preconfigure_smsc_chip()
2924 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE, smsc_ircc_set_transceiver_smsc_ircc_atc()
2927 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) && smsc_ircc_set_transceiver_smsc_ircc_atc()
2933 __func__, inb(fir_base + IRCC_ATC)); smsc_ircc_set_transceiver_smsc_ircc_atc()
2970 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select()
3009 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); smsc_ircc_set_transceiver_toshiba_sat1800()
H A Dali-ircc.c194 reg = inb(cfg_base+1); ali_ircc_init()
202 revision = inb(cfg_base+1); ali_ircc_init()
492 hi = inb(cfg_base+1); ali_ircc_probe_53()
494 low = inb(cfg_base+1); ali_ircc_probe_53()
503 reg = inb(cfg_base+1); ali_ircc_probe_53()
509 reg = inb(cfg_base+1); ali_ircc_probe_53()
520 reg = inb(cfg_base+1); ali_ircc_probe_53()
526 reg = inb(cfg_base+1); ali_ircc_probe_53()
564 version = inb(iobase+FIR_ID_VR); ali_ircc_setup()
583 outb(inb(iobase+FIR_IRDA_CR) | IRDA_CR_CRC, iobase+FIR_IRDA_CR); ali_ircc_setup()
590 tmp = inb(iobase+FIR_LCR_B); ali_ircc_setup()
637 reg = inb(cfg_base+1); ali_ircc_read_dongle_id()
691 self->InterruptID = inb(iobase+FIR_IIR); ali_ircc_fir_interrupt()
692 self->BusStatus = inb(iobase+FIR_BSR); ali_ircc_fir_interrupt()
695 self->LineStatus = inb(iobase+FIR_LSR); ali_ircc_fir_interrupt()
696 //self->ier = inb(iobase+FIR_IER); 2000/12/1 04:32PM ali_ircc_fir_interrupt()
771 tmp = inb(iobase+FIR_CR); ali_ircc_fir_interrupt()
816 iir = inb(iobase+UART_IIR) & UART_IIR_ID; ali_ircc_sir_interrupt()
819 lsr = inb(iobase+UART_LSR); ali_ircc_sir_interrupt()
874 inb(iobase+UART_RX)); ali_ircc_sir_receive()
881 } while (inb(iobase+UART_LSR) & UART_LSR_DR); ali_ircc_sir_receive()
916 while(!(inb(iobase+UART_LSR) & UART_LSR_TEMT)) ali_ircc_sir_write_wakeup()
1058 inb(iobase+UART_LSR); ali_ircc_sir_change_speed()
1059 inb(iobase+UART_SCR); ali_ircc_sir_change_speed()
1114 tmp = inb(iobase+FIR_IRDA_CR); ali_ircc_change_dongle_speed()
1289 if (!(inb(iobase+UART_LSR) & UART_LSR_THRE)) { ali_ircc_sir_write()
1510 outb(inb(iobase+FIR_CR) | CR_TIMER_EN, iobase+FIR_CR); ali_ircc_fir_hard_xmit()
1568 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR); ali_ircc_dma_xmit()
1603 tmp = inb(iobase+FIR_LCR_B); ali_ircc_dma_xmit()
1607 __func__, inb(iobase + FIR_LCR_B)); ali_ircc_dma_xmit()
1613 outb(inb(iobase+FIR_CR) | CR_DMA_EN | CR_DMA_BURST, iobase+FIR_CR); ali_ircc_dma_xmit()
1629 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR); ali_ircc_dma_xmit_complete()
1633 if((inb(iobase+FIR_LSR) & LSR_FRAME_ABORT) == LSR_FRAME_ABORT) ali_ircc_dma_xmit_complete()
1703 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR); ali_ircc_dma_receive()
1711 self->LineStatus = inb(iobase+FIR_LSR) ; ali_ircc_dma_receive()
1729 tmp = inb(iobase+FIR_LCR_B); ali_ircc_dma_receive()
1732 __func__, inb(iobase + FIR_LCR_B)); ali_ircc_dma_receive()
1758 MessageCount = inb(iobase+ FIR_LSR)&0x07; ali_ircc_dma_receive_complete()
1767 status = inb(iobase+FIR_LSR); ali_ircc_dma_receive_complete()
1770 len = inb(iobase+FIR_RX_DSR_HI) & 0x0f; ali_ircc_dma_receive_complete()
1772 len |= inb(iobase+FIR_RX_DSR_LO); ali_ircc_dma_receive_complete()
1848 val = inb(iobase+FIR_BSR); ali_ircc_dma_receive_complete()
1871 outb(inb(iobase+FIR_CR) | CR_TIMER_EN, iobase+FIR_CR); ali_ircc_dma_receive_complete()
2063 if((inb(iobase+FIR_FIFO_FR) & 0x3f) != 0) ali_ircc_is_receiving()
2183 //tmp = inb(iobase+FIR_LCR_B); /* SIP enable */ SIR2FIR()
2204 val = inb(iobase+UART_RX); FIR2SIR()
2205 val = inb(iobase+UART_LSR); FIR2SIR()
2206 val = inb(iobase+UART_MSR); FIR2SIR()
/linux-4.1.27/drivers/staging/xgifb/
H A Dvb_util.c13 return inb(port + 1); xgifb_reg_get()
/linux-4.1.27/arch/x86/boot/
H A Dearly_serial_console.c32 c = inb(port + LCR); early_serial_init()
102 lcr = inb(port + LCR); probe_baud()
104 dll = inb(port + DLL); probe_baud()
105 dlh = inb(port + DLH); probe_baud()
H A Da20.c30 status = inb(0x64); empty_8042()
39 (void)inb(0x60); empty_8042()
118 port_a = inb(0x92); /* Configuration port A */ enable_a20_fast()
H A Dvideo-vga.c136 return (inb(0x3cc) & 1) ? 0x3d4 : 0x3b4; vga_crtc()
153 csel = inb(0x3cc); vga_set_480_scanlines()
/linux-4.1.27/arch/mips/sgi-ip22/
H A Dip22-eisa.c59 sig[i] = inb(addr + i); decode_eisa_sig()
76 u8 eisa_irq = inb(EIU_INTRPT_ACK); ip22_eisa_intr()
78 inb(EISA_DMA1_STATUS); ip22_eisa_intr()
79 inb(EISA_DMA2_STATUS); ip22_eisa_intr()
/linux-4.1.27/drivers/parport/
H A Dparport_pc.c118 ectr = inb(ECONTROL(pb)); frob_econtrol()
152 oecr = inb(ECONTROL(p)); change_mode()
167 if (inb(ECONTROL(p)) & 0x01) change_mode()
175 while (!(inb(ECONTROL(p)) & 0x01)) { change_mode()
250 s->u.pc.ecr = inb(ECONTROL(p)); parport_pc_save_state()
278 status = inb(STATUS(port)); parport_pc_epp_read_data()
292 *((char *)buf) = inb(EPPDATA(port)); parport_pc_epp_read_data()
297 status = inb(STATUS(port)); parport_pc_epp_read_data()
312 if (inb(STATUS(port)) & 0x01) { parport_pc_epp_read_data()
319 *((char *)buf) = inb(EPPDATA(port)); parport_pc_epp_read_data()
321 if (inb(STATUS(port)) & 0x01) { parport_pc_epp_read_data()
341 if (inb(STATUS(port)) & 0x01) { parport_pc_epp_write_data()
350 if (inb(STATUS(port)) & 0x01) { parport_pc_epp_write_data()
366 if (inb(STATUS(port)) & 0x01) { parport_pc_epp_read_addr()
373 *((char *)buf) = inb(EPPADDR(port)); parport_pc_epp_read_addr()
375 if (inb(STATUS(port)) & 0x01) { parport_pc_epp_read_addr()
392 if (inb(STATUS(port)) & 0x01) { parport_pc_epp_write_addr()
401 if (inb(STATUS(port)) & 0x01) { parport_pc_epp_write_addr()
494 unsigned char ecrval = inb(ECONTROL(port)); parport_pc_fifo_write_block_pio()
522 ecrval = inb(ECONTROL(port)); parport_pc_fifo_write_block_pio()
554 ecrval = inb(ECONTROL(port)); parport_pc_fifo_write_block_pio()
652 if (!(inb(ECONTROL(port)) & (1<<2))) { parport_pc_fifo_write_block_dma()
757 if (inb(ECONTROL(port)) & 0x2) { parport_pc_compat_write_block_pio()
853 if (inb(ECONTROL(port)) & 0x2) { parport_pc_ecp_write_block_pio()
970 cr1 = inb(io + 1); show_parconfig_smsc37c669()
972 cr4 = inb(io + 1); show_parconfig_smsc37c669()
974 cra = inb(io + 1); show_parconfig_smsc37c669()
976 cr23 = inb(io + 1); show_parconfig_smsc37c669()
978 cr26 = inb(io + 1); show_parconfig_smsc37c669()
980 cr27 = inb(io + 1); show_parconfig_smsc37c669()
1066 cr30 = inb(io + 1); show_parconfig_winbond()
1068 cr60 = inb(io + 1); show_parconfig_winbond()
1070 cr61 = inb(io + 1); show_parconfig_winbond()
1072 cr70 = inb(io + 1); show_parconfig_winbond()
1074 cr74 = inb(io + 1); show_parconfig_winbond()
1076 crf0 = inb(io + 1); show_parconfig_winbond()
1202 origval = inb(io); /* Save original value */ winbond_check()
1206 x_devid = inb(io + 1); winbond_check()
1208 x_devrev = inb(io + 1); winbond_check()
1210 x_oldid = inb(io + 1); winbond_check()
1216 devid = inb(io + 1); /* Read EFDR, extended function data register */ winbond_check()
1218 devrev = inb(io + 1); winbond_check()
1220 oldid = inb(io + 1); winbond_check()
1240 origval[0] = inb(io); /* Save original values */ winbond_check2()
1241 origval[1] = inb(io + 1); winbond_check2()
1242 origval[2] = inb(io + 2); winbond_check2()
1246 x_devid = inb(io + 2); winbond_check2()
1248 x_devrev = inb(io + 2); winbond_check2()
1250 x_oldid = inb(io + 2); winbond_check2()
1255 devid = inb(io + 2); /* Read EFDR, extended function data register */ winbond_check2()
1257 devrev = inb(io + 2); winbond_check2()
1259 oldid = inb(io + 2); winbond_check2()
1281 origval = inb(io); /* Save original value */ smsc_check()
1285 x_oldid = inb(io + 1); smsc_check()
1287 x_oldrev = inb(io + 1); smsc_check()
1289 x_id = inb(io + 1); smsc_check()
1291 x_rev = inb(io + 1); smsc_check()
1297 oldid = inb(io + 1); /* Read EFDR, extended function data register */ smsc_check()
1299 oldrev = inb(io + 1); smsc_check()
1301 id = inb(io + 1); smsc_check()
1303 rev = inb(io + 1); smsc_check()
1349 origval = inb(0x2e); /* Save original value */ detect_and_report_it87()
1355 dev = inb(0x2f) << 8; detect_and_report_it87()
1357 dev |= inb(0x2f); detect_and_report_it87()
1364 r = inb(0x2f); detect_and_report_it87()
1434 r = inb(CONTROL(pb)); parport_SPP_supported()
1438 r = inb(CONTROL(pb)); parport_SPP_supported()
1500 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) { parport_ECR_present()
1503 r = inb(CONTROL(pb)); parport_ECR_present()
1504 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2)) parport_ECR_present()
1508 if ((inb(ECONTROL(pb)) & 0x3) != 0x1) parport_ECR_present()
1512 if (inb(ECONTROL(pb)) != 0x35) parport_ECR_present()
1593 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++) parport_ECP_supported()
1613 inb(FIFO(pb)); parport_ECP_supported()
1615 if (inb(ECONTROL(pb)) & (1<<2)) parport_ECP_supported()
1638 if (inb(ECONTROL(pb)) & (1<<2)) parport_ECP_supported()
1654 config = inb(CONFIGA(pb)); parport_ECP_supported()
1683 configb = inb(CONFIGB(pb)); parport_ECP_supported()
1713 unsigned char ecr = inb(ECONTROL(pb)); intel_bug_present_check_epp()
1754 oecr = inb(ECONTROL(pb)); parport_ECPPS2_supported()
1806 oecr = inb(ECONTROL(pb)); parport_ECPEPP_supported()
1858 unsigned char oecr = inb(ECONTROL(pb)); programmable_irq_support()
1865 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07; programmable_irq_support()
1884 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++) irq_probe_ECP()
1909 oecr = inb(ECONTROL(pb)); irq_probe_EPP()
1988 unsigned char oecr = inb(ECONTROL(p)); programmable_dma_support()
1993 dma = inb(CONFIGB(p)) & 0x07; programmable_dma_support()
2325 test = inb(inta_addr[i]); sio_ite_8872_probe()
2336 type = inb(inta_addr[i] + 0x18); sio_ite_8872_probe()
2487 tmp = inb(VIA_CONFIG_DATA); sio_via_probe()
2490 tmp2 = inb(VIA_CONFIG_DATA); sio_via_probe()
2507 port1 = inb(VIA_CONFIG_DATA) << 2; sio_via_probe()
/linux-4.1.27/drivers/media/rc/
H A Dite-cir.c564 iflags = inb(dev->cir_addr + IT87_IIR) & IT87_II; it87_get_irq_causes()
592 val = inb(dev->cir_addr + IT87_RCR) it87_set_carrier_params()
619 fifo = inb(dev->cir_addr + IT87_RSR) & IT87_RXFBC; it87_get_rx_bytes()
622 *(buf++) = inb(dev->cir_addr + IT87_DR); it87_get_rx_bytes()
638 return inb(dev->cir_addr + IT87_TSR) & IT87_TXFBC; it87_get_tx_used_slots()
654 outb(inb(dev->cir_addr + IT87_RCR) | IT87_RXACT, it87_idle_rx()
658 outb(inb(dev->cir_addr + IT87_TCR1) | IT87_FIFOCLR, it87_idle_rx()
668 outb(inb(dev->cir_addr + IT87_IER) & ~(IT87_RDAIE | IT87_RFOIE), it87_disable_rx()
672 outb(inb(dev->cir_addr + IT87_RCR) & ~IT87_RXEN, it87_disable_rx()
686 outb(inb(dev->cir_addr + IT87_RCR) | IT87_RXEN, it87_enable_rx()
693 outb(inb(dev->cir_addr + IT87_IER) | IT87_RDAIE | IT87_RFOIE | IT87_IEC, it87_enable_rx()
704 outb(inb(dev->cir_addr + IT87_IER) & ~IT87_TLDLIE, it87_disable_tx_interrupt()
715 outb(inb(dev->cir_addr + IT87_IER) | IT87_TLDLIE | IT87_IEC, it87_enable_tx_interrupt()
725 outb(inb(dev->cir_addr + IT87_IER) & it87_disable()
733 outb(IT87_FIFOCLR | inb(dev->cir_addr + IT87_TCR1), it87_disable()
744 outb((inb(dev->cir_addr + IT87_IER) & it87_init_hardware()
753 outb(inb(dev->cir_addr + IT87_IER) & ~IT87_BR, it87_init_hardware()
781 iflags = inb(dev->cir_addr + IT8708_C0IIR); it8708_get_irq_causes()
804 outb(inb(dev->cir_addr + IT8708_BANKSEL) | IT8708_HRAE, it8708_set_carrier_params()
807 val = (inb(dev->cir_addr + IT8708_C0CFR) it8708_set_carrier_params()
815 outb(inb(dev->cir_addr + IT8708_BANKSEL) & ~IT8708_HRAE, it8708_set_carrier_params()
819 val = inb(dev->cir_addr + IT8708_C0RCR) it8708_set_carrier_params()
830 val = inb(dev->cir_addr + IT8708_C0TCR) & ~IT85_TXMPW; it8708_set_carrier_params()
844 fifo = inb(dev->cir_addr + IT8708_C0RFSR) & IT85_RXFBC; it8708_get_rx_bytes()
847 *(buf++) = inb(dev->cir_addr + IT8708_C0DR); it8708_get_rx_bytes()
863 return inb(dev->cir_addr + IT8708_C0TFSR) & IT85_TXFBC; it8708_get_tx_used_slots()
879 outb(inb(dev->cir_addr + IT8708_C0RCR) | IT85_RXACT, it8708_idle_rx()
883 outb(inb(dev->cir_addr + IT8708_C0MSTCR) | IT85_FIFOCLR, it8708_idle_rx()
893 outb(inb(dev->cir_addr + IT8708_C0IER) & it8708_disable_rx()
898 outb(inb(dev->cir_addr + IT8708_C0RCR) & ~IT85_RXEN, it8708_disable_rx()
912 outb(inb(dev->cir_addr + IT8708_C0RCR) | IT85_RXEN, it8708_enable_rx()
919 outb(inb(dev->cir_addr + IT8708_C0IER) it8708_enable_rx()
931 outb(inb(dev->cir_addr + IT8708_C0IER) & ~IT85_TLDLIE, it8708_disable_tx_interrupt()
942 outb(inb(dev->cir_addr + IT8708_C0IER) it8708_enable_tx_interrupt()
953 outb(inb(dev->cir_addr + IT8708_C0IER) & it8708_disable()
961 outb(IT85_FIFOCLR | inb(dev->cir_addr + IT8708_C0MSTCR), it8708_disable()
971 outb(inb(dev->cir_addr + IT8708_C0IER) & it8708_init_hardware()
976 outb(inb(dev->cir_addr + IT8708_BANKSEL) | IT8708_HRAE, it8708_init_hardware()
983 outb(inb(dev->cir_addr + IT8708_BANKSEL) & ~IT8708_HRAE, it8708_init_hardware()
987 outb((inb(dev->cir_addr + IT8708_C0MSTCR) & it8708_init_hardware()
994 outb((inb(dev->cir_addr + IT8708_C0RCR) & it8708_init_hardware()
1001 outb((inb(dev->cir_addr + IT8708_C0TCR) & it8708_init_hardware()
1017 return inb(dev->cir_addr + IT8709_RAM_VAL); it8709_rm()
/linux-4.1.27/drivers/net/ethernet/8390/
H A Dwd.c177 checksum += inb(ioaddr + 8 + i); wd_probe1()
178 if (inb(ioaddr + 8) == 0xff /* Extra check to avoid soundcard. */ wd_probe1()
179 || inb(ioaddr + 9) == 0xff wd_probe1()
195 dev->dev_addr[i] = inb(ioaddr + 8 + i); wd_probe1()
204 if (inb(ioaddr+0) == 'P' && inb(ioaddr+1) == 'D') { wd_probe1()
205 unsigned char reg5 = inb(ioaddr+5); wd_probe1()
207 switch (inb(ioaddr+2)) { wd_probe1()
224 if (inb(ioaddr+i) != inb(ioaddr+8+i)) wd_probe1()
231 int tmp = inb(ioaddr+1); /* fiddle with 16bit bit */ wd_probe1()
233 if (((inb( ioaddr+1) & 0x01) == 0x01) /* A 16 bit card */ wd_probe1()
235 int asic_reg5 = inb(ioaddr+WD_CMDREG5); wd_probe1()
248 if ( !ancient && (inb(ioaddr+1) & 0x01) != (word16 & 0x01)) wd_probe1()
251 (inb(ioaddr+1) & 0x01) ? 16 : 8); wd_probe1()
261 int reg0 = inb(ioaddr); wd_probe1()
267 int high_addr_bits = inb(ioaddr+WD_CMDREG5) & 0x1f; wd_probe1()
281 int reg1 = inb(ioaddr+1); wd_probe1()
282 int reg4 = inb(ioaddr+4); wd_probe1()
359 if (inb(ioaddr+14) & 0x20) wd_probe1()
360 outb(inb(ioaddr+4)|0x80, ioaddr+4); wd_probe1()
H A Dapne.c224 outb(inb(ioaddr + NE_RESET), ioaddr + NE_RESET); apne_probe1()
226 while ((inb(ioaddr + NE_EN0_ISR) & ENISR_RESET) == 0) apne_probe1()
263 SA_prom[i] = inb(ioaddr + NE_DATAPORT); apne_probe1()
264 SA_prom[i+1] = inb(ioaddr + NE_DATAPORT); apne_probe1()
369 outb(inb(NE_BASE + NE_RESET), NE_BASE + NE_RESET); apne_reset_8390()
375 while ((inb(NE_BASE+NE_EN0_ISR) & ENISR_RESET) == 0) apne_reset_8390()
420 *ptrc++ = inb(NE_BASE + NE_DATAPORT); apne_get_8390_hdr()
463 buf[count-1] = inb(NE_BASE + NE_DATAPORT); apne_block_input()
468 *ptrc++ = inb(NE_BASE + NE_DATAPORT); apne_block_input()
523 while ((inb(NE_BASE + NE_EN0_ISR) & ENISR_RDC) == 0) apne_block_output()
H A Dne2k-pci.c258 reg0 = inb(ioaddr); ne2k_pci_init_one()
266 regd = inb(ioaddr + 0x0d); ne2k_pci_init_one()
269 inb(ioaddr + EN0_COUNTER0); /* Clear the counter by reading. */ ne2k_pci_init_one()
270 if (inb(ioaddr + EN0_COUNTER0) != 0) { ne2k_pci_init_one()
293 outb(inb(ioaddr + NE_RESET), ioaddr + NE_RESET); ne2k_pci_init_one()
298 while ((inb(ioaddr + EN0_ISR) & ENISR_RESET) == 0) ne2k_pci_init_one()
341 SA_prom[i] = inb(ioaddr + NE_DATAPORT); ne2k_pci_init_one()
419 outb(inb(ioaddr + 0x20) | 0x80, ioaddr + 0x20); set_holtek_fdx()
463 outb(inb(NE_BASE + NE_RESET), NE_BASE + NE_RESET); ne2k_pci_reset_8390()
469 while ((inb(NE_BASE+EN0_ISR) & ENISR_RESET) == 0) ne2k_pci_reset_8390()
544 buf[count-1] = inb(NE_BASE + NE_DATAPORT); ne2k_pci_block_input()
557 *buf = inb(NE_BASE + NE_DATAPORT); ne2k_pci_block_input()
626 while ((inb(nic_base + EN0_ISR) & ENISR_RDC) == 0) ne2k_pci_block_output()
H A Dsmc-ultra.c213 unsigned char idreg = inb(ioaddr + 7); ultra_probe1()
214 unsigned char reg4 = inb(ioaddr + 4) & 0x7f; ultra_probe1()
231 checksum += inb(ioaddr + 8 + i); ultra_probe1()
243 dev->dev_addr[i] = inb(ioaddr + 8 + i); ultra_probe1()
253 outb(0x80 | inb(ioaddr + 0x0c), ioaddr + 0x0c); ultra_probe1()
254 piomode = inb(ioaddr + 0x8); ultra_probe1()
255 addr = inb(ioaddr + 0xb); ultra_probe1()
256 irqreg = inb(ioaddr + 0xd); ultra_probe1()
401 outb(inb(ioaddr + 4) | 0x80, ioaddr + 4); ultra_open()
402 outb((inb(ioaddr + 13) & ~0x4C) | irq2reg[dev->irq], ioaddr + 13); ultra_open()
403 outb(inb(ioaddr + 4) & 0x7f, ioaddr + 4); ultra_open()
H A D8390p.c6 #define ei_inb(_p) inb(_p)
/linux-4.1.27/drivers/media/radio/
H A Dradio-zoltrix.c95 inb(isa->io + 3); /* Zoltrix needs to be read to confirm */ zoltrix_s_mute_volume()
101 inb(isa->io + 2); zoltrix_s_mute_volume()
127 inb(isa->io + 3); /* Zoltrix needs to be read to confirm */ zoltrix_s_frequency()
156 inb(isa->io + 2); zoltrix_s_frequency()
172 a = inb(isa->io); zoltrix_g_rxsubchans()
174 b = inb(isa->io); zoltrix_g_rxsubchans()
189 a = inb(isa->io); zoltrix_g_signal()
191 b = inb(isa->io); zoltrix_g_signal()
H A Dradio-trust.c67 #define TR_DELAY do { inb(tr->isa.io); inb(tr->isa.io); inb(tr->isa.io); } while (0)
143 v |= inb(isa->io); trust_g_signal()
H A Dradio-cadet.c122 if ((inb(dev->io + 1) & 0x40) == 0) cadet_getstereo()
137 curvol = inb(dev->io + 1); /* Save current volume/mute setting */ cadet_gettune()
145 fifo = (fifo << 1) | ((inb(dev->io + 1) >> 7) & 0x01); cadet_gettune()
148 dev->tunestat &= inb(dev->io + 1); cadet_gettune()
248 curvol = inb(dev->io + 1); cadet_setfreq()
270 outb(inb(dev->io + 1) & 0x7f, dev->io + 1); cadet_setfreq()
291 if ((inb(dev->io + 1) & 0x20) != 0) cadet_handler()
295 while ((inb(dev->io) & 0x80) != 0) { cadet_handler()
296 dev->rdsbuf[dev->rdsin] = inb(dev->io + 1); cadet_handler()
385 outb(inb(dev->io + 1) & 0x7f, dev->io + 1); vidioc_g_tuner()
388 if (inb(dev->io + 1) & 0x80) vidioc_g_tuner()
H A Dradio-aztech.c99 if (inb(isa->io) & AZTECH_BIT_MONO) aztech_g_rxsubchans()
106 return (inb(isa->io) & AZTECH_BIT_NOT_TUNED) ? 0 : 0xffff; aztech_g_signal()
H A Dradio-sf16fmi.c114 res = (int)inb(fmi->io + 1); fmi_getsigstr()
297 ((inb(io) & 0xf9) == 0xf9 && (inb(io) & 0x4) == 0)) fmi_init()
307 if (inb(io) == 0xff) { fmi_init()
/linux-4.1.27/drivers/input/serio/
H A Di8042-io.h51 return inb(I8042_DATA_REG); i8042_read_data()
56 return inb(I8042_STATUS_REG); i8042_read_status()
H A Dpcips2.c52 stat = inb(ps2if->base + PS2_STATUS); pcips2_write()
70 status = inb(ps2if->base + PS2_STATUS); pcips2_interrupt()
74 scancode = inb(ps2if->base + PS2_DATA); pcips2_interrupt()
93 status = inb(ps2if->base + PS2_STATUS); pcips2_flush_input()
96 scancode = inb(ps2if->base + PS2_DATA); pcips2_flush_input()
/linux-4.1.27/arch/x86/platform/ts5500/
H A Dts5500.c128 sbc->id = inb(TS5500_PRODUCT_CODE_ADDR); ts5500_detect_config()
139 tmp = inb(TS5500_SRAM_RS485_ADC_ADDR); ts5500_detect_config()
144 tmp = inb(TS5500_ERESET_ITR_ADDR); ts5500_detect_config()
148 tmp = inb(TS5500_LED_JP_ADDR); ts5500_detect_config()
245 return (inb(TS5500_LED_JP_ADDR) & TS5500_LED) ? LED_FULL : LED_OFF; ts5500_led_get()
267 if (inb(TS5500_ADC_CONV_BUSY_ADDR) & TS5500_ADC_CONV_BUSY) ts5500_adc_convert()
271 lsb = inb(TS5500_ADC_CONV_INIT_LSB_ADDR); ts5500_adc_convert()
272 msb = inb(TS5500_ADC_CONV_MSB_ADDR); ts5500_adc_convert()
/linux-4.1.27/kernel/debug/kdb/
H A Dkdb_keyboard.c44 (inb(KBD_STATUS_REG) == 0xff && inb(KBD_DATA_REG) == 0xff)) { kdb_get_kbd_char()
50 if ((inb(KBD_STATUS_REG) & KBD_STAT_OBF) == 0) kdb_get_kbd_char()
56 scancode = inb(KBD_DATA_REG); kdb_get_kbd_char()
57 scanstatus = inb(KBD_STATUS_REG); kdb_get_kbd_char()
227 while ((inb(KBD_STATUS_REG) & KBD_STAT_OBF) == 0) kdb_kbd_cleanup_state()
233 scancode = inb(KBD_DATA_REG); kdb_kbd_cleanup_state()
234 scanstatus = inb(KBD_STATUS_REG); kdb_kbd_cleanup_state()
/linux-4.1.27/drivers/staging/speakup/
H A Dserialio.c76 if (inb(ser->port + UART_LSR) == 0xff) { spk_serial_init()
128 inb(speakup_info.port_tts+UART_LSR); start_serial_interrupt()
129 inb(speakup_info.port_tts+UART_RX); start_serial_interrupt()
130 inb(speakup_info.port_tts+UART_IIR); start_serial_interrupt()
131 inb(speakup_info.port_tts+UART_MSR); start_serial_interrupt()
H A Dserialio.h38 ((inb(speakup_info.port_tts + UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
/linux-4.1.27/drivers/tty/
H A Dmxser.c296 oldlcr = inb(baseio + UART_LCR); mxser_enable_must_enchance_mode()
299 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); mxser_enable_must_enchance_mode()
312 oldlcr = inb(baseio + UART_LCR); mxser_disable_must_enchance_mode()
315 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); mxser_disable_must_enchance_mode()
328 oldlcr = inb(baseio + UART_LCR); mxser_set_must_xon1_value()
331 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); mxser_set_must_xon1_value()
345 oldlcr = inb(baseio + UART_LCR); mxser_set_must_xoff1_value()
348 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); mxser_set_must_xoff1_value()
362 oldlcr = inb(info->ioaddr + UART_LCR); mxser_set_must_fifo_value()
365 efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER); mxser_set_must_fifo_value()
381 oldlcr = inb(baseio + UART_LCR); mxser_set_must_enum_value()
384 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); mxser_set_must_enum_value()
399 oldlcr = inb(baseio + UART_LCR); mxser_get_must_hardware_id()
402 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); mxser_get_must_hardware_id()
407 *pId = inb(baseio + MOXA_MUST_HWID_REGISTER); mxser_get_must_hardware_id()
417 oldlcr = inb(baseio + UART_LCR); SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL()
420 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL()
432 oldlcr = inb(baseio + UART_LCR); mxser_enable_must_tx_software_flow_control()
435 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); mxser_enable_must_tx_software_flow_control()
448 oldlcr = inb(baseio + UART_LCR); mxser_disable_must_tx_software_flow_control()
451 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); mxser_disable_must_tx_software_flow_control()
463 oldlcr = inb(baseio + UART_LCR); mxser_enable_must_rx_software_flow_control()
466 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); mxser_enable_must_rx_software_flow_control()
479 oldlcr = inb(baseio + UART_LCR); mxser_disable_must_rx_software_flow_control()
482 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); mxser_disable_must_rx_software_flow_control()
497 oldmcr = inb(io + UART_MCR); CheckIsMoxaMust()
500 if ((hwid = inb(io + UART_MCR)) != 0) { CheckIsMoxaMust()
539 status = inb(baseaddr + UART_MSR); mxser_get_msr()
553 return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0; mxser_carrier_raised()
563 outb(inb(mp->ioaddr + UART_MCR) | mxser_dtr_rts()
566 outb(inb(mp->ioaddr + UART_MCR)&~(UART_MCR_DTR | UART_MCR_RTS), mxser_dtr_rts()
608 cval = inb(info->ioaddr + UART_LCR); mxser_set_baud()
719 status = inb(info->ioaddr + UART_MSR); mxser_change_speed()
899 if (inb(info->ioaddr + UART_LSR) == 0xff) { mxser_activate()
911 (void) inb(info->ioaddr + UART_LSR); mxser_activate()
912 (void) inb(info->ioaddr + UART_RX); mxser_activate()
913 (void) inb(info->ioaddr + UART_IIR); mxser_activate()
914 (void) inb(info->ioaddr + UART_MSR); mxser_activate()
935 (void) inb(info->ioaddr + UART_LSR); mxser_activate()
936 (void) inb(info->ioaddr + UART_RX); mxser_activate()
937 (void) inb(info->ioaddr + UART_IIR); mxser_activate()
938 (void) inb(info->ioaddr + UART_MSR); mxser_activate()
989 (void) inb(info->ioaddr + UART_RX); mxser_shutdown_port()
1030 fcr = inb(info->ioaddr + UART_FCR); mxser_flush_buffer()
1062 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) { mxser_close_port()
1319 status = inb(info->ioaddr + UART_LSR); mxser_get_lsr_info()
1340 status = inb(info->ioaddr + UART_MSR); mxser_tiocmget()
1388 (void)inb(port); mxser_program_mode()
1389 (void)inb(port); mxser_program_mode()
1391 (void)inb(port); mxser_program_mode()
1393 id = inb(port + 1) & 0x1F; mxser_program_mode()
1402 n = inb(port + 2); mxser_program_mode()
1427 n = inb(port + 5); mxser_normal_mode()
1431 (void)inb(port); mxser_normal_mode()
1469 (void)inb(port); mxser_read_register()
1474 if (inb(port) & CHIP_DI) mxser_read_register()
1533 status = inb(ip->ioaddr + UART_MSR); mxser_ioctl_special()
1622 opmode = inb(ip->opmode_ioaddr)>>((p % 4) * 2); mxser_ioctl_special()
1698 val = inb(info->opmode_ioaddr); mxser_ioctl()
1706 opmode = inb(info->opmode_ioaddr) >> shiftbit; mxser_ioctl()
1759 lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_THRE; mxser_ioctl()
1772 mcr = inb(info->ioaddr + UART_MCR); mxser_ioctl()
2018 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) { mxser_wait_until_sent()
2052 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC, mxser_rs_break()
2055 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC, mxser_rs_break()
2083 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER); mxser_receive_chars()
2092 ch = inb(port->ioaddr + UART_RX); mxser_receive_chars()
2104 ch = inb(port->ioaddr + UART_RX); mxser_receive_chars()
2145 *status = inb(port->ioaddr + UART_LSR); mxser_receive_chars()
2238 irqbits = inb(brd->vector) & brd->vector_mask; mxser_interrupt()
2253 iir = inb(port->ioaddr + UART_IIR); mxser_interrupt()
2262 status = inb(port->ioaddr + UART_LSR); mxser_interrupt()
2264 inb(port->ioaddr + UART_MSR); mxser_interrupt()
2269 status = inb(port->ioaddr + UART_LSR); mxser_interrupt()
2295 msr = inb(port->ioaddr + UART_MSR); mxser_interrupt()
2418 outb(inb(info->ioaddr + UART_IER) & 0xf0, mxser_initbrd()
2525 scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB); mxser_get_ISA_conf()
2530 scratch = inb(cap + UART_IIR); mxser_get_ISA_conf()
/linux-4.1.27/drivers/net/appletalk/
H A Dcops.c380 inb(ioaddr+DAYNA_RESET); cops_irq()
385 inb(ioaddr); cops_irq()
397 status = (inb(ioaddr+DAYNA_CARD_STATUS)&3); cops_irq()
403 if((inb(ioaddr+TANG_CARD_STATUS)& TANG_TX_READY) !=0) cops_irq()
476 while(timeout++ < 5 && (inb(ioaddr+TANG_CARD_STATUS)&TANG_TX_READY)==0) tangent_wait_reset()
490 inb(ioaddr); /* Clear request latch. */ cops_reset()
500 inb(ioaddr+DAYNA_RESET); /* Clear the reset */ cops_reset()
562 if((inb(ioaddr+DAYNA_CARD_STATUS)&3)==1) cops_load()
588 inb(ioaddr); cops_load()
593 inb(ioaddr); /* Clear initial ready signal. */ cops_load()
611 while((inb(ioaddr+DAYNA_CARD_STATUS)&DAYNA_TX_READY)==0) cops_nodeid()
614 if((inb(ioaddr+DAYNA_CARD_STATUS)&0x03)==DAYNA_RX_REQUEST) cops_nodeid()
628 while(inb(ioaddr+TANG_CARD_STATUS)&TANG_RX_READY) cops_nodeid()
652 if((inb(ioaddr+DAYNA_CARD_STATUS)&0x03)==DAYNA_RX_REQUEST) cops_nodeid()
657 if(inb(ioaddr+TANG_CARD_STATUS)&TANG_RX_READY) cops_nodeid()
690 status=inb(ioaddr+TANG_CARD_STATUS); cops_poll()
695 status = inb(ioaddr+TANG_CARD_STATUS); cops_poll()
721 status=inb(ioaddr+DAYNA_CARD_STATUS); cops_interrupt()
730 status=inb(ioaddr+TANG_CARD_STATUS); cops_interrupt()
735 status=inb(ioaddr+TANG_CARD_STATUS); cops_interrupt()
768 if((inb(ioaddr+DAYNA_CARD_STATUS)&0x03)==DAYNA_RX_READY) cops_rx()
782 pkt_len = inb(ioaddr) & 0xFF; cops_rx()
784 pkt_len = inb(ioaddr) & 0x00FF; cops_rx()
785 pkt_len |= (inb(ioaddr) << 8); cops_rx()
787 rsp_type=inb(ioaddr); cops_rx()
797 inb(ioaddr); cops_rx()
859 if((inb(ioaddr+TANG_CARD_STATUS)&TANG_TX_READY)==0) cops_timeout()
888 while((inb(ioaddr+DAYNA_CARD_STATUS)&DAYNA_TX_READY)==0) cops_send_packet()
891 while((inb(ioaddr+TANG_CARD_STATUS)&TANG_TX_READY)==0) cops_send_packet()
905 while((inb(ioaddr+DAYNA_CARD_STATUS)&DAYNA_TX_READY)==0); cops_send_packet()
/linux-4.1.27/sound/isa/gus/
H A Dgus_io.c33 inb(GUSP(gus, DRAM)); snd_gf1_delay()
52 value = inb(gus->gf1.reg_data8); __snd_gf1_ctrl_stop()
75 return inb(gus->gf1.reg_data8); __snd_gf1_look8()
99 inb(gus->gf1.reg_timerctrl); __snd_gf1_adlib_write()
100 inb(gus->gf1.reg_timerctrl); __snd_gf1_adlib_write()
102 inb(gus->gf1.reg_timerctrl); __snd_gf1_adlib_write()
103 inb(gus->gf1.reg_timerctrl); __snd_gf1_adlib_write()
332 res = inb(gus->gf1.reg_dram); snd_gf1_peek()
508 printk(KERN_INFO " -S- mix control = 0x%x\n", inb(GUSP(gus, MIXCNTRLREG)));
509 printk(KERN_INFO " -S- IRQ status = 0x%x\n", inb(GUSP(gus, IRQSTAT)));
510 printk(KERN_INFO " -S- timer control = 0x%x\n", inb(GUSP(gus, TIMERCNTRL)));
511 printk(KERN_INFO " -S- timer data = 0x%x\n", inb(GUSP(gus, TIMERDATA)));
512 printk(KERN_INFO " -S- status read = 0x%x\n", inb(GUSP(gus, REGCNTRLS)));
H A Dgus_irq.c40 status = inb(gus->gf1.reg_irqstat); snd_gus_interrupt()
70 voice, voice_status, inb(GUSP(gus, GF1PAGE))); snd_gus_interrupt()
/linux-4.1.27/drivers/net/
H A Dsb1000.c267 a = inb(ioaddr[0] + 7); card_wait_for_busy_clear()
273 a = inb(ioaddr[0] + 7); card_wait_for_busy_clear()
291 a = inb(ioaddr[1] + 6); card_wait_for_ready()
297 a = inb(ioaddr[1] + 6); card_wait_for_ready()
305 in[1] = inb(ioaddr[0] + 1); card_wait_for_ready()
306 in[2] = inb(ioaddr[0] + 2); card_wait_for_ready()
307 in[3] = inb(ioaddr[0] + 3); card_wait_for_ready()
308 in[4] = inb(ioaddr[0] + 4); card_wait_for_ready()
309 in[0] = inb(ioaddr[0] + 5); card_wait_for_ready()
310 in[6] = inb(ioaddr[0] + 6); card_wait_for_ready()
311 in[5] = inb(ioaddr[1] + 6); card_wait_for_ready()
335 inb(ioaddr[0] + 7); card_send_command()
371 while (inb(ioaddr[1] + 6) & 0x80) { sb1000_wait_for_ready()
379 while (!(inb(ioaddr[1] + 6) & 0x40)) { sb1000_wait_for_ready()
386 inb(ioaddr[0] + 7); sb1000_wait_for_ready()
397 while (inb(ioaddr[1] + 6) & 0x80) { sb1000_wait_for_ready_clear()
405 while (inb(ioaddr[1] + 6) & 0x40) { sb1000_wait_for_ready_clear()
435 in[1] = inb(ioaddr[0] + 1); sb1000_read_status()
436 in[2] = inb(ioaddr[0] + 2); sb1000_read_status()
437 in[3] = inb(ioaddr[0] + 3); sb1000_read_status()
438 in[4] = inb(ioaddr[0] + 4); sb1000_read_status()
439 in[0] = inb(ioaddr[0] + 5); sb1000_read_status()
468 inb(port); sb1000_reset()
471 inb(port); sb1000_reset()
474 inb(port); sb1000_reset()
477 inb(port); sb1000_reset()
1109 st = inb(ioaddr[1] + 6); sb1000_interrupt()
1117 st = inb(ioaddr[0] + 7); sb1000_interrupt()
/linux-4.1.27/arch/x86/kernel/
H A Di8259.c102 ret = inb(PIC_MASTER_CMD) & mask; i8259A_irq_pending()
104 ret = inb(PIC_SLAVE_CMD) & (mask >> 8); i8259A_irq_pending()
131 value = inb(PIC_MASTER_CMD) & irqmask; i8259A_irq_real()
136 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); i8259A_irq_real()
175 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */ mask_and_ack_8259A()
182 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ mask_and_ack_8259A()
242 trigger[0] = inb(0x4d0) & 0xF8; save_ELCR()
243 trigger[1] = inb(0x4d1) & 0xDE; save_ELCR()
317 new_val = inb(PIC_MASTER_IMR); init_8259A()
/linux-4.1.27/drivers/net/can/sja1000/
H A Dtscan1.c81 return inb((unsigned long)priv->reg_base + reg); tscan1_read()
102 if (inb(pld_base + TSCAN1_ID1) != TSCAN1_ID1_VALUE || tscan1_probe()
103 inb(pld_base + TSCAN1_ID2) != TSCAN1_ID2_VALUE) { tscan1_probe()
108 switch (inb(pld_base + TSCAN1_JUMPERS) & (TSCAN1_JP4 | TSCAN1_JP5)) { tscan1_probe()
/linux-4.1.27/drivers/tty/serial/8250/
H A D8250_fintek.c74 if (inb(DATA_PORT) != CHIP_ID1_VAL) fintek_8250_check_id()
78 if (inb(DATA_PORT) != CHIP_ID2_VAL) fintek_8250_check_id()
82 if (inb(DATA_PORT) != VENDOR_ID1_VAL) fintek_8250_check_id()
86 if (inb(DATA_PORT) != VENDOR_ID2_VAL) fintek_8250_check_id()
/linux-4.1.27/arch/mn10300/unit-asb2303/include/unit/
H A Dsmc91111.h27 #define SMC_inb(a, r) inb((unsigned long) ((a) + (r)))
/linux-4.1.27/arch/arm/kernel/
H A Ddma-isa.c52 count = 1 + inb(io_port); isa_get_dma_residue()
53 count |= inb(io_port) << 8; isa_get_dma_residue()
174 if (inb(0) == 0x55 && inb(0) == 0xaa) { isa_init_dma()
H A Disa.c12 * iopl, inb, outb and friends in userspace via glibc emulation.
/linux-4.1.27/drivers/net/arcnet/
H A Dcom90io.c76 #define ASTATUS() inb(_STATUS)
98 return inb(_MEMDATA); get_buffer_byte()
126 *(dest++) = inb(_MEMDATA); get_whole_buffer()
171 inb(_RESET); com90io_probe()
199 if ((status = inb(_MEMDATA)) != 0xd1) { com90io_probe()
270 outb((inb(_CONFIG) & ~IOMAPflag), _CONFIG); com90io_found()
300 inb(_RESET); com90io_reset()
425 outb((inb(_CONFIG) & ~IOMAPflag), _CONFIG); com90io_exit()
/linux-4.1.27/drivers/net/ethernet/mellanox/mlx5/core/
H A Dmad.c39 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb, mlx5_core_mad_ifc() argument
60 memcpy(in->data, inb, sizeof(in->data)); mlx5_core_mad_ifc()
/linux-4.1.27/include/linux/
H A Dparport_pc.h72 unsigned char val = inb (DATA (p)); parport_pc_read_data()
84 unsigned char ecr = inb (ECONTROL (p)); dump_parport_state()
85 unsigned char dcr = inb (CONTROL (p)); dump_parport_state()
86 unsigned char dsr = inb (STATUS (p)); dump_parport_state()
99 dcr = i ? priv->ctr : inb (CONTROL (p)); dump_parport_state()
212 return inb(STATUS(p)); parport_pc_read_status()
H A Dcom20020.h138 #define ASTATUS() inb(_STATUS)
139 #define ADIAGSTATUS() inb(_DIAGSTAT)
/linux-4.1.27/arch/mips/kernel/
H A Di8259.c100 ret = inb(PIC_MASTER_CMD) & mask; i8259A_irq_pending()
102 ret = inb(PIC_SLAVE_CMD) & (mask >> 8); i8259A_irq_pending()
128 value = inb(PIC_MASTER_CMD) & irqmask; i8259A_irq_real()
133 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); i8259A_irq_real()
172 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */ mask_and_ack_8259A()
177 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ mask_and_ack_8259A()
/linux-4.1.27/sound/drivers/opl4/
H A Dopl4_lib.c35 while ((inb(opl4->fm_port) & OPL4_STATUS_BUSY) && --timeout > 0) snd_opl4_wait()
56 return inb(opl4->pcm_port + 1); snd_opl4_read()
116 inb(opl4->fm_port); snd_opl4_enable_opl4()
117 inb(opl4->fm_port); snd_opl4_enable_opl4()
119 inb(opl4->fm_port); snd_opl4_enable_opl4()
120 inb(opl4->fm_port); snd_opl4_enable_opl4()
/linux-4.1.27/drivers/net/hamradio/
H A Dbaycom_ser_hdx.c225 cur_s = inb(MSR(dev->base_addr)) & 0x10; /* the CTS line */ ser12_rx()
362 hdlcdrv_setdcd(&bc->hdrv, !((inb(MSR(dev->base_addr)) ^ bc->opt_dcd) & 0x80)); ser12_rx()
387 if ((iir = inb(IIR(dev->base_addr))) & 1) ser12_interrupt()
393 inb(LSR(dev->base_addr)); ser12_interrupt()
397 inb(RBR(dev->base_addr)); ser12_interrupt()
414 inb(MSR(dev->base_addr)); ser12_interrupt()
417 iir = inb(IIR(dev->base_addr)); ser12_interrupt()
446 b1 = inb(MCR(iobase)); ser12_check_uart()
448 b2 = inb(MSR(iobase)); ser12_check_uart()
450 b3 = inb(MSR(iobase)) & 0xf0; ser12_check_uart()
455 inb(RBR(iobase)); ser12_check_uart()
456 inb(RBR(iobase)); ser12_check_uart()
458 u = uart_tab[(inb(IIR(iobase)) >> 6) & 3]; ser12_check_uart()
461 b1 = inb(SCR(iobase)); ser12_check_uart()
463 b2 = inb(SCR(iobase)); ser12_check_uart()
H A Dbaycom_ser_fdx.c297 if ((iir = inb(IIR(dev->base_addr))) & 1) ser12_interrupt()
301 msr = inb(MSR(dev->base_addr)); ser12_interrupt()
308 inb(LSR(dev->base_addr)); ser12_interrupt()
312 inb(RBR(dev->base_addr)); ser12_interrupt()
335 msr = inb(MSR(dev->base_addr)); ser12_interrupt()
341 iir = inb(IIR(dev->base_addr)); ser12_interrupt()
387 b1 = inb(MCR(iobase)); ser12_check_uart()
389 b2 = inb(MSR(iobase)); ser12_check_uart()
391 b3 = inb(MSR(iobase)) & 0xf0; ser12_check_uart()
396 inb(RBR(iobase)); ser12_check_uart()
397 inb(RBR(iobase)); ser12_check_uart()
399 u = uart_tab[(inb(IIR(iobase)) >> 6) & 3]; ser12_check_uart()
402 b1 = inb(SCR(iobase)); ser12_check_uart()
404 b2 = inb(SCR(iobase)); ser12_check_uart()
H A Dyam.c314 inb(LSR(iobase)); fpga_reset()
315 inb(MSR(iobase)); fpga_reset()
339 while ((inb(LSR(iobase)) & LSR_TSRE) == 0) fpga_write()
462 rc = inb(MSR(iobase)); /* check DONE signal */ fpga_download()
490 inb(RBR(dev->base_addr)); yam_set_uart()
491 inb(MSR(dev->base_addr)); yam_set_uart()
516 b1 = inb(MCR(iobase)); yam_check_uart()
518 b2 = inb(MSR(iobase)); yam_check_uart()
520 b3 = inb(MSR(iobase)) & 0xf0; yam_check_uart()
525 inb(RBR(iobase)); yam_check_uart()
526 inb(RBR(iobase)); yam_check_uart()
528 u = uart_tab[(inb(IIR(iobase)) >> 6) & 3]; yam_check_uart()
531 b1 = inb(SCR(iobase)); yam_check_uart()
533 b2 = inb(SCR(iobase)); yam_check_uart()
759 while ((iir = IIR_MASK & inb(IIR(dev->base_addr))) != IIR_NOPEND) { yam_interrupt()
760 unsigned char msr = inb(MSR(dev->base_addr)); yam_interrupt()
761 unsigned char lsr = inb(LSR(dev->base_addr)); yam_interrupt()
782 rxb = inb(RBR(dev->base_addr)); yam_interrupt()
910 inb(LSR(yam_dev->base_addr)); yam_open()
/linux-4.1.27/sound/isa/es1688/
H A Des1688_lib.c44 if ((inb(ES1688P(chip, STATUS)) & 0x80) == 0) { snd_es1688_dsp_command()
59 if (inb(ES1688P(chip, DATA_AVAIL)) & 0x80) snd_es1688_dsp_get_byte()
60 return inb(ES1688P(chip, READ)); snd_es1688_dsp_get_byte()
61 snd_printd("es1688 get byte failed: 0x%lx = 0x%x!!!\n", ES1688P(chip, DATA_AVAIL), inb(ES1688P(chip, DATA_AVAIL))); snd_es1688_dsp_get_byte()
98 result = inb(ES1688P(chip, MIXER_DATA)); snd_es1688_mixer_read()
111 for (i = 0; i < 1000 && !(inb(ES1688P(chip, DATA_AVAIL)) & 0x80); i++); snd_es1688_reset()
112 if (inb(ES1688P(chip, READ)) != 0xaa) { snd_es1688_reset()
132 inb(ES1688P(chip, ENABLE1)); /* ENABLE1 */ snd_es1688_probe()
133 inb(ES1688P(chip, ENABLE1)); /* ENABLE1 */ snd_es1688_probe()
134 inb(ES1688P(chip, ENABLE1)); /* ENABLE1 */ snd_es1688_probe()
135 inb(ES1688P(chip, ENABLE2)); /* ENABLE2 */ snd_es1688_probe()
136 inb(ES1688P(chip, ENABLE1)); /* ENABLE1 */ snd_es1688_probe()
137 inb(ES1688P(chip, ENABLE2)); /* ENABLE2 */ snd_es1688_probe()
138 inb(ES1688P(chip, ENABLE1)); /* ENABLE1 */ snd_es1688_probe()
139 inb(ES1688P(chip, ENABLE1)); /* ENABLE1 */ snd_es1688_probe()
140 inb(ES1688P(chip, ENABLE2)); /* ENABLE2 */ snd_es1688_probe()
141 inb(ES1688P(chip, ENABLE1)); /* ENABLE1 */ snd_es1688_probe()
142 inb(ES1688P(chip, ENABLE0)); /* ENABLE0 */ snd_es1688_probe()
145 snd_printdd("ESS: [0x%lx] reset failed... 0x%x\n", chip->port, inb(ES1688P(chip, READ))); snd_es1688_probe()
152 if (inb(ES1688P(chip, DATA_AVAIL)) & 0x80) { snd_es1688_probe()
154 major = inb(ES1688P(chip, READ)); snd_es1688_probe()
156 minor = inb(ES1688P(chip, READ)); snd_es1688_probe()
499 inb(ES1688P(chip, DATA_AVAIL)); /* ack interrupt */ snd_es1688_interrupt()
/linux-4.1.27/drivers/platform/x86/
H A Dapple-gmux.c84 return inb(gmux_data->iostart + port); gmux_pio_read8()
113 u8 gwr = inb(gmux_data->iostart + GMUX_PORT_WRITE); gmux_index_wait_ready()
116 inb(gmux_data->iostart + GMUX_PORT_READ); gmux_index_wait_ready()
117 gwr = inb(gmux_data->iostart + GMUX_PORT_WRITE); gmux_index_wait_ready()
128 u8 gwr = inb(gmux_data->iostart + GMUX_PORT_WRITE); gmux_index_wait_complete()
131 gwr = inb(gmux_data->iostart + GMUX_PORT_WRITE); gmux_index_wait_complete()
137 inb(gmux_data->iostart + GMUX_PORT_READ); gmux_index_wait_complete()
150 val = inb(gmux_data->iostart + GMUX_PORT_VALUE); gmux_index_read8()
241 val = inb(gmux_data->iostart + 0xcc) | gmux_is_indexed()
242 (inb(gmux_data->iostart + 0xcd) << 8); gmux_is_indexed()
H A Damilo-rfkill.c67 if (inb(M7440_PORT1) != val1 || inb(M7440_PORT2) != val2) amilo_m7440_rfkill_set_block()
H A Dhdaps.c87 return inb(port) & 0xff; __get_latch()
125 if (inb(0x1604) != STATE_FRESH) { __device_refresh()
148 inb(0x161f); __device_complete()
149 inb(0x1604); __device_complete()
169 *val = inb(port); hdaps_readb_one()
187 km_activity = inb(HDAPS_PORT_KMACT); __hdaps_read_pair()
/linux-4.1.27/sound/pci/ice1712/
H A Dice1724.c122 return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0; stdclock_is_spdif_master()
142 old_cmd = inb(ICEMT1724(ice, AC97_CMD)); snd_vt1724_ac97_ready()
157 if ((inb(ICEMT1724(ice, AC97_CMD)) & bit) == 0) snd_vt1724_ac97_wait_bit()
225 mask = (unsigned int)inb(ICEREG1724(ice, GPIO_WRITE_MASK_22)); snd_vt1724_get_gpio_mask()
244 data = (unsigned int)inb(ICEREG1724(ice, GPIO_DATA_22)); snd_vt1724_get_gpio_data()
259 for (count = inb(ICEREG1724(ice, MPU_RXFIFO)); count > 0; --count) vt1724_midi_clear_rx()
260 inb(ICEREG1724(ice, MPU_DATA)); vt1724_midi_clear_rx()
279 count = 31 - inb(ICEREG1724(ice, MPU_TXFIFO)); vt1724_midi_write()
299 count = inb(ICEREG1724(ice, MPU_RXFIFO)); vt1724_midi_read()
303 buffer[i] = inb(ICEREG1724(ice, MPU_DATA)); vt1724_midi_read()
311 u8 mask = inb(ICEREG1724(ice, IRQMASK)); enable_midi_irq()
364 if (inb(ICEREG1724(ice, MPU_CTRL)) & VT1724_MPU_TX_EMPTY) vt1724_midi_output_drain()
426 status = inb(ICEREG1724(ice, IRQSTAT)); snd_vt1724_interrupt()
432 status = inb(ICEREG1724(ice, IRQSTAT)); snd_vt1724_interrupt()
476 unsigned char mtstat = inb(ICEMT1724(ice, IRQ)); snd_vt1724_interrupt()
509 unsigned char fstat = inb(ICEMT1724(ice, DMA_FIFO_ERR)); snd_vt1724_interrupt()
511 outb(VT1724_MULTI_FIFO_ERR | inb(ICEMT1724(ice, DMA_INT_MASK)), ICEMT1724(ice, DMA_INT_MASK)); snd_vt1724_interrupt()
576 old = inb(ICEMT1724(ice, DMA_PAUSE));
589 old = inb(ICEMT1724(ice, DMA_CONTROL));
624 rate = stdclock_rate_list[inb(ICEMT1724(ice, RATE)) & 15]; stdclock_get_rate()
645 val = old = inb(ICEMT1724(ice, I2S_FORMAT)); stdclock_set_mclk()
671 if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) || snd_vt1724_set_pro_rate()
672 (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) { snd_vt1724_set_pro_rate()
1180 cbit = inb(ICEREG1724(ice, SPDIF_CFG)); update_spdif_bits()
1401 if (inb(ICEMT1724(ice, BURST)) < val) snd_vt1724_playback_indep_prepare()
1500 outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD)); snd_vt1724_ac97_mixer()
1502 outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD)); snd_vt1724_ac97_mixer()
1568 idx, inb(ice->port+idx)); snd_vt1724_proc_read()
1571 idx, inb(ice->profi_port+idx)); snd_vt1724_proc_read()
1772 ucontrol->value.integer.value[0] = inb(ICEREG1724(ice, SPDIF_CFG)) & snd_vt1724_spdif_sw_get()
1784 old = val = inb(ICEREG1724(ice, SPDIF_CFG)); snd_vt1724_spdif_sw_put()
1915 oval = inb(ICEMT1724(ice, RATE)); stdclock_set_spdif_clock()
1918 i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT)); stdclock_set_spdif_clock()
2186 inb(ICEMT1724(ice, MONITOR_PEAKDATA)); snd_vt1724_pro_peak_get()
2266 while ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_BUSY) && t--) wait_i2c_busy()
2282 val = inb(ICEREG1724(ice, I2C_DATA)); snd_vt1724_read_i2c()
2314 if ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_EEPROM) != 0) snd_vt1724_read_eeprom()
2397 inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */ snd_vt1724_chip_reset()
2400 inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */ snd_vt1724_chip_reset()
2817 ice->pm_saved_spdif_cfg = inb(ICEREG1724(ice, SPDIF_CFG)); snd_vt1724_suspend()
/linux-4.1.27/drivers/char/
H A Dtlclk.c46 #include <asm/io.h> /* inb/outb */
145 #define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port)
220 inb(TLCLK_REG6); tlclk_open()
229 inb(TLCLK_REG6); /* Clear interrupt events */ tlclk_open()
287 ret_val = ((inb(TLCLK_REG1) & 0x08) >> 3); show_current_ref()
303 ret_val = inb(TLCLK_REG5); show_telclock_version()
319 ret_val = (inb(TLCLK_REG2) & 0xf0); show_alarms()
799 telclk_interrupt = (inb(TLCLK_REG7) & 0x0f); tlclk_init()
863 if ((inb(TLCLK_REG1) & 0x08) != (flags & 0x08)) switchover_timeout()
866 if ((inb(TLCLK_REG1) & 0x08) != (flags & 0x08)) switchover_timeout()
882 int_events = inb(TLCLK_REG6); tlclk_interrupt()
886 if (inb(TLCLK_REG2) & SEC_LOST_MASK) tlclk_interrupt()
899 if (inb(TLCLK_REG2) & PRI_LOST_MASK) tlclk_interrupt()
924 tlclk_timer_data = inb(TLCLK_REG1); tlclk_interrupt()
H A Dtoshiba.c118 scan = inb(tosh_fn); tosh_fn_status()
122 scan = inb(0xe5); tosh_fn_status()
149 al = inb(0xe5); tosh_emulate_fan()
158 al = inb(0xe5); tosh_emulate_fan()
169 al = inb(0xe5); tosh_emulate_fan()
185 al = inb(0xe5); tosh_emulate_fan()
194 al = inb(0xe5); tosh_emulate_fan()
204 al = inb(0xe5); tosh_emulate_fan()
234 "inb $0xb2,%%al\n\t" tosh_smm()
/linux-4.1.27/drivers/isdn/act2000/
H A Dact2000_isa.c34 if ((reg = inb(portbase + ISA_COR)) != 0xff) { act2000_isa_reset()
41 if (inb(portbase + ISA_ISR) & ISA_ISR_SERIAL) act2000_isa_reset()
69 istatus = (inb(ISA_PORT_ISR) & 0x07); act2000_isa_interrupt()
92 reg = (inb(ISA_PORT_COR) & ~ISA_COR_IRQOFF) | ISA_COR_PERR; act2000_isa_select_irq()
202 if (inb(ISA_PORT_SOS) & ISA_SOS_READY) { act2000_isa_writeb()
219 if (inb(ISA_PORT_SIS) & ISA_SIS_READY) { act2000_isa_readb()
220 *data = inb(ISA_PORT_SDI); act2000_isa_readb()
/linux-4.1.27/arch/powerpc/sysdev/
H A Di8259.c49 irq = inb(0x20) & 7; i8259_irq()
56 irq = (inb(0xA0) & 7) + 8; i8259_irq()
70 if(~inb(0x20) & 0x80) i8259_irq()
87 inb(0xA1); /* DUMMY */ i8259_mask_and_ack_irq()
93 inb(0x21); /* DUMMY */ i8259_mask_and_ack_irq()
/linux-4.1.27/sound/isa/sb/
H A Dsb_common.c51 if ((inb(SBP(chip, STATUS)) & 0x80) == 0) { snd_sbdsp_command()
64 if (inb(SBP(chip, DATA_AVAIL)) & 0x80) { snd_sbdsp_get_byte()
65 val = inb(SBP(chip, READ)); snd_sbdsp_get_byte()
85 if (inb(SBP(chip, DATA_AVAIL)) & 0x80) { snd_sbdsp_reset()
86 if (inb(SBP(chip, READ)) == 0xaa) snd_sbdsp_reset()
H A Dsb8_midi.c46 inb(SBP(chip, DATA_AVAIL)); /* ack interrupt */ snd_sb8dsp_midi_interrupt()
52 if (inb(SBP(chip, DATA_AVAIL)) & 0x80) { snd_sb8dsp_midi_interrupt()
53 byte = inb(SBP(chip, READ)); snd_sb8dsp_midi_interrupt()
195 while ((inb(SBP(chip, STATUS)) & 0x80) != 0 && --timeout > 0) snd_sb8dsp_midi_output_write()
/linux-4.1.27/drivers/net/ethernet/3com/
H A D3c574_cs.c372 mcr = inb(ioaddr + 2); tc574_config()
479 inw(ioaddr+RxStatus), inb(ioaddr+TxStatus), dump_status()
635 inb(ioaddr + i); tc574_reset()
639 inb(ioaddr + 12); tc574_reset()
640 inb(ioaddr + 13); tc574_reset()
717 u_char tx_status = inb(ioaddr + TxStatus); pop_tx_status()
876 if ((inw(ioaddr + EL3_STATUS) & IntLatch) && (inb(ioaddr + Timer) == 0xff)) { media_check()
967 dev->stats.tx_carrier_errors += inb(ioaddr + 0); update_stats()
968 dev->stats.tx_heartbeat_errors += inb(ioaddr + 1); update_stats()
969 /* Multiple collisions. */ inb(ioaddr + 2); update_stats()
970 dev->stats.collisions += inb(ioaddr + 3); update_stats()
971 dev->stats.tx_window_errors += inb(ioaddr + 4); update_stats()
972 dev->stats.rx_fifo_errors += inb(ioaddr + 5); update_stats()
973 dev->stats.tx_packets += inb(ioaddr + 6); update_stats()
974 up = inb(ioaddr + 9); update_stats()
976 /* Rx packets */ inb(ioaddr + 7); update_stats()
977 /* Tx deferrals */ inb(ioaddr + 8); update_stats()
982 /* BadSSD */ inb(ioaddr + 12); update_stats()
983 up = inb(ioaddr + 13); update_stats()
H A D3c515.c804 inb(ioaddr + i); corkscrew_open()
809 inb(ioaddr + 12); corkscrew_open()
971 dev->name, inb(ioaddr + TxStatus), corkscrew_timeout()
974 if ((inb(ioaddr + TxStatus) & 0x88) == 0x88) corkscrew_timeout()
1099 while (--i > 0 && (tx_status = inb(ioaddr + TxStatus)) > 0) { corkscrew_start_xmit()
1136 latency = inb(ioaddr + Timer); corkscrew_interrupt()
1224 pr_cont(" %2.2x", inb(ioaddr + reg)); corkscrew_interrupt()
1277 unsigned char rx_error = inb(ioaddr + RxErrors); corkscrew_rx()
1425 inb(ioaddr + TxStatus)); corkscrew_close()
1493 dev->stats.tx_carrier_errors += inb(ioaddr + 0); update_stats()
1494 dev->stats.tx_heartbeat_errors += inb(ioaddr + 1); update_stats()
1495 /* Multiple collisions. */ inb(ioaddr + 2); update_stats()
1496 dev->stats.collisions += inb(ioaddr + 3); update_stats()
1497 dev->stats.tx_window_errors += inb(ioaddr + 4); update_stats()
1498 dev->stats.rx_fifo_errors += inb(ioaddr + 5); update_stats()
1499 dev->stats.tx_packets += inb(ioaddr + 6); update_stats()
1500 dev->stats.tx_packets += (inb(ioaddr + 9) & 0x30) << 4; update_stats()
1501 /* Rx packets */ inb(ioaddr + 7); update_stats()
1503 /* Tx deferrals */ inb(ioaddr + 8); update_stats()
1511 inb(ioaddr + 12); update_stats()
H A D3c589_cs.c433 inb(ioaddr+TX_STATUS), inw(ioaddr+TX_FREE)); dump_status()
462 inb(ioaddr+i); tc589_reset()
551 u_char tx_status = inb(ioaddr + TX_STATUS); pop_tx_status()
695 (inb(ioaddr + EL3_TIMER) == 0xff)) { media_check()
727 errs = inb(ioaddr + 0); media_check()
798 dev->stats.tx_carrier_errors += inb(ioaddr + 0); update_stats()
799 dev->stats.tx_heartbeat_errors += inb(ioaddr + 1); update_stats()
801 inb(ioaddr + 2); update_stats()
802 dev->stats.collisions += inb(ioaddr + 3); update_stats()
803 dev->stats.tx_window_errors += inb(ioaddr + 4); update_stats()
804 dev->stats.rx_fifo_errors += inb(ioaddr + 5); update_stats()
805 dev->stats.tx_packets += inb(ioaddr + 6); update_stats()
807 inb(ioaddr + 7); update_stats()
809 inb(ioaddr + 8); update_stats()
/linux-4.1.27/drivers/isdn/sc/
H A Dmessage.c44 if (inb(sc_adapter[card]->ioport[FIFO_STATUS]) & RF_HAS_DATA) { receivemessage()
55 inb(sc_adapter[card]->ioport[FIFO_READ]); receivemessage()
137 while (!(inb(sc_adapter[card]->ioport[FIFO_STATUS]) & WF_NOT_FULL)) sendmessage()
/linux-4.1.27/drivers/gpio/
H A Dgpio-it8761e.c50 return inb(port + 1); read_reg()
86 return !!(inb(reg) & (1 << bit)); it8761e_gpio_get()
124 curr_vals = inb(reg); it8761e_gpio_set()
/linux-4.1.27/drivers/video/fbdev/via/
H A Dvia_utility.c226 color_r = inb(LUT_DATA); viafb_get_gamma_table()
227 color_g = inb(LUT_DATA); viafb_get_gamma_table()
228 color_b = inb(LUT_DATA); viafb_get_gamma_table()
/linux-4.1.27/arch/parisc/lib/
H A Dio.c136 *p = inb(port); insb()
143 w = inb(port) << 24; insb()
144 w |= inb(port) << 16; insb()
145 w |= inb(port) << 8; insb()
146 w |= inb(port); insb()
153 *p = inb(port); insb()
/linux-4.1.27/drivers/net/wan/
H A Dn2.c137 #define sca_in(reg, card) inb(sca_reg(reg, card))
153 return inb(card->io + N2_PSR) & PSR_PAGEBITS; sca_get_page()
159 u8 psr = inb(card->io + N2_PSR); openwin()
171 u8 mcr = inb(io + N2_MCR); n2_set_iface()
215 u8 mcr = inb(io + N2_MCR) | (port->phy_node ? TX422_PORT1:TX422_PORT0); n2_open()
225 outb(inb(io + N2_PCR) | PCR_ENWIN, io + N2_PCR); /* open window */ n2_open()
226 outb(inb(io + N2_PSR) | PSR_DMAEN, io + N2_PSR); /* enable dma */ n2_open()
238 u8 mcr = inb(io+N2_MCR) | (port->phy_node ? TX422_PORT1 : TX422_PORT0); n2_close()
H A Dsbni.c409 if( inb( ioaddr + CSR0 ) & 0x01 ) sbni_probe1()
515 if( inb( dev->base_addr + CSR0 ) & (RC_RDY | TR_RDY) ) sbni_interrupt()
519 (inb( nl->second->base_addr+CSR0 ) & (RC_RDY | TR_RDY)) ) sbni_interrupt()
546 outb( (inb( ioaddr + CSR0 ) & ~EN_INT) | TR_REQ, ioaddr + CSR0 ); handle_channel()
550 csr0 = inb( ioaddr + CSR0 ); handle_channel()
563 csr0 = inb( ioaddr + CSR0 ); handle_channel()
572 outb( inb( ioaddr + CSR0 ) & ~TR_REQ, ioaddr + CSR0 ); handle_channel()
575 outb( inb( ioaddr + CSR0 ) | EN_INT, ioaddr + CSR0 ); handle_channel()
608 outb( inb( ioaddr + CSR0 ) ^ CT_ZER, ioaddr + CSR0 ); recv_frame()
666 outb( inb( dev->base_addr + CSR0 ) & ~TR_REQ, dev->base_addr + CSR0 ); send_frame()
670 outb( inb( dev->base_addr + CSR0 ) | TR_REQ, send_frame()
861 outb( inb( dev->base_addr + CSR0 ) | TR_REQ, dev->base_addr + CSR0 ); prepare_to_send()
942 crc = CRC32( inb( ioaddr + DAT ), crc ); skip_tail()
960 if( inb( ioaddr + DAT ) != SBNI_SIG ) check_fhdr()
963 value = inb( ioaddr + DAT ); check_fhdr()
966 value = inb( ioaddr + DAT ); check_fhdr()
977 value = inb( ioaddr + DAT ); check_fhdr()
981 crc = CRC32( inb( ioaddr + DAT ), crc ); /* reserved byte */ check_fhdr()
1043 csr0 = inb( dev->base_addr + CSR0 ); sbni_watchdog()
1057 csr0 = inb( dev->base_addr + CSR0 ); sbni_watchdog()
1124 inb( dev->base_addr + CSR0 ); /* needs for PCI cards */ change_level()
1142 inb( dev->base_addr + CSR0 ); timeout_change_level()
1279 csr0 = inb( ioaddr + CSR0 ); sbni_card_probe()
/linux-4.1.27/arch/x86/kernel/apic/
H A Dvector.c665 v = inb(0xa1) << 8 | inb(0x21); print_PIC()
668 v = inb(0xa0) << 8 | inb(0x20); print_PIC()
673 v = inb(0xa0) << 8 | inb(0x20); print_PIC()
681 v = inb(0x4d1) << 8 | inb(0x4d0); print_PIC()
/linux-4.1.27/drivers/bluetooth/
H A Dbt3c_cs.c139 unsigned short value = inb(iobase + DATA_L); bt3c_get()
141 value |= inb(iobase + DATA_H) << 8; bt3c_get()
250 bt_cb(info->rx_skb)->pkt_type = inb(iobase + DATA_L); bt3c_receive()
251 inb(iobase + DATA_H); bt3c_receive()
284 __u8 x = inb(iobase + DATA_L); bt3c_receive()
287 inb(iobase + DATA_H); bt3c_receive()
350 iir = inb(iobase + CONTROL); bt3c_interrupt()
523 outb(inb(iobase + CONTROL) | 0x40, iobase + CONTROL); bt3c_load_firmware()
H A Ddtl1_cs.c115 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) dtl1_write()
229 *skb_put(info->rx_skb, 1) = inb(iobase + UART_RX); dtl1_receive()
284 } while (inb(iobase + UART_LSR) & UART_LSR_DR); dtl1_receive()
305 iir = inb(iobase + UART_IIR) & UART_IIR_ID; dtl1_interrupt()
310 lsr = inb(iobase + UART_LSR); dtl1_interrupt()
335 iir = inb(iobase + UART_IIR) & UART_IIR_ID; dtl1_interrupt()
339 msr = inb(iobase + UART_MSR); dtl1_interrupt()
485 info->ri_latch = inb(info->p_dev->resource[0]->start + UART_MSR) dtl1_open()
H A Dbtuart_cs.c116 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) btuart_write()
203 bt_cb(info->rx_skb)->pkt_type = inb(iobase + UART_RX); btuart_receive()
236 *skb_put(info->rx_skb, 1) = inb(iobase + UART_RX); btuart_receive()
283 } while (inb(iobase + UART_LSR) & UART_LSR_DR); btuart_receive()
303 iir = inb(iobase + UART_IIR) & UART_IIR_ID; btuart_interrupt()
308 lsr = inb(iobase + UART_LSR); btuart_interrupt()
333 iir = inb(iobase + UART_IIR) & UART_IIR_ID; btuart_interrupt()
/linux-4.1.27/arch/sh/boards/mach-hp6xx/
H A Dsetup.c67 v8 = inb(PKDR); dac_audio_start()
85 v8 = inb(PKDR); dac_audio_stop()
/linux-4.1.27/arch/mips/pci/
H A Dops-sni.c50 *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); pcimt_read()
125 *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); pcit_read()
/linux-4.1.27/arch/arm/mach-ebsa110/include/mach/
H A Dio.h41 #define inb(p) __inb16(p) macro
44 #define inb(p) __inb8(p) macro
/linux-4.1.27/sound/drivers/
H A Dserial-u16550.c216 while ((status = inb(uart->base + UART_LSR)) & UART_LSR_DR) { snd_uart16550_io_loop()
218 c = inb(uart->base + UART_RX); snd_uart16550_io_loop()
258 status = inb(uart->base + UART_MSR); snd_uart16550_io_loop()
262 status = inb(uart->base + UART_MSR); snd_uart16550_io_loop()
305 inb(uart->base + UART_IIR); snd_uart16550_interrupt()
350 c = inb(io_base + UART_IER); snd_uart16550_detect()
357 c = inb(io_base + UART_SCR); snd_uart16550_detect()
364 c = inb(io_base + UART_SCR); snd_uart16550_detect()
393 if ((inb(uart->base + UART_IIR) & 0xf0) == 0xc0) snd_uart16550_do_open()
396 uart->old_line_ctrl_reg = inb(uart->base + UART_LCR); snd_uart16550_do_open()
399 uart->old_divisor_lsb = inb(uart->base + UART_DLL); snd_uart16550_do_open()
400 uart->old_divisor_msb = inb(uart->base + UART_DLM); snd_uart16550_do_open()
459 inb(uart->base + UART_LSR); /* Clear any pre-existing overrun indication */ snd_uart16550_do_open()
460 inb(uart->base + UART_IIR); /* Clear any pre-existing transmit interrupt */ snd_uart16550_do_open()
461 inb(uart->base + UART_RX); /* Clear any pre-existing receive interrupt */ snd_uart16550_do_open()
499 inb(uart->base + UART_IIR); /* Clear any outstanding interrupts */ snd_uart16550_do_close()
619 && (inb(uart->base + UART_MSR) & UART_MSR_CTS)))) { /* CTS? */ snd_uart16550_output_byte()
622 if ((inb(uart->base + UART_LSR) & UART_LSR_THRE) != 0) { snd_uart16550_output_byte()
/linux-4.1.27/drivers/scsi/pcmcia/
H A Dsym53c500_cs.c252 i = inb(base + PIO_STATUS); SYM53C500_pio_read()
290 *request++ = inb(base + PIO_FIFO); SYM53C500_pio_read()
307 i = inb(base + PIO_STATUS); SYM53C500_pio_write()
370 pio_status = inb(port_base + PIO_STATUS); SYM53C500_intr()
372 status = inb(port_base + STAT_REG); SYM53C500_intr()
373 DEB(seq_reg = inb(port_base + SEQ_REG)); SYM53C500_intr()
374 int_reg = inb(port_base + INT_REG); SYM53C500_intr()
375 DEB(fifo_size = inb(port_base + FIFO_FLAGS) & 0x1f); SYM53C500_intr()
485 curSC->SCp.Status = inb(port_base + SCSI_FIFO);
486 curSC->SCp.Message = inb(port_base + SCSI_FIFO);
488 VDEB(printk("SCSI FIFO size=%d\n", inb(port_base + FIFO_FLAGS) & 0x1f));
/linux-4.1.27/drivers/char/pcmcia/
H A Dcm4000_cs.c173 #define xinb inb
184 val = inb(port); xinb()
185 pr_debug("%.2x=inb(%.4x)\n", val, port); xinb()
312 tmp = inb(REG_NUM_BYTES(iobase)) | io_read_num_rec_bytes()
313 (inb(REG_FLAGS0(iobase)) & 4 ? 0x100 : 0); io_read_num_rec_bytes()
529 if (inb(REG_FLAGS0(iobase)) & 0x08) {
569 pts_reply[i] = inb(REG_BUF_DATA(iobase));
608 if (inb(REG_FLAGS0(iobase)) & 8) {
615 if ((inb(REG_FLAGS0(iobase)) & 8) == 0) {
737 flags0 = inb(REG_FLAGS0(iobase));
802 dev->atr[i] = inb(REG_BUF_DATA(iobase));
974 dev->flags0 = inb(REG_FLAGS0(iobase));
1122 dev->flags0 = inb(REG_FLAGS0(iobase));
1149 tmp = inb(REG_FLAGS1(iobase));
1241 if (inb(REG_FLAGS0(iobase)) & 0x08)
1260 infolen = inb(REG_FLAGS1(iobase));
1297 if ((inb(REG_BUF_ADDR(iobase)) & 0x80)) {
1305 dev->procbyte = inb(REG_FLAGS1(iobase));
1310 if (inb(REG_FLAGS0(iobase)) & 0x08) {
1316 infolen = inb(REG_FLAGS1(iobase));
1326 if (inb(REG_FLAGS0(iobase)) & 0x08)
1336 dev->procbyte = inb(REG_FLAGS1(iobase));
/linux-4.1.27/drivers/isdn/hisax/
H A Dnetjet.h16 #define bytein(addr) inb(addr)
/linux-4.1.27/drivers/leds/
H A Dleds-hp6xx.c25 v8 = inb(PKDR); hp6xxled_green_set()
/linux-4.1.27/drivers/misc/altera-stapl/
H A Daltera-lpt.c40 data = inb((u16)(port + 0x378)); byteblaster_read()
/linux-4.1.27/drivers/staging/vt6655/
H A Dupc.h79 byData = inb(0x61); \
/linux-4.1.27/arch/x86/pci/
H A Ddirect.c36 *value = inb(0xCFC + (reg & 3)); pci_conf1_read()
119 *value = inb(PCI_CONF2_ADDRESS(dev, reg)); pci_conf2_read()
253 if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 && pci_check_type2()
/linux-4.1.27/arch/x86/realmode/rm/
H A Dwakemain.c28 inb(0x61); /* Dummy read of System Control Port B */ beep()
/linux-4.1.27/drivers/block/
H A Dsmart1,2.h238 chan = inb(h->io_mem_addr + SMART1_SYSTEM_DOORBELL) & CHANNEL_CLEAR; smart1_fifo_full()
247 if (inb(h->io_mem_addr + SMART1_SYSTEM_DOORBELL) & CHANNEL_BUSY) { smart1_completed()
251 status = inb(h->io_mem_addr + SMART1_LISTSTATUS); smart1_completed()
268 chan = inb(h->io_mem_addr + SMART1_SYSTEM_DOORBELL) & CHANNEL_BUSY; smart1_intr_pending()
H A Dhd.c170 i |= inb(0x40) << 8; read_timer()
226 hd_error = inb(HD_ERROR); dump_status()
236 printk(", CHS=%d/%d/%d", (inb(HD_HCYL)<<8) + inb(HD_LCYL), dump_status()
237 inb(HD_CURRENT) & 0xf, inb(HD_SECTOR)); dump_status()
248 hd_error = inb(HD_ERROR); dump_status()
362 else if ((hd_error = inb(HD_ERROR)) != 1) reset_controller()
/linux-4.1.27/arch/mips/include/asm/mach-malta/
H A Dmc146818rtc.h35 return inb(MALTA_RTC_DAT_REG); CMOS_READ()
/linux-4.1.27/arch/sh/drivers/pci/
H A Dpci-dreamcast.c67 idbuf[i] = inb(GAPSPCI_REGS+i); gapspci_init()
/linux-4.1.27/arch/parisc/include/asm/
H A Dio.h237 #define inb_p inb
252 extern unsigned char inb(int addr);
260 #define inb eisa_in8 macro
267 static inline char inb(unsigned long addr) inb() function
/linux-4.1.27/arch/hexagon/include/asm/
H A Dio.h222 * inb - read byte from I/O port or something
227 static inline u8 inb(unsigned long port) inb() function
266 #define inb_p inb
275 u8 x = inb(port); insb()
/linux-4.1.27/drivers/isdn/hardware/avm/
H A Davmcard.h224 return inb(base + B1_ANALYSE); b1outp()
230 return inb(base + B1_INSTAT) & 0x1; b1_rx_full()
238 return inb(base + B1_READ); b1_get_byte()
255 return inb(base + B1_OUTSTAT) & 0x1; b1_tx_empty()
396 return inb(base + offset); t1inp()
401 return (inb(base + T1_IDENT) & ~0x82) == 1; t1_isfastlink()
406 return inb(base + T1_FIFOSTAT); t1_fifostatus()
H A Db1.c109 if ((inb(base + B1_INSTAT) & 0xfc) b1_detect()
110 || (inb(base + B1_OUTSTAT) & 0xfc)) b1_detect()
117 if ((inb(base + B1_INSTAT) & 0xfe) != 0x2 b1_detect()
118 /* || (inb(base + B1_OUTSTAT) & 0xfe) != 0x2 */) b1_detect()
125 if ((inb(base + B1_INSTAT) & 0xfe) b1_detect()
126 || (inb(base + B1_OUTSTAT) & 0xfe)) b1_detect()
147 card->class = inb(card->port + B1_ANALYSE); b1_getrevision()
148 card->revision = inb(card->port + B1_REVISION); b1_getrevision()
/linux-4.1.27/sound/drivers/opl3/
H A Dopl3_lib.c79 inb(opl3->l_port); snd_opl3_command()
80 inb(opl3->l_port); snd_opl3_command()
83 inb(opl3->l_port); snd_opl3_command()
84 inb(opl3->l_port); snd_opl3_command()
108 signature = stat1 = inb(opl3->l_port); /* Status register */ snd_opl3_detect()
120 stat2 = inb(opl3->l_port); snd_opl3_detect()
304 status = inb(opl3->l_port); snd_opl3_interrupt()
/linux-4.1.27/sound/isa/
H A Dsscape.c230 return inb(ODIE_DATA_IO(io_base)); sscape_read_unsafe()
256 if ((inb(HOST_CTRL_IO(io_base)) & RX_READY) != 0) host_read_unsafe()
257 data = inb(HOST_DATA_IO(io_base)); host_read_unsafe()
285 if ((inb(HOST_CTRL_IO(io_base)) & TX_READY) != 0) { host_write_unsafe()
320 return ((inb(MPU401C(mpu)) & 0xc0) == 0x80); verify_mpu401()
723 if ((inb(HOST_CTRL_IO(s->io_base)) & 0x78) != 0) detect_sscape()
726 d = inb(ODIE_ADDR_IO(s->io_base)) & 0xf0; detect_sscape()
738 if ((inb(ODIE_ADDR_IO(s->io_base)) & 0x9f) != 0x0a) detect_sscape()
742 if ((inb(ODIE_ADDR_IO(s->io_base)) & 0x9f) != 0x0e) detect_sscape()
746 d = inb(ODIE_DATA_IO(s->io_base)); detect_sscape()
761 if ((inb(wss_io) & 0x80) == 0) detect_sscape()
768 if ((inb(wss_io) & 0x80) != 0) detect_sscape()
771 if (inb(wss_io + 2) == 0xff) detect_sscape()
777 if ((inb(wss_io) & 0x80) != 0) detect_sscape()
784 if ((inb(wss_io) & 0x80) == 0) detect_sscape()
/linux-4.1.27/drivers/hwmon/
H A Dsch56xx-common.c84 return inb(base + 1); superio_inb()
127 val = inb(addr + 1); sch56xx_send_cmd()
155 val = inb(addr + 8); sch56xx_send_cmd()
175 val = inb(addr + 1); sch56xx_send_cmd()
202 return inb(addr + 4); sch56xx_send_cmd()
357 val = inb(data->addr + 9); watchdog_start()
/linux-4.1.27/drivers/net/ethernet/fujitsu/
H A Dfmvj18x_cs.c494 dev->dev_addr[i] = inb(ioaddr + UNGERMANN_MAC_ID + i); fmvj18x_config()
512 dev->dev_addr[i] = inb(ioaddr + MAC_ID + i); fmvj18x_config()
727 tx_stat = inb(ioaddr + TX_STATUS); fjn_interrupt()
728 rx_stat = inb(ioaddr + RX_STATUS); fjn_interrupt()
737 if (rx_stat || (inb(ioaddr + RX_MODE) & F_BUF_EMP) == 0) { fjn_interrupt()
780 inb(ioaddr + TX_STATUS) & F_TMT_RDY fjn_tx_timeout()
960 dev->name, inb(ioaddr + RX_STATUS)); fjn_rx()
962 while ((inb(ioaddr + RX_MODE) & F_BUF_EMP) == 0) { fjn_rx()
966 inb(ioaddr + RX_MODE), status); fjn_rx()
1027 if ((inb(ioaddr + RX_MODE) & F_BUF_EMP) == F_BUF_EMP) fjn_rx()
1035 "%d ticks.\n", dev->name, inb(ioaddr + RX_MODE), i); fjn_rx()
1129 int saved_config_0 = inb(ioaddr + CONFIG_0); set_rx_mode()
1162 saved_bank = inb(ioaddr + CONFIG_1);
/linux-4.1.27/drivers/isdn/hardware/mISDN/
H A Diohelper.h41 return inb(hw->ap.port + off); \
60 return inb(hw->ap.port); \
/linux-4.1.27/drivers/video/backlight/
H A Dapple_bl.c76 intensity = inb(0xb3) >> 4; intel_chipset_get_intensity()
121 intensity = inb(0x52f) >> 4; nvidia_chipset_get_intensity()
/linux-4.1.27/arch/mips/sni/
H A Dtime.c111 (void) inb(0x40); dosample()
112 msb = inb(0x40); dosample()
/linux-4.1.27/arch/powerpc/include/asm/
H A Dfloppy.h65 st=inb(virtual_dma_port+4) & 0xa0 ; floppy_hardint()
75 st = inb(virtual_dma_port+4); floppy_hardint()
/linux-4.1.27/arch/m68k/include/asm/
H A Dfloppy.h214 st=inb(virtual_dma_port+4) & 0xa0 ; floppy_hardint()
225 st = inb(virtual_dma_port+4); floppy_hardint()
H A Dio_no.h113 #define inb(addr) readb(addr) macro
120 #define inb_p(addr) inb(addr)
/linux-4.1.27/sound/isa/msnd/
H A Dmsnd.c71 if (inb(io + HP_ISR) & HPISR_TXDE) snd_msnd_wait_TXDE()
83 if (!(inb(io + HP_CVR) & HPCVR_HC)) snd_msnd_wait_HC0()
139 inb(dev->io + HP_RXL); snd_msnd_upload_host()
140 inb(dev->io + HP_CVR); snd_msnd_upload_host()
157 outb(inb(dev->io + HP_ICR) | HPICR_TREQ, dev->io + HP_ICR); snd_msnd_enable_irq()
161 outb(inb(dev->io + HP_ICR) & ~HPICR_TREQ, dev->io + HP_ICR); snd_msnd_enable_irq()
162 outb(inb(dev->io + HP_ICR) | HPICR_RREQ, dev->io + HP_ICR); snd_msnd_enable_irq()
192 outb(inb(dev->io + HP_ICR) & ~HPICR_RREQ, dev->io + HP_ICR); snd_msnd_disable_irq()

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