Home
last modified time | relevance | path

Searched refs:I915_WRITE (Results 1 – 37 of 37) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Di915_suspend.c71 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); in i915_restore_display()
77 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask); in i915_restore_display()
79 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask); in i915_restore_display()
83 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); in i915_restore_display()
84 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); in i915_restore_display()
85 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); in i915_restore_display()
86 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); in i915_restore_display()
88 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); in i915_restore_display()
89 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); in i915_restore_display()
90 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); in i915_restore_display()
[all …]
Dintel_pm.c60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | in gen9_init_clock_gating()
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in skl_init_clock_gating()
82 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | in skl_init_clock_gating()
86 I915_WRITE(FF_SLICE_CS_CHICKEN2, in skl_init_clock_gating()
93 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | in skl_init_clock_gating()
313 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); in intel_set_memory_cxsr()
317 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in intel_set_memory_cxsr()
321 I915_WRITE(DSPFW3, val); in intel_set_memory_cxsr()
325 I915_WRITE(FW_BLC_SELF, val); in intel_set_memory_cxsr()
329 I915_WRITE(INSTPM, val); in intel_set_memory_cxsr()
[all …]
Dintel_sprite.c174 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); in intel_update_primary_plane()
176 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); in intel_update_primary_plane()
274 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); in skl_update_plane()
275 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); in skl_update_plane()
276 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); in skl_update_plane()
286 I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x); in skl_update_plane()
287 I915_WRITE(PLANE_STRIDE(pipe, plane), fb->pitches[0] / stride_div); in skl_update_plane()
288 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); in skl_update_plane()
289 I915_WRITE(PLANE_SIZE(pipe, plane), (crtc_h << 16) | crtc_w); in skl_update_plane()
290 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); in skl_update_plane()
[all …]
Dintel_dsi.c73 I915_WRITE(reg, val); in write_data()
132 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); in intel_dsi_host_transfer()
139 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); in intel_dsi_host_transfer()
225 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
231 I915_WRITE(MIPI_DPI_CONTROL(port), cmd); in dpi_send_cmd()
303 I915_WRITE(VLV_CHICKEN_3, temp); in intel_dsi_port_enable()
319 I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); in intel_dsi_port_enable()
335 I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); in intel_dsi_port_disable()
360 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); in intel_dsi_device_ready()
368 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); in intel_dsi_device_ready()
[all …]
Di915_irq.c93 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
103 I915_WRITE(type##IMR, 0xffffffff); \
105 I915_WRITE(type##IER, 0); \
106 I915_WRITE(type##IIR, 0xffffffff); \
108 I915_WRITE(type##IIR, 0xffffffff); \
120 I915_WRITE((reg), 0xffffffff); \
122 I915_WRITE((reg), 0xffffffff); \
[all …]
Di915_drv.c1123 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); in vlv_restore_gunit_s0ix_state()
1124 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); in vlv_restore_gunit_s0ix_state()
1125 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); in vlv_restore_gunit_s0ix_state()
1126 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); in vlv_restore_gunit_s0ix_state()
1127 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); in vlv_restore_gunit_s0ix_state()
1130 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]); in vlv_restore_gunit_s0ix_state()
1132 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); in vlv_restore_gunit_s0ix_state()
1133 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); in vlv_restore_gunit_s0ix_state()
1135 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); in vlv_restore_gunit_s0ix_state()
1136 I915_WRITE(GAM_ECOCHK, s->ecochk); in vlv_restore_gunit_s0ix_state()
[all …]
Dintel_audio.c111 I915_WRITE(reg_elda, tmp); in intel_eld_uptodate()
136 I915_WRITE(G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_disable()
166 I915_WRITE(G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
171 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); in g4x_audio_codec_enable()
175 I915_WRITE(G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
195 I915_WRITE(HSW_AUD_CFG(pipe), tmp); in hsw_audio_codec_disable()
201 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); in hsw_audio_codec_disable()
222 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); in hsw_audio_codec_enable()
234 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); in hsw_audio_codec_enable()
239 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i)); in hsw_audio_codec_enable()
[all …]
Dintel_i2c.c66 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); in intel_i2c_reset()
67 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); in intel_i2c_reset()
83 I915_WRITE(DSPCLK_GATE_D, val); in intel_i2c_quirk_set()
223 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); in gmbus_wait_hw_status()
237 I915_WRITE(GMBUS4 + reg_offset, 0); in gmbus_wait_hw_status()
258 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); in gmbus_wait_idle()
263 I915_WRITE(GMBUS4 + reg_offset, 0); in gmbus_wait_idle()
279 I915_WRITE(GMBUS1 + reg_offset, in gmbus_xfer_read_chunk()
342 I915_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer_write_chunk()
343 I915_WRITE(GMBUS1 + reg_offset, in gmbus_xfer_write_chunk()
[all …]
Dintel_fbc.c57 I915_WRITE(FBC_CONTROL, fbc_ctl); in i8xx_fbc_disable()
94 I915_WRITE(FBC_TAG + (i * 4), 0); in i8xx_fbc_enable()
102 I915_WRITE(FBC_CONTROL2, fbc_ctl2); in i8xx_fbc_enable()
103 I915_WRITE(FBC_FENCE_OFF, crtc->y); in i8xx_fbc_enable()
114 I915_WRITE(FBC_CONTROL, fbc_ctl); in i8xx_fbc_enable()
145 I915_WRITE(DPFC_FENCE_YOFF, crtc->y); in g4x_fbc_enable()
148 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); in g4x_fbc_enable()
164 I915_WRITE(DPFC_CONTROL, dpfc_ctl); in g4x_fbc_disable()
179 I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); in intel_fbc_nuke()
214 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); in ilk_fbc_enable()
[all …]
Dintel_tv.c862 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); in intel_enable_tv()
871 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); in intel_disable_tv()
989 I915_WRITE(TV_H_CTL_1, hctl1); in set_tv_mode_timings()
990 I915_WRITE(TV_H_CTL_2, hctl2); in set_tv_mode_timings()
991 I915_WRITE(TV_H_CTL_3, hctl3); in set_tv_mode_timings()
992 I915_WRITE(TV_V_CTL_1, vctl1); in set_tv_mode_timings()
993 I915_WRITE(TV_V_CTL_2, vctl2); in set_tv_mode_timings()
994 I915_WRITE(TV_V_CTL_3, vctl3); in set_tv_mode_timings()
995 I915_WRITE(TV_V_CTL_4, vctl4); in set_tv_mode_timings()
996 I915_WRITE(TV_V_CTL_5, vctl5); in set_tv_mode_timings()
[all …]
Dintel_ddi.c287 I915_WRITE(reg, ddi_translations[i].trans1); in intel_prepare_ddi_buffers()
289 I915_WRITE(reg, ddi_translations[i].trans2); in intel_prepare_ddi_buffers()
299 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1); in intel_prepare_ddi_buffers()
301 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2); in intel_prepare_ddi_buffers()
356 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | in hsw_fdi_link_train()
364 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); in hsw_fdi_link_train()
370 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); in hsw_fdi_link_train()
373 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); in hsw_fdi_link_train()
380 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
390 I915_WRITE(DDI_BUF_CTL(PORT_E), in hsw_fdi_link_train()
[all …]
Dintel_sideband.c60 I915_WRITE(VLV_IOSF_ADDR, addr); in vlv_sideband_rw()
62 I915_WRITE(VLV_IOSF_DATA, *val); in vlv_sideband_rw()
63 I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd); in vlv_sideband_rw()
73 I915_WRITE(VLV_IOSF_DATA, 0); in vlv_sideband_rw()
224 I915_WRITE(SBI_ADDR, (reg << 16)); in intel_sbi_read()
230 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); in intel_sbi_read()
254 I915_WRITE(SBI_ADDR, (reg << 16)); in intel_sbi_write()
255 I915_WRITE(SBI_DATA, value); in intel_sbi_write()
261 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); in intel_sbi_write()
Dintel_psr.c90 I915_WRITE(ctl_reg, 0); in intel_psr_write_vsc()
95 I915_WRITE(data_reg + i, *data++); in intel_psr_write_vsc()
97 I915_WRITE(data_reg + i, 0); in intel_psr_write_vsc()
100 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); in intel_psr_write_vsc()
117 I915_WRITE(VLV_VSCSDP(pipe), val); in vlv_psr_setup_vsc()
175 I915_WRITE(aux_data_reg + i, in hsw_psr_enable_sink()
188 I915_WRITE(aux_ctl_reg, val); in hsw_psr_enable_sink()
190 I915_WRITE(aux_ctl_reg, in hsw_psr_enable_sink()
207 I915_WRITE(VLV_PSRCTL(pipe), in vlv_psr_enable_source()
226 I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | in vlv_psr_activate()
[all …]
Dintel_hdmi.c150 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
154 I915_WRITE(VIDEO_DIP_DATA, *data); in g4x_write_infoframe()
159 I915_WRITE(VIDEO_DIP_DATA, 0); in g4x_write_infoframe()
166 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
201 I915_WRITE(reg, val); in ibx_write_infoframe()
205 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in ibx_write_infoframe()
210 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); in ibx_write_infoframe()
217 I915_WRITE(reg, val); in ibx_write_infoframe()
253 I915_WRITE(reg, val); in cpt_write_infoframe()
257 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in cpt_write_infoframe()
[all …]
Dintel_crt.c147 I915_WRITE(SPLL_CTL, in hsw_crt_pre_enable()
185 I915_WRITE(BCLRPAT(crtc->pipe), 0); in intel_crt_set_dpms()
202 I915_WRITE(crt->adpa_reg, adpa); in intel_crt_set_dpms()
220 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); in hsw_crt_post_disable()
355 I915_WRITE(crt->adpa_reg, adpa); in intel_ironlake_crt_detect_hotplug()
362 I915_WRITE(crt->adpa_reg, save_adpa); in intel_ironlake_crt_detect_hotplug()
392 I915_WRITE(crt->adpa_reg, adpa); in valleyview_crt_detect_hotplug()
397 I915_WRITE(crt->adpa_reg, save_adpa); in valleyview_crt_detect_hotplug()
448 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); in intel_crt_detect_hotplug()
461 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); in intel_crt_detect_hotplug()
[all …]
Dintel_panel.c564 I915_WRITE(BLC_PWM_PCH_CTL2, val | level); in bdw_set_backlight()
574 I915_WRITE(BLC_PWM_CPU_CTL, tmp | level); in pch_set_backlight()
602 I915_WRITE(BLC_PWM_CTL, tmp | level); in i9xx_set_backlight()
616 I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level); in vlv_set_backlight()
705 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); in pch_disable_backlight()
708 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); in pch_disable_backlight()
725 I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); in i965_disable_backlight()
741 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp & ~BLM_PWM_ENABLE); in vlv_disable_backlight()
785 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); in bdw_enable_backlight()
789 I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2); in bdw_enable_backlight()
[all …]
Dintel_display.c1600 I915_WRITE(reg, dpll); in vlv_enable_pll()
1607 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1611 I915_WRITE(reg, dpll); in vlv_enable_pll()
1614 I915_WRITE(reg, dpll); in vlv_enable_pll()
1617 I915_WRITE(reg, dpll); in vlv_enable_pll()
1648 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1655 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1698 I915_WRITE(DPLL(!crtc->pipe), in i9xx_enable_pll()
1702 I915_WRITE(reg, dpll); in i9xx_enable_pll()
1709 I915_WRITE(DPLL_MD(crtc->pipe), in i9xx_enable_pll()
[all …]
Dintel_fifo_underrun.c112 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_check_fifo_underruns()
132 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_set_fifo_underrun_reporting()
159 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivybridge_set_fifo_underrun_reporting()
187 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in broadwell_set_fifo_underrun_reporting()
212 I915_WRITE(SERR_INT, in cpt_set_fifo_underrun_reporting()
Dintel_ringbuffer.h33 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
36 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
39 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
42 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
45 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
48 #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
Dintel_runtime_pm.c244 I915_WRITE(HSW_PWR_WELL_DRIVER, in hsw_set_power_well()
257 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); in hsw_set_power_well()
364 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); in skl_set_power_well()
377 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); in skl_set_power_well()
409 I915_WRITE(HSW_PWR_WELL_BIOS, 0); in hsw_power_well_sync_hw()
439 I915_WRITE(HSW_PWR_WELL_BIOS, 0); in skl_power_well_sync_hw()
602 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | in vlv_dpio_cmn_power_well_enable()
619 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); in vlv_dpio_cmn_power_well_enable()
633 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); in vlv_dpio_cmn_power_well_disable()
653 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | in chv_dpio_cmn_power_well_enable()
[all …]
Dintel_lvds.c205 I915_WRITE(lvds_encoder->reg, temp); in intel_pre_enable_lvds()
228 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
230 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); in intel_enable_lvds()
257 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); in intel_disable_lvds()
261 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); in intel_disable_lvds()
932 I915_WRITE(PCH_PP_CONTROL, in intel_lvds_init()
935 I915_WRITE(PP_CONTROL, in intel_lvds_init()
Di915_gem_gtt.c985 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); in vgpu_mm_switch()
986 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); in vgpu_mm_switch()
1029 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); in gen6_mm_switch()
1030 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); in gen6_mm_switch()
1044 I915_WRITE(RING_MODE_GEN7(ring), in gen8_ppgtt_enable()
1057 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); in gen7_ppgtt_enable()
1066 I915_WRITE(GAM_ECOCHK, ecochk); in gen7_ppgtt_enable()
1070 I915_WRITE(RING_MODE_GEN7(ring), in gen7_ppgtt_enable()
1081 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | in gen6_ppgtt_enable()
1085 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); in gen6_ppgtt_enable()
[all …]
Di915_gem_stolen.c213 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); in i915_setup_compression()
215 I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); in i915_setup_compression()
228 I915_WRITE(FBC_CFB_BASE, in i915_setup_compression()
230 I915_WRITE(FBC_LL_BASE, in i915_setup_compression()
Dintel_dp.c371 I915_WRITE(intel_dp->output_reg, DP); in vlv_power_sequencer_kick()
374 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); in vlv_power_sequencer_kick()
377 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); in vlv_power_sequencer_kick()
604 I915_WRITE(pp_div_reg, pp_div | 0x1F); in edp_notify_handler()
605 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); in edp_notify_handler()
863 I915_WRITE(ch_data + i, in intel_dp_aux_ch()
868 I915_WRITE(ch_ctl, send_ctl); in intel_dp_aux_ch()
873 I915_WRITE(ch_ctl, in intel_dp_aux_ch()
1510 I915_WRITE(DP_A, dpa_ctl); in ironlake_set_pll_cpu_edp()
1723 I915_WRITE(pp_ctrl_reg, pp); in edp_panel_vdd_on()
[all …]
Dintel_dvo.c177 I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); in intel_disable_dvo()
193 I915_WRITE(dvo_reg, temp | DVO_ENABLE); in intel_enable_dvo()
335 I915_WRITE(dvo_srcdim_reg, in intel_dvo_pre_enable()
339 I915_WRITE(dvo_reg, dvo_val); in intel_dvo_pre_enable()
Dintel_ringbuffer.c471 I915_WRITE(HWS_PGA, addr); in ring_setup_phys_status_page()
510 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); in intel_ring_setup_status_page()
526 I915_WRITE(reg, in intel_ring_setup_status_page()
1065 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); in init_render_ring()
1074 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in init_render_ring()
1079 I915_WRITE(GFX_MODE, in init_render_ring()
1084 I915_WRITE(GFX_MODE_GEN7, in init_render_ring()
1094 I915_WRITE(CACHE_MODE_0, in init_render_ring()
1099 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in init_render_ring()
1489 I915_WRITE(IMR, dev_priv->irq_mask); in i9xx_ring_get_irq()
[all …]
Dintel_lrc.c309 I915_WRITE(RING_ELSP(ring), desc[1]); in execlists_elsp_write()
310 I915_WRITE(RING_ELSP(ring), desc[0]); in execlists_elsp_write()
311 I915_WRITE(RING_ELSP(ring), desc[3]); in execlists_elsp_write()
314 I915_WRITE(RING_ELSP(ring), desc[2]); in execlists_elsp_write()
513 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), in intel_lrc_irq_handler()
1137 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); in gen8_init_common_ring()
1140 I915_WRITE(RING_HWS_PGA(ring->mmio_base), in gen8_init_common_ring()
1145 I915_WRITE(RING_MODE_GEN7(ring), in gen8_init_common_ring()
1173 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in gen8_init_render_ring()
1175 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in gen8_init_render_ring()
[all …]
Di915_gem.c3082 I915_WRITE(fence_reg, 0); in i965_write_fence_reg()
3104 I915_WRITE(fence_reg + 4, val >> 32); in i965_write_fence_reg()
3107 I915_WRITE(fence_reg + 0, val); in i965_write_fence_reg()
3110 I915_WRITE(fence_reg + 4, 0); in i965_write_fence_reg()
3155 I915_WRITE(reg, val); in i915_write_fence_reg()
3187 I915_WRITE(FENCE_REG_830_0 + reg * 4, val); in i830_write_fence_reg()
4666 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in i915_gem_init_swizzling()
4672 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); in i915_gem_init_swizzling()
4674 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in i915_gem_init_swizzling()
4676 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in i915_gem_init_swizzling()
[all …]
Dintel_overlay.c1324 I915_WRITE(OGAMC0, attrs->gamma0); in intel_overlay_attrs()
1325 I915_WRITE(OGAMC1, attrs->gamma1); in intel_overlay_attrs()
1326 I915_WRITE(OGAMC2, attrs->gamma2); in intel_overlay_attrs()
1327 I915_WRITE(OGAMC3, attrs->gamma3); in intel_overlay_attrs()
1328 I915_WRITE(OGAMC4, attrs->gamma4); in intel_overlay_attrs()
1329 I915_WRITE(OGAMC5, attrs->gamma5); in intel_overlay_attrs()
Dintel_frontbuffer.c88 I915_WRITE(dpll_reg, dpll); in intel_increase_pllclock()
Dintel_uncore.c1357 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); in g4x_do_reset()
1367 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); in g4x_do_reset()
1380 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, in ironlake_do_reset()
1387 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, in ironlake_do_reset()
1394 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0); in ironlake_do_reset()
Dintel_dp_mst.c176 I915_WRITE(PORT_CLK_SEL(port), in intel_mst_pre_enable_dp()
200 I915_WRITE(DP_TP_STATUS(port), temp); in intel_mst_pre_enable_dp()
Dintel_sdvo.c244 I915_WRITE(intel_sdvo->sdvo_reg, val); in intel_sdvo_write_sdvox()
261 I915_WRITE(GEN3_SDVOB, bval); in intel_sdvo_write_sdvox()
263 I915_WRITE(GEN3_SDVOC, cval); in intel_sdvo_write_sdvox()
1449 I915_WRITE(intel_sdvo->sdvo_reg, temp); in intel_disable_sdvo()
1453 I915_WRITE(intel_sdvo->sdvo_reg, temp); in intel_disable_sdvo()
Di915_debugfs.c1617 I915_WRITE(ILK_DPFC_CONTROL, val ? in i915_fbc_fc_set()
3361 I915_WRITE(PORT_DFT2_G4X, tmp); in vlv_pipe_crc_ctl_reg()
3429 I915_WRITE(PORT_DFT_I9XX, in i9xx_pipe_crc_ctl_reg()
3437 I915_WRITE(PORT_DFT2_G4X, tmp); in i9xx_pipe_crc_ctl_reg()
3464 I915_WRITE(PORT_DFT2_G4X, tmp); in vlv_undo_pipe_scramble_reset()
3478 I915_WRITE(PORT_DFT2_G4X, tmp); in g4x_undo_pipe_scramble_reset()
3481 I915_WRITE(PORT_DFT_I9XX, in g4x_undo_pipe_scramble_reset()
3661 I915_WRITE(PIPE_CRC_CTL(pipe), val); in pipe_crc_set_source()
4466 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); in i915_cache_sharing_set()
Dintel_bios.c1326 I915_WRITE(PP_ON_DELAYS, 0x019007d0); in intel_setup_bios()
1329 I915_WRITE(PP_OFF_DELAYS, 0x015e07d0); in intel_setup_bios()
Di915_dma.c961 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); in i915_driver_load()
Di915_drv.h3179 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) macro