Searched refs:interrupt (Results 1 - 200 of 7236) sorted by relevance

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/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/interrupt-controller/
H A Dmips-gic.h4 #include <dt-bindings/interrupt-controller/irq.h>
H A Darm-gic.h8 #include <dt-bindings/interrupt-controller/irq.h>
10 /* interrupt specifier cell 0 */
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/interrupt-controller/
H A Dmips-gic.h4 #include <dt-bindings/interrupt-controller/irq.h>
H A Darm-gic.h8 #include <dt-bindings/interrupt-controller/irq.h>
10 /* interrupt specifier cell 0 */
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/interrupt-controller/
H A Dmips-gic.h4 #include <dt-bindings/interrupt-controller/irq.h>
H A Darm-gic.h8 #include <dt-bindings/interrupt-controller/irq.h>
10 /* interrupt specifier cell 0 */
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/interrupt-controller/
H A Dmips-gic.h4 #include <dt-bindings/interrupt-controller/irq.h>
H A Darm-gic.h8 #include <dt-bindings/interrupt-controller/irq.h>
10 /* interrupt specifier cell 0 */
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/interrupt-controller/
H A Dmips-gic.h4 #include <dt-bindings/interrupt-controller/irq.h>
H A Darm-gic.h8 #include <dt-bindings/interrupt-controller/irq.h>
10 /* interrupt specifier cell 0 */
/linux-4.1.27/include/dt-bindings/interrupt-controller/
H A Dmips-gic.h4 #include <dt-bindings/interrupt-controller/irq.h>
H A Darm-gic.h8 #include <dt-bindings/interrupt-controller/irq.h>
10 /* interrupt specifier cell 0 */
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A Dregs-rtc.h16 #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
17 #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
18 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
19 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
H A Dirqs.h21 #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
22 #define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */
23 #define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */
25 #define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */
27 #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
39 #define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */
41 #define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */
59 #define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */
62 #define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */
/linux-4.1.27/arch/powerpc/sysdev/
H A Dmpc8xx_pic.h5 #include <linux/interrupt.h>
11 * Some internal interrupt registers use an 8-bit mask for the interrupt
H A Dxilinx_intc.c13 * This is a driver for the interrupt controller typically found in
16 * The interrupt sense levels are hard coded into the FPGA design with
49 /* The following table allows the interrupt type, edge or level,
50 * to be cached after being read from the device tree until the interrupt
55 /* Map the interrupt type from the device tree to the interrupt types
56 * used by the interrupt subsystem
66 * The interrupt controller is setup such that it doesn't work well with
67 * the level interrupt handler in the kernel because the handler acks the
68 * interrupt before calling the application interrupt handler. To deal with
154 /* keep a copy of the interrupt type til the interrupt is mapped xilinx_intc_xlate()
158 /* Xilinx uses 2 interrupt entries, the 1st being the h/w xilinx_intc_xlate()
159 * interrupt number, the 2nd being the interrupt type, edge or level xilinx_intc_xlate()
200 /* Setup interrupt controller */ xilinx_intc_init()
223 * Support code for cascading to 8259 interrupt controllers
233 /* Let xilinx_intc end the interrupt */ xilinx_i8259_cascade()
249 pr_err("virtex_ml510: Failed to map cascade interrupt\n"); xilinx_i8259_setup_cascade()
275 * Initialize master Xilinx interrupt controller
281 /* find top level interrupt controller */ for_each_matching_node()
H A Di8259.c2 * i8259 interrupt controller driver.
12 #include <linux/interrupt.h>
30 * Acknowledge the IRQ using either the PCI host bridge's interrupt
47 /* Perform an interrupt acknowledge cycle on controller 1. */ i8259_irq()
52 * Interrupt is cascaded so perform interrupt i8259_irq()
62 * This may be a spurious interrupt. i8259_irq()
64 * Read the interrupt status register (ISR). If the most i8259_irq()
66 * interrupt. i8259_irq()
222 * @intack_addr: PCI interrupt acknowledge (real) address which will return
236 /* init master interrupt controller */ i8259_init()
242 /* init slave interrupt controller */ i8259_init()
258 /* Set interrupt masks */ i8259_init()
283 printk(KERN_INFO "i8259 legacy interrupt controller initialized\n"); i8259_init()
H A Dfsl_msi.h40 u32 ibs_shift; /* Shift of interrupt bit select */
41 u32 srs_shift; /* Shift of the shared interrupt register select */
/linux-4.1.27/arch/m68k/amiga/
H A Damiints.c2 * Amiga Linux interrupt handling code
10 #include <linux/interrupt.h>
22 * Enable/disable a particular machine specific interrupt source.
23 * Note that this may affect other interrupts in case of a shared interrupt.
25 * internal data, that may not be changed by the interrupt at the same time.
46 * The builtin Amiga hardware interrupt handlers.
53 /* if serial transmit buffer empty, interrupt */ ami_int1()
59 /* if floppy disk transfer complete, interrupt */ ami_int1()
65 /* if software interrupt set, interrupt */ ami_int1()
76 /* if a blitter interrupt */ ami_int3()
82 /* if a copper interrupt */ ami_int3()
88 /* if a vertical blank interrupt */ ami_int3()
99 /* if audio 0 interrupt */ ami_int4()
105 /* if audio 1 interrupt */ ami_int4()
111 /* if audio 2 interrupt */ ami_int4()
117 /* if audio 3 interrupt */ ami_int4()
128 /* if serial receive buffer full interrupt */ ami_int5()
130 /* acknowledge of IF_RBF must be done by the serial interrupt */ ami_int5()
134 /* if a disk sync interrupt */ ami_int5()
167 /* turn off all interrupts and enable the master interrupt bit */ amiga_init_IRQ()
/linux-4.1.27/arch/m68k/include/asm/
H A Damigaints.h2 ** amigaints.h -- Amiga Linux interrupt handling structs and prototypes
43 /* copper interrupt */
46 /* vertical blanking interrupt */
49 /* Blitter done interrupt */
58 /* CIA interrupt sources */
75 #define IF_INTEN 0x4000 /* master interrupt bit in INT* registers */
76 #define IF_EXTER 0x2000 /* external level 6 and CIA B interrupt */
77 #define IF_DSKSYN 0x1000 /* disk sync interrupt */
78 #define IF_RBF 0x0800 /* serial receive buffer full interrupt */
79 #define IF_AUD3 0x0400 /* audio channel 3 done interrupt */
80 #define IF_AUD2 0x0200 /* audio channel 2 done interrupt */
81 #define IF_AUD1 0x0100 /* audio channel 1 done interrupt */
82 #define IF_AUD0 0x0080 /* audio channel 0 done interrupt */
83 #define IF_BLIT 0x0040 /* blitter done interrupt */
84 #define IF_VERTB 0x0020 /* vertical blanking interrupt */
85 #define IF_COPER 0x0010 /* copper interrupt */
86 #define IF_PORTS 0x0008 /* external level 2 and CIA A interrupt */
87 #define IF_SOFT 0x0004 /* software initiated interrupt */
89 #define IF_TBE 0x0001 /* serial transmit buffer empty interrupt */
91 /* CIA interrupt control register bits */
103 /* to access the interrupt control registers of CIA's use only
H A Dmac_baboon.h19 * bit 1: IDE interrupt active?
24 short mb_ifr; /* (0xD8) media bay interrupt flags register:
27 * bit 1: IDE controller interrupt
28 * bit 2: media bay status change interrupt
H A Dirq.h9 * With EtherNAT add-on card on Atari, the highest interrupt
37 * General interrupt sources are the level 1-7.
38 * Adding an interrupt service routine for one of these sources
40 * Each one is called in succession. Each individual interrupt
47 #define IRQ_AUTO_1 1 /* level 1 interrupt */
48 #define IRQ_AUTO_2 2 /* level 2 interrupt */
49 #define IRQ_AUTO_3 3 /* level 3 interrupt */
50 #define IRQ_AUTO_4 4 /* level 4 interrupt */
51 #define IRQ_AUTO_5 5 /* level 5 interrupt */
52 #define IRQ_AUTO_6 6 /* level 6 interrupt */
53 #define IRQ_AUTO_7 7 /* level 7 interrupt (non-maskable) */
H A Dq40ints.h2 * contains some Q40 related interrupt definitions
12 /* masks for interrupt regiosters*/
H A Datari_stdma.h6 #include <linux/interrupt.h>
H A Dmcfintc.h16 * Most of the older ColdFire parts use the same simple interrupt
22 * related to) the actual interrupt number they use. So knowing the IRQ
24 * interrupt control purposes.
46 * IMR bit position definitions. Not all ColdFire parts with this interrupt
47 * controller actually support all of these interrupt sources. But the bit
72 * There is no one-is-one correspondance between the interrupt number (irq)
H A DMC68EZ328.h228 #define SPI_IRQ_NUM 0 /* SPI interrupt */
229 #define TMR_IRQ_NUM 1 /* Timer interrupt */
230 #define UART_IRQ_NUM 2 /* UART interrupt */
231 #define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
232 #define RTC_IRQ_NUM 4 /* RTC interrupt */
254 #define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
255 #define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
256 #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
257 #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
258 #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
283 #define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
284 #define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
285 #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
286 #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
287 #define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
289 #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
312 #define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
313 #define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
314 #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
315 #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
316 #define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
318 #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
1049 #define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */
1050 #define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occurred */
1074 #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1075 #define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
1076 #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1077 #define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
1078 #define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
1079 #define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */
1080 #define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */
1081 #define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */
1082 #define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */
1083 #define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */
1084 #define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */
1085 #define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */
1086 #define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */
1094 #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
1095 #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1096 #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
1097 #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1098 #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
1099 #define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
1100 #define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */
1101 #define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */
1102 #define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */
1103 #define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */
1104 #define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */
1105 #define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */
1106 #define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */
1107 #define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */
H A Dsun3ints.h2 * sun3ints.h -- Linux/Sun3 interrupt handling code definitions
15 #include <linux/interrupt.h>
/linux-4.1.27/arch/m32r/include/asm/opsput/
H A Dopsput_lan.h29 * ICUCR3: control register for CFIREQ# interrupt
30 * ICUCR4: control register for CFC Card insert interrupt
31 * ICUCR5: control register for CFC Card eject interrupt
32 * ICUCR6: control register for external interrupt
33 * ICUCR11: control register for MMC Card insert/eject interrupt
34 * ICUCR13: control register for SC error interrupt
35 * ICUCR14: control register for SC receive interrupt
36 * ICUCR15: control register for SC send interrupt
37 * ICUCR16: control register for SIO0 receive interrupt
38 * ICUCR17: control register for SIO0 send interrupt
/linux-4.1.27/arch/mn10300/include/asm/
H A Dintctl-regs.h1 /* MN10300 On-board interrupt controller registers
37 /* non-maskable interrupt control */
40 #define NMICR_NMIF 0x0001 /* NMI pin interrupt flag */
44 /* maskable interrupt control */
45 #define GxICR_DETECT 0x0001 /* interrupt detect flag */
46 #define GxICR_REQUEST 0x0010 /* interrupt request flag */
47 #define GxICR_ENABLE 0x0100 /* interrupt enable flag */
48 #define GxICR_LEVEL 0x7000 /* interrupt priority level */
67 #define XIRQxICR(X) GxICR((X)) /* external interrupt control regs */
H A Dcpu-regs.h42 #define EPSW_IM 0x00000700 /* interrupt mode */
43 #define EPSW_IM_0 0x00000000 /* interrupt mode 0 */
44 #define EPSW_IM_1 0x00000100 /* interrupt mode 1 */
45 #define EPSW_IM_2 0x00000200 /* interrupt mode 2 */
46 #define EPSW_IM_3 0x00000300 /* interrupt mode 3 */
47 #define EPSW_IM_4 0x00000400 /* interrupt mode 4 */
48 #define EPSW_IM_5 0x00000500 /* interrupt mode 5 */
49 #define EPSW_IM_6 0x00000600 /* interrupt mode 6 */
50 #define EPSW_IM_7 0x00000700 /* interrupt mode 7 */
51 #define EPSW_IE 0x00000800 /* interrupt enable */
55 #define EPSW_NMID 0x00020000 /* nonmaskable interrupt disable */
59 #define EPSW_IM_SHIFT 8 /* EPSW_IM_SHIFT determines the interrupt mode */
124 /* interrupt/exception control registers */
125 #define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */
126 #define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */
127 #define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */
128 #define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */
129 #define IVAR4 __SYSREG(0xc0000010, u16) /* interrupt vector 4 */
130 #define IVAR5 __SYSREG(0xc0000014, u16) /* interrupt vector 5 */
131 #define IVAR6 __SYSREG(0xc0000018, u16) /* interrupt vector 6 */
135 #define TBR_INT_CODE 0x00ffffff /* interrupt code */
139 #define sISR __SYSREG(0xc0000044, u32) /* Supervisor interrupt status */
140 #define sISR_IRQICE 0x00000001 /* ICE interrupt */
141 #define sISR_ISTEP 0x00000002 /* single step interrupt */
144 #define sISR_PIEXE 0x00000010 /* program interrupt */
146 #define sISR_IBREAK 0x00000040 /* instraction break interrupt */
147 #define sISR_DBSRL 0x00000080 /* debug serial interrupt */
148 #define sISR_PERIDB 0x00000100 /* peripheral debug interrupt */
150 #define sISR_OBREAK 0x00000400 /* operand break interrupt */
154 #define sISR_DBG 0x00008000 /* debug reserved interrupt */
322 #define ASR_IW 0x00000002 /* interrupt */
327 #define ASRU_IW ASR_IW /* interrupt */
H A Drtc-regs.h30 #define RTCRA_RS 0x0f /* periodic timer interrupt cycle setting */
58 #define RTCRB_UIE 0x10 /* update interrupt disable */
59 #define RTCRB_AIE 0x20 /* alarm interrupt disable */
60 #define RTCRB_PIE 0x40 /* periodic interrupt disable */
64 #define RTSRC_UF 0x10 /* update end interrupt flag */
65 #define RTSRC_AF 0x20 /* alarm interrupt flag */
66 #define RTSRC_PF 0x40 /* periodic interrupt flag */
67 #define RTSRC_IRQF 0x80 /* interrupt flag */
H A Dexceptions.h38 EXCEP_TRAP = 0x000128, /* program interrupt (PI instruction) */
63 EXCEP_NMI = 0x000248, /* non-maskable interrupt */
64 EXCEP_IRQ_LEVEL0 = 0x000280, /* level 0 maskable interrupt */
65 EXCEP_IRQ_LEVEL1 = 0x000288, /* level 1 maskable interrupt */
66 EXCEP_IRQ_LEVEL2 = 0x000290, /* level 2 maskable interrupt */
67 EXCEP_IRQ_LEVEL3 = 0x000298, /* level 3 maskable interrupt */
68 EXCEP_IRQ_LEVEL4 = 0x0002a0, /* level 4 maskable interrupt */
69 EXCEP_IRQ_LEVEL5 = 0x0002a8, /* level 5 maskable interrupt */
70 EXCEP_IRQ_LEVEL6 = 0x0002b0, /* level 6 maskable interrupt */
H A Dirq.h1 /* MN10300 Hardware interrupt definitions
21 /* this number is used when no interrupt has been assigned */
/linux-4.1.27/include/linux/amba/
H A Dserial.h54 #define UART011_RIS 0x3c /* Raw interrupt status. */
55 #define UART011_MIS 0x40 /* Masked interrupt status. */
66 #define ST_UART011_ABIMSC 0x15C /* Autobaud interrupt mask/clear register. */
152 #define UART011_OEIM (1 << 10) /* overrun error interrupt mask */
153 #define UART011_BEIM (1 << 9) /* break error interrupt mask */
154 #define UART011_PEIM (1 << 8) /* parity error interrupt mask */
155 #define UART011_FEIM (1 << 7) /* framing error interrupt mask */
156 #define UART011_RTIM (1 << 6) /* receive timeout interrupt mask */
157 #define UART011_TXIM (1 << 5) /* transmit interrupt mask */
158 #define UART011_RXIM (1 << 4) /* receive interrupt mask */
159 #define UART011_DSRMIM (1 << 3) /* DSR interrupt mask */
160 #define UART011_DCDMIM (1 << 2) /* DCD interrupt mask */
161 #define UART011_CTSMIM (1 << 1) /* CTS interrupt mask */
162 #define UART011_RIMIM (1 << 0) /* RI interrupt mask */
164 #define UART011_OEIS (1 << 10) /* overrun error interrupt status */
165 #define UART011_BEIS (1 << 9) /* break error interrupt status */
166 #define UART011_PEIS (1 << 8) /* parity error interrupt status */
167 #define UART011_FEIS (1 << 7) /* framing error interrupt status */
168 #define UART011_RTIS (1 << 6) /* receive timeout interrupt status */
169 #define UART011_TXIS (1 << 5) /* transmit interrupt status */
170 #define UART011_RXIS (1 << 4) /* receive interrupt status */
171 #define UART011_DSRMIS (1 << 3) /* DSR interrupt status */
172 #define UART011_DCDMIS (1 << 2) /* DCD interrupt status */
173 #define UART011_CTSMIS (1 << 1) /* CTS interrupt status */
174 #define UART011_RIMIS (1 << 0) /* RI interrupt status */
176 #define UART011_OEIC (1 << 10) /* overrun error interrupt clear */
177 #define UART011_BEIC (1 << 9) /* break error interrupt clear */
178 #define UART011_PEIC (1 << 8) /* parity error interrupt clear */
179 #define UART011_FEIC (1 << 7) /* framing error interrupt clear */
180 #define UART011_RTIC (1 << 6) /* receive timeout interrupt clear */
181 #define UART011_TXIC (1 << 5) /* transmit interrupt clear */
182 #define UART011_RXIC (1 << 4) /* receive interrupt clear */
183 #define UART011_DSRMIC (1 << 3) /* DSR interrupt clear */
184 #define UART011_DCDMIC (1 << 2) /* DCD interrupt clear */
185 #define UART011_CTSMIC (1 << 1) /* CTS interrupt clear */
186 #define UART011_RIMIC (1 << 0) /* RI interrupt clear */
/linux-4.1.27/arch/x86/kvm/
H A Dirq.c2 * irq.c: API for in kernel interrupt controller
41 * check if there is pending interrupt from
53 * check if there is injectable interrupt:
54 * when virtual interrupt delivery enabled,
55 * interrupt from apic will handled by hardware,
61 return v->arch.interrupt.pending; kvm_cpu_has_injectable_intr()
73 * check if there is pending interrupt without
79 return v->arch.interrupt.pending; kvm_cpu_has_interrupt()
89 * Read pending interrupt(from non-APIC source)
100 * Read pending interrupt vector and intack.
107 return v->arch.interrupt.nr; kvm_cpu_get_interrupt()
/linux-4.1.27/arch/x86/include/asm/
H A Dedac.h4 /* ECC atomic, DMA, SMP and interrupt safe scrub function */
12 * are interrupt, DMA and SMP safe. atomic_scrub()
H A Dmath_emu.h8 following a device-not-present interrupt, part of it saved
H A Dmshyperv.h5 #include <linux/interrupt.h>
/linux-4.1.27/arch/mips/include/asm/
H A Di8259.h4 * i8259A interrupt definitions.
46 * Do the traditional i8259 interrupt polling thing. This is for the few
47 * cases where no better interrupt acknowledge method is available and we
56 /* Perform an interrupt acknowledge cycle on controller 1. */ i8259_irq()
61 * Interrupt is cascaded so perform interrupt i8259_irq()
70 * This may be a spurious interrupt. i8259_irq()
72 * Read the interrupt status register (ISR). If the most i8259_irq()
74 * interrupt. i8259_irq()
H A Dedac.h6 /* ECC atomic, DMA, SMP and interrupt safe scrub function */
17 * so we are interrupt, DMA and SMP safe. atomic_scrub()
H A Dhw_irq.h16 * interrupt-retrigger: NOP for now. This may not be appropriate for all
/linux-4.1.27/include/linux/
H A Dirqreturn.h6 * @IRQ_NONE interrupt was not from this device
7 * @IRQ_HANDLED interrupt was handled by this device
H A Dioc4.h12 #include <linux/interrupt.h>
62 } sio_ir; /* Serial interrupt state */
74 } other_ir; /* Other interrupt state */
75 union ioc4_sio_int sio_ies; /* Serial interrupt enable set */
76 union ioc4_other_int other_ies; /* Other interrupt enable set */
77 union ioc4_sio_int sio_iec; /* Serial interrupt enable clear */
78 union ioc4_other_int other_iec; /* Other interrupt enable clear */
100 } int_out; /* External interrupt output control */
131 #define IOC4_GPCR_DIR_0 0x01 /* External interrupt output */
132 #define IOC4_GPCR_DIR_1 0x02 /* External interrupt input */
142 #define IOC4_GPCR_EDGE_1 0x02 /* External interrupt input */
H A Dds17287rtc.h50 /* interrupt causes */
59 #define DS_XCTRL4B_RIE 0x04 /* ram clear interrupt enable */
60 #define DS_XCTRL4B_WFE 0x02 /* wake up alarm interrupt enable */
61 #define DS_XCTRL4B_KFE 0x01 /* kickstart interrupt enable */
63 /* interrupt enable bits */
/linux-4.1.27/arch/mips/include/asm/mach-pmcs-msp71xx/
H A Dmsp_cic_int.h2 * Defines for the MSP interrupt controller.
31 * We attempt to keep the interrupt numbers as consistent as possible
56 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
58 * interrupt routine. For now, just use hard-coded values.
62 /* External interrupt 0 */
64 /* External interrupt 1 */
66 /* External interrupt 2 */
68 /* External interrupt 3 */
70 /* CPU interface interrupt */
72 /* External interrupt 4 */
78 /* External interrupt 5 */
80 /* TDM interrupt */
88 /* Peripheral interrupt */
104 /* External interrupt 5 */
120 /* External interrupt 5 */
122 /* VPE0 Software interrupt */
124 /* VPE0 Software interrupt */
127 * IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
H A Dmsp_slp_int.h2 * Defines for the MSP interrupt controller.
31 * and are assigned the interrupt range 0-7. The second level is the SLM
32 * interrupt controller and is assigned the range 8-39. The third level
35 * relevant subsystems so the core interrupt code needs only concern
54 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
56 * interrupt routine. For now, just use hard-coded values.
60 /* External interrupt 0 */
62 /* External interrupt 1 */
64 /* External interrupt 2 */
66 /* External interrupt 3 */
72 * Some MSP produces have this interrupt labelled as Voice and some are *
79 /* TDM interrupt */
87 /* Peripheral interrupt */
117 * IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
H A Dmsp_int.h2 * Defines for the MSP interrupt handlers.
29 * The PMC-Sierra MSP product line has at least two different interrupt
30 * controllers, the SLP register based scheme and the CIC interrupt
40 #error "What sort of interrupt controller does *your* MSP have?"
/linux-4.1.27/arch/x86/include/asm/trace/
H A Dirq_vectors.h42 * local_timer - called when entering/exiting a local timer interrupt
63 * x86_platform_ipi - called when entering/exiting a x86 platform ipi interrupt
69 * irq_work - called when entering/exiting a irq work interrupt
86 * call_function - called when entering/exiting a call function interrupt
93 * single interrupt vector handler
98 * threshold_apic - called when entering/exiting a threshold apic interrupt
104 * thermal_apic - called when entering/exiting a thermal apic interrupt
/linux-4.1.27/arch/mips/include/asm/mach-pnx833x/
H A Dirq.h28 * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
29 * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
32 * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
33 * connected to PIC, which uses core hardware interrupt 2, and also
34 * a timer interrupt through hardware interrupt 5.
35 * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
H A Dirq-mapping.h29 * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
30 * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
33 * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
34 * connected to PIC, which uses core hardware interrupt 2, and also
35 * a timer interrupt through hardware interrupt 5.
36 * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
/linux-4.1.27/arch/m68k/coldfire/
H A Dintc.c2 * intc.c -- support for the old ColdFire interrupt controller
14 #include <linux/interrupt.h>
23 * The irq numbers are either based on "level" of interrupt or fixed
24 * for an autovector-able interrupt. So we keep a local data structure
31 * Define the miniumun and maximum external interrupt numbers.
32 * This is also used as the "level" interrupt numbers.
95 * interrupt controller. That is, the device raising the interrupt can also
96 * supply the vector number to interrupt through. The AVR register of the
97 * interrupt controller enables or disables this for each external interrupt,
99 * the interrupt system API's, and needs to be done by the driver that
H A Dintc-2.c4 * General interrupt controller code for the many ColdFire cores that use
5 * interrupt controllers with 63 interrupt sources, organized as 56 fully-
6 * programmable + 7 fixed-level interrupt sources. This includes the 523x
23 #include <linux/interrupt.h>
41 #define EINT1 65 /* EDGE Port interrupt 1 */
42 #define EINT7 71 /* EDGE Port interrupt 7 */
106 * traditional priority interrupt scheme of the m68k/ColdFire. This
107 * only needs to be set once for an interrupt, and we will never change
136 /* Set EPORT line as interrupt source */ intc_irq_startup()
197 /* Mask all interrupt sources */ init_IRQ()
H A Dintc-525x.c15 #include <linux/interrupt.h>
79 /* set the interrupt base for the second interrupt controller */ mcf_intc2_init()
82 /* GPIO interrupt sources */ mcf_intc2_init()
H A Dintc-5272.c2 * intc.c -- interrupt controller or ColdFire 5272 SoC
14 #include <linux/interrupt.h>
23 * The 5272 ColdFire interrupt controller is nothing like any other
24 * ColdFire interrupt controller - it truly is completely different.
35 * internal interrupt sources which are level triggered). Which means
77 * The act of masking the interrupt also has a side effect of 'ack'ing
78 * an interrupt on this irq (for the external irqs). So this mask function
144 * of masking an interrupt.
165 /* Mask all interrupt sources */ init_IRQ()
H A Dintc-simr.c16 #include <linux/interrupt.h>
33 #define EINT1 65 /* EDGE Port interrupt 1 */
34 #define EINT4 66 /* EDGE Port interrupt 4 */
35 #define EINT7 67 /* EDGE Port interrupt 7 */
51 #define EINT1 65 /* EDGE Port interrupt 1 */
52 #define EINT7 71 /* EDGE Port interrupt 7 */
62 * There maybe one, two or three interrupt control units, each has 64
112 /* Set EPORT line as interrupt source */ intc_irq_startup()
181 /* Mask all interrupt sources */ init_IRQ()
H A Dintc-5249.c14 #include <linux/interrupt.h>
52 /* GPIO interrupt sources */ mcf_intc2_init()
/linux-4.1.27/drivers/isdn/sc/
H A DMakefile10 ioctl.o interrupt.o message.o timer.o
/linux-4.1.27/arch/powerpc/kernel/
H A Dswsusp_64.c12 #include <linux/interrupt.h>
/linux-4.1.27/arch/blackfin/mach-common/
H A DMakefile7 interrupt.o arch_checks.o ints-priority.o
H A Dinterrupt.S32 /* Common interrupt entry code. First we do CLI, then push
35 * R0 contains the interrupt number, while R1 may contain the value of IPEND,
144 /* interrupt routine for ivhw - 5 */
239 /* interrupt routine for core timer - 6 */
243 /* interrupt routine for evt7 - 7 */
260 /* interrupt routine for system_call - 15 */
274 * level to EVT14 to prepare the caller for a normal interrupt
280 * priority domain after the pipeline delivered an interrupt,
283 * nested on the Blackfin, so we have to fake an interrupt return
286 * - before branching to __ipipe_sync_root(), in order to play any interrupt
291 * to using a threaded interrupt model for the Linux kernel.
312 /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
316 /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
/linux-4.1.27/arch/frv/kernel/
H A Dpm-mb93093.c16 #include <linux/interrupt.h>
28 * Setup interrupt masks, etc to enable wakeup by power switch
32 /* mask all but FPGA interrupt sources. */ mb93093_power_switch_setup()
38 * Cleanup interrupt masks, etc after wakeup by power switch
/linux-4.1.27/arch/m68k/mac/
H A Doss.c7 * VIA chip with prorammable interrupt levels.
9 * 990502 (jmt) - Major rewrite for new interrupt architecture as well as some
12 * to mostly match the A/UX interrupt scheme supported on the
48 /* do this by setting the source's interrupt level to zero. */ oss_init()
97 * Unlike the VIA/RBV this is on its own autovector interrupt level.
128 * Register the OSS and NuBus interrupt dispatchers.
150 /* OSS_VIA1 gets enabled here because it has no machspec interrupt. */ oss_register_interrupts()
155 * Enable an OSS interrupt
158 * just maps the machspec interrupt numbers to the right OSS interrupt
159 * source (if the OSS handles that interrupt) and then sets the interrupt
160 * level for that source to nonzero, thus enabling the interrupt.
193 * Disable an OSS interrupt
195 * Same as above except we set the source's interrupt level to zero,
196 * to disable the interrupt.
H A Dmacints.c7 * interrupts with exception vectors 0x19-0x1f). The following interrupt levels
10 * - slot 0: one second interrupt (CA2)
42 * an alternate interrupt mapping, as used by A/UX. It spreads ethernet and
53 * For OSS Macintoshes (IIfx only), we apply an interrupt mapping similar to
72 * - slot 1: SCC channel A interrupt
73 * - slot 2: SCC channel B interrupt
80 * Finally we have good 'ole level 7, the non-maskable interrupt:
85 * The current interrupt logic looks something like this:
89 * VIA/RBV/OSS/PSC chips) to determine the actual interrupt source. Using
90 * this information a machspec interrupt number is generated by placing the
91 * index of the interrupt hardware into the low three bits and the original
92 * autovector interrupt number in the upper 5 bits. The handlers for the
93 * resulting machspec interrupt are then called.
99 * then forms a new machspec interrupt number as above with the slot number
101 * bits. The handlers for this new machspec interrupt number are then
105 * case. They're hidden behind the Nubus slot $C interrupt thus adding a
113 #include <linux/interrupt.h>
157 /* Make sure the SONIC interrupt is cleared or things get ugly */ mac_init_IRQ()
191 * mac_irq_enable - enable an interrupt source
192 * mac_irq_disable - disable an interrupt source
/linux-4.1.27/arch/arm/mach-shmobile/
H A Dirqs.h8 #define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */
/linux-4.1.27/kernel/irq/
H A Dautoprobe.c6 * This file contains the interrupt probing code and driver APIs.
11 #include <linux/interrupt.h>
18 * Autodetection depends on the fact that any interrupt that
20 * "IRQS_WAITING" cleared and the interrupt disabled.
25 * probe_irq_on - begin an interrupt autodetect
27 * Commence probing for an interrupt. The interrupts are scanned
28 * and a mask of potential interrupt lines is returned.
107 * probe_irq_mask - scan a bitmap of interrupt lines
110 * Scan the interrupt lines and return a bitmap of active
111 * autodetect interrupts. The interrupt probe logic state
142 * probe_irq_off - end an interrupt autodetect
145 * Scans the unused interrupt lines and returns the line which
146 * appears to have triggered the interrupt. If no interrupt was
147 * found then zero is returned. If more than one interrupt is
151 * The interrupt probe logic state is returned to its previous
H A Ddummychip.c5 * This file contains the dummy interrupt chip implementation
7 #include <linux/interrupt.h>
49 * real dumb interrupt sources
H A Dchip.c7 * This file contains the core interrupt handling code, for irq-chip
16 #include <linux/interrupt.h>
75 * @data: Pointer to interrupt specific data
219 * irq_disable - Mark interrupt disabled
223 * use a lazy disable approach. That means we mark the interrupt
226 * common case where no interrupt happens after we marked it
227 * disabled. If an interrupt happens, then the interrupt flow
301 * @irq: the interrupt number
303 * Handle interrupts which are nested into a threaded interrupt
353 * If the interrupt is not in progress and is not an armed irq_may_run()
354 * wakeup interrupt, proceed. irq_may_run()
360 * If the interrupt is an armed wakeup source, mark it pending irq_may_run()
375 * @irq: the interrupt number
376 * @desc: the interrupt description structure for this irq
378 * Simple interrupts are either sent from a demultiplexing interrupt
379 * handler or come from hardware, where no interrupt hardware control
418 * spurious interrupt or a primary handler handling it cond_unmask_irq()
428 * @irq: the interrupt number
429 * @desc: the interrupt description structure for this irq
432 * the active level. This may require to mask the interrupt and unmask
434 * interrupt line is back to inactive.
485 * spurious interrupt or a primary handler handling it cond_unmask_eoi_irq()
499 * @irq: the interrupt number
500 * @desc: the interrupt description structure for this irq
503 * call when the interrupt has been serviced. This enables support
504 * for modern forms of interrupt handlers, which handle the flow
549 * @irq: the interrupt number
550 * @desc: the interrupt description structure for this irq
555 * interrupt can happen on the same source even before the first one
557 * might be necessary to disable (mask) the interrupt depending on the
558 * controller hardware. This requires to reenable the interrupt inside
621 * @irq: the interrupt number
622 * @desc: the interrupt description structure for this irq
668 * @irq: the interrupt number
669 * @desc: the interrupt description structure for this irq
691 * @irq: the interrupt number
692 * @desc: the interrupt description structure for this irq
741 * cannot enable/startup the interrupt at this point. __irq_set_handler()
879 * irq_chip_ack_parent - Acknowledge the parent interrupt
880 * @data: Pointer to interrupt specific data
889 * irq_chip_mask_parent - Mask the parent interrupt
890 * @data: Pointer to interrupt specific data
899 * irq_chip_unmask_parent - Unmask the parent interrupt
900 * @data: Pointer to interrupt specific data
909 * irq_chip_eoi_parent - Invoke EOI on the parent interrupt
910 * @data: Pointer to interrupt specific data
919 * irq_chip_set_affinity_parent - Set affinity on the parent interrupt
920 * @data: Pointer to interrupt specific data
937 * irq_chip_set_type_parent - Set IRQ type on the parent interrupt
938 * @data: Pointer to interrupt specific data
954 * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware
955 * @data: Pointer to interrupt specific data
957 * Iterate through the domain hierarchy of the interrupt and check
970 * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
971 * @data: Pointer to interrupt specific data
988 * @data: Pointer to interrupt specific data
H A Ddevres.c2 #include <linux/interrupt.h>
29 * devm_request_threaded_irq - allocate an interrupt line for a managed device
30 * @dev: device to request interrupt for
33 * @thread_fn: function to be called in a threaded interrupt context. NULL
76 * devm_request_any_context_irq - allocate an interrupt line for a managed device
77 * @dev: device to request interrupt for
80 * @thread_fn: function to be called in a threaded interrupt context. NULL
121 * devm_free_irq - free an interrupt
122 * @dev: device to free interrupt for
H A Dpm.c11 #include <linux/interrupt.h>
102 * suspend_device_irqs - disable all currently enabled interrupt lines
110 * suspendable via an interrupt request with the flag IRQF_NO_SUSPEND
115 * interrupt and notifies the pm core about the wakeup.
143 /* Force resume the interrupt? */ resume_irq()
174 * irq_pm_syscore_ops - enable interrupt lines early
176 * Enable all interrupt lines with %IRQF_EARLY_RESUME set.
196 * resume_device_irqs - enable interrupt lines disabled by suspend_device_irqs()
198 * Enable all non-%IRQF_EARLY_RESUME interrupt lines previously
/linux-4.1.27/include/asm-generic/
H A Dhw_irq.h4 * hw_irq.h has internal declarations for the low-level interrupt
H A Dmsi.h13 * struct msi_alloc_info - Default structure for MSI interrupt allocation.
15 * @hwirq: Associated hw interrupt number in the domain
H A Dirqflags.h13 /* read interrupt enabled status */
18 /* set interrupt enabled status */
58 /* test hardware interrupt enable bit */
H A Dsimd.h9 * taking an interrupt, !in_interrupt() should be a reasonable default.
/linux-4.1.27/include/linux/bcma/
H A Dbcma_driver_mips.h5 /* which sbflags get routed to mips interrupt 1 */
8 /* which sbflags get routed to mips interrupt 2 */
11 /* which sbflags get routed to mips interrupt 3 */
14 /* which sbflags get routed to mips interrupt 4 */
/linux-4.1.27/include/linux/iio/
H A Dtriggered_buffer.h4 #include <linux/interrupt.h>
/linux-4.1.27/include/linux/input/
H A Dauo-pixcir-ts.h28 * periodical: interrupt is asserted periodicaly
29 * compare coordinates: interrupt is asserted when coordinates change
30 * indicate touch: interrupt is asserted during touch
37 * @gpio_int interrupt gpio
H A Dpixcir_ts.h29 * periodical: interrupt is asserted periodicaly
30 * diff coordinates: interrupt is asserted when coordinates change
31 * level on touch: interrupt level asserted during touch
32 * pulse on touch: interrupt pulse asserted druing touch
/linux-4.1.27/arch/x86/kernel/cpu/mcheck/
H A Dthreshold.c4 #include <linux/interrupt.h>
15 printk(KERN_ERR "Unexpected threshold interrupt at vector %x\n", default_threshold_interrupt()
/linux-4.1.27/arch/unicore32/include/mach/
H A Dregs-rtc.h30 * ALarm interrupt Enable RTC_RTSR_ALE
34 * 1 Hz clock interrupt Enable RTC_RTSR_HZE
/linux-4.1.27/include/uapi/linux/
H A Dhpet.h16 #define HPET_IE_ON _IO('h', 0x01) /* interrupt on */
17 #define HPET_IE_OFF _IO('h', 0x02) /* interrupt off */
/linux-4.1.27/arch/mips/pmcs-msp71xx/
H A Dmsp_irq_slp.c14 #include <linux/interrupt.h>
27 /* check for PER interrupt range */ unmask_msp_slp_irq()
38 /* check for PER interrupt range */ mask_msp_slp_irq()
46 * While we ack the interrupt interrupts are disabled and thus we don't need
53 /* check for PER interrupt range */ ack_msp_slp_irq()
91 /* check for PER interrupt */ msp_slp_irq_dispatch()
97 /* check for spurious interrupt */ msp_slp_irq_dispatch()
99 printk(KERN_ERR "Spurious %s interrupt?\n", msp_slp_irq_dispatch()
H A Dmsp_irq.c14 #include <linux/interrupt.h>
34 /* vectored interrupt implementation */
46 * and are assigned the interrupt range 0-7. The second level is the SLM sec_int_dispatch()
47 * interrupt controller and is assigned the range 8-39. The third level sec_int_dispatch()
50 * relevant subsystems so the core interrupt code needs only concern sec_int_dispatch()
62 * jump to the correct interrupt routine plat_irq_dispatch()
124 /* assume we'll be using vectored interrupt mode except in UP mode*/ arch_init_irq()
128 /* initialize the 1st-level CPU based interrupt controller */ arch_init_irq()
150 * Setup the 2nd-level SLP register based interrupt controller. arch_init_irq()
/linux-4.1.27/arch/arm/mach-mmp/include/mach/
H A Dregs-rtc.h18 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
19 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
/linux-4.1.27/arch/mips/dec/
H A Dtc.c74 tdev->interrupt = dec_interrupt[DEC_IRQ_TC0]; tc_device_get_irq()
77 tdev->interrupt = dec_interrupt[DEC_IRQ_TC1]; tc_device_get_irq()
80 tdev->interrupt = dec_interrupt[DEC_IRQ_TC2]; tc_device_get_irq()
86 tdev->interrupt = dec_interrupt[DEC_IRQ_TC5]; tc_device_get_irq()
89 tdev->interrupt = dec_interrupt[DEC_IRQ_TC6]; tc_device_get_irq()
92 tdev->interrupt = -1; tc_device_get_irq()
H A Dreset.c7 #include <linux/interrupt.h>
/linux-4.1.27/include/linux/spi/
H A Dmcp23s08.h25 /* Marks the device as a interrupt controller.
26 * NOTE: The interrupt functionality is only supported for i2c
33 * with two interrupt outputs (these are the devices ending with 17 and
35 * IO 8-15 are bank 2. These chips have two different interrupt outputs:
38 * occurred on. If it is not set, the interrupt are only generated for
40 * On devices with only one interrupt output this property is useless.
/linux-4.1.27/arch/mips/kernel/
H A Dcevt-r4k.c10 #include <linux/interrupt.h>
41 * Possibly handle a performance counter interrupt.
42 * Return true if the timer interrupt should not be checked
47 * The performance counter overflow interrupt may be shared with the handle_perf_irq()
48 * timer interrupt (cp0_perfcount_irq < 0). If it is and a handle_perf_irq()
50 * and we can't reliably determine if a counter interrupt has also handle_perf_irq()
51 * happened (!r2) then don't check for a timer interrupt. handle_perf_irq()
67 * performance counter interrupt was pending, so we have to run c0_compare_interrupt()
68 * the performance counter interrupt handler anyway. c0_compare_interrupt()
76 * interrupt. Being the paranoiacs we are we check anyway. c0_compare_interrupt()
93 * IRQF_SHARED: The timer interrupt may be shared with other interrupts
106 * FIXME: This doesn't hold for the relocated E9000 compare interrupt.
115 * Compare interrupt can be routed and latched outside the core,
116 * so wait up to worst case number of cycle counter ticks for timer interrupt
192 * interrupt number of it's liking. r4k_clockevent_init()
H A Dirq-msc01.c12 #include <linux/interrupt.h>
29 /* mask off an interrupt */ mask_msc_irq()
40 /* unmask an interrupt */ unmask_msc_irq()
86 /* read the interrupt vector register */ ll_msc_irq()
91 /* Ignore spurious interrupt */ ll_msc_irq()
124 /* Reset interrupt controller - initialises all registers to 0 */ init_msc_irqs()
157 MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ init_msc_irqs()
/linux-4.1.27/drivers/staging/fsl-mc/bus/
H A Ddpmcp.h136 * dpmcp_set_irq() - Set IRQ information for the DPMCP to trigger an interrupt.
139 * @irq_index: Identifies the interrupt index to configure
141 * signal a message-based interrupt
158 * @irq_index: The interrupt index to configure
159 * @type: Interrupt type: 0 represents message interrupt
162 * signal the message-based interrupt
177 * dpmcp_set_irq_enable() - Set overall interrupt state.
180 * @irq_index: The interrupt index to configure
184 * Each interrupt can have up to 32 causes. The enable/disable control's the
185 * overall interrupt state. if the interrupt is disabled no causes will cause
186 * an interrupt.
196 * dpmcp_get_irq_enable() - Get overall interrupt state
199 * @irq_index: The interrupt index to configure
200 * @en: Returned interrupt state - enable = 1, disable = 0
210 * dpmcp_set_irq_mask() - Set interrupt mask.
213 * @irq_index: The interrupt index to configure
214 * @mask: Event mask to trigger interrupt;
219 * Every interrupt can have up to 32 causes and the interrupt model supports
230 * dpmcp_get_irq_mask() - Get interrupt mask.
233 * @irq_index: The interrupt index to configure
234 * @mask: Returned event mask to trigger interrupt
236 * Every interrupt can have up to 32 causes and the interrupt model supports
251 * @irq_index: The interrupt index to configure
253 * 0 = no interrupt pending
254 * 1 = interrupt pending
264 * dpmcp_clear_irq_status() - Clear a pending interrupt's status
268 * @irq_index: The interrupt index to configure
/linux-4.1.27/arch/blackfin/mach-bf518/include/mach/
H A DdefBF518.h49 #define ALIE 0x1 /* Alarm interrupt enable */
50 #define RXEIE 0x2 /* Receive event interrupt enable */
51 #define RXGIE 0x4 /* Receive general interrupt enable */
52 #define TXIE 0x8 /* Transmit interrupt enable */
53 #define RXOVE 0x10 /* Receive overrun error interrupt enable */
54 #define TXOVE 0x20 /* Transmit overrun error interrupt enable */
55 #define ASIE 0x40 /* Auxiliary snapshot interrupt enable */
60 #define RXEL 0x2 /* Receive event interrupt status */
61 #define RXGL 0x4 /* Receive general interrupt status */
65 #define ASL 0x40 /* Auxiliary snapshot interrupt status */
/linux-4.1.27/arch/m32r/include/asm/m32700ut/
H A Dm32700ut_lan.h29 * ICUCR3: control register for CFIREQ# interrupt
30 * ICUCR4: control register for CFC Card insert interrupt
31 * ICUCR5: control register for CFC Card eject interrupt
32 * ICUCR6: control register for external interrupt
33 * ICUCR11: control register for MMC Card insert/eject interrupt
34 * ICUCR13: control register for SC error interrupt
35 * ICUCR14: control register for SC receive interrupt
36 * ICUCR15: control register for SC send interrupt
37 * ICUCR16: control register for SIO0 receive interrupt
38 * ICUCR17: control register for SIO0 send interrupt
/linux-4.1.27/sound/pci/
H A Dad1889.h72 #define AD_DMA_RESIC 0x80 /* RES dma interrupt current byte count */
73 #define AD_DMA_RESIB 0x84 /* RES dma interrupt base byte count */
75 #define AD_DMA_ADCIC 0x88 /* ADC dma interrupt current byte count */
76 #define AD_DMA_ADCIB 0x8c /* ADC dma interrupt base byte count */
78 #define AD_DMA_SYNIC 0x90 /* synth dma interrupt current byte count */
79 #define AD_DMA_SYNIB 0x94 /* synth dma interrupt base byte count */
81 #define AD_DMA_WAVIC 0x98 /* wave dma interrupt current byte count */
82 #define AD_DMA_WAVIB 0x9c /* wave dma interrupt base byte count */
96 #define AD_DMA_IM 0x000c /* interrupt mode mask */
98 #define AD_DMA_IM_CNT 0x0004 /* interrupt on count */
99 #define AD_DMA_IM_SGD 0x0008 /* interrupt on SGD flag */
100 #define AD_DMA_IM_EOL 0x000c /* interrupt on End of Linked List */
106 #define AD_DMA_DISR 0xc0 /* dma interrupt status */
107 #define AD_DMA_DISR_RESI 0x000001 /* resampler channel interrupt */
108 #define AD_DMA_DISR_ADCI 0x000002 /* ADC channel interrupt */
109 #define AD_DMA_DISR_SYNI 0x000004 /* synthesis channel interrupt */
110 #define AD_DMA_DISR_WAVI 0x000008 /* wave channel interrupt */
114 #define AD_DMA_DISR_PMAI 0x004000 /* pci master abort interrupt */
115 #define AD_DMA_DISR_PTAI 0x008000 /* pci target abort interrupt */
116 #define AD_DMA_DISR_PTAE 0x010000 /* pci target abort interrupt enable */
117 #define AD_DMA_DISR_PMAE 0x020000 /* pci master abort interrupt enable */
120 /* interrupt mask */
/linux-4.1.27/arch/mn10300/kernel/
H A Dmn10300-serial-low.S36 # serial port interrupt virtual DMA entry point
37 # - intended to run at interrupt priority 1 (not affected by local_irq_disable)
46 movhu (IAGR),a2 # see if which interrupt is
59 # serial port receive interrupt virtual DMA entry point
60 # - intended to run at interrupt priority 1 (not affected by local_irq_disable)
62 # - induces a scheduler tick timer interrupt when done, which we then subvert
71 movbu d2,(e3) # ACK the interrupt
94 movhu d2,(a2) # request a slow interrupt
106 # serial port transmit interrupt virtual DMA entry point
107 # - intended to run at interrupt priority 1 (not affected by local_irq_disable)
109 # - induces a scheduler tick timer interrupt when done, which we then subvert
118 movbu d2,(e3) # ACK the interrupt
159 movhu d2,(a2) # request a slow interrupt
168 movhu d2,(e3) # disable the interrupt
H A Dgdb-io-ttysm-low.S3 # MN10300 On-chip serial Rx interrupt handler for GDB stub I/O
28 # GDB stub serial receive interrupt entry point
29 # - intended to run at interrupt priority 0
57 movbu d2,(GxICR(SCgRXIRQ)) # ACK the interrupt
71 # debugging interrupt - enter the GDB stub proper
H A Dsmp-low.S27 # IPI interrupt handler
54 # Cache flush IPI interrupt handler
66 movbu d2,(GxICR(FLUSH_CACHE_IPI)) # ACK the interrupt
75 # SMP boot CPU IPI interrupt handler
79 /* clear interrupt */
H A Dmn10300-serial.h44 u8 intr_flags; /* interrupt flags */
45 volatile u16 *rx_icr; /* Rx interrupt control register */
46 volatile u16 *tx_icr; /* Tx interrupt control register */
52 const char *rx_name; /* Rx interrupt handler name of serial port */
53 const char *tx_name; /* Tx interrupt handler name of serial port */
54 const char *tm_name; /* Timer interrupt handler name */
60 volatile u8 *_intr; /* interrupt register pointer */
63 volatile u16 *_tmicr; /* timer interrupt control register */
H A Dgdb-io-serial-low.S3 # 16550 serial Rx interrupt handler for gdbstub I/O
28 # GDB stub serial receive interrupt entry point
29 # - intended to run at interrupt priority 0
61 movbu d2,(XIRQxICR(GDBPORT_SERIAL_IRQ)) # ACK the interrupt
H A Dprofile-low.S3 # Fast profiling interrupt handler
29 # Profiling interrupt entry point
30 # - intended to run at interrupt priority 1
64 movbu d2,(TM11ICR) # ACK the interrupt
H A Dirq.c1 /* MN10300 Arch-specific interrupt handling
12 #include <linux/interrupt.h>
38 * MN10300 interrupt controller operations
110 /* the MN10300 PIC latches its interrupt request bit, even after the mn10300_cpupic_unmask_clear()
111 * device has ceased to assert its interrupt line and the interrupt mn10300_cpupic_unmask_clear()
215 * mark an interrupt to be ACK'd after interrupt handlers have been run rather
225 * initialise the interrupt system
233 /* due to the PIC latching interrupt requests, even init_IRQ()
255 /* make sure local_irq_enable() doesn't muck up the interrupt priority do_IRQ()
269 /* ask the interrupt controller for the next IRQ to process do_IRQ()
290 * Display interrupt management information through /proc/interrupts
/linux-4.1.27/drivers/media/pci/cx25821/
H A Dcx25821-reg.h66 #define PCI_INT_MSK 0x040010 /* PCI interrupt mask */
67 #define PCI_INT_STAT 0x040014 /* PCI interrupt status */
68 #define PCI_INT_MSTAT 0x040018 /* PCI interrupt masked status */
97 #define VID_A_INT_MSK 0x040020 /* Video A interrupt mask */
98 #define VID_A_INT_STAT 0x040024 /* Video A interrupt status */
99 #define VID_A_INT_MSTAT 0x040028 /* Video A interrupt masked status */
100 #define VID_A_INT_SSTAT 0x04002C /* Video A interrupt set status */
103 #define VID_B_INT_MSK 0x040030 /* Video B interrupt mask */
104 #define VID_B_INT_STAT 0x040034 /* Video B interrupt status */
105 #define VID_B_INT_MSTAT 0x040038 /* Video B interrupt masked status */
106 #define VID_B_INT_SSTAT 0x04003C /* Video B interrupt set status */
109 #define VID_C_INT_MSK 0x040040 /* Video C interrupt mask */
110 #define VID_C_INT_STAT 0x040044 /* Video C interrupt status */
111 #define VID_C_INT_MSTAT 0x040048 /* Video C interrupt masked status */
112 #define VID_C_INT_SSTAT 0x04004C /* Video C interrupt set status */
115 #define VID_D_INT_MSK 0x040050 /* Video D interrupt mask */
116 #define VID_D_INT_STAT 0x040054 /* Video D interrupt status */
117 #define VID_D_INT_MSTAT 0x040058 /* Video D interrupt masked status */
118 #define VID_D_INT_SSTAT 0x04005C /* Video D interrupt set status */
121 #define VID_E_INT_MSK 0x040060 /* Video E interrupt mask */
122 #define VID_E_INT_STAT 0x040064 /* Video E interrupt status */
123 #define VID_E_INT_MSTAT 0x040068 /* Video E interrupt masked status */
124 #define VID_E_INT_SSTAT 0x04006C /* Video E interrupt set status */
127 #define VID_F_INT_MSK 0x040070 /* Video F interrupt mask */
128 #define VID_F_INT_STAT 0x040074 /* Video F interrupt status */
129 #define VID_F_INT_MSTAT 0x040078 /* Video F interrupt masked status */
130 #define VID_F_INT_SSTAT 0x04007C /* Video F interrupt set status */
133 #define VID_G_INT_MSK 0x040080 /* Video G interrupt mask */
134 #define VID_G_INT_STAT 0x040084 /* Video G interrupt status */
135 #define VID_G_INT_MSTAT 0x040088 /* Video G interrupt masked status */
136 #define VID_G_INT_SSTAT 0x04008C /* Video G interrupt set status */
139 #define VID_H_INT_MSK 0x040090 /* Video H interrupt mask */
140 #define VID_H_INT_STAT 0x040094 /* Video H interrupt status */
141 #define VID_H_INT_MSTAT 0x040098 /* Video H interrupt masked status */
142 #define VID_H_INT_SSTAT 0x04009C /* Video H interrupt set status */
145 #define VID_I_INT_MSK 0x0400A0 /* Video I interrupt mask */
146 #define VID_I_INT_STAT 0x0400A4 /* Video I interrupt status */
147 #define VID_I_INT_MSTAT 0x0400A8 /* Video I interrupt masked status */
148 #define VID_I_INT_SSTAT 0x0400AC /* Video I interrupt set status */
151 #define VID_J_INT_MSK 0x0400B0 /* Video J interrupt mask */
152 #define VID_J_INT_STAT 0x0400B4 /* Video J interrupt status */
153 #define VID_J_INT_MSTAT 0x0400B8 /* Video J interrupt masked status */
154 #define VID_J_INT_SSTAT 0x0400BC /* Video J interrupt set status */
170 #define AUD_A_INT_MSK 0x0400C0 /* Audio Int interrupt mask */
171 #define AUD_A_INT_STAT 0x0400C4 /* Audio Int interrupt status */
172 #define AUD_A_INT_MSTAT 0x0400C8 /* Audio Int interrupt masked status */
173 #define AUD_A_INT_SSTAT 0x0400CC /* Audio Int interrupt set status */
176 #define AUD_B_INT_MSK 0x0400D0 /* Audio Int interrupt mask */
177 #define AUD_B_INT_STAT 0x0400D4 /* Audio Int interrupt status */
178 #define AUD_B_INT_MSTAT 0x0400D8 /* Audio Int interrupt masked status */
179 #define AUD_B_INT_SSTAT 0x0400DC /* Audio Int interrupt set status */
182 #define AUD_C_INT_MSK 0x0400E0 /* Audio Int interrupt mask */
183 #define AUD_C_INT_STAT 0x0400E4 /* Audio Int interrupt status */
184 #define AUD_C_INT_MSTAT 0x0400E8 /* Audio Int interrupt masked status */
185 #define AUD_C_INT_SSTAT 0x0400EC /* Audio Int interrupt set status */
188 #define AUD_D_INT_MSK 0x0400F0 /* Audio Int interrupt mask */
189 #define AUD_D_INT_STAT 0x0400F4 /* Audio Int interrupt status */
190 #define AUD_D_INT_MSTAT 0x0400F8 /* Audio Int interrupt masked status */
191 #define AUD_D_INT_SSTAT 0x0400FC /* Audio Int interrupt set status */
194 #define AUD_E_INT_MSK 0x040100 /* Audio Int interrupt mask */
195 #define AUD_E_INT_STAT 0x040104 /* Audio Int interrupt status */
196 #define AUD_E_INT_MSTAT 0x040108 /* Audio Int interrupt masked status */
197 #define AUD_E_INT_SSTAT 0x04010C /* Audio Int interrupt set status */
211 #define MBIF_A_INT_MSK 0x040110 /* MBIF Int interrupt mask */
212 #define MBIF_A_INT_STAT 0x040114 /* MBIF Int interrupt status */
213 #define MBIF_A_INT_MSTAT 0x040118 /* MBIF Int interrupt masked status */
214 #define MBIF_A_INT_SSTAT 0x04011C /* MBIF Int interrupt set status */
217 #define MBIF_B_INT_MSK 0x040120 /* MBIF Int interrupt mask */
218 #define MBIF_B_INT_STAT 0x040124 /* MBIF Int interrupt status */
219 #define MBIF_B_INT_MSTAT 0x040128 /* MBIF Int interrupt masked status */
220 #define MBIF_B_INT_SSTAT 0x04012C /* MBIF Int interrupt set status */
229 #define AUD_EXT_INT_MSK 0x040060 /* Audio Ext interrupt mask */
230 #define AUD_EXT_INT_STAT 0x040064 /* Audio Ext interrupt status */
231 #define AUD_EXT_INT_MSTAT 0x040068 /* Audio Ext interrupt masked status */
232 #define AUD_EXT_INT_SSTAT 0x04006C /* Audio Ext interrupt set status */
246 #define GPIO_LO_INT_MSK 0x11003C /* GPIO interrupt mask */
247 #define GPIO_LO_INT_STAT 0x110044 /* GPIO interrupt status */
248 #define GPIO_LO_INT_MSTAT 0x11004C /* GPIO interrupt masked status */
249 #define GPIO_LO_ISM_SNS 0x110054 /* GPIO interrupt sensitivity */
250 #define GPIO_LO_ISM_POL 0x11005C /* GPIO interrupt polarity */
252 #define GPIO_HI_INT_MSK 0x110040 /* GPIO interrupt mask */
253 #define GPIO_HI_INT_STAT 0x110048 /* GPIO interrupt status */
254 #define GPIO_HI_INT_MSTAT 0x110050 /* GPIO interrupt masked status */
255 #define GPIO_HI_ISM_SNS 0x110058 /* GPIO interrupt sensitivity */
256 #define GPIO_HI_ISM_POL 0x110060 /* GPIO interrupt polarity */
924 #define GPIO_ISM 0x110014 /* GPIO interrupt sensitivity mode */
/linux-4.1.27/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.h20 /* External GPIO and wakeup interrupt related definitions */
34 /* helpers to access interrupt service register */
41 /* Exynos specific external interrupt trigger types */
84 * generated by the external wakeup interrupt controller.
85 * @irq: interrupt number within the domain.
86 * @bank: bank responsible for this interrupt
95 * generated by the external wakeup interrupt controller.
/linux-4.1.27/arch/powerpc/platforms/pseries/
H A Devent_sources.c33 /* Check for obsolete "open-pic-interrupt" property. If present, then request_event_sources_irqs()
34 * map those interrupts using the default interrupt host and default request_event_sources_irqs()
37 opicprop = of_get_property(np, "open-pic-interrupt", &opicplen); request_event_sources_irqs()
46 "interrupt number for %s\n", request_event_sources_irqs()
55 /* Else use normal interrupt tree parsing */ request_event_sources_irqs()
65 "interrupt number for %s\n", request_event_sources_irqs()
77 pr_err("event-sources: Unable to request interrupt " request_event_sources_irqs()
/linux-4.1.27/arch/mips/loongson/lemote-2f/
H A Dirq.c11 #include <linux/interrupt.h>
48 * This may be a spurious interrupt. mach_i8259_irq()
50 * Read the interrupt status register (ISR). If the most mach_i8259_irq()
52 * interrupt. mach_i8259_irq()
111 * 0-15 ------> i8259 interrupt mach_init_irq()
112 * 16-23 ------> mips cpu interrupt mach_init_irq()
120 /* Sets the first-level interrupt dispatcher. */ mach_init_irq()
/linux-4.1.27/arch/tile/kernel/
H A Dirq.c17 #include <linux/interrupt.h>
31 * This is initialized to have just a single interrupt that the kernel
40 /* Define per-tile device interrupt statistics state. */
53 * enabled IRQs before exiting the outermost interrupt.
70 * The interrupt handling path, implemented in terms of HV interrupt
85 * masked by a previous interrupt. Then, mask out the ones tile_dev_intr()
94 * then puts the pending interrupt mask into a system save reg tile_dev_intr()
101 /* Track time spent here in an interrupt context. */ tile_dev_intr()
129 * including any that were reenabled during interrupt tile_dev_intr()
147 * Remove an irq from the disabled mask. If we're in an interrupt
148 * context, defer enabling the HW interrupt until we leave.
159 * Add an irq to the disabled mask. We disable the HW interrupt
161 * in an interrupt context, the return path is careful to avoid
162 * unmasking a newly disabled interrupt.
171 /* Mask an interrupt. */ tile_irq_chip_mask()
177 /* Unmask an interrupt. */ tile_irq_chip_unmask()
184 * Clear an interrupt before processing it so that any new assertions
220 /* Enable interrupt delivery. */ setup_irq_regs()
231 * interrupt vector (whether modeled by the HV on tile_irq_activate()
233 * level-style semantics for each bit. An interrupt fires tile_irq_activate()
/linux-4.1.27/arch/m68k/atari/
H A Dstdma.c21 /* stdma_release(). Additionally, the caller gives his interrupt */
24 /* On the Falcon, the IDE bus uses just the ACSI/Floppy interrupt, but */
26 /* chip. The interrupt is routed to falhd.c if IDE is configured, the */
27 /* model is a Falcon and the interrupt was caused by the HD controller */
36 #include <linux/interrupt.h>
63 * stdma_try_lock - attempt to acquire ST DMA interrupt "lock"
64 * @handler: interrupt handler to use after acquisition
93 * stdma_lock() may not be called from an interrupt! You have to
97 * Inputs: A interrupt function that is called until the lock is
143 * @handler: interrupt handler previously used to acquire lock.
188 * It sets up the interrupt and its service routine. The int is registered
203 pr_err("Couldn't register ST-DMA interrupt\n"); stdma_init()
210 * Purpose: The interrupt routine for the ST-DMA. It calls the isr
H A Dataints.c2 * arch/m68k/atari/ataints.c -- Atari Linux interrupt handling code
11 * number of possible ints a constant defined in interrupt.h, which is
18 * interrupt sources if there were no TT MFP!
24 * Total rewrite of Atari interrupt handling, for new scheme see comments
57 * Atari interrupt handling scheme:
60 * All interrupt source have an internal number (defined in
67 * Bitmap for free interrupt vector numbers
128 * interrupt instance.
184 * EtherNAT CPLD interrupt handling
185 * CPLD interrupt register is at phys. 0x80000023
186 * Need this mapped in at interrupt startup time
200 * map CPLD interrupt register atari_ethernat_startup()
205 * do _not_ enable the USB chip interrupt here - causes interrupt storm atari_ethernat_startup()
206 * and triggers dead interrupt watchdog atari_ethernat_startup()
220 * map CPLD interrupt register atari_ethernat_enable()
231 * map CPLD interrupt register atari_ethernat_disable()
312 /* If no SCU and no Hades, the HSYNC interrupt needs to be atari_init_IRQ()
340 /* prepare timer D data for use as poll interrupt */ atari_init_IRQ()
349 pr_err("Couldn't register %s interrupt\n", stmfp_base.name); atari_init_IRQ()
352 * EtherNAT ethernet / USB interrupt handlers atari_init_IRQ()
361 * atari_register_vme_int() returns the number of a free interrupt vector for
/linux-4.1.27/drivers/net/ethernet/altera/
H A Daltera_sgdmahw.h82 /* bit 0: interrupt on error
83 * bit 1: interrupt on eop
84 * bit 2: interrupt after every descriptor
85 * bit 3: interrupt after last descrip in a chain
86 * bit 4: global interrupt enable
89 * bit 7: interrupt on max descriptors
90 * bits 8-15: max descriptors to generate interrupt
96 * bit 31: clear interrupt
124 #define SGDMA_CTRLREG_CLRINT BIT(31)/* Clears interrupt */
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dradeon_irq_kms.c61 * Handle hotplug events outside the interrupt handler proper.
70 * was a hot plug interrupt. It walks the connector table
112 * This function disables all interrupt sources on the GPU.
157 * This function disables all interrupt sources on the GPU (all asics).
267 * radeon_irq_kms_init - init driver interrupt info
311 * radeon_irq_kms_fini - tear down driver interrupt info
330 * radeon_irq_kms_sw_irq_get - enable software interrupt
333 * @ring: ring whose interrupt you want to enable
335 * Enables the software interrupt for a specific ring (all asics).
336 * The software interrupt is generally used to signal a fence on
354 * radeon_irq_kms_sw_irq_get_delayed - enable software interrupt
357 * @ring: ring whose interrupt you want to enable
359 * Enables the software interrupt for a specific ring (all asics).
360 * The software interrupt is generally used to signal a fence on
369 * radeon_irq_kms_sw_irq_put - disable software interrupt
372 * @ring: ring whose interrupt you want to disable
374 * Disables the software interrupt for a specific ring (all asics).
375 * The software interrupt is generally used to signal a fence on
393 * radeon_irq_kms_pflip_irq_get - enable pageflip interrupt
396 * @crtc: crtc whose interrupt you want to enable
398 * Enables the pageflip interrupt for a specific crtc (all asics).
399 * For pageflips we use the vblank interrupt source.
419 * radeon_irq_kms_pflip_irq_put - disable pageflip interrupt
422 * @crtc: crtc whose interrupt you want to disable
424 * Disables the pageflip interrupt for a specific crtc (all asics).
425 * For pageflips we use the vblank interrupt source.
445 * radeon_irq_kms_enable_afmt - enable audio format change interrupt
448 * @block: afmt block whose interrupt you want to enable
450 * Enables the afmt change interrupt for a specific afmt block (all asics).
467 * radeon_irq_kms_disable_afmt - disable audio format change interrupt
470 * @block: afmt block whose interrupt you want to disable
472 * Disables the afmt change interrupt for a specific afmt block (all asics).
488 * radeon_irq_kms_enable_hpd - enable hotplug detect interrupt
493 * Enables the hotplug detect interrupt for a specific hpd pin (all asics).
511 * radeon_irq_kms_disable_hpd - disable hotplug detect interrupt
516 * Disables the hotplug detect interrupt for a specific hpd pin (all asics).
/linux-4.1.27/arch/tile/gxio/
H A Diorpc_uart.c19 union iorpc_interrupt interrupt; member in struct:cfg_interrupt_param
28 params->interrupt.kernel.x = inter_x; gxio_uart_cfg_interrupt()
29 params->interrupt.kernel.y = inter_y; gxio_uart_cfg_interrupt()
30 params->interrupt.kernel.ipi = inter_ipi; gxio_uart_cfg_interrupt()
31 params->interrupt.kernel.event = inter_event; gxio_uart_cfg_interrupt()
H A Diorpc_usb_host.c19 union iorpc_interrupt interrupt; member in struct:cfg_interrupt_param
28 params->interrupt.kernel.x = inter_x; gxio_usb_host_cfg_interrupt()
29 params->interrupt.kernel.y = inter_y; gxio_usb_host_cfg_interrupt()
30 params->interrupt.kernel.ipi = inter_ipi; gxio_usb_host_cfg_interrupt()
31 params->interrupt.kernel.event = inter_event; gxio_usb_host_cfg_interrupt()
/linux-4.1.27/arch/m68k/sun3/
H A Dsun3ints.c2 * linux/arch/m68k/sun3/sun3ints.c -- Sun-3(x) Linux interrupt handling code
13 #include <linux/interrupt.h>
94 pr_err("Couldn't register %s interrupt\n", "int5"); sun3_init_IRQ()
96 pr_err("Couldn't register %s interrupt\n", "int7"); sun3_init_IRQ()
98 pr_err("Couldn't register %s interrupt\n", "vec255"); sun3_init_IRQ()
/linux-4.1.27/drivers/of/
H A Dirq.c17 * device tree to actual irq numbers on an interrupt controller
30 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
31 * @dev: Device node of the device whose interrupt is to be mapped
32 * @index: Index of the interrupt to map
49 * of_irq_find_parent - Given a device node, find its interrupt parent node
52 * Returns a pointer to the interrupt parent node, or NULL if the interrupt
64 parp = of_get_property(child, "interrupt-parent", NULL); of_irq_find_parent()
75 } while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL); of_irq_find_parent()
81 * of_irq_parse_raw - Low level interrupt tree parsing
82 * @parent: the device interrupt parent
88 * This function is a low-level interrupt tree walking function. It
91 * node exist for the parent. It takes an interrupt specifier structure as
92 * input, walks the tree looking for any interrupt-map properties, translates
110 /* First get the #interrupt-cells property of the current cursor of_irq_parse_raw()
115 tmp = of_get_property(ipar, "#interrupt-cells", NULL); of_irq_parse_raw()
160 /* Now start the actual "proper" walk of the interrupt tree */ of_irq_parse_raw()
162 /* Now check if cursor is an interrupt-controller and if it is of_irq_parse_raw()
165 if (of_get_property(ipar, "interrupt-controller", NULL) != of_irq_parse_raw()
172 * interrupt-map parsing does not work without a reg of_irq_parse_raw()
180 /* Now look for an interrupt-map */ of_irq_parse_raw()
181 imap = of_get_property(ipar, "interrupt-map", &imaplen); of_irq_parse_raw()
182 /* No interrupt map, check for an interrupt parent */ of_irq_parse_raw()
191 imask = of_get_property(ipar, "interrupt-map-mask", NULL); of_irq_parse_raw()
195 /* Parse interrupt-map */ of_irq_parse_raw()
205 /* Get the interrupt parent */ of_irq_parse_raw()
222 /* Get #interrupt-cells and #address-cells of new of_irq_parse_raw()
225 tmp = of_get_property(newpar, "#interrupt-cells", NULL); of_irq_parse_raw()
227 pr_debug(" -> parent lacks #interrupt-cells!\n"); of_irq_parse_raw()
253 * interrupt specifier into the out_irq structure of_irq_parse_raw()
279 * of_irq_parse_one - Resolve an interrupt for a device
280 * @device: the device whose interrupt is to be resolved
281 * @index: index of the interrupt to resolve
284 * This function resolves an interrupt for a node by walking the interrupt tree,
285 * finding which interrupt controller node it is attached to, and returning the
286 * interrupt specifier that can be used to retrieve a Linux IRQ number.
306 "#interrupt-cells", index, out_irq); of_irq_parse_one()
319 /* Look for the interrupt parent. */ of_irq_parse_one()
324 /* Get size of interrupt specifier */ of_irq_parse_one()
325 tmp = of_get_property(p, "#interrupt-cells", NULL); of_irq_parse_one()
347 /* Check if there are any interrupt-map translations to process */ of_irq_parse_one()
372 * Get optional "interrupt-names" property to add a name of_irq_to_resource()
375 of_property_read_string_index(dev, "interrupt-names", index, of_irq_to_resource()
430 index = of_property_match_string(dev, "interrupt-names", name); of_irq_get_byname()
480 * of_irq_init - Scan and init matching interrupt controllers in DT
483 * This function scans the device tree for matching interrupt controller nodes,
496 if (!of_find_property(np, "interrupt-controller", NULL) || for_each_matching_node()
501 * pointer, interrupt-parent device_node etc. for_each_matching_node()
515 * The root irq controller is the one without an interrupt-parent.
/linux-4.1.27/drivers/net/ethernet/amd/
H A Dhplance.h8 #define HPLANCE_STATUS 0x03 /* DIO register: interrupt enable/status */
11 #define LE_IE 0x80 /* interrupt enable */
12 #define LE_IR 0x40 /* interrupt requested */
/linux-4.1.27/arch/openrisc/kernel/
H A Dirq.c17 #include <linux/interrupt.h>
25 /* read interrupt enabled status */ arch_local_save_flags()
32 /* set interrupt enabled status */ arch_local_irq_restore()
/linux-4.1.27/arch/arm/mach-footbridge/
H A Dpersonal-pci.c29 /* line corresponds to the bit controlling this interrupt personal_server_map_irq()
30 * in the footbridge. Ignore the first 8 interrupt bits, personal_server_map_irq()
35 /* no interrupt */ personal_server_map_irq()
/linux-4.1.27/arch/arm/mach-omap1/
H A Dfpga.c125 * All of the FPGA interrupt request inputs except for the touchscreen are
127 * interrupts are acknowledged as a side-effect of reading the interrupt
128 * status register from the FPGA. The edge-sensitive interrupt inputs
129 * cause a problem with level interrupt requests, such as Ethernet. The
130 * problem occurs when a level interrupt request is asserted while its
131 * interrupt input is masked in the FPGA, which results in a missed
132 * interrupt.
136 * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt
138 * interrupt is run with all interrupts masked.
143 * interrupts at the interrupt controller via disable_irq/enable_irq
158 * The touchscreen interrupt is level-sensitive, so omap1510_fpga_init_irq()
176 * The FPGA interrupt line is connected to GPIO13. Claim this pin for omap1510_fpga_init_irq()
H A Dams-delta-fiq-handler.S109 ldr r10, [r12, #IRQ_SIR_FIQ_REG_OFFSET] @ get requested interrupt number
114 cmp r10, #INT_GPIO_BANK1 @ is it GPIO bank interrupt?
118 orr r8, r11, r8, lsl r10 @ mask spurious interrupt
126 gpio: @ GPIO bank interrupt handler
133 beq exit @ no - spurious interrupt? exit
143 @ Keyboard clock FIQ mode interrupt handler
145 str r10, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack the interrupt
189 @ Key done - restore interrupt mask
222 hksw: @Is hook switch interrupt requested?
228 @ Hook switch interrupt FIQ mode simple handler
232 @ Increment hook switch interrupt counter
239 mdm: @Is it a modem interrupt?
241 beq irq @ no - check for next interrupt
245 @ Modem FIQ mode interrupt handler stub
247 @ Increment modem interrupt counter
254 irq: @ Place deferred_fiq interrupt request
260 b restart @ check for next GPIO interrupt
/linux-4.1.27/include/linux/mfd/
H A Djanz.h25 * Read access: interrupt status
26 * Write access: interrupt disable
33 * Write access: interrupt enable
/linux-4.1.27/drivers/irqchip/
H A Dirq-metag.c2 * Meta internal (HWSTATMETA) interrupt code.
11 #include <linux/interrupt.h>
24 * struct metag_internal_irq_priv - private meta internal interrupt data
34 /* Private data for the one and only internal interrupt controller */
93 /* Clear (toggle) the bit in HWSTATMETA for our interrupt. */ metag_internal_irq_startup()
96 /* Enable the interrupt by unmasking it */ metag_internal_irq_startup()
114 /* Clear (toggle) the bit in HWSTATMETA for our interrupt. */ metag_internal_irq_shutdown()
146 /* there is no interrupt mask, so unvector the interrupt */ metag_internal_irq_mask()
167 /* there is no interrupt mask, so revector the interrupt */ metag_internal_irq_unmask()
171 * Re-trigger interrupt metag_internal_irq_unmask()
176 * because if the interrupt fires again after we clear it we metag_internal_irq_unmask()
177 * could end up clearing it again and the interrupt handler metag_internal_irq_unmask()
190 * metag_internal_irq_set_affinity - set the affinity for an interrupt
198 * Wire up this interrupt from *VECINT to the Meta core. metag_internal_irq_set_affinity()
200 * Note that we can't wire up *VECINT to interrupt more than metag_internal_irq_set_affinity()
201 * one cpu (the interrupt code doesn't support it), so we just metag_internal_irq_set_affinity()
216 * @irq: the interrupt number
217 * @desc: the interrupt description structure for this irq
219 * The cpu receives an interrupt on TR1 when an interrupt has
300 * This sets up a virtual irq for a specified hardware interrupt. The irq chip
306 /* only register interrupt if it is mapped */ metag_internal_intc_map()
/linux-4.1.27/drivers/net/can/softing/
H A Dsofting_platform.h16 * 8bit, exclusive interrupt, ...
18 * 16bit, shared interrupt
/linux-4.1.27/arch/sparc/include/asm/
H A Dsignal.h14 * interrupt handler's irq structure should be statically allocated
17 * of interrupt usage and that sucks. Also without a flag like this
H A Dirq_32.h15 #include <linux/interrupt.h>
H A Dintr_queue.h4 /* Sun4v interrupt queue registers, accessed via ASI_QUEUE. */
/linux-4.1.27/arch/tile/include/asm/
H A Dirq.h34 * per-cpu; there is no global interrupt controller to implement
50 * to tell the generic irq code what kind of interrupt is mapped to a
54 /* per-cpu interrupt; use enable/disable_percpu_irq() to mask */
56 /* global interrupt, hardware responsible for clearing. */
58 /* global interrupt, software responsible for clearing. */
67 * IRQ subsystem an opportunity to do interrupt-type-specific
72 * for enabling and disabling the interrupt. This would allow the
74 * PCI subsystem, which in turn could enable or disable the interrupt
H A Dirqflags.h44 * Set and clear kernel interrupt masks.
116 * Note that in particular, the tile timer interrupt comes and goes
119 * interrupts, as is the the hardwall UDN_FIREWALL interrupt.
121 * is always claimed as an "active interrupt" so we can query that bit
177 /* Prevent the given interrupt from being enabled next time we enable irqs. */
178 #define arch_local_irq_mask(interrupt) \
179 this_cpu_and(interrupts_enabled_mask, ~(1ULL << (interrupt)))
181 /* Prevent the given interrupt from being enabled immediately. */
182 #define arch_local_irq_mask_now(interrupt) do { \
183 arch_local_irq_mask(interrupt); \
184 interrupt_mask_set(interrupt); \
187 /* Allow the given interrupt to be enabled next time we enable irqs. */
188 #define arch_local_irq_unmask(interrupt) \
189 this_cpu_or(interrupts_enabled_mask, (1ULL << (interrupt)))
191 /* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
192 #define arch_local_irq_unmask_now(interrupt) do { \
193 arch_local_irq_unmask(interrupt); \
195 interrupt_mask_reset(interrupt); \
245 * are interrupted after only writing half of the mask, the interrupt
247 * will enable interrupts itself on return from the interrupt handler
/linux-4.1.27/arch/metag/kernel/
H A Dkick.c8 * The Meta KICK interrupt mechanism is generally a useful feature, so
9 * we provide an interface for registering multiple interrupt
10 * handlers. All the registered interrupt handlers are "chained". When
11 * a KICK interrupt is received the first function in the list is
12 * called. If that interrupt handler cannot handle the KICK the next
14 * out of functions). As soon as one function handles the interrupt no
17 * The only downside of chaining interrupt handlers is that each
90 * can't nest KICK interrupts in a KICK interrupt handler. kick_handler()
/linux-4.1.27/arch/mips/include/asm/mips-boards/
H A Dsead3int.h19 /* CPU interrupt offsets */
26 /* GIC interrupt offsets */
H A Dmaltaint.h20 /* CPU interrupt offsets */
25 #define MIPSCPU_INT_GIC MIPSCPU_INT_MB0 /* GIC chained interrupt */
39 /* SOC-it Classic interrupt offsets */
48 /* SOC-it EIC interrupt offsets */
/linux-4.1.27/include/linux/platform_data/
H A Dmmc-pxamci.h5 #include <linux/interrupt.h>
12 unsigned long detect_delay_ms; /* delay in millisecond before detecting cards after interrupt */
H A Dmailbox-omap.h29 * @usr_id: mailbox user id for identifying the interrupt into
30 * the MPU interrupt controller.
42 * @intr_type: type of interrupt configuration registers used
45 * h/w block can interrupt
H A Dpinctrl-single.h2 * irq: optional wake-up interrupt
H A Dpca953x.h16 /* interrupt base */
/linux-4.1.27/arch/sh/boards/mach-se/7721/
H A Dirq.c12 #include <linux/interrupt.h>
19 /* board specific interrupt sources */
/linux-4.1.27/arch/ia64/include/asm/
H A Dhw_irq.h9 #include <linux/interrupt.h>
31 * 15 spurious interrupt (see IVR)
50 #define IA64_CPE_VECTOR 0x1e /* corrected platform error interrupt vector */
51 #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */
75 #define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */
76 #define IA64_PERFMON_VECTOR 0xee /* performance monitor interrupt vector */
77 #define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */
81 #define IA64_IPI_VECTOR 0xfe /* inter-processor interrupt vector */
87 /* IA64 inter-cpu interrupt related definitions */
93 IA64_IPI_DM_INT = 0x0, /* pend an external interrupt */
96 IA64_IPI_DM_INIT = 0x5, /* pend an INIT interrupt */
97 IA64_IPI_DM_EXTINT = 0x7, /* pend an 8259-compatible interrupt. */
115 extern struct irq_chip irq_type_ia64_lsapic; /* CPU-internal interrupt controller */
167 * Next follows the irq descriptor interface. On IA-64, each CPU supports 256 interrupt
168 * vectors. On smaller systems, there is a one-to-one correspondence between interrupt
169 * vectors and the Linux irq numbers. However, larger systems may have multiple interrupt
171 * interrupt domain that a CPU belongs to. This API abstracts such platform-dependent
185 * done in the context of the interrupt domain that the currently executing CPU belongs
/linux-4.1.27/arch/arc/include/asm/
H A Dirq.h12 #define NR_CPU_IRQS 32 /* number of interrupt lines of ARC770 CPU */
19 #include <linux/interrupt.h>
/linux-4.1.27/drivers/misc/mic/host/
H A Dmic_intr.h25 #include <linux/interrupt.h>
37 * the interrupt.The number of types needs to be in sync with
42 * MIC_INTR_ERR: The source is an error interrupt e.g. SBOX ERR
43 * MIC_NUM_INTR_TYPES: Total number of interrupt sources.
53 * struct mic_intr_info - Contains h/w specific interrupt sources
57 * interrupt types.
58 * @intr_len: Contains the length of the interrupt types.
73 * @mic_intr_lock: spinlock to protect the interrupt callback list.
76 * mic_intr_lock is used to protect against interrupt handler.
118 * struct mic_hw_intr_ops: MIC HW specific interrupt operations
119 * @intr_init: Initialize H/W specific interrupt information.
/linux-4.1.27/drivers/s390/cio/
H A Dairq.c30 * register_adapter_interrupt() - register adapter interrupt handler
31 * @airq: pointer to adapter interrupt descriptor
60 * unregister_adapter_interrupt - unregister adapter interrupt handler
61 * @airq: pointer to adapter interrupt descriptor
115 * airq_iv_create - create an interrupt vector
116 * @bits: number of bits in the interrupt vector
119 * Returns a pointer to an interrupt vector structure
174 * airq_iv_release - release an interrupt vector
175 * @iv: pointer to interrupt vector structure
189 * airq_iv_alloc - allocate irq bits from an interrupt vector
190 * @iv: pointer to an interrupt vector structure
227 * airq_iv_free - free irq bits of an interrupt vector
228 * @iv: pointer to interrupt vector structure
240 /* Clear (possibly left over) interrupt bit */ airq_iv_free()
255 * airq_iv_scan - scan interrupt vector for non-zero bits
256 * @iv: pointer to interrupt vector structure
260 * Returns the bit number of the next non-zero interrupt bit, or
/linux-4.1.27/drivers/staging/fsl-mc/include/
H A Ddpbp.h150 * dpbp_set_irq() - Set IRQ information for the DPBP to trigger an interrupt.
153 * @irq_index: Identifies the interrupt index to configure
155 * signal a message-based interrupt
172 * @irq_index: The interrupt index to configure
173 * @type: Interrupt type: 0 represents message interrupt
176 * signal the message-based interrupt
191 * dpbp_set_irq_enable() - Set overall interrupt state.
194 * @irq_index: The interrupt index to configure
198 * Each interrupt can have up to 32 causes. The enable/disable control's the
199 * overall interrupt state. if the interrupt is disabled no causes will cause
200 * an interrupt.
210 * dpbp_get_irq_enable() - Get overall interrupt state
213 * @irq_index: The interrupt index to configure
214 * @en: Returned interrupt state - enable = 1, disable = 0
224 * dpbp_set_irq_mask() - Set interrupt mask.
227 * @irq_index: The interrupt index to configure
228 * @mask: Event mask to trigger interrupt;
233 * Every interrupt can have up to 32 causes and the interrupt model supports
244 * dpbp_get_irq_mask() - Get interrupt mask.
247 * @irq_index: The interrupt index to configure
248 * @mask: Returned event mask to trigger interrupt
250 * Every interrupt can have up to 32 causes and the interrupt model supports
265 * @irq_index: The interrupt index to configure
267 * 0 = no interrupt pending
268 * 1 = interrupt pending
278 * dpbp_clear_irq_status() - Clear a pending interrupt's status
282 * @irq_index: The interrupt index to configure
/linux-4.1.27/drivers/usb/dwc2/
H A Dcore_intr.c2 * core_intr.c - DesignWare HS OTG Controller common interrupt handling
38 * This file contains the common interrupt handlers
44 #include <linux/interrupt.h>
76 * When the PRTINT interrupt fires, there are certain status bits in the Host
90 /* Clear interrupt */ dwc2_handle_usb_port_intr()
104 /* Clear interrupt */ dwc2_handle_mode_mismatch_intr()
110 * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
180 * Print statements during the HNP interrupt handling dwc2_handle_otg_intr()
194 * Need to disable SOF interrupt immediately. dwc2_handle_otg_intr()
196 * interrupt handler won't handle the interrupt dwc2_handle_otg_intr()
198 * interrupt handler won't get called if the dwc2_handle_otg_intr()
200 * interrupt does not get handled and Linux dwc2_handle_otg_intr()
230 * The disconnect interrupt is set at the same time as dwc2_handle_otg_intr()
232 * interrupts are cleared so the disconnect interrupt dwc2_handle_otg_intr()
246 /* Need to disable SOF interrupt immediately */ dwc2_handle_otg_intr()
281 /* Need to disable SOF interrupt immediately */ dwc2_handle_conn_id_status_change_intr()
299 /* Clear interrupt */ dwc2_handle_conn_id_status_change_intr()
304 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
318 /* Clear interrupt */ dwc2_handle_session_req_intr()
329 * This interrupt indicates that the DWC_otg controller has detected a
366 /* Clear interrupt */ dwc2_handle_wakeup_detected_intr()
371 * This interrupt indicates that a device has been disconnected from the
390 * This interrupt indicates that SUSPEND state has been detected on the USB.
392 * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
429 /* Clear interrupt */ dwc2_handle_usb_suspend_intr()
464 * Common interrupt handler
510 * The port interrupt occurs while in device mode with HPRT0 dwc2_handle_common_intr()
515 " --Port interrupt received in Device mode--\n"); dwc2_handle_common_intr()
/linux-4.1.27/drivers/net/ethernet/dec/tulip/
H A DMakefile17 tulip-objs := eeprom.o interrupt.o media.o \
/linux-4.1.27/drivers/staging/rtl8723au/include/
H A DHal8723UHWImg_CE.h6 /* FW v16 enable usb interrupt */
/linux-4.1.27/drivers/pcmcia/
H A Dpd6729.h12 /* Default ISA interrupt mask */
/linux-4.1.27/drivers/net/wireless/ath/wil6210/
H A DMakefile9 wil6210-y += interrupt.o
/linux-4.1.27/arch/um/include/shared/
H A Dirq_kern.h9 #include <linux/interrupt.h>
/linux-4.1.27/include/net/
H A Dflowcache.h4 #include <linux/interrupt.h>
/linux-4.1.27/arch/sh/boards/mach-se/7780/
H A Dirq.c14 #include <linux/interrupt.h>
26 /* enable all interrupt at FPGA */ init_se7780_IRQ()
28 /* mask SM501 interrupt */ init_se7780_IRQ()
30 /* enable all interrupt at FPGA */ init_se7780_IRQ()
/linux-4.1.27/arch/mips/kvm/
H A DMakefile11 interrupt.o stats.o commpage.o \
H A Dinterrupt.c23 #include "interrupt.h"
38 * Cause bits to reflect the pending timer interrupt, kvm_mips_queue_timer_int_cb()
40 * delivering the interrupt: kvm_mips_queue_timer_int_cb()
61 * Cause bits to reflect the pending IO interrupt, kvm_mips_queue_io_int_cb()
63 * delivering the interrupt: kvm_mips_queue_io_int_cb()
115 /* Deliver the interrupt of the corresponding priority, if possible. */ kvm_mips_irq_deliver_cb()
166 /* Are we allowed to deliver the interrupt ??? */ kvm_mips_irq_deliver_cb()
181 kvm_err("Trying to deliver interrupt when EXL is already set\n"); kvm_mips_irq_deliver_cb()
186 /* XXXSL Set PC to the interrupt exception entry point */ kvm_mips_irq_deliver_cb()
/linux-4.1.27/arch/mips/loongson/fuloong-2e/
H A Dirq.c10 #include <linux/interrupt.h>
51 * 0-15 ------> i8259 interrupt mach_init_irq()
52 * 16-23 ------> mips cpu interrupt mach_init_irq()
60 /* Sets the first-level interrupt dispatcher. */ mach_init_irq()
/linux-4.1.27/arch/mn10300/unit-asb2364/
H A Dirq-fpga.c1 /* ASB2364 FPGA interrupt multiplexing
12 #include <linux/interrupt.h>
55 * FPGA PIC interrupt handler
74 * Define an interrupt action for each FPGA PIC output
/linux-4.1.27/arch/c6x/include/asm/
H A Dirq.h27 * These interrupt vectors are prioritized with IRQ 4 having the highest
32 * feed into one of the 12 general interrupt vectors. The remaining 8 vectors
33 * can each route a single SoC interrupt directly.
40 /* This number is used when no interrupt has been assigned */
/linux-4.1.27/arch/arm/mach-rpc/
H A Dtime.c18 #include <linux/interrupt.h>
48 * We have not had an interrupt between reading count1 ioc_timer_gettimeoffset()
55 * We have just had another interrupt between reading ioc_timer_gettimeoffset()
85 * Set up timer interrupt.
/linux-4.1.27/arch/alpha/kernel/
H A Dirq_pyxis.c49 /* Disable the interrupt. */ pyxis_mask_and_ack_irq()
52 /* Ack PYXIS PCI interrupt. */ pyxis_mask_and_ack_irq()
72 /* Read the interrupt summary register of PYXIS */ pyxis_device_interrupt()
78 * the appropriate interrupt handler. pyxis_device_interrupt()
/linux-4.1.27/include/clocksource/
H A Dpxa.h2 * PXA clocksource, clockevents, and OST interrupt handlers.
/linux-4.1.27/include/linux/i2c/
H A Dmax732x.h10 /* interrupt base */
/linux-4.1.27/include/linux/irqchip/
H A Dxtensa-mx.h2 * Xtensa MX interrupt distributor
H A Dxtensa-pic.h2 * Xtensa built-in interrupt controller
/linux-4.1.27/drivers/ide/
H A Dmacide.c16 #include <linux/interrupt.h>
45 #define IDE_IFR 0x101 /* (0x101) IDE interrupt flags on Quadra:
47 * Bit 0+1: some interrupt flags
48 * Bit 2+3: some interrupt enable
50 * Bit 5: IDE interrupt flag (any hwif)
51 * Bit 6: maybe IDE interrupt enable (any hwif) ??
52 * Bit 7: Any interrupt condition
/linux-4.1.27/arch/arm/plat-orion/
H A Dtime.c17 #include <linux/interrupt.h>
84 * Clear and enable clockevent timer interrupt. orion_clkevt_next_event()
124 * Enable timer interrupt. orion_clkevt_mode()
143 * Disable timer interrupt. orion_clkevt_mode()
149 * ACK pending timer interrupt. orion_clkevt_mode()
168 * ACK timer interrupt and call event handler. orion_timer_interrupt()
221 * Setup clockevent timer (interrupt-driven). orion_time_init()
/linux-4.1.27/arch/powerpc/include/asm/
H A Depapr_hcalls.h128 * ev_int_set_config - configure the specified interrupt epapr_paravirt_early_init()
129 * @interrupt: the interrupt number epapr_paravirt_early_init()
130 * @config: configuration for this interrupt epapr_paravirt_early_init()
131 * @priority: interrupt priority epapr_paravirt_early_init()
136 static inline unsigned int ev_int_set_config(unsigned int interrupt, ev_int_set_config() argument
146 r3 = interrupt; ev_int_set_config()
160 * ev_int_get_config - return the config of the specified interrupt
161 * @interrupt: the interrupt number
162 * @config: returned configuration for this interrupt
163 * @priority: returned interrupt priority
168 static inline unsigned int ev_int_get_config(unsigned int interrupt, ev_int_get_config() argument
178 r3 = interrupt; ev_int_get_config()
193 * ev_int_set_mask - sets the mask for the specified interrupt source
194 * @interrupt: the interrupt number
199 static inline unsigned int ev_int_set_mask(unsigned int interrupt, ev_int_set_mask() argument
207 r3 = interrupt; ev_int_set_mask()
219 * ev_int_get_mask - returns the mask for the specified interrupt source
220 * @interrupt: the interrupt number
221 * @mask: returned mask for this interrupt (0=enabled, 1=disabled)
225 static inline unsigned int ev_int_get_mask(unsigned int interrupt, ev_int_get_mask() argument
233 r3 = interrupt; ev_int_get_mask()
246 * ev_int_eoi - signal the end of interrupt processing
247 * @interrupt: the interrupt number
250 * interrupt, which must be the interrupt currently in service. By
251 * definition, this is also the highest-priority interrupt.
255 static inline unsigned int ev_int_eoi(unsigned int interrupt) ev_int_eoi() argument
261 r3 = interrupt; ev_int_eoi()
391 * ev_int_iack - acknowledge an interrupt
392 * @handle: handle to the target interrupt controller
393 * @vector: returned interrupt vector
395 * If handle is zero, the function returns the next interrupt source
397 * of interrupt controllers. If non-zero, specifies a handle to the
398 * interrupt controller that is the target of the acknowledge.
445 * ev_idle -- wait for next interrupt on this core
H A Dedac.h14 * ECC atomic, DMA, SMP and interrupt safe scrub function.
27 * so we are interrupt, DMA and SMP safe. atomic_scrub()
/linux-4.1.27/sound/pci/emu10k1/
H A Dirq.c49 dev_err(emu->card->dev, "interrupt: PCI error\n"); snd_emu10k1_interrupt()
71 if (pvoice->use && pvoice->interrupt != NULL) { snd_emu10k1_interrupt()
72 pvoice->interrupt(emu, pvoice); snd_emu10k1_interrupt()
86 if (pvoice->use && pvoice->interrupt != NULL) { snd_emu10k1_interrupt()
87 pvoice->interrupt(emu, pvoice); snd_emu10k1_interrupt()
121 if (emu->midi.interrupt) snd_emu10k1_interrupt()
122 emu->midi.interrupt(emu, status); snd_emu10k1_interrupt()
128 if (emu->midi2.interrupt) snd_emu10k1_interrupt()
129 emu->midi2.interrupt(emu, status); snd_emu10k1_interrupt()
188 "unhandled interrupt: 0x%08x\n", status); snd_emu10k1_interrupt()
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Damplc_dio200.c139 * digital inputs come from the interrupt status register. The number of
140 * channels matches the number of interrupt sources. The PC214E does not
141 * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
166 * When an interrupt source is enabled in the interrupt source enable
168 * bit to 1 in the interrupt status register.
170 * When the interrupt status register value as a whole (actually, just the
172 * generate an interrupt. No further interrupts will occur until the
173 * interrupt status register is cleared to zero. To clear a bit to zero in
174 * the interrupt status register, the corresponding interrupt source must
175 * be disabled in the interrupt source enable register (there is no
176 * separate interrupt clear register).
178 * The PC214E does not have an interrupt source enable register or an
179 * interrupt status register; its 'INTERRUPT' subdevice has a single
180 * channel and its interrupt source is selected by the position of jumper
186 * 'INTERRUPT' subdevice. The channel list selects the interrupt sources
188 * TRIG_NOW). The scan begins a short time after the hardware interrupt
189 * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
190 * scan_begin_arg == 0). The value read from the interrupt status register
H A Daddi_apci_1032.c38 * interrupts (if an interrupt handler can be set up successfully).
42 * Change-Of-State (COS) interrupt configuration:
49 * - interrupt is generated when any enabled channel meets the desired
50 * interrupt condition
54 * - interrupt is generated when all enabled channels meet the desired
55 * interrupt condition
56 * - after an interrupt, a change in level must occur on the selected
74 #include <linux/interrupt.h>
95 unsigned int ctrl; /* interrupt mode OR (edge) . AND (level) */
102 /* Reset the interrupt status register */ apci1032_reset()
104 /* Disable the and/or interrupt */ apci1032_reset()
231 * Enable the COS interrupt as configured by apci1032_cos_insn_config().
264 /* check interrupt is from this device */ apci1032_interrupt()
269 /* check interrupt is enabled */ apci1032_interrupt()
274 /* disable the interrupt */ apci1032_interrupt()
281 /* enable the interrupt */ apci1032_interrupt()
336 /* Change-Of-State (COS) interrupt subdevice */ apci1032_auto_attach()
/linux-4.1.27/drivers/gpu/host1x/
H A Dintr.h22 #include <linux/interrupt.h>
89 /* Initialize host1x sync point interrupt */
92 /* Deinitialize host1x sync point interrupt */
95 /* Enable host1x sync point interrupt */
98 /* Disable host1x sync point interrupt */
/linux-4.1.27/arch/sh/drivers/pci/
H A Dfixups-dreamcast.c21 #include <linux/interrupt.h>
82 * The interrupt routing semantics here are quite trivial. pcibios_map_platform_irq()
84 * We basically only support one interrupt, so we only bother pcibios_map_platform_irq()
85 * updating a device's interrupt line with this single shared pcibios_map_platform_irq()
86 * interrupt. Keeps routing quite simple, doesn't it? pcibios_map_platform_irq()
/linux-4.1.27/arch/mips/include/asm/sn/
H A Dintr.h11 /* Number of interrupt levels associated with each interrupt register. */
21 * Macros to manipulate the interrupt register on the calling hub chip.
30 * When clearing the interrupt, make sure this clear does make it
50 * Hard-coded interrupt levels:
/linux-4.1.27/sound/soc/txx9/
H A Dtxx9aclc.h12 #include <linux/interrupt.h>
30 #define ACINTSTS 0x10 /* interrupt status */
31 #define ACINTMSTS 0x14 /* interrupt masked status */
32 #define ACINTEN 0x18 /* interrupt enable */
33 #define ACINTDIS 0x1c /* interrupt disable */
/linux-4.1.27/arch/mips/sgi-ip27/
H A Dip27-irq.c2 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
17 #include <linux/interrupt.h>
39 * Linux has a controller-independent x86 interrupt architecture.
42 * interrupt source is transparently wired to the appropriate
44 * interrupt-controller.
46 * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
51 * interrupt controllers, without having to do assembly magic.
154 panic("CPU %d got a profiling interrupt", smp_processor_id()); ip27_prof_timer()
159 panic("CPU %d got a hub error interrupt", smp_processor_id()); ip27_hub_error()
/linux-4.1.27/arch/powerpc/oprofile/
H A Dop_model_7450.c55 /* Unfreezes the counters on this CPU, enables the interrupt,
56 * enables the counters to trigger the interrupt, and sets the
104 * how much before the next interrupt, and we interrupt fsl7450_reg_setup()
148 /* Clear the freeze bit, and enable the interrupt. fsl7450_start()
170 /* Handle the interrupt on this CPU, and log a sample for each
171 * event that triggered the interrupt */ fsl7450_handle_interrupt()
198 /* The freeze bit was set by the interrupt. */ fsl7450_handle_interrupt()
199 /* Clear the freeze bit, and reenable the interrupt. fsl7450_handle_interrupt()
/linux-4.1.27/drivers/acpi/acpica/
H A Devgpeutil.c76 /* Walk the interrupt level descriptor list */ acpi_ev_walk_gpe_list()
81 /* Walk all Gpe Blocks attached to this interrupt level */ acpi_ev_walk_gpe_list()
157 * DESCRIPTION: Get or Create a GPE interrupt block. There is one interrupt
158 * block per unique interrupt level used for GPEs. Should be
196 /* Install new interrupt descriptor with spin lock */ acpi_ev_get_gpe_xrupt_block()
213 /* Install new interrupt handler if not SCI_INT */ acpi_ev_get_gpe_xrupt_block()
221 "Could not install GPE interrupt handler at level 0x%X", acpi_ev_get_gpe_xrupt_block()
235 * PARAMETERS: gpe_xrupt - A GPE interrupt info block
240 * interrupt handler if not the SCI interrupt.
251 /* We never want to remove the SCI interrupt handler */ acpi_ev_delete_gpe_xrupt()
258 /* Disable this interrupt */ acpi_ev_delete_gpe_xrupt()
267 /* Unlink the interrupt block with lock */ acpi_ev_delete_gpe_xrupt()
/linux-4.1.27/arch/m68k/68360/
H A Dcommproc.c40 #include <linux/interrupt.h>
65 /* CPM interrupt vector functions. */
94 * - Set sdma interrupt service mask to 7 m360_cpm_reset()
127 /* Initialize the CPM interrupt controller. cpm_interrupt_init()
147 /* Set our interrupt handler with the core CPU. */ cpm_interrupt_init()
156 /* master CPM interrupt enable */ cpm_interrupt_init()
162 /* CPM interrupt controller interrupt.
190 /* After servicing the interrupt, we have to remove the status cpm_interrupt()
198 /* The CPM can generate the error interrupt when there is a race condition
201 * tests in the interrupt handler.
208 /* Install a CPM interrupt handler.
217 /* printk(KERN_INFO "CPM interrupt %x replacing %x\n", */ cpm_install_handler()
227 /* Free a CPM interrupt handler.
/linux-4.1.27/sound/arm/
H A Daaci.h38 #define AACI_SLISTAT 0x06c /* slot interrupt status */
39 #define AACI_SLIEN 0x070 /* slot interrupt enable */
40 #define AACI_INTCLR 0x074 /* interrupt clear */
44 #define AACI_ALLINTS 0x084 /* all fifo interrupt status */
91 * interrupt status register bits.
102 * interrupt enable register bits.
113 * interrupt status. P51
118 #define ISR_RX (1 << 3) /* rx interrupt status */
119 #define ISR_TX (1 << 2) /* tx interrupt status */
124 * interrupt enable. P52
129 #define IE_RX (1 << 3) /* rx interrupt status */
130 #define IE_TX (1 << 2) /* tx interrupt status */
137 #define SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */
138 #define SLFR_RGPIOINTR (1 << 12) /* raw gpio interrupt */
/linux-4.1.27/drivers/crypto/ux500/cryp/
H A Dcryp_irqp.h32 * 18h | CRYP_RIS | Raw interrupt status
34 * 1ch | CRYP_MIS | Masked interrupt status.
54 * @ris - Raw interrupt status
55 * @mis - Masked interrupt statu register
91 u32 ris; /* Raw interrupt status */
92 u32 mis; /* Masked interrupt statu register */
/linux-4.1.27/arch/tile/include/gxio/
H A Duart.h50 * @param bind_cpu_x X coordinate of CPU to which interrupt will be delivered.
51 * @param bind_cpu_y Y coordinate of CPU to which interrupt will be delivered.
52 * @param bind_interrupt IPI interrupt number.
53 * @param bind_event Sub-interrupt event bit number; a negative value can
54 * disable the interrupt.
56 * configured to interrupt.
/linux-4.1.27/arch/sh/boards/mach-cayman/
H A Dirq.c4 * This file handles the board specific parts of the Cayman interrupt system
14 #include <linux/interrupt.h>
32 the same SH-5 interrupt */
36 printk(KERN_INFO "CAYMAN: spurious SMSC interrupt\n"); cayman_interrupt_smsc()
42 printk(KERN_INFO "CAYMAN: spurious PCI interrupt, IRQ %d\n", irq); cayman_interrupt_pci2()
154 /* Setup the SMSC interrupt */ init_cayman_irq()
/linux-4.1.27/arch/mips/pci/
H A Dfixup-lemote2f.c21 /* PCI interrupt pins
23 * These should not be changed, or you should consider loongson2f interrupt
101 /* the uart1 and uart2 interrupt in PIC is enabled as default */ loongson_cs5536_isa_fixup()
115 /* enable the AUDIO interrupt in PIC */ loongson_cs5536_acc_fixup()
123 /* enable the OHCI interrupt in PIC */ loongson_cs5536_ohci_fixup()
124 /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */ loongson_cs5536_ohci_fixup()
/linux-4.1.27/arch/cris/include/arch-v32/arch/
H A Dirq.h78 * which will acknowledge the interrupt, is run. The actual blocking is made
95 * This is subtle. The timer interrupt is crucial and it should not be disabled
96 * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it
102 * multiple_irq handler is run and it prioritizes the timer interrupt. However
105 * The non-blocking here is based on the knowledge that the timer interrupt runs
107 * timer irq handler is run to acknowledge the interrupt.
/linux-4.1.27/arch/hexagon/kernel/
H A Dirq_cpu.c2 * First-level interrupt controller model for Hexagon.
21 #include <linux/interrupt.h>
67 * The hexagon core comes with a first-level interrupt controller
70 * macro cells that provide one or more second-level interrupt
76 * The first-level interrupt controller is wrapped by the VM, which
77 * virtualizes the interrupt controller for us. It provides a very
/linux-4.1.27/arch/arm/mach-realview/include/mach/
H A Dirqs-pb1176.h28 * ARM1176 DevChip interrupt sources (primary GIC)
31 #define IRQ_DC1176_SOFTINT (IRQ_DC1176_GIC_START + 1) /* Software interrupt */
32 #define IRQ_DC1176_COMMRx (IRQ_DC1176_GIC_START + 2) /* Debug Comm Rx interrupt */
33 #define IRQ_DC1176_COMMTx (IRQ_DC1176_GIC_START + 3) /* Debug Comm Tx interrupt */
34 #define IRQ_DC1176_CORE_PMU (IRQ_DC1176_GIC_START + 7) /* Core PMU interrupt */
54 * RealView PB1176 interrupt sources (secondary GIC)
/linux-4.1.27/arch/blackfin/include/asm/
H A Ddef_LPBlackfin.h494 #define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
495 #define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
496 #define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
498 #define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
499 #define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
500 #define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
501 #define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
502 #define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
503 #define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
504 #define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
505 #define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
506 #define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
507 #define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
508 #define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
509 #define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
512 #define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
513 #define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
514 #define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
516 #define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
517 #define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
518 #define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
519 #define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
520 #define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
521 #define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
522 #define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
523 #define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
524 #define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
525 #define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
526 #define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
527 #define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
598 #define TINT 0x00000008 /* Timer generated interrupt 0=no
599 * interrupt has been generated,
600 * 1=interrupt has been generated
/linux-4.1.27/drivers/scsi/
H A Deata_pio.h40 #define DBG_INTR 0 /* Trace interrupt service routine. */
41 #define DBG_INTR2 0 /* Trace interrupt service routine. */
/linux-4.1.27/arch/x86/platform/intel-mid/device_libs/
H A Dplatform_wdt.c14 #include <linux/interrupt.h>
39 dev_warn(&pdev->dev, "cannot find interrupt %d in ioapic\n", tangier_probe()
/linux-4.1.27/arch/tile/include/hv/
H A Ddrv_pcie_rc_intf.h23 /** File offset for reading the interrupt base number used for PCIE legacy
34 int intr; /**< interrupt number used for downcall */
/linux-4.1.27/arch/microblaze/kernel/
H A Dirq.c15 #include <linux/interrupt.h>
51 /* process the entire interrupt tree in one go */ init_IRQ()
/linux-4.1.27/arch/mips/include/asm/mach-cobalt/
H A Dirq.h31 * 0 - Software interrupt 0 (unused)
32 * 1 - Software interrupt 0 (unused)
/linux-4.1.27/drivers/tty/serial/
H A Dm32r_sio_reg.h127 #define UART_LSR_BI 0x00 /* Break interrupt indicator */
137 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
139 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
141 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
142 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
147 #define UART_IER_MSI 0x00 /* Enable Modem status interrupt */
148 #define UART_IER_RLSI 0x08 /* Enable receiver line status interrupt */
150 #define UART_IER_RDI 0x04 /* Enable receiver data interrupt */
/linux-4.1.27/drivers/pinctrl/qcom/
H A Dpinctrl-msm.h42 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
52 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
53 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
55 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
56 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
59 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
60 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
61 * @intr_detection_width: Number of bits used for specifying interrupt type,
/linux-4.1.27/arch/sh/boards/mach-highlander/
H A Dirq-r7780rp.c20 /* board specific interrupt sources */
61 printk(KERN_INFO "Using r7780rp interrupt controller.\n"); highlander_plat_irq_setup()
/linux-4.1.27/arch/sh/boards/mach-sdk7780/
H A Dirq.c19 /* board specific interrupt sources */
38 printk(KERN_INFO "Using SDK7780 interrupt controller.\n"); init_sdk7780_IRQ()
/linux-4.1.27/arch/blackfin/include/mach-common/
H A Dirq.h13 * Core events interrupt source definitions
39 #define IRQ_UNUSED 4 /* - unused interrupt */
/linux-4.1.27/arch/m32r/include/asm/m32104ut/
H A Dm32104ut_pld.h63 * ICUCR3: control register for CFIREQ# interrupt
64 * ICUCR4: control register for CFC Card insert interrupt
65 * ICUCR5: control register for CFC Card eject interrupt
66 * ICUCR6: control register for external interrupt
67 * ICUCR11: control register for MMC Card insert/eject interrupt
68 * ICUCR13: control register for SC error interrupt
69 * ICUCR14: control register for SC receive interrupt
70 * ICUCR15: control register for SC send interrupt
/linux-4.1.27/arch/m32r/kernel/
H A Dirq.c13 * This file contains the lowest level m32r-specific interrupt
20 #include <linux/interrupt.h>
/linux-4.1.27/arch/arm/mach-ux500/
H A Dpm.c29 /* Dual A9 core interrupt management unit registers */
80 * db8500_prcmu_gic_decouple function. Disabling an interrupt only
81 * disables the forwarding of the interrupt to any CPU interface. It
82 * does not prevent the interrupt from changing state, for example
84 * active. Hence, we have to check the interrupt is pending *and* is
101 return true; /* There is a pending interrupt */ prcmu_gic_pending_irq()
108 * This function checks if there are pending interrupt on the
121 return true; /* There is a pending interrupt */ prcmu_pending_irq()
/linux-4.1.27/drivers/iommu/
H A Dirq_remapping.h18 * This header file contains stuff that is shared between different interrupt
60 /* Set the CPU affinity of a remapped interrupt */
67 /* Create MSI msg to use for interrupt remapping */
78 /* Setup interrupt remapping for an HPET MSI */
/linux-4.1.27/drivers/misc/mei/
H A DMakefile8 mei-objs += interrupt.o
/linux-4.1.27/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h176 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
178 #define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */
184 #define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels
189 /* Masks of interrupts at each interrupt level: */
198 /* Masks of interrupts at each range 1..n of interrupt levels: */
207 /* Level of each interrupt: */
225 #define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
226 #define XCHAL_HAVE_DEBUG_EXTERN_INT 0 /* OCD external db interrupt */
228 /* Type of each interrupt: */
247 /* Masks of interrupts for each type of interrupt: */
256 /* Interrupt numbers assigned to specific interrupt sources: */
262 /* Interrupt numbers for levels at which only one interrupt is configured: */
267 * External interrupt vectors/levels.
268 * These macros describe how Xtensa processor interrupt numbers
275 /* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
/linux-4.1.27/arch/microblaze/include/asm/
H A Dirq.h18 /* should be defined in each interrupt controller driver */
/linux-4.1.27/arch/mips/include/asm/mach-ip27/
H A Dirq.h14 * A hardwired interrupt number is completly stupid for this system - a
/linux-4.1.27/arch/powerpc/platforms/cell/
H A Dspider-pic.c23 #include <linux/interrupt.h>
31 #include "interrupt.h"
151 * be the same as the interrupt source number. I don't know whether spider_set_irq_type()
188 /* Spider interrupts have 2 cells, first is the interrupt source, spider_host_xlate()
221 * crap and we don't know on which BE iic interrupt we are hooked on at
226 * interrupt-map property which is pretty strange.
243 tmp = of_get_property(pic->host->of_node, "#interrupt-cells", NULL); spider_find_cascade_and_node()
247 imap = of_get_property(pic->host->of_node, "interrupt-map", &imaplen); spider_find_cascade_and_node()
254 tmp = of_get_property(iic, "#interrupt-cells", NULL); spider_find_cascade_and_node()
260 /* Assume unit is last entry of interrupt specifier */ spider_find_cascade_and_node()
263 tmp = of_get_property(iic, "ibm,interrupt-server-ranges", NULL); spider_find_cascade_and_node()
276 /* Manufacture an IIC interrupt number of class 2 */ spider_find_cascade_and_node()
313 /* enable interrupt packets to be output */ spider_init_one()
316 /* Hook up the cascade interrupt to the iic and nodeid */ spider_init_one()
326 /* Enable the interrupt detection enable bit. Do this last! */ spider_init_one()
344 (dn = of_find_node_by_name(dn, "interrupt-controller"));) { spider_init_IRQ()

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