Searched refs:pm (Results 1 - 200 of 1752) sorted by relevance

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/linux-4.1.27/drivers/input/touchscreen/
H A Dpenmount.c54 struct pm { struct
63 void (*parse_packet)(struct pm *);
70 static void pm_mtevent(struct pm *pm, struct input_dev *input) pm_mtevent() argument
74 for (i = 0; i < pm->maxcontacts; ++i) { pm_mtevent()
77 pm->slots[i].active); pm_mtevent()
78 if (pm->slots[i].active) { pm_mtevent()
79 input_event(input, EV_ABS, ABS_MT_POSITION_X, pm->slots[i].x); pm_mtevent()
80 input_event(input, EV_ABS, ABS_MT_POSITION_Y, pm->slots[i].y); pm_mtevent()
103 static void pm_parse_9000(struct pm *pm) pm_parse_9000() argument
105 struct input_dev *dev = pm->dev; pm_parse_9000()
107 if ((pm->data[0] & 0x80) && pm->packetsize == ++pm->idx) { pm_parse_9000()
108 input_report_abs(dev, ABS_X, pm->data[1] * 128 + pm->data[2]); pm_parse_9000()
109 input_report_abs(dev, ABS_Y, pm->data[3] * 128 + pm->data[4]); pm_parse_9000()
110 input_report_key(dev, BTN_TOUCH, !!(pm->data[0] & 0x40)); pm_parse_9000()
112 pm->idx = 0; pm_parse_9000()
116 static void pm_parse_6000(struct pm *pm) pm_parse_6000() argument
118 struct input_dev *dev = pm->dev; pm_parse_6000()
120 if ((pm->data[0] & 0xbf) == 0x30 && pm->packetsize == ++pm->idx) { pm_parse_6000()
121 if (pm_checkpacket(pm->data)) { pm_parse_6000()
123 pm->data[2] * 256 + pm->data[1]); pm_parse_6000()
125 pm->data[4] * 256 + pm->data[3]); pm_parse_6000()
126 input_report_key(dev, BTN_TOUCH, pm->data[0] & 0x40); pm_parse_6000()
129 pm->idx = 0; pm_parse_6000()
133 static void pm_parse_3000(struct pm *pm) pm_parse_3000() argument
135 struct input_dev *dev = pm->dev; pm_parse_3000()
137 if ((pm->data[0] & 0xce) == 0x40 && pm->packetsize == ++pm->idx) { pm_parse_3000()
138 if (pm_checkpacket(pm->data)) { pm_parse_3000()
139 int slotnum = pm->data[0] & 0x0f; pm_parse_3000()
140 pm->slots[slotnum].active = pm->data[0] & 0x30; pm_parse_3000()
141 pm->slots[slotnum].x = pm->data[2] * 256 + pm->data[1]; pm_parse_3000()
142 pm->slots[slotnum].y = pm->data[4] * 256 + pm->data[3]; pm_parse_3000()
143 pm_mtevent(pm, dev); pm_parse_3000()
145 pm->idx = 0; pm_parse_3000()
149 static void pm_parse_6250(struct pm *pm) pm_parse_6250() argument
151 struct input_dev *dev = pm->dev; pm_parse_6250()
153 if ((pm->data[0] & 0xb0) == 0x30 && pm->packetsize == ++pm->idx) { pm_parse_6250()
154 if (pm_checkpacket(pm->data)) { pm_parse_6250()
155 int slotnum = pm->data[0] & 0x0f; pm_parse_6250()
156 pm->slots[slotnum].active = pm->data[0] & 0x40; pm_parse_6250()
157 pm->slots[slotnum].x = pm->data[2] * 256 + pm->data[1]; pm_parse_6250()
158 pm->slots[slotnum].y = pm->data[4] * 256 + pm->data[3]; pm_parse_6250()
159 pm_mtevent(pm, dev); pm_parse_6250()
161 pm->idx = 0; pm_parse_6250()
168 struct pm *pm = serio_get_drvdata(serio); pm_interrupt() local
170 pm->data[pm->idx] = data; pm_interrupt()
172 pm->parse_packet(pm); pm_interrupt()
183 struct pm *pm = serio_get_drvdata(serio); pm_disconnect() local
187 input_unregister_device(pm->dev); pm_disconnect()
188 kfree(pm); pm_disconnect()
201 struct pm *pm; pm_connect() local
206 pm = kzalloc(sizeof(struct pm), GFP_KERNEL); pm_connect()
208 if (!pm || !input_dev) { pm_connect()
213 pm->serio = serio; pm_connect()
214 pm->dev = input_dev; pm_connect()
215 snprintf(pm->phys, sizeof(pm->phys), "%s/input0", serio->phys); pm_connect()
216 pm->maxcontacts = 1; pm_connect()
219 input_dev->phys = pm->phys; pm_connect()
232 pm->packetsize = 5; pm_connect()
233 pm->parse_packet = pm_parse_9000; pm_connect()
239 pm->packetsize = 6; pm_connect()
240 pm->parse_packet = pm_parse_6000; pm_connect()
246 pm->packetsize = 6; pm_connect()
247 pm->parse_packet = pm_parse_3000; pm_connect()
250 pm->maxcontacts = PM_3000_MTSLOT; pm_connect()
254 pm->packetsize = 6; pm_connect()
255 pm->parse_packet = pm_parse_6250; pm_connect()
258 pm->maxcontacts = PM_6250_MTSLOT; pm_connect()
262 input_set_abs_params(pm->dev, ABS_X, 0, max_x, 0, 0); pm_connect()
263 input_set_abs_params(pm->dev, ABS_Y, 0, max_y, 0, 0); pm_connect()
265 if (pm->maxcontacts > 1) { pm_connect()
266 input_mt_init_slots(pm->dev, pm->maxcontacts, 0); pm_connect()
267 input_set_abs_params(pm->dev, pm_connect()
269 input_set_abs_params(pm->dev, pm_connect()
273 serio_set_drvdata(serio, pm); pm_connect()
279 err = input_register_device(pm->dev); pm_connect()
288 kfree(pm); pm_connect()
H A Dad7879-i2c.c13 #include <linux/pm.h>
98 .pm = &ad7879_pm_ops,
H A Dad7879-spi.c10 #include <linux/pm.h>
153 .pm = &ad7879_pm_ops,
H A Dipaq-micro-ts.c17 #include <linux/pm.h>
156 .pm = &micro_ts_dev_pm_ops,
H A Dcyttsp4_i2c.c78 .pm = &cyttsp4_pm_ops,
H A Dcyttsp_i2c.c78 .pm = &cyttsp_pm_ops,
/linux-4.1.27/drivers/base/power/
H A Dgeneric_ops.c9 #include <linux/pm.h>
24 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_runtime_suspend() local
27 ret = pm && pm->runtime_suspend ? pm->runtime_suspend(dev) : 0; pm_generic_runtime_suspend()
43 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_runtime_resume() local
46 ret = pm && pm->runtime_resume ? pm->runtime_resume(dev) : 0; pm_generic_runtime_resume()
65 if (drv && drv->pm && drv->pm->prepare) pm_generic_prepare()
66 ret = drv->pm->prepare(dev); pm_generic_prepare()
77 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_suspend_noirq() local
79 return pm && pm->suspend_noirq ? pm->suspend_noirq(dev) : 0; pm_generic_suspend_noirq()
89 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_suspend_late() local
91 return pm && pm->suspend_late ? pm->suspend_late(dev) : 0; pm_generic_suspend_late()
101 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_suspend() local
103 return pm && pm->suspend ? pm->suspend(dev) : 0; pm_generic_suspend()
113 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_freeze_noirq() local
115 return pm && pm->freeze_noirq ? pm->freeze_noirq(dev) : 0; pm_generic_freeze_noirq()
125 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_freeze_late() local
127 return pm && pm->freeze_late ? pm->freeze_late(dev) : 0; pm_generic_freeze_late()
137 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_freeze() local
139 return pm && pm->freeze ? pm->freeze(dev) : 0; pm_generic_freeze()
149 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_poweroff_noirq() local
151 return pm && pm->poweroff_noirq ? pm->poweroff_noirq(dev) : 0; pm_generic_poweroff_noirq()
161 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_poweroff_late() local
163 return pm && pm->poweroff_late ? pm->poweroff_late(dev) : 0; pm_generic_poweroff_late()
173 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_poweroff() local
175 return pm && pm->poweroff ? pm->poweroff(dev) : 0; pm_generic_poweroff()
185 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_thaw_noirq() local
187 return pm && pm->thaw_noirq ? pm->thaw_noirq(dev) : 0; pm_generic_thaw_noirq()
197 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_thaw_early() local
199 return pm && pm->thaw_early ? pm->thaw_early(dev) : 0; pm_generic_thaw_early()
209 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_thaw() local
211 return pm && pm->thaw ? pm->thaw(dev) : 0; pm_generic_thaw()
221 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_resume_noirq() local
223 return pm && pm->resume_noirq ? pm->resume_noirq(dev) : 0; pm_generic_resume_noirq()
233 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_resume_early() local
235 return pm && pm->resume_early ? pm->resume_early(dev) : 0; pm_generic_resume_early()
245 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_resume() local
247 return pm && pm->resume ? pm->resume(dev) : 0; pm_generic_resume()
257 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_restore_noirq() local
259 return pm && pm->restore_noirq ? pm->restore_noirq(dev) : 0; pm_generic_restore_noirq()
269 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_restore_early() local
271 return pm && pm->restore_early ? pm->restore_early(dev) : 0; pm_generic_restore_early()
281 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pm_generic_restore() local
283 return pm && pm->restore ? pm->restore(dev) : 0; pm_generic_restore()
297 if (drv && drv->pm && drv->pm->complete) pm_generic_complete()
298 drv->pm->complete(dev); pm_generic_complete()
H A Dmain.c24 #include <linux/pm.h>
26 #include <linux/pm-trace.h>
426 * dpm_watchdog_set - Enable pm watchdog for given device.
493 } else if (dev->type && dev->type->pm) { device_resume_noirq()
495 callback = pm_noirq_op(dev->type->pm, state); device_resume_noirq()
496 } else if (dev->class && dev->class->pm) { device_resume_noirq()
498 callback = pm_noirq_op(dev->class->pm, state); device_resume_noirq()
499 } else if (dev->bus && dev->bus->pm) { device_resume_noirq()
501 callback = pm_noirq_op(dev->bus->pm, state); device_resume_noirq()
504 if (!callback && dev->driver && dev->driver->pm) { device_resume_noirq()
506 callback = pm_noirq_op(dev->driver->pm, state); device_resume_noirq()
622 } else if (dev->type && dev->type->pm) { device_resume_early()
624 callback = pm_late_early_op(dev->type->pm, state); device_resume_early()
625 } else if (dev->class && dev->class->pm) { device_resume_early()
627 callback = pm_late_early_op(dev->class->pm, state); device_resume_early()
628 } else if (dev->bus && dev->bus->pm) { device_resume_early()
630 callback = pm_late_early_op(dev->bus->pm, state); device_resume_early()
633 if (!callback && dev->driver && dev->driver->pm) { device_resume_early()
635 callback = pm_late_early_op(dev->driver->pm, state); device_resume_early()
768 if (dev->type && dev->type->pm) { device_resume()
770 callback = pm_op(dev->type->pm, state); device_resume()
775 if (dev->class->pm) { device_resume()
777 callback = pm_op(dev->class->pm, state); device_resume()
787 if (dev->bus->pm) { device_resume()
789 callback = pm_op(dev->bus->pm, state); device_resume()
798 if (!callback && dev->driver && dev->driver->pm) { device_resume()
800 callback = pm_op(dev->driver->pm, state); device_resume()
905 } else if (dev->type && dev->type->pm) { device_complete()
907 callback = dev->type->pm->complete; device_complete()
908 } else if (dev->class && dev->class->pm) { device_complete()
910 callback = dev->class->pm->complete; device_complete()
911 } else if (dev->bus && dev->bus->pm) { device_complete()
913 callback = dev->bus->pm->complete; device_complete()
916 if (!callback && dev->driver && dev->driver->pm) { device_complete()
918 callback = dev->driver->pm->complete; device_complete()
1039 } else if (dev->type && dev->type->pm) { __device_suspend_noirq()
1041 callback = pm_noirq_op(dev->type->pm, state); __device_suspend_noirq()
1042 } else if (dev->class && dev->class->pm) { __device_suspend_noirq()
1044 callback = pm_noirq_op(dev->class->pm, state); __device_suspend_noirq()
1045 } else if (dev->bus && dev->bus->pm) { __device_suspend_noirq()
1047 callback = pm_noirq_op(dev->bus->pm, state); __device_suspend_noirq()
1050 if (!callback && dev->driver && dev->driver->pm) { __device_suspend_noirq()
1052 callback = pm_noirq_op(dev->driver->pm, state); __device_suspend_noirq()
1185 } else if (dev->type && dev->type->pm) { __device_suspend_late()
1187 callback = pm_late_early_op(dev->type->pm, state); __device_suspend_late()
1188 } else if (dev->class && dev->class->pm) { __device_suspend_late()
1190 callback = pm_late_early_op(dev->class->pm, state); __device_suspend_late()
1191 } else if (dev->bus && dev->bus->pm) { __device_suspend_late()
1193 callback = pm_late_early_op(dev->bus->pm, state); __device_suspend_late()
1196 if (!callback && dev->driver && dev->driver->pm) { __device_suspend_late()
1198 callback = pm_late_early_op(dev->driver->pm, state); __device_suspend_late()
1395 if (dev->type && dev->type->pm) { __device_suspend()
1397 callback = pm_op(dev->type->pm, state); __device_suspend()
1402 if (dev->class->pm) { __device_suspend()
1404 callback = pm_op(dev->class->pm, state); __device_suspend()
1415 if (dev->bus->pm) { __device_suspend()
1417 callback = pm_op(dev->bus->pm, state); __device_suspend()
1427 if (!callback && dev->driver && dev->driver->pm) { __device_suspend()
1429 callback = pm_op(dev->driver->pm, state); __device_suspend()
1573 } else if (dev->type && dev->type->pm) { device_prepare()
1575 callback = dev->type->pm->prepare; device_prepare()
1576 } else if (dev->class && dev->class->pm) { device_prepare()
1578 callback = dev->class->pm->prepare; device_prepare()
1579 } else if (dev->bus && dev->bus->pm) { device_prepare()
1581 callback = dev->bus->pm->prepare; device_prepare()
1584 if (!callback && dev->driver && dev->driver->pm) { device_prepare()
1586 callback = dev->driver->pm->prepare; device_prepare()
/linux-4.1.27/drivers/media/platform/s5p-mfc/
H A Ds5p_mfc_pm.c27 static struct s5p_mfc_pm *pm; variable in typeref:struct:s5p_mfc_pm
38 pm = &dev->pm; s5p_mfc_init_pm()
40 pm->clock_gate = clk_get(&dev->plat_dev->dev, MFC_GATE_CLK_NAME); s5p_mfc_init_pm()
41 if (IS_ERR(pm->clock_gate)) { s5p_mfc_init_pm()
43 ret = PTR_ERR(pm->clock_gate); s5p_mfc_init_pm()
47 ret = clk_prepare(pm->clock_gate); s5p_mfc_init_pm()
54 pm->clock = clk_get(&dev->plat_dev->dev, MFC_SCLK_NAME); s5p_mfc_init_pm()
55 if (IS_ERR(pm->clock)) { s5p_mfc_init_pm()
58 clk_set_rate(pm->clock, MFC_SCLK_RATE); s5p_mfc_init_pm()
59 ret = clk_prepare_enable(pm->clock); s5p_mfc_init_pm()
67 atomic_set(&pm->power, 0); s5p_mfc_init_pm()
69 pm->device = &dev->plat_dev->dev; s5p_mfc_init_pm()
70 pm_runtime_enable(pm->device); s5p_mfc_init_pm()
78 clk_put(pm->clock); s5p_mfc_init_pm()
80 clk_put(pm->clock_gate); s5p_mfc_init_pm()
88 pm->clock) { s5p_mfc_final_pm()
89 clk_disable_unprepare(pm->clock); s5p_mfc_final_pm()
90 clk_put(pm->clock); s5p_mfc_final_pm()
92 clk_unprepare(pm->clock_gate); s5p_mfc_final_pm()
93 clk_put(pm->clock_gate); s5p_mfc_final_pm()
95 pm_runtime_disable(pm->device); s5p_mfc_final_pm()
106 ret = clk_enable(pm->clock_gate); s5p_mfc_clock_on()
116 clk_disable(pm->clock_gate); s5p_mfc_clock_off()
122 return pm_runtime_get_sync(pm->device); s5p_mfc_power_on()
124 atomic_set(&pm->power, 1); s5p_mfc_power_on()
132 return pm_runtime_put_sync(pm->device); s5p_mfc_power_off()
134 atomic_set(&pm->power, 0); s5p_mfc_power_off()
/linux-4.1.27/drivers/input/misc/
H A Dpowermate.c87 struct powermate_device *pm = urb->context; powermate_irq() local
88 struct device *dev = &pm->intf->dev; powermate_irq()
109 input_report_key(pm->input, BTN_0, pm->data[0] & 0x01); powermate_irq()
110 input_report_rel(pm->input, REL_DIAL, pm->data[1]); powermate_irq()
111 input_sync(pm->input); powermate_irq()
120 /* Decide if we need to issue a control message and do so. Must be called with pm->lock taken */ powermate_sync_state()
121 static void powermate_sync_state(struct powermate_device *pm) powermate_sync_state() argument
123 if (pm->requires_update == 0) powermate_sync_state()
125 if (pm->config->status == -EINPROGRESS) powermate_sync_state()
128 if (pm->requires_update & UPDATE_PULSE_ASLEEP){ powermate_sync_state()
129 pm->configcr->wValue = cpu_to_le16( SET_PULSE_ASLEEP ); powermate_sync_state()
130 pm->configcr->wIndex = cpu_to_le16( pm->pulse_asleep ? 1 : 0 ); powermate_sync_state()
131 pm->requires_update &= ~UPDATE_PULSE_ASLEEP; powermate_sync_state()
132 }else if (pm->requires_update & UPDATE_PULSE_AWAKE){ powermate_sync_state()
133 pm->configcr->wValue = cpu_to_le16( SET_PULSE_AWAKE ); powermate_sync_state()
134 pm->configcr->wIndex = cpu_to_le16( pm->pulse_awake ? 1 : 0 ); powermate_sync_state()
135 pm->requires_update &= ~UPDATE_PULSE_AWAKE; powermate_sync_state()
136 }else if (pm->requires_update & UPDATE_PULSE_MODE){ powermate_sync_state()
155 if (pm->pulse_speed < 255) { powermate_sync_state()
157 arg = 255 - pm->pulse_speed; powermate_sync_state()
158 } else if (pm->pulse_speed > 255) { powermate_sync_state()
160 arg = pm->pulse_speed - 255; powermate_sync_state()
165 pm->configcr->wValue = cpu_to_le16( (pm->pulse_table << 8) | SET_PULSE_MODE ); powermate_sync_state()
166 pm->configcr->wIndex = cpu_to_le16( (arg << 8) | op ); powermate_sync_state()
167 pm->requires_update &= ~UPDATE_PULSE_MODE; powermate_sync_state()
168 } else if (pm->requires_update & UPDATE_STATIC_BRIGHTNESS) { powermate_sync_state()
169 pm->configcr->wValue = cpu_to_le16( SET_STATIC_BRIGHTNESS ); powermate_sync_state()
170 pm->configcr->wIndex = cpu_to_le16( pm->static_brightness ); powermate_sync_state()
171 pm->requires_update &= ~UPDATE_STATIC_BRIGHTNESS; powermate_sync_state()
174 pm->requires_update = 0; /* fudge the bug */ powermate_sync_state()
178 /* printk("powermate: %04x %04x\n", pm->configcr->wValue, pm->configcr->wIndex); */ powermate_sync_state()
180 pm->configcr->bRequestType = 0x41; /* vendor request */ powermate_sync_state()
181 pm->configcr->bRequest = 0x01; powermate_sync_state()
182 pm->configcr->wLength = 0; powermate_sync_state()
184 usb_fill_control_urb(pm->config, pm->udev, usb_sndctrlpipe(pm->udev, 0), powermate_sync_state()
185 (void *) pm->configcr, NULL, 0, powermate_sync_state()
186 powermate_config_complete, pm); powermate_sync_state()
188 if (usb_submit_urb(pm->config, GFP_ATOMIC)) powermate_sync_state()
195 struct powermate_device *pm = urb->context; powermate_config_complete() local
201 spin_lock_irqsave(&pm->lock, flags); powermate_config_complete()
202 powermate_sync_state(pm); powermate_config_complete()
203 spin_unlock_irqrestore(&pm->lock, flags); powermate_config_complete()
207 static void powermate_pulse_led(struct powermate_device *pm, int static_brightness, int pulse_speed, powermate_pulse_led() argument
225 spin_lock_irqsave(&pm->lock, flags); powermate_pulse_led()
228 if (static_brightness != pm->static_brightness) { powermate_pulse_led()
229 pm->static_brightness = static_brightness; powermate_pulse_led()
230 pm->requires_update |= UPDATE_STATIC_BRIGHTNESS; powermate_pulse_led()
232 if (pulse_asleep != pm->pulse_asleep) { powermate_pulse_led()
233 pm->pulse_asleep = pulse_asleep; powermate_pulse_led()
234 pm->requires_update |= (UPDATE_PULSE_ASLEEP | UPDATE_STATIC_BRIGHTNESS); powermate_pulse_led()
236 if (pulse_awake != pm->pulse_awake) { powermate_pulse_led()
237 pm->pulse_awake = pulse_awake; powermate_pulse_led()
238 pm->requires_update |= (UPDATE_PULSE_AWAKE | UPDATE_STATIC_BRIGHTNESS); powermate_pulse_led()
240 if (pulse_speed != pm->pulse_speed || pulse_table != pm->pulse_table) { powermate_pulse_led()
241 pm->pulse_speed = pulse_speed; powermate_pulse_led()
242 pm->pulse_table = pulse_table; powermate_pulse_led()
243 pm->requires_update |= UPDATE_PULSE_MODE; powermate_pulse_led()
246 powermate_sync_state(pm); powermate_pulse_led()
248 spin_unlock_irqrestore(&pm->lock, flags); powermate_pulse_led()
255 struct powermate_device *pm = input_get_drvdata(dev); powermate_input_event() local
271 powermate_pulse_led(pm, static_brightness, pulse_speed, pulse_table, pulse_asleep, pulse_awake); powermate_input_event()
277 static int powermate_alloc_buffers(struct usb_device *udev, struct powermate_device *pm) powermate_alloc_buffers() argument
279 pm->data = usb_alloc_coherent(udev, POWERMATE_PAYLOAD_SIZE_MAX, powermate_alloc_buffers()
280 GFP_ATOMIC, &pm->data_dma); powermate_alloc_buffers()
281 if (!pm->data) powermate_alloc_buffers()
284 pm->configcr = kmalloc(sizeof(*(pm->configcr)), GFP_KERNEL); powermate_alloc_buffers()
285 if (!pm->configcr) powermate_alloc_buffers()
291 static void powermate_free_buffers(struct usb_device *udev, struct powermate_device *pm) powermate_free_buffers() argument
294 pm->data, pm->data_dma); powermate_free_buffers()
295 kfree(pm->configcr); powermate_free_buffers()
304 struct powermate_device *pm; powermate_probe() local
322 pm = kzalloc(sizeof(struct powermate_device), GFP_KERNEL); powermate_probe()
324 if (!pm || !input_dev) powermate_probe()
327 if (powermate_alloc_buffers(udev, pm)) powermate_probe()
330 pm->irq = usb_alloc_urb(0, GFP_KERNEL); powermate_probe()
331 if (!pm->irq) powermate_probe()
334 pm->config = usb_alloc_urb(0, GFP_KERNEL); powermate_probe()
335 if (!pm->config) powermate_probe()
338 pm->udev = udev; powermate_probe()
339 pm->intf = intf; powermate_probe()
340 pm->input = input_dev; powermate_probe()
342 usb_make_path(udev, pm->phys, sizeof(pm->phys)); powermate_probe()
343 strlcat(pm->phys, "/input0", sizeof(pm->phys)); powermate_probe()
345 spin_lock_init(&pm->lock); powermate_probe()
360 input_dev->phys = pm->phys; powermate_probe()
364 input_set_drvdata(input_dev, pm); powermate_probe()
384 usb_fill_int_urb(pm->irq, udev, pipe, pm->data, powermate_probe()
386 pm, endpoint->bInterval); powermate_probe()
387 pm->irq->transfer_dma = pm->data_dma; powermate_probe()
388 pm->irq->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; powermate_probe()
391 if (usb_submit_urb(pm->irq, GFP_KERNEL)) { powermate_probe()
396 error = input_register_device(pm->input); powermate_probe()
402 pm->requires_update = UPDATE_PULSE_ASLEEP | UPDATE_PULSE_AWAKE | UPDATE_PULSE_MODE | UPDATE_STATIC_BRIGHTNESS; powermate_probe()
403 powermate_pulse_led(pm, 0x80, 255, 0, 1, 0); // set default pulse parameters powermate_probe()
405 usb_set_intfdata(intf, pm); powermate_probe()
408 fail5: usb_kill_urb(pm->irq); powermate_probe()
409 fail4: usb_free_urb(pm->config); powermate_probe()
410 fail3: usb_free_urb(pm->irq); powermate_probe()
411 fail2: powermate_free_buffers(udev, pm); powermate_probe()
413 kfree(pm); powermate_probe()
420 struct powermate_device *pm = usb_get_intfdata (intf); powermate_disconnect() local
423 if (pm) { powermate_disconnect()
424 pm->requires_update = 0; powermate_disconnect()
425 usb_kill_urb(pm->irq); powermate_disconnect()
426 input_unregister_device(pm->input); powermate_disconnect()
427 usb_free_urb(pm->irq); powermate_disconnect()
428 usb_free_urb(pm->config); powermate_disconnect()
429 powermate_free_buffers(interface_to_usbdev(intf), pm); powermate_disconnect() local
431 kfree(pm); powermate_disconnect()
H A Dad714x-i2c.c13 #include <linux/pm.h>
110 .pm = &ad714x_i2c_pm,
H A Dad714x-spi.c12 #include <linux/pm.h>
117 .pm = &ad714x_spi_pm,
H A Dadxl34x-spi.c13 #include <linux/pm.h>
124 .pm = &adxl34x_spi_pm,
H A Dadxl34x-i2c.c14 #include <linux/pm.h>
142 .pm = &adxl34x_i2c_pm,
/linux-4.1.27/arch/arm/mach-rockchip/
H A DMakefile4 obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
/linux-4.1.27/arch/arm/mach-zynq/
H A DMakefile6 obj-y := common.o slcr.o pm.o
/linux-4.1.27/arch/arm/mach-lpc32xx/
H A DMakefile6 obj-y += pm.o suspend.o
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dradeon_pm.c58 for (i = 0; i < rdev->pm.num_power_states; i++) { radeon_pm_get_type_index()
59 if (rdev->pm.power_state[i].type == ps_type) { radeon_pm_get_type_index()
66 return rdev->pm.default_power_state_index; radeon_pm_get_type_index()
71 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { radeon_pm_acpi_event_handler()
72 mutex_lock(&rdev->pm.mutex); radeon_pm_acpi_event_handler()
74 rdev->pm.dpm.ac_power = true; radeon_pm_acpi_event_handler()
76 rdev->pm.dpm.ac_power = false; radeon_pm_acpi_event_handler()
79 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); radeon_pm_acpi_event_handler()
81 mutex_unlock(&rdev->pm.mutex); radeon_pm_acpi_event_handler()
82 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { radeon_pm_acpi_event_handler()
83 if (rdev->pm.profile == PM_PROFILE_AUTO) { radeon_pm_acpi_event_handler()
84 mutex_lock(&rdev->pm.mutex); radeon_pm_acpi_event_handler()
87 mutex_unlock(&rdev->pm.mutex); radeon_pm_acpi_event_handler()
94 switch (rdev->pm.profile) { radeon_pm_update_profile()
96 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; radeon_pm_update_profile()
100 if (rdev->pm.active_crtc_count > 1) radeon_pm_update_profile()
101 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; radeon_pm_update_profile()
103 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; radeon_pm_update_profile()
105 if (rdev->pm.active_crtc_count > 1) radeon_pm_update_profile()
106 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; radeon_pm_update_profile()
108 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; radeon_pm_update_profile()
112 if (rdev->pm.active_crtc_count > 1) radeon_pm_update_profile()
113 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; radeon_pm_update_profile()
115 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; radeon_pm_update_profile()
118 if (rdev->pm.active_crtc_count > 1) radeon_pm_update_profile()
119 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; radeon_pm_update_profile()
121 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; radeon_pm_update_profile()
124 if (rdev->pm.active_crtc_count > 1) radeon_pm_update_profile()
125 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; radeon_pm_update_profile()
127 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; radeon_pm_update_profile()
131 if (rdev->pm.active_crtc_count == 0) { radeon_pm_update_profile()
132 rdev->pm.requested_power_state_index = radeon_pm_update_profile()
133 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; radeon_pm_update_profile()
134 rdev->pm.requested_clock_mode_index = radeon_pm_update_profile()
135 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; radeon_pm_update_profile()
137 rdev->pm.requested_power_state_index = radeon_pm_update_profile()
138 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; radeon_pm_update_profile()
139 rdev->pm.requested_clock_mode_index = radeon_pm_update_profile()
140 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; radeon_pm_update_profile()
159 if (rdev->pm.active_crtcs) { radeon_sync_with_vblank()
160 rdev->pm.vblank_sync = false; radeon_sync_with_vblank()
162 rdev->irq.vblank_queue, rdev->pm.vblank_sync, radeon_sync_with_vblank()
172 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && radeon_set_power_state()
173 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) radeon_set_power_state()
177 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. radeon_set_power_state()
178 clock_info[rdev->pm.requested_clock_mode_index].sclk; radeon_set_power_state()
179 if (sclk > rdev->pm.default_sclk) radeon_set_power_state()
180 sclk = rdev->pm.default_sclk; radeon_set_power_state()
186 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && radeon_set_power_state()
188 rdev->pm.active_crtc_count && radeon_set_power_state()
189 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || radeon_set_power_state()
190 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) radeon_set_power_state()
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. radeon_set_power_state()
192 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; radeon_set_power_state()
194 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. radeon_set_power_state()
195 clock_info[rdev->pm.requested_clock_mode_index].mclk; radeon_set_power_state()
197 if (mclk > rdev->pm.default_mclk) radeon_set_power_state()
198 mclk = rdev->pm.default_mclk; radeon_set_power_state()
201 if (sclk < rdev->pm.current_sclk) radeon_set_power_state()
206 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { radeon_set_power_state()
218 if (sclk != rdev->pm.current_sclk) { radeon_set_power_state()
222 rdev->pm.current_sclk = sclk; radeon_set_power_state()
227 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { radeon_set_power_state()
231 rdev->pm.current_mclk = mclk; radeon_set_power_state()
241 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; radeon_set_power_state()
242 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; radeon_set_power_state()
244 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); radeon_set_power_state()
252 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && radeon_pm_set_clocks()
253 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) radeon_pm_set_clocks()
257 down_write(&rdev->pm.mclk_lock); radeon_pm_set_clocks()
270 up_write(&rdev->pm.mclk_lock); radeon_pm_set_clocks()
280 if (rdev->pm.active_crtcs & (1 << i)) { radeon_pm_set_clocks()
281 rdev->pm.req_vblank |= (1 << i); radeon_pm_set_clocks()
291 if (rdev->pm.req_vblank & (1 << i)) { radeon_pm_set_clocks()
292 rdev->pm.req_vblank &= ~(1 << i); radeon_pm_set_clocks()
300 if (rdev->pm.active_crtc_count) radeon_pm_set_clocks()
303 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; radeon_pm_set_clocks()
306 up_write(&rdev->pm.mclk_lock); radeon_pm_set_clocks()
316 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); radeon_pm_print_states()
317 for (i = 0; i < rdev->pm.num_power_states; i++) { radeon_pm_print_states()
318 power_state = &rdev->pm.power_state[i]; radeon_pm_print_states()
321 if (i == rdev->pm.default_power_state_index) radeon_pm_print_states()
350 int cp = rdev->pm.profile; radeon_get_pm_profile()
372 mutex_lock(&rdev->pm.mutex); radeon_set_pm_profile()
373 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { radeon_set_pm_profile()
375 rdev->pm.profile = PM_PROFILE_DEFAULT; radeon_set_pm_profile()
377 rdev->pm.profile = PM_PROFILE_AUTO; radeon_set_pm_profile()
379 rdev->pm.profile = PM_PROFILE_LOW; radeon_set_pm_profile()
381 rdev->pm.profile = PM_PROFILE_MID; radeon_set_pm_profile()
383 rdev->pm.profile = PM_PROFILE_HIGH; radeon_set_pm_profile()
394 mutex_unlock(&rdev->pm.mutex); radeon_set_pm_profile()
405 int pm = rdev->pm.pm_method; radeon_get_pm_method() local
408 (pm == PM_METHOD_DYNPM) ? "dynpm" : radeon_get_pm_method()
409 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); radeon_get_pm_method()
428 if (rdev->pm.pm_method == PM_METHOD_DPM) { radeon_set_pm_method()
434 mutex_lock(&rdev->pm.mutex); radeon_set_pm_method()
435 rdev->pm.pm_method = PM_METHOD_DYNPM; radeon_set_pm_method()
436 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; radeon_set_pm_method()
437 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; radeon_set_pm_method()
438 mutex_unlock(&rdev->pm.mutex); radeon_set_pm_method()
440 mutex_lock(&rdev->pm.mutex); radeon_set_pm_method()
442 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; radeon_set_pm_method()
443 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; radeon_set_pm_method()
444 rdev->pm.pm_method = PM_METHOD_PROFILE; radeon_set_pm_method()
445 mutex_unlock(&rdev->pm.mutex); radeon_set_pm_method()
446 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); radeon_set_pm_method()
462 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; radeon_get_dpm_state() local
465 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : radeon_get_dpm_state()
466 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); radeon_get_dpm_state()
477 mutex_lock(&rdev->pm.mutex); radeon_set_dpm_state()
479 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; radeon_set_dpm_state()
481 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; radeon_set_dpm_state()
483 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; radeon_set_dpm_state()
485 mutex_unlock(&rdev->pm.mutex); radeon_set_dpm_state()
489 mutex_unlock(&rdev->pm.mutex); radeon_set_dpm_state()
506 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; radeon_get_dpm_forced_performance_level()
532 mutex_lock(&rdev->pm.mutex); radeon_set_dpm_forced_performance_level()
544 if (rdev->pm.dpm.thermal_active) { radeon_set_dpm_forced_performance_level()
553 mutex_unlock(&rdev->pm.mutex); radeon_set_dpm_forced_performance_level()
672 if (rdev->asic->pm.get_temperature) radeon_hwmon_show_temp()
689 temp = rdev->pm.dpm.thermal.min_temp; radeon_hwmon_show_temp_thresh()
691 temp = rdev->pm.dpm.thermal.max_temp; radeon_hwmon_show_temp_thresh()
724 if (rdev->pm.pm_method != PM_METHOD_DPM && hwmon_attributes_visible()
734 if (rdev->pm.no_fan && hwmon_attributes_visible()
778 switch (rdev->pm.int_thermal_type) { radeon_hwmon_init()
787 if (rdev->asic->pm.get_temperature == NULL) radeon_hwmon_init()
789 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev, radeon_hwmon_init()
792 if (IS_ERR(rdev->pm.int_hwmon_dev)) { radeon_hwmon_init()
793 err = PTR_ERR(rdev->pm.int_hwmon_dev); radeon_hwmon_init()
807 if (rdev->pm.int_hwmon_dev) radeon_hwmon_fini()
808 hwmon_device_unregister(rdev->pm.int_hwmon_dev); radeon_hwmon_fini()
815 pm.dpm.thermal.work); radeon_dpm_thermal_work_handler()
819 if (!rdev->pm.dpm_enabled) radeon_dpm_thermal_work_handler()
822 if (rdev->asic->pm.get_temperature) { radeon_dpm_thermal_work_handler()
825 if (temp < rdev->pm.dpm.thermal.min_temp) radeon_dpm_thermal_work_handler()
827 dpm_state = rdev->pm.dpm.user_state; radeon_dpm_thermal_work_handler()
829 if (rdev->pm.dpm.thermal.high_to_low) radeon_dpm_thermal_work_handler()
831 dpm_state = rdev->pm.dpm.user_state; radeon_dpm_thermal_work_handler()
833 mutex_lock(&rdev->pm.mutex); radeon_dpm_thermal_work_handler()
835 rdev->pm.dpm.thermal_active = true; radeon_dpm_thermal_work_handler()
837 rdev->pm.dpm.thermal_active = false; radeon_dpm_thermal_work_handler()
838 rdev->pm.dpm.state = dpm_state; radeon_dpm_thermal_work_handler()
839 mutex_unlock(&rdev->pm.mutex); radeon_dpm_thermal_work_handler()
846 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? radeon_dpm_single_display()
883 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { radeon_dpm_pick_power_state()
884 ps = &rdev->pm.dpm.ps[i]; radeon_dpm_pick_power_state()
917 if (rdev->pm.dpm.uvd_ps) radeon_dpm_pick_power_state()
918 return rdev->pm.dpm.uvd_ps; radeon_dpm_pick_power_state()
938 return rdev->pm.dpm.boot_ps; radeon_dpm_pick_power_state()
967 if (rdev->pm.dpm.uvd_ps) { radeon_dpm_pick_power_state()
968 return rdev->pm.dpm.uvd_ps; radeon_dpm_pick_power_state()
1000 if (!rdev->pm.dpm_enabled) radeon_dpm_change_power_state_locked()
1003 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { radeon_dpm_change_power_state_locked()
1005 if ((!rdev->pm.dpm.thermal_active) && radeon_dpm_change_power_state_locked()
1006 (!rdev->pm.dpm.uvd_active)) radeon_dpm_change_power_state_locked()
1007 rdev->pm.dpm.state = rdev->pm.dpm.user_state; radeon_dpm_change_power_state_locked()
1009 dpm_state = rdev->pm.dpm.state; radeon_dpm_change_power_state_locked()
1013 rdev->pm.dpm.requested_ps = ps; radeon_dpm_change_power_state_locked()
1018 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { radeon_dpm_change_power_state_locked()
1020 if (ps->vce_active != rdev->pm.dpm.vce_active) radeon_dpm_change_power_state_locked()
1023 if (rdev->pm.dpm.single_display != single_display) radeon_dpm_change_power_state_locked()
1029 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { radeon_dpm_change_power_state_locked()
1034 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; radeon_dpm_change_power_state_locked()
1035 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; radeon_dpm_change_power_state_locked()
1043 if (rdev->pm.dpm.new_active_crtcs == radeon_dpm_change_power_state_locked()
1044 rdev->pm.dpm.current_active_crtcs) { radeon_dpm_change_power_state_locked()
1047 if ((rdev->pm.dpm.current_active_crtc_count > 1) && radeon_dpm_change_power_state_locked()
1048 (rdev->pm.dpm.new_active_crtc_count > 1)) { radeon_dpm_change_power_state_locked()
1053 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; radeon_dpm_change_power_state_locked()
1054 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; radeon_dpm_change_power_state_locked()
1064 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); radeon_dpm_change_power_state_locked()
1066 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); radeon_dpm_change_power_state_locked()
1070 down_write(&rdev->pm.mclk_lock); radeon_dpm_change_power_state_locked()
1074 ps->vce_active = rdev->pm.dpm.vce_active; radeon_dpm_change_power_state_locked()
1096 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; radeon_dpm_change_power_state_locked()
1100 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; radeon_dpm_change_power_state_locked()
1101 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; radeon_dpm_change_power_state_locked()
1102 rdev->pm.dpm.single_display = single_display; radeon_dpm_change_power_state_locked()
1105 if (rdev->pm.dpm.thermal_active) { radeon_dpm_change_power_state_locked()
1106 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; radeon_dpm_change_power_state_locked()
1110 rdev->pm.dpm.forced_level = level; radeon_dpm_change_power_state_locked()
1113 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); radeon_dpm_change_power_state_locked()
1119 up_write(&rdev->pm.mclk_lock); radeon_dpm_change_power_state_locked()
1128 mutex_lock(&rdev->pm.mutex); radeon_dpm_enable_uvd()
1131 enable |= rdev->pm.dpm.sd > 0; radeon_dpm_enable_uvd()
1132 enable |= rdev->pm.dpm.hd > 0; radeon_dpm_enable_uvd()
1135 mutex_unlock(&rdev->pm.mutex); radeon_dpm_enable_uvd()
1138 mutex_lock(&rdev->pm.mutex); radeon_dpm_enable_uvd()
1139 rdev->pm.dpm.uvd_active = true; radeon_dpm_enable_uvd()
1142 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) radeon_dpm_enable_uvd()
1144 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) radeon_dpm_enable_uvd()
1146 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) radeon_dpm_enable_uvd()
1148 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) radeon_dpm_enable_uvd()
1153 rdev->pm.dpm.state = dpm_state; radeon_dpm_enable_uvd()
1154 mutex_unlock(&rdev->pm.mutex); radeon_dpm_enable_uvd()
1156 mutex_lock(&rdev->pm.mutex); radeon_dpm_enable_uvd()
1157 rdev->pm.dpm.uvd_active = false; radeon_dpm_enable_uvd()
1158 mutex_unlock(&rdev->pm.mutex); radeon_dpm_enable_uvd()
1168 mutex_lock(&rdev->pm.mutex); radeon_dpm_enable_vce()
1169 rdev->pm.dpm.vce_active = true; radeon_dpm_enable_vce()
1171 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; radeon_dpm_enable_vce()
1172 mutex_unlock(&rdev->pm.mutex); radeon_dpm_enable_vce()
1174 mutex_lock(&rdev->pm.mutex); radeon_dpm_enable_vce()
1175 rdev->pm.dpm.vce_active = false; radeon_dpm_enable_vce()
1176 mutex_unlock(&rdev->pm.mutex); radeon_dpm_enable_vce()
1184 mutex_lock(&rdev->pm.mutex); radeon_pm_suspend_old()
1185 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { radeon_pm_suspend_old()
1186 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) radeon_pm_suspend_old()
1187 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; radeon_pm_suspend_old()
1189 mutex_unlock(&rdev->pm.mutex); radeon_pm_suspend_old()
1191 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); radeon_pm_suspend_old()
1196 mutex_lock(&rdev->pm.mutex); radeon_pm_suspend_dpm()
1200 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; radeon_pm_suspend_dpm()
1201 rdev->pm.dpm_enabled = false; radeon_pm_suspend_dpm()
1202 mutex_unlock(&rdev->pm.mutex); radeon_pm_suspend_dpm()
1207 if (rdev->pm.pm_method == PM_METHOD_DPM) radeon_pm_suspend()
1219 if (rdev->pm.default_vddc) radeon_pm_resume_old()
1220 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, radeon_pm_resume_old()
1222 if (rdev->pm.default_vddci) radeon_pm_resume_old()
1223 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, radeon_pm_resume_old()
1225 if (rdev->pm.default_sclk) radeon_pm_resume_old()
1226 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); radeon_pm_resume_old()
1227 if (rdev->pm.default_mclk) radeon_pm_resume_old()
1228 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); radeon_pm_resume_old()
1231 mutex_lock(&rdev->pm.mutex); radeon_pm_resume_old()
1232 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; radeon_pm_resume_old()
1233 rdev->pm.current_clock_mode_index = 0; radeon_pm_resume_old()
1234 rdev->pm.current_sclk = rdev->pm.default_sclk; radeon_pm_resume_old()
1235 rdev->pm.current_mclk = rdev->pm.default_mclk; radeon_pm_resume_old()
1236 if (rdev->pm.power_state) { radeon_pm_resume_old()
1237 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; radeon_pm_resume_old()
1238 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; radeon_pm_resume_old()
1240 if (rdev->pm.pm_method == PM_METHOD_DYNPM radeon_pm_resume_old()
1241 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { radeon_pm_resume_old()
1242 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; radeon_pm_resume_old()
1243 schedule_delayed_work(&rdev->pm.dynpm_idle_work, radeon_pm_resume_old()
1246 mutex_unlock(&rdev->pm.mutex); radeon_pm_resume_old()
1255 mutex_lock(&rdev->pm.mutex); radeon_pm_resume_dpm()
1256 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; radeon_pm_resume_dpm()
1259 mutex_unlock(&rdev->pm.mutex); radeon_pm_resume_dpm()
1262 rdev->pm.dpm_enabled = true; radeon_pm_resume_dpm()
1270 if (rdev->pm.default_vddc) radeon_pm_resume_dpm()
1271 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, radeon_pm_resume_dpm()
1273 if (rdev->pm.default_vddci) radeon_pm_resume_dpm()
1274 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, radeon_pm_resume_dpm()
1276 if (rdev->pm.default_sclk) radeon_pm_resume_dpm()
1277 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); radeon_pm_resume_dpm()
1278 if (rdev->pm.default_mclk) radeon_pm_resume_dpm()
1279 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); radeon_pm_resume_dpm()
1285 if (rdev->pm.pm_method == PM_METHOD_DPM) radeon_pm_resume()
1295 rdev->pm.profile = PM_PROFILE_DEFAULT; radeon_pm_init_old()
1296 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; radeon_pm_init_old()
1297 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; radeon_pm_init_old()
1298 rdev->pm.dynpm_can_upclock = true; radeon_pm_init_old()
1299 rdev->pm.dynpm_can_downclock = true; radeon_pm_init_old()
1300 rdev->pm.default_sclk = rdev->clock.default_sclk; radeon_pm_init_old()
1301 rdev->pm.default_mclk = rdev->clock.default_mclk; radeon_pm_init_old()
1302 rdev->pm.current_sclk = rdev->clock.default_sclk; radeon_pm_init_old()
1303 rdev->pm.current_mclk = rdev->clock.default_mclk; radeon_pm_init_old()
1304 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; radeon_pm_init_old()
1317 if (rdev->pm.default_vddc) radeon_pm_init_old()
1318 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, radeon_pm_init_old()
1320 if (rdev->pm.default_vddci) radeon_pm_init_old()
1321 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, radeon_pm_init_old()
1323 if (rdev->pm.default_sclk) radeon_pm_init_old()
1324 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); radeon_pm_init_old()
1325 if (rdev->pm.default_mclk) radeon_pm_init_old()
1326 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); radeon_pm_init_old()
1335 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); radeon_pm_init_old()
1337 if (rdev->pm.num_power_states > 1) { radeon_pm_init_old()
1352 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { radeon_dpm_print_power_states()
1354 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); radeon_dpm_print_power_states()
1363 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; radeon_pm_init_dpm()
1364 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; radeon_pm_init_dpm()
1365 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; radeon_pm_init_dpm()
1366 rdev->pm.default_sclk = rdev->clock.default_sclk; radeon_pm_init_dpm()
1367 rdev->pm.default_mclk = rdev->clock.default_mclk; radeon_pm_init_dpm()
1368 rdev->pm.current_sclk = rdev->clock.default_sclk; radeon_pm_init_dpm()
1369 rdev->pm.current_mclk = rdev->clock.default_mclk; radeon_pm_init_dpm()
1370 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; radeon_pm_init_dpm()
1382 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); radeon_pm_init_dpm()
1383 mutex_lock(&rdev->pm.mutex); radeon_pm_init_dpm()
1385 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; radeon_pm_init_dpm()
1390 mutex_unlock(&rdev->pm.mutex); radeon_pm_init_dpm()
1393 rdev->pm.dpm_enabled = true; radeon_pm_init_dpm()
1404 rdev->pm.dpm_enabled = false; radeon_pm_init_dpm()
1408 if (rdev->pm.default_vddc) radeon_pm_init_dpm()
1409 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, radeon_pm_init_dpm()
1411 if (rdev->pm.default_vddci) radeon_pm_init_dpm()
1412 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, radeon_pm_init_dpm()
1414 if (rdev->pm.default_sclk) radeon_pm_init_dpm()
1415 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); radeon_pm_init_dpm()
1416 if (rdev->pm.default_mclk) radeon_pm_init_dpm()
1417 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); radeon_pm_init_dpm()
1468 rdev->pm.pm_method = PM_METHOD_PROFILE; radeon_pm_init()
1472 rdev->pm.pm_method = PM_METHOD_PROFILE; radeon_pm_init()
1474 rdev->pm.pm_method = PM_METHOD_DPM; radeon_pm_init()
1476 rdev->pm.pm_method = PM_METHOD_PROFILE; radeon_pm_init()
1506 rdev->pm.pm_method = PM_METHOD_PROFILE; radeon_pm_init()
1510 rdev->pm.pm_method = PM_METHOD_PROFILE; radeon_pm_init()
1512 rdev->pm.pm_method = PM_METHOD_PROFILE; radeon_pm_init()
1514 rdev->pm.pm_method = PM_METHOD_PROFILE; radeon_pm_init()
1516 rdev->pm.pm_method = PM_METHOD_DPM; radeon_pm_init()
1520 rdev->pm.pm_method = PM_METHOD_PROFILE; radeon_pm_init()
1524 if (rdev->pm.pm_method == PM_METHOD_DPM) radeon_pm_init()
1534 if (rdev->pm.pm_method == PM_METHOD_DPM) { radeon_pm_late_init()
1535 if (rdev->pm.dpm_enabled) { radeon_pm_late_init()
1536 if (!rdev->pm.sysfs_initialized) { radeon_pm_late_init()
1551 rdev->pm.sysfs_initialized = true; radeon_pm_late_init()
1554 mutex_lock(&rdev->pm.mutex); radeon_pm_late_init()
1556 mutex_unlock(&rdev->pm.mutex); radeon_pm_late_init()
1558 rdev->pm.dpm_enabled = false; radeon_pm_late_init()
1568 if ((rdev->pm.num_power_states > 1) && radeon_pm_late_init()
1569 (!rdev->pm.sysfs_initialized)) { radeon_pm_late_init()
1578 rdev->pm.sysfs_initialized = true; radeon_pm_late_init()
1586 if (rdev->pm.num_power_states > 1) { radeon_pm_fini_old()
1587 mutex_lock(&rdev->pm.mutex); radeon_pm_fini_old()
1588 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { radeon_pm_fini_old()
1589 rdev->pm.profile = PM_PROFILE_DEFAULT; radeon_pm_fini_old()
1592 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { radeon_pm_fini_old()
1594 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; radeon_pm_fini_old()
1595 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; radeon_pm_fini_old()
1598 mutex_unlock(&rdev->pm.mutex); radeon_pm_fini_old()
1600 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); radeon_pm_fini_old()
1607 kfree(rdev->pm.power_state); radeon_pm_fini_old()
1612 if (rdev->pm.num_power_states > 1) { radeon_pm_fini_dpm()
1613 mutex_lock(&rdev->pm.mutex); radeon_pm_fini_dpm()
1615 mutex_unlock(&rdev->pm.mutex); radeon_pm_fini_dpm()
1626 kfree(rdev->pm.power_state); radeon_pm_fini_dpm()
1631 if (rdev->pm.pm_method == PM_METHOD_DPM) radeon_pm_fini()
1643 if (rdev->pm.num_power_states < 2) radeon_pm_compute_clocks_old()
1646 mutex_lock(&rdev->pm.mutex); radeon_pm_compute_clocks_old()
1648 rdev->pm.active_crtcs = 0; radeon_pm_compute_clocks_old()
1649 rdev->pm.active_crtc_count = 0; radeon_pm_compute_clocks_old()
1655 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); radeon_pm_compute_clocks_old()
1656 rdev->pm.active_crtc_count++; radeon_pm_compute_clocks_old()
1661 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { radeon_pm_compute_clocks_old()
1664 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { radeon_pm_compute_clocks_old()
1665 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { radeon_pm_compute_clocks_old()
1666 if (rdev->pm.active_crtc_count > 1) { radeon_pm_compute_clocks_old()
1667 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { radeon_pm_compute_clocks_old()
1668 cancel_delayed_work(&rdev->pm.dynpm_idle_work); radeon_pm_compute_clocks_old()
1670 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; radeon_pm_compute_clocks_old()
1671 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; radeon_pm_compute_clocks_old()
1677 } else if (rdev->pm.active_crtc_count == 1) { radeon_pm_compute_clocks_old()
1680 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { radeon_pm_compute_clocks_old()
1681 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; radeon_pm_compute_clocks_old()
1682 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; radeon_pm_compute_clocks_old()
1686 schedule_delayed_work(&rdev->pm.dynpm_idle_work, radeon_pm_compute_clocks_old()
1688 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { radeon_pm_compute_clocks_old()
1689 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; radeon_pm_compute_clocks_old()
1690 schedule_delayed_work(&rdev->pm.dynpm_idle_work, radeon_pm_compute_clocks_old()
1695 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { radeon_pm_compute_clocks_old()
1696 cancel_delayed_work(&rdev->pm.dynpm_idle_work); radeon_pm_compute_clocks_old()
1698 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; radeon_pm_compute_clocks_old()
1699 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; radeon_pm_compute_clocks_old()
1707 mutex_unlock(&rdev->pm.mutex); radeon_pm_compute_clocks_old()
1716 if (!rdev->pm.dpm_enabled) radeon_pm_compute_clocks_dpm()
1719 mutex_lock(&rdev->pm.mutex); radeon_pm_compute_clocks_dpm()
1722 rdev->pm.dpm.new_active_crtcs = 0; radeon_pm_compute_clocks_dpm()
1723 rdev->pm.dpm.new_active_crtc_count = 0; radeon_pm_compute_clocks_dpm()
1729 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); radeon_pm_compute_clocks_dpm()
1730 rdev->pm.dpm.new_active_crtc_count++; radeon_pm_compute_clocks_dpm()
1737 rdev->pm.dpm.ac_power = true; radeon_pm_compute_clocks_dpm()
1739 rdev->pm.dpm.ac_power = false; radeon_pm_compute_clocks_dpm()
1743 mutex_unlock(&rdev->pm.mutex); radeon_pm_compute_clocks_dpm()
1749 if (rdev->pm.pm_method == PM_METHOD_DPM) radeon_pm_compute_clocks()
1764 if (rdev->pm.active_crtcs & (1 << crtc)) { radeon_pm_in_vbl()
1781 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, radeon_pm_debug_check_in_vbl()
1791 pm.dynpm_idle_work.work); radeon_dynpm_idle_work_handler()
1794 mutex_lock(&rdev->pm.mutex); radeon_dynpm_idle_work_handler()
1795 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { radeon_dynpm_idle_work_handler()
1810 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { radeon_dynpm_idle_work_handler()
1811 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; radeon_dynpm_idle_work_handler()
1812 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && radeon_dynpm_idle_work_handler()
1813 rdev->pm.dynpm_can_upclock) { radeon_dynpm_idle_work_handler()
1814 rdev->pm.dynpm_planned_action = radeon_dynpm_idle_work_handler()
1816 rdev->pm.dynpm_action_timeout = jiffies + radeon_dynpm_idle_work_handler()
1820 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { radeon_dynpm_idle_work_handler()
1821 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; radeon_dynpm_idle_work_handler()
1822 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && radeon_dynpm_idle_work_handler()
1823 rdev->pm.dynpm_can_downclock) { radeon_dynpm_idle_work_handler()
1824 rdev->pm.dynpm_planned_action = radeon_dynpm_idle_work_handler()
1826 rdev->pm.dynpm_action_timeout = jiffies + radeon_dynpm_idle_work_handler()
1834 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && radeon_dynpm_idle_work_handler()
1835 jiffies > rdev->pm.dynpm_action_timeout) { radeon_dynpm_idle_work_handler()
1840 schedule_delayed_work(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler()
1843 mutex_unlock(&rdev->pm.mutex); radeon_dynpm_idle_work_handler()
1862 } else if (rdev->pm.dpm_enabled) { radeon_debugfs_pm_info()
1863 mutex_lock(&rdev->pm.mutex); radeon_debugfs_pm_info()
1868 mutex_unlock(&rdev->pm.mutex); radeon_debugfs_pm_info()
1870 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); radeon_debugfs_pm_info()
1873 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); radeon_debugfs_pm_info()
1876 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); radeon_debugfs_pm_info()
1877 if (rdev->asic->pm.get_memory_clock) radeon_debugfs_pm_info()
1879 if (rdev->pm.current_vddc) radeon_debugfs_pm_info()
1880 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); radeon_debugfs_pm_info()
1881 if (rdev->asic->pm.get_pcie_lanes) radeon_debugfs_pm_info()
H A Dr600_dpm.c145 if (rps == rdev->pm.dpm.current_ps) r600_dpm_print_ps_status()
147 if (rps == rdev->pm.dpm.requested_ps) r600_dpm_print_ps_status()
149 if (rps == rdev->pm.dpm.boot_ps) r600_dpm_print_ps_status()
755 rdev->pm.dpm.thermal.min_temp = low_temp; r600_set_thermal_temperature_range()
756 rdev->pm.dpm.thermal.max_temp = high_temp; r600_set_thermal_temperature_range()
789 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { r600_dpm_late_enable()
855 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); r600_get_platform_caps()
856 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); r600_get_platform_caps()
857 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); r600_get_platform_caps()
892 rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; r600_parse_extended_power_table()
893 rdev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); r600_parse_extended_power_table()
894 rdev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed); r600_parse_extended_power_table()
895 rdev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh); r600_parse_extended_power_table()
896 rdev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin); r600_parse_extended_power_table()
897 rdev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed); r600_parse_extended_power_table()
898 rdev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh); r600_parse_extended_power_table()
900 rdev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax); r600_parse_extended_power_table()
902 rdev->pm.dpm.fan.t_max = 10900; r600_parse_extended_power_table()
903 rdev->pm.dpm.fan.cycle_delay = 100000; r600_parse_extended_power_table()
905 rdev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode; r600_parse_extended_power_table()
906 rdev->pm.dpm.fan.default_max_fan_pwm = r600_parse_extended_power_table()
908 rdev->pm.dpm.fan.default_fan_output_sensitivity = 4836; r600_parse_extended_power_table()
909 rdev->pm.dpm.fan.fan_output_sensitivity = r600_parse_extended_power_table()
912 rdev->pm.dpm.fan.ucode_fan_control = true; r600_parse_extended_power_table()
923 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, r600_parse_extended_power_table()
932 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, r600_parse_extended_power_table()
935 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); r600_parse_extended_power_table()
943 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, r600_parse_extended_power_table()
946 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); r600_parse_extended_power_table()
947 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); r600_parse_extended_power_table()
955 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, r600_parse_extended_power_table()
958 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); r600_parse_extended_power_table()
959 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); r600_parse_extended_power_table()
960 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries); r600_parse_extended_power_table()
970 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = r600_parse_extended_power_table()
973 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = r600_parse_extended_power_table()
976 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = r600_parse_extended_power_table()
978 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = r600_parse_extended_power_table()
989 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries = r600_parse_extended_power_table()
993 if (!rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { r600_parse_extended_power_table()
1000 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = r600_parse_extended_power_table()
1002 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk = r600_parse_extended_power_table()
1004 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage = r600_parse_extended_power_table()
1009 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.count = r600_parse_extended_power_table()
1017 rdev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit); r600_parse_extended_power_table()
1018 rdev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit); r600_parse_extended_power_table()
1019 rdev->pm.dpm.near_tdp_limit_adjusted = rdev->pm.dpm.near_tdp_limit; r600_parse_extended_power_table()
1020 rdev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit); r600_parse_extended_power_table()
1021 if (rdev->pm.dpm.tdp_od_limit) r600_parse_extended_power_table()
1022 rdev->pm.dpm.power_control = true; r600_parse_extended_power_table()
1024 rdev->pm.dpm.power_control = false; r600_parse_extended_power_table()
1025 rdev->pm.dpm.tdp_adjustment = 0; r600_parse_extended_power_table()
1026 rdev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold); r600_parse_extended_power_table()
1027 rdev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage); r600_parse_extended_power_table()
1028 rdev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope); r600_parse_extended_power_table()
1036 rdev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL); r600_parse_extended_power_table()
1037 if (!rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { r600_parse_extended_power_table()
1043 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { r600_parse_extended_power_table()
1044 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 = r600_parse_extended_power_table()
1046 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 = r600_parse_extended_power_table()
1048 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 = r600_parse_extended_power_table()
1051 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc = r600_parse_extended_power_table()
1053 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage = r600_parse_extended_power_table()
1059 rdev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries; r600_parse_extended_power_table()
1090 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries = r600_parse_extended_power_table()
1092 if (!rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) { r600_parse_extended_power_table()
1096 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count = r600_parse_extended_power_table()
1104 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = r600_parse_extended_power_table()
1106 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = r600_parse_extended_power_table()
1108 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v = r600_parse_extended_power_table()
1119 rdev->pm.dpm.vce_states[i].evclk = r600_parse_extended_power_table()
1121 rdev->pm.dpm.vce_states[i].ecclk = r600_parse_extended_power_table()
1123 rdev->pm.dpm.vce_states[i].clk_idx = r600_parse_extended_power_table()
1125 rdev->pm.dpm.vce_states[i].pstate = r600_parse_extended_power_table()
1144 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = r600_parse_extended_power_table()
1146 if (!rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) { r600_parse_extended_power_table()
1150 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = r600_parse_extended_power_table()
1157 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = r600_parse_extended_power_table()
1159 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk = r600_parse_extended_power_table()
1161 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v = r600_parse_extended_power_table()
1176 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries = r600_parse_extended_power_table()
1178 if (!rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) { r600_parse_extended_power_table()
1182 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count = r600_parse_extended_power_table()
1186 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk = r600_parse_extended_power_table()
1188 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v = r600_parse_extended_power_table()
1199 rdev->pm.dpm.dyn_state.ppm_table = r600_parse_extended_power_table()
1201 if (!rdev->pm.dpm.dyn_state.ppm_table) { r600_parse_extended_power_table()
1205 rdev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; r600_parse_extended_power_table()
1206 rdev->pm.dpm.dyn_state.ppm_table->cpu_core_number = r600_parse_extended_power_table()
1208 rdev->pm.dpm.dyn_state.ppm_table->platform_tdp = r600_parse_extended_power_table()
1210 rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp = r600_parse_extended_power_table()
1212 rdev->pm.dpm.dyn_state.ppm_table->platform_tdc = r600_parse_extended_power_table()
1214 rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc = r600_parse_extended_power_table()
1216 rdev->pm.dpm.dyn_state.ppm_table->apu_tdp = r600_parse_extended_power_table()
1218 rdev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = r600_parse_extended_power_table()
1220 rdev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power = r600_parse_extended_power_table()
1222 rdev->pm.dpm.dyn_state.ppm_table->tj_max = r600_parse_extended_power_table()
1234 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries = r600_parse_extended_power_table()
1236 if (!rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) { r600_parse_extended_power_table()
1240 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count = r600_parse_extended_power_table()
1244 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk = r600_parse_extended_power_table()
1246 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v = r600_parse_extended_power_table()
1257 rdev->pm.dpm.dyn_state.cac_tdp_table = r600_parse_extended_power_table()
1259 if (!rdev->pm.dpm.dyn_state.cac_tdp_table) { r600_parse_extended_power_table()
1267 rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = r600_parse_extended_power_table()
1274 rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255; r600_parse_extended_power_table()
1277 rdev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP); r600_parse_extended_power_table()
1278 rdev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp = r600_parse_extended_power_table()
1280 rdev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC); r600_parse_extended_power_table()
1281 rdev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit = r600_parse_extended_power_table()
1283 rdev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit = r600_parse_extended_power_table()
1285 rdev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage = r600_parse_extended_power_table()
1287 rdev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage = r600_parse_extended_power_table()
1297 struct radeon_dpm_dynamic_state *dyn_state = &rdev->pm.dpm.dyn_state; r600_free_extended_power_table()
H A Dr600.c313 rdev->pm.dynpm_can_upclock = true; r600_pm_get_dynpm_state()
314 rdev->pm.dynpm_can_downclock = true; r600_pm_get_dynpm_state()
320 if (rdev->pm.num_power_states > 2) r600_pm_get_dynpm_state()
323 switch (rdev->pm.dynpm_planned_action) { r600_pm_get_dynpm_state()
325 rdev->pm.requested_power_state_index = min_power_state_index; r600_pm_get_dynpm_state()
326 rdev->pm.requested_clock_mode_index = 0; r600_pm_get_dynpm_state()
327 rdev->pm.dynpm_can_downclock = false; r600_pm_get_dynpm_state()
330 if (rdev->pm.current_power_state_index == min_power_state_index) { r600_pm_get_dynpm_state()
331 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; r600_pm_get_dynpm_state()
332 rdev->pm.dynpm_can_downclock = false; r600_pm_get_dynpm_state()
334 if (rdev->pm.active_crtc_count > 1) { r600_pm_get_dynpm_state()
335 for (i = 0; i < rdev->pm.num_power_states; i++) { r600_pm_get_dynpm_state()
336 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) r600_pm_get_dynpm_state()
338 else if (i >= rdev->pm.current_power_state_index) { r600_pm_get_dynpm_state()
339 rdev->pm.requested_power_state_index = r600_pm_get_dynpm_state()
340 rdev->pm.current_power_state_index; r600_pm_get_dynpm_state()
343 rdev->pm.requested_power_state_index = i; r600_pm_get_dynpm_state()
348 if (rdev->pm.current_power_state_index == 0) r600_pm_get_dynpm_state()
349 rdev->pm.requested_power_state_index = r600_pm_get_dynpm_state()
350 rdev->pm.num_power_states - 1; r600_pm_get_dynpm_state()
352 rdev->pm.requested_power_state_index = r600_pm_get_dynpm_state()
353 rdev->pm.current_power_state_index - 1; r600_pm_get_dynpm_state()
356 rdev->pm.requested_clock_mode_index = 0; r600_pm_get_dynpm_state()
358 if ((rdev->pm.active_crtc_count > 0) && r600_pm_get_dynpm_state()
359 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. r600_pm_get_dynpm_state()
360 clock_info[rdev->pm.requested_clock_mode_index].flags & r600_pm_get_dynpm_state()
362 rdev->pm.requested_power_state_index++; r600_pm_get_dynpm_state()
366 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { r600_pm_get_dynpm_state()
367 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; r600_pm_get_dynpm_state()
368 rdev->pm.dynpm_can_upclock = false; r600_pm_get_dynpm_state()
370 if (rdev->pm.active_crtc_count > 1) { r600_pm_get_dynpm_state()
371 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { r600_pm_get_dynpm_state()
372 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) r600_pm_get_dynpm_state()
374 else if (i <= rdev->pm.current_power_state_index) { r600_pm_get_dynpm_state()
375 rdev->pm.requested_power_state_index = r600_pm_get_dynpm_state()
376 rdev->pm.current_power_state_index; r600_pm_get_dynpm_state()
379 rdev->pm.requested_power_state_index = i; r600_pm_get_dynpm_state()
384 rdev->pm.requested_power_state_index = r600_pm_get_dynpm_state()
385 rdev->pm.current_power_state_index + 1; r600_pm_get_dynpm_state()
387 rdev->pm.requested_clock_mode_index = 0; r600_pm_get_dynpm_state()
390 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; r600_pm_get_dynpm_state()
391 rdev->pm.requested_clock_mode_index = 0; r600_pm_get_dynpm_state()
392 rdev->pm.dynpm_can_upclock = false; r600_pm_get_dynpm_state()
403 if (rdev->pm.active_crtc_count > 1) { r600_pm_get_dynpm_state()
404 rdev->pm.requested_power_state_index = -1; r600_pm_get_dynpm_state()
406 for (i = 1; i < rdev->pm.num_power_states; i++) { r600_pm_get_dynpm_state()
407 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) r600_pm_get_dynpm_state()
409 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || r600_pm_get_dynpm_state()
410 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { r600_pm_get_dynpm_state()
411 rdev->pm.requested_power_state_index = i; r600_pm_get_dynpm_state()
416 if (rdev->pm.requested_power_state_index == -1) r600_pm_get_dynpm_state()
417 rdev->pm.requested_power_state_index = 0; r600_pm_get_dynpm_state()
419 rdev->pm.requested_power_state_index = 1; r600_pm_get_dynpm_state()
421 switch (rdev->pm.dynpm_planned_action) { r600_pm_get_dynpm_state()
423 rdev->pm.requested_clock_mode_index = 0; r600_pm_get_dynpm_state()
424 rdev->pm.dynpm_can_downclock = false; r600_pm_get_dynpm_state()
427 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { r600_pm_get_dynpm_state()
428 if (rdev->pm.current_clock_mode_index == 0) { r600_pm_get_dynpm_state()
429 rdev->pm.requested_clock_mode_index = 0; r600_pm_get_dynpm_state()
430 rdev->pm.dynpm_can_downclock = false; r600_pm_get_dynpm_state()
432 rdev->pm.requested_clock_mode_index = r600_pm_get_dynpm_state()
433 rdev->pm.current_clock_mode_index - 1; r600_pm_get_dynpm_state()
435 rdev->pm.requested_clock_mode_index = 0; r600_pm_get_dynpm_state()
436 rdev->pm.dynpm_can_downclock = false; r600_pm_get_dynpm_state()
439 if ((rdev->pm.active_crtc_count > 0) && r600_pm_get_dynpm_state()
440 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. r600_pm_get_dynpm_state()
441 clock_info[rdev->pm.requested_clock_mode_index].flags & r600_pm_get_dynpm_state()
443 rdev->pm.requested_clock_mode_index++; r600_pm_get_dynpm_state()
447 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { r600_pm_get_dynpm_state()
448 if (rdev->pm.current_clock_mode_index == r600_pm_get_dynpm_state()
449 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { r600_pm_get_dynpm_state()
450 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; r600_pm_get_dynpm_state()
451 rdev->pm.dynpm_can_upclock = false; r600_pm_get_dynpm_state()
453 rdev->pm.requested_clock_mode_index = r600_pm_get_dynpm_state()
454 rdev->pm.current_clock_mode_index + 1; r600_pm_get_dynpm_state()
456 rdev->pm.requested_clock_mode_index = r600_pm_get_dynpm_state()
457 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; r600_pm_get_dynpm_state()
458 rdev->pm.dynpm_can_upclock = false; r600_pm_get_dynpm_state()
462 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; r600_pm_get_dynpm_state()
463 rdev->pm.requested_clock_mode_index = 0; r600_pm_get_dynpm_state()
464 rdev->pm.dynpm_can_upclock = false; r600_pm_get_dynpm_state()
474 rdev->pm.power_state[rdev->pm.requested_power_state_index]. r600_pm_get_dynpm_state()
475 clock_info[rdev->pm.requested_clock_mode_index].sclk, r600_pm_get_dynpm_state()
476 rdev->pm.power_state[rdev->pm.requested_power_state_index]. r600_pm_get_dynpm_state()
477 clock_info[rdev->pm.requested_clock_mode_index].mclk, r600_pm_get_dynpm_state()
478 rdev->pm.power_state[rdev->pm.requested_power_state_index]. r600_pm_get_dynpm_state()
484 if (rdev->pm.num_power_states == 2) { rs780_pm_init_profile()
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; rs780_pm_init_profile()
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; rs780_pm_init_profile()
488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
489 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
491 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; rs780_pm_init_profile()
492 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; rs780_pm_init_profile()
493 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
496 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; rs780_pm_init_profile()
497 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; rs780_pm_init_profile()
498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
501 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; rs780_pm_init_profile()
502 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; rs780_pm_init_profile()
503 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
504 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
506 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; rs780_pm_init_profile()
507 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; rs780_pm_init_profile()
508 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
509 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
511 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; rs780_pm_init_profile()
512 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; rs780_pm_init_profile()
513 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
514 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
516 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; rs780_pm_init_profile()
517 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; rs780_pm_init_profile()
518 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
519 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
520 } else if (rdev->pm.num_power_states == 3) { rs780_pm_init_profile()
522 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; rs780_pm_init_profile()
523 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; rs780_pm_init_profile()
524 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
525 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
527 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; rs780_pm_init_profile()
528 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; rs780_pm_init_profile()
529 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
530 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
532 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; rs780_pm_init_profile()
533 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; rs780_pm_init_profile()
534 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
535 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
537 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; rs780_pm_init_profile()
538 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; rs780_pm_init_profile()
539 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
540 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
542 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; rs780_pm_init_profile()
543 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; rs780_pm_init_profile()
544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
545 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
547 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; rs780_pm_init_profile()
548 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; rs780_pm_init_profile()
549 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
550 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
552 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; rs780_pm_init_profile()
553 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; rs780_pm_init_profile()
554 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
555 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
558 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; rs780_pm_init_profile()
559 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; rs780_pm_init_profile()
560 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
561 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
563 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; rs780_pm_init_profile()
564 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; rs780_pm_init_profile()
565 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
566 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
568 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; rs780_pm_init_profile()
569 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; rs780_pm_init_profile()
570 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
571 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
573 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; rs780_pm_init_profile()
574 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; rs780_pm_init_profile()
575 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
576 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
578 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; rs780_pm_init_profile()
579 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; rs780_pm_init_profile()
580 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
581 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
583 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; rs780_pm_init_profile()
584 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; rs780_pm_init_profile()
585 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
586 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
588 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; rs780_pm_init_profile()
589 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; rs780_pm_init_profile()
590 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; rs780_pm_init_profile()
591 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; rs780_pm_init_profile()
602 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
603 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
604 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
605 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; r600_pm_init_profile()
607 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
608 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
609 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
610 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; r600_pm_init_profile()
612 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
613 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
614 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
615 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; r600_pm_init_profile()
617 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
618 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
619 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
620 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; r600_pm_init_profile()
622 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
623 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
624 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
625 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; r600_pm_init_profile()
627 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
628 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
629 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
630 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; r600_pm_init_profile()
632 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
633 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
634 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
635 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; r600_pm_init_profile()
637 if (rdev->pm.num_power_states < 4) { r600_pm_init_profile()
639 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
640 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
641 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
642 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; r600_pm_init_profile()
644 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; r600_pm_init_profile()
645 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; r600_pm_init_profile()
646 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
647 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; r600_pm_init_profile()
649 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; r600_pm_init_profile()
650 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; r600_pm_init_profile()
651 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
652 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; r600_pm_init_profile()
654 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; r600_pm_init_profile()
655 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; r600_pm_init_profile()
656 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
657 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; r600_pm_init_profile()
659 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; r600_pm_init_profile()
660 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; r600_pm_init_profile()
661 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
662 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; r600_pm_init_profile()
664 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; r600_pm_init_profile()
665 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; r600_pm_init_profile()
666 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
667 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; r600_pm_init_profile()
669 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; r600_pm_init_profile()
670 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; r600_pm_init_profile()
671 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
672 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; r600_pm_init_profile()
675 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
676 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r600_pm_init_profile()
677 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
678 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; r600_pm_init_profile()
684 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; r600_pm_init_profile()
685 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; r600_pm_init_profile()
686 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
687 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; r600_pm_init_profile()
689 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; r600_pm_init_profile()
690 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; r600_pm_init_profile()
691 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
692 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; r600_pm_init_profile()
695 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; r600_pm_init_profile()
696 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; r600_pm_init_profile()
697 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
698 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; r600_pm_init_profile()
704 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; r600_pm_init_profile()
705 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; r600_pm_init_profile()
706 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
707 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; r600_pm_init_profile()
709 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; r600_pm_init_profile()
710 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; r600_pm_init_profile()
711 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
712 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; r600_pm_init_profile()
715 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; r600_pm_init_profile()
716 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; r600_pm_init_profile()
717 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; r600_pm_init_profile()
718 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; r600_pm_init_profile()
725 int req_ps_idx = rdev->pm.requested_power_state_index; r600_pm_misc()
726 int req_cm_idx = rdev->pm.requested_clock_mode_index; r600_pm_misc()
727 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; r600_pm_misc()
734 if (voltage->voltage != rdev->pm.current_vddc) { r600_pm_misc()
736 rdev->pm.current_vddc = voltage->voltage; r600_pm_misc()
3118 if (rdev->pm.pm_method == PM_METHOD_DPM) r600_resume()
4047 rdev->pm.vblank_sync = true; r600_irq_process()
4077 rdev->pm.vblank_sync = true; r600_irq_process()
4210 rdev->pm.dpm.thermal.high_to_low = false; r600_irq_process()
4215 rdev->pm.dpm.thermal.high_to_low = true; r600_irq_process()
4235 if (queue_thermal && rdev->pm.dpm_enabled) r600_irq_process()
4236 schedule_work(&rdev->pm.dpm.thermal.work); r600_irq_process()
H A Dr420.c42 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; r420_pm_init_profile()
43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r420_pm_init_profile()
44 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; r420_pm_init_profile()
45 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; r420_pm_init_profile()
47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; r420_pm_init_profile()
48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; r420_pm_init_profile()
49 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; r420_pm_init_profile()
50 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; r420_pm_init_profile()
52 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; r420_pm_init_profile()
53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; r420_pm_init_profile()
54 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; r420_pm_init_profile()
55 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; r420_pm_init_profile()
57 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; r420_pm_init_profile()
58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r420_pm_init_profile()
59 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; r420_pm_init_profile()
60 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; r420_pm_init_profile()
62 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; r420_pm_init_profile()
63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r420_pm_init_profile()
64 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; r420_pm_init_profile()
65 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; r420_pm_init_profile()
67 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; r420_pm_init_profile()
68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r420_pm_init_profile()
69 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; r420_pm_init_profile()
70 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; r420_pm_init_profile()
72 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; r420_pm_init_profile()
73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r420_pm_init_profile()
74 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; r420_pm_init_profile()
75 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; r420_pm_init_profile()
H A Dci_dpm.c195 struct ci_power_info *pi = rdev->pm.dpm.priv; ci_get_pi()
280 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) ci_populate_bapm_vddc_vid_sidd()
282 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) ci_populate_bapm_vddc_vid_sidd()
284 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != ci_populate_bapm_vddc_vid_sidd()
285 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) ci_populate_bapm_vddc_vid_sidd()
288 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { ci_populate_bapm_vddc_vid_sidd()
289 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { ci_populate_bapm_vddc_vid_sidd()
290 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); ci_populate_bapm_vddc_vid_sidd()
291 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); ci_populate_bapm_vddc_vid_sidd()
292 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); ci_populate_bapm_vddc_vid_sidd()
294 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); ci_populate_bapm_vddc_vid_sidd()
295 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); ci_populate_bapm_vddc_vid_sidd()
335 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; ci_populate_tdc_limit()
368 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) || ci_populate_fuzzy_fan()
369 (rdev->pm.dpm.fan.fan_output_sensitivity == 0)) ci_populate_fuzzy_fan()
370 rdev->pm.dpm.fan.fan_output_sensitivity = ci_populate_fuzzy_fan()
371 rdev->pm.dpm.fan.default_fan_output_sensitivity; ci_populate_fuzzy_fan()
374 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity); ci_populate_fuzzy_fan()
417 rdev->pm.dpm.dyn_state.cac_tdp_table; ci_populate_bapm_vddc_base_leakage_sidd()
434 rdev->pm.dpm.dyn_state.cac_tdp_table; ci_populate_bapm_parameters_in_dpm_table()
435 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; ci_populate_bapm_parameters_in_dpm_table()
669 rdev->pm.dpm.dyn_state.cac_tdp_table; ci_enable_power_containment()
743 rdev->pm.dpm.dyn_state.cac_tdp_table; ci_power_control_set_level()
751 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment); ci_power_control_set_level()
797 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; ci_apply_state_adjust_rules()
798 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; ci_apply_state_adjust_rules()
804 if ((rdev->pm.dpm.new_active_crtc_count > 1) || ci_apply_state_adjust_rules()
815 if (rdev->pm.dpm.ac_power) ci_apply_state_adjust_rules()
816 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; ci_apply_state_adjust_rules()
818 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; ci_apply_state_adjust_rules()
820 if (rdev->pm.dpm.ac_power == false) { ci_apply_state_adjust_rules()
840 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) ci_apply_state_adjust_rules()
841 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; ci_apply_state_adjust_rules()
842 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) ci_apply_state_adjust_rules()
843 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; ci_apply_state_adjust_rules()
891 rdev->pm.dpm.thermal.min_temp = low_temp; ci_thermal_set_temperature_range()
892 rdev->pm.dpm.thermal.max_temp = high_temp; ci_thermal_set_temperature_range()
960 rdev->pm.dpm.fan.ucode_fan_control = false; ci_thermal_setup_fan_table()
967 rdev->pm.dpm.fan.ucode_fan_control = false; ci_thermal_setup_fan_table()
971 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; ci_thermal_setup_fan_table()
975 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; ci_thermal_setup_fan_table()
976 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; ci_thermal_setup_fan_table()
978 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; ci_thermal_setup_fan_table()
979 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; ci_thermal_setup_fan_table()
984 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); ci_thermal_setup_fan_table()
985 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); ci_thermal_setup_fan_table()
986 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); ci_thermal_setup_fan_table()
993 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); ci_thermal_setup_fan_table()
1003 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * ci_thermal_setup_fan_table()
1019 rdev->pm.dpm.fan.ucode_fan_control = false; ci_thermal_setup_fan_table()
1038 rdev->pm.dpm.fan.default_max_fan_pwm); ci_fan_ctrl_start_smc_fan_control()
1072 if (rdev->pm.no_fan) ci_fan_ctrl_get_fan_speed_percent()
1099 if (rdev->pm.no_fan) ci_fan_ctrl_set_fan_speed_percent()
1128 if (rdev->pm.dpm.fan.ucode_fan_control) ci_fan_ctrl_set_mode()
1133 if (rdev->pm.dpm.fan.ucode_fan_control) ci_fan_ctrl_set_mode()
1159 if (rdev->pm.no_fan)
1162 if (rdev->pm.fan_pulses_per_revolution == 0)
1180 if (rdev->pm.no_fan)
1183 if (rdev->pm.fan_pulses_per_revolution == 0)
1186 if ((speed < rdev->pm.fan_min_rpm) ||
1187 (speed > rdev->pm.fan_max_rpm))
1190 if (rdev->pm.dpm.fan.ucode_fan_control)
1223 if (rdev->pm.dpm.fan.ucode_fan_control) { ci_thermal_start_smc_fan_control()
1233 if (rdev->pm.fan_pulses_per_revolution) { ci_thermal_initialize()
1235 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); ci_thermal_initialize()
1255 if (rdev->pm.dpm.fan.ucode_fan_control) { ci_thermal_start_thermal_controller()
1267 if (!rdev->pm.no_fan) ci_thermal_stop_thermal_controller()
1339 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { ci_get_leakage_voltages()
1441 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) ci_enable_vr_hot_gpio_interrupt()
1627 rdev->pm.dpm.dyn_state.cac_tdp_table;
1965 if (rdev->pm.dpm.new_active_crtc_count > 0) ci_program_display_gap()
1985 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1)); ci_program_display_gap()
2117 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, ci_construct_voltage_tables()
2135 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, ci_construct_voltage_tables()
2153 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, ci_construct_voltage_tables()
2284 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { ci_populate_mvdd_value()
2285 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { ci_populate_mvdd_value()
2291 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) ci_populate_mvdd_value()
2307 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) ci_get_std_voltage_value_sidd()
2310 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { ci_get_std_voltage_value_sidd()
2311 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { ci_get_std_voltage_value_sidd()
2313 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { ci_get_std_voltage_value_sidd()
2315 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) ci_get_std_voltage_value_sidd()
2318 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; ci_get_std_voltage_value_sidd()
2320 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; ci_get_std_voltage_value_sidd()
2322 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; ci_get_std_voltage_value_sidd()
2328 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { ci_get_std_voltage_value_sidd()
2330 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { ci_get_std_voltage_value_sidd()
2332 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) ci_get_std_voltage_value_sidd()
2335 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; ci_get_std_voltage_value_sidd()
2337 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; ci_get_std_voltage_value_sidd()
2339 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; ci_get_std_voltage_value_sidd()
2563 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { ci_populate_smc_initial_state()
2564 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= ci_populate_smc_initial_state()
2571 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { ci_populate_smc_initial_state()
2572 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= ci_populate_smc_initial_state()
2626 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; ci_populate_smc_uvd_level()
2630 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; ci_populate_smc_uvd_level()
2632 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; ci_populate_smc_uvd_level()
2634 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; ci_populate_smc_uvd_level()
2669 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; ci_populate_smc_vce_level()
2673 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; ci_populate_smc_vce_level()
2675 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; ci_populate_smc_vce_level()
2702 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); ci_populate_smc_acp_level()
2706 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; ci_populate_smc_acp_level()
2708 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; ci_populate_smc_acp_level()
2734 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; ci_populate_smc_samu_level()
2738 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; ci_populate_smc_samu_level()
2740 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; ci_populate_smc_samu_level()
2853 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { ci_populate_single_memory_level()
2855 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, ci_populate_single_memory_level()
2861 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { ci_populate_single_memory_level()
2863 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, ci_populate_single_memory_level()
2869 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { ci_populate_single_memory_level()
2871 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, ci_populate_single_memory_level()
2881 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, ci_populate_single_memory_level()
2903 (rdev->pm.dpm.new_active_crtc_count <= 2)) ci_populate_single_memory_level()
3096 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time; ci_populate_ulv_level()
3107 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) ci_populate_ulv_level()
3111 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; ci_populate_ulv_level()
3113 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) ci_populate_ulv_level()
3117 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * ci_populate_ulv_level()
3198 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, ci_populate_single_graphic_level()
3210 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, ci_populate_single_graphic_level()
3415 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; ci_setup_default_dpm_tables()
3417 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; ci_setup_default_dpm_tables()
3419 &rdev->pm.dpm.dyn_state.cac_leakage_table; ci_setup_default_dpm_tables()
3484 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; ci_setup_default_dpm_tables()
3494 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; ci_setup_default_dpm_tables()
3529 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; ci_init_smc_table()
3542 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) ci_init_smc_table()
3545 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) ci_init_smc_table()
3756 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; ci_apply_disp_minimum_voltage_request()
3758 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; ci_apply_disp_minimum_voltage_request()
3859 if (rdev->pm.dpm.current_active_crtc_count != ci_find_dpm_states_clocks_in_dpm_table()
3860 rdev->pm.dpm.new_active_crtc_count) ci_find_dpm_states_clocks_in_dpm_table()
3904 if (rdev->pm.dpm.ac_power) ci_enable_uvd_dpm()
3905 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; ci_enable_uvd_dpm()
3907 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; ci_enable_uvd_dpm()
3912 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { ci_enable_uvd_dpm()
3913 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { ci_enable_uvd_dpm()
3953 if (rdev->pm.dpm.ac_power) ci_enable_vce_dpm()
3954 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; ci_enable_vce_dpm()
3956 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; ci_enable_vce_dpm()
3960 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { ci_enable_vce_dpm()
3961 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { ci_enable_vce_dpm()
3986 if (rdev->pm.dpm.ac_power)
3987 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3989 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3993 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3994 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4017 if (rdev->pm.dpm.ac_power)
4018 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4020 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4024 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4025 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4051 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) ci_update_uvd_dpm()
4055 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; ci_update_uvd_dpm()
4071 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; ci_get_vce_boot_level()
4298 rdev->pm.dpm.forced_level = level; ci_dpm_force_performance_level()
4886 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; ci_set_private_data_variables_based_on_pptable()
4888 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; ci_set_private_data_variables_based_on_pptable()
4890 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; ci_set_private_data_variables_based_on_pptable()
4913 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = ci_set_private_data_variables_based_on_pptable()
4915 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = ci_set_private_data_variables_based_on_pptable()
4917 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = ci_set_private_data_variables_based_on_pptable()
4919 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = ci_set_private_data_variables_based_on_pptable()
5032 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); ci_patch_dependency_tables_with_leakage()
5034 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); ci_patch_dependency_tables_with_leakage()
5036 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); ci_patch_dependency_tables_with_leakage()
5038 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); ci_patch_dependency_tables_with_leakage()
5040 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); ci_patch_dependency_tables_with_leakage()
5042 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); ci_patch_dependency_tables_with_leakage()
5044 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); ci_patch_dependency_tables_with_leakage()
5046 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); ci_patch_dependency_tables_with_leakage()
5048 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); ci_patch_dependency_tables_with_leakage()
5050 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); ci_patch_dependency_tables_with_leakage()
5052 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); ci_patch_dependency_tables_with_leakage()
5054 &rdev->pm.dpm.dyn_state.cac_leakage_table); ci_patch_dependency_tables_with_leakage()
5098 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; ci_dpm_pre_set_power_state()
5133 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; ci_dpm_enable()
5288 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; ci_dpm_disable()
5434 rdev->pm.dpm.boot_ps = rps; ci_parse_pplib_non_clock_info()
5436 rdev->pm.dpm.uvd_ps = rps; ci_parse_pplib_non_clock_info()
5540 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * ci_parse_power_table()
5542 if (!rdev->pm.dpm.ps) ci_parse_power_table()
5551 if (!rdev->pm.power_state[i].clock_info) ci_parse_power_table()
5555 kfree(rdev->pm.dpm.ps); ci_parse_power_table()
5558 rdev->pm.dpm.ps[i].ps_priv = ps; ci_parse_power_table()
5559 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], ci_parse_power_table()
5574 &rdev->pm.dpm.ps[i], k, ci_parse_power_table()
5580 rdev->pm.dpm.num_ps = state_array->ucNumEntries; ci_parse_power_table()
5585 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; ci_parse_power_table()
5592 rdev->pm.dpm.vce_states[i].sclk = sclk; ci_parse_power_table()
5593 rdev->pm.dpm.vce_states[i].mclk = mclk; ci_parse_power_table()
5630 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { ci_dpm_fini()
5631 kfree(rdev->pm.dpm.ps[i].ps_priv); ci_dpm_fini()
5633 kfree(rdev->pm.dpm.ps); ci_dpm_fini()
5634 kfree(rdev->pm.dpm.priv); ci_dpm_fini()
5635 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); ci_dpm_fini()
5653 rdev->pm.dpm.priv = pi; ci_dpm_init()
5741 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = ci_dpm_init()
5743 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { ci_dpm_init()
5747 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; ci_dpm_init()
5748 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; ci_dpm_init()
5749 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; ci_dpm_init()
5750 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; ci_dpm_init()
5751 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; ci_dpm_init()
5752 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; ci_dpm_init()
5753 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; ci_dpm_init()
5754 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; ci_dpm_init()
5755 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; ci_dpm_init()
5757 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; ci_dpm_init()
5758 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; ci_dpm_init()
5759 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; ci_dpm_init()
5761 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; ci_dpm_init()
5762 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; ci_dpm_init()
5763 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; ci_dpm_init()
5764 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; ci_dpm_init()
5783 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; ci_dpm_init()
5786 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; ci_dpm_init()
5792 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC; ci_dpm_init()
5795 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC; ci_dpm_init()
5835 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { ci_dpm_init()
5841 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; ci_dpm_init()
5844 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { ci_dpm_init()
5850 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; ci_dpm_init()
5873 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) ci_dpm_init()
5883 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || ci_dpm_init()
5884 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) ci_dpm_init()
5885 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = ci_dpm_init()
5886 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; ci_dpm_init()
H A Drs690.c81 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); rs690_pm_info()
82 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); rs690_pm_info()
84 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); rs690_pm_info()
86 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); rs690_pm_info()
87 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); rs690_pm_info()
89 rdev->pm.igp_system_mclk.full = dfixed_const(400); rs690_pm_info()
90 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); rs690_pm_info()
91 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); rs690_pm_info()
95 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); rs690_pm_info()
96 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); rs690_pm_info()
98 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); rs690_pm_info()
100 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); rs690_pm_info()
102 rdev->pm.igp_system_mclk.full = dfixed_const(66700); rs690_pm_info()
103 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); rs690_pm_info()
104 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq)); rs690_pm_info()
105 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); rs690_pm_info()
106 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); rs690_pm_info()
110 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); rs690_pm_info()
111 rdev->pm.igp_system_mclk.full = dfixed_const(200); rs690_pm_info()
112 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); rs690_pm_info()
113 rdev->pm.igp_ht_link_width.full = dfixed_const(8); rs690_pm_info()
119 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); rs690_pm_info()
120 rdev->pm.igp_system_mclk.full = dfixed_const(200); rs690_pm_info()
121 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); rs690_pm_info()
122 rdev->pm.igp_ht_link_width.full = dfixed_const(8); rs690_pm_info()
128 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); rs690_pm_info()
133 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, rs690_pm_info()
134 rdev->pm.igp_ht_link_width); rs690_pm_info()
135 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); rs690_pm_info()
136 if (tmp.full < rdev->pm.max_bandwidth.full) { rs690_pm_info()
138 rdev->pm.max_bandwidth.full = tmp.full; rs690_pm_info()
144 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); rs690_pm_info()
146 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); rs690_pm_info()
280 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) rs690_crtc_bandwidth_compute()
283 selected_sclk = rdev->pm.current_sclk; rs690_crtc_bandwidth_compute()
292 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); rs690_crtc_bandwidth_compute()
356 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full && rs690_crtc_bandwidth_compute()
357 rdev->pm.sideport_bandwidth.full) rs690_crtc_bandwidth_compute()
358 max_bandwidth = rdev->pm.sideport_bandwidth; rs690_crtc_bandwidth_compute()
361 b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a); rs690_crtc_bandwidth_compute()
365 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full && rs690_crtc_bandwidth_compute()
366 rdev->pm.k8_bandwidth.full) rs690_crtc_bandwidth_compute()
367 max_bandwidth = rdev->pm.k8_bandwidth; rs690_crtc_bandwidth_compute()
368 if (max_bandwidth.full > rdev->pm.ht_bandwidth.full && rs690_crtc_bandwidth_compute()
369 rdev->pm.ht_bandwidth.full) rs690_crtc_bandwidth_compute()
370 max_bandwidth = rdev->pm.ht_bandwidth; rs690_crtc_bandwidth_compute()
H A Dradeon_atombios.c2053 rdev->pm.power_state[state_index].misc = misc; radeon_atombios_parse_misc_flags_1_3()
2054 rdev->pm.power_state[state_index].misc2 = misc2; radeon_atombios_parse_misc_flags_1_3()
2057 rdev->pm.power_state[state_index].type = radeon_atombios_parse_misc_flags_1_3()
2060 rdev->pm.power_state[state_index].type = radeon_atombios_parse_misc_flags_1_3()
2063 rdev->pm.power_state[state_index].type = radeon_atombios_parse_misc_flags_1_3()
2066 rdev->pm.power_state[state_index].type = radeon_atombios_parse_misc_flags_1_3()
2069 rdev->pm.power_state[state_index].type = radeon_atombios_parse_misc_flags_1_3()
2071 rdev->pm.power_state[state_index].flags &= radeon_atombios_parse_misc_flags_1_3()
2075 rdev->pm.power_state[state_index].type = radeon_atombios_parse_misc_flags_1_3()
2078 rdev->pm.power_state[state_index].type = radeon_atombios_parse_misc_flags_1_3()
2080 rdev->pm.default_power_state_index = state_index; radeon_atombios_parse_misc_flags_1_3()
2081 rdev->pm.power_state[state_index].default_clock_mode = radeon_atombios_parse_misc_flags_1_3()
2082 &rdev->pm.power_state[state_index].clock_info[0]; radeon_atombios_parse_misc_flags_1_3()
2084 rdev->pm.power_state[state_index].clock_info[0].flags |= radeon_atombios_parse_misc_flags_1_3()
2113 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); radeon_atombios_parse_power_table_1_3()
2114 if (rdev->pm.i2c_bus) { radeon_atombios_parse_power_table_1_3()
2120 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); radeon_atombios_parse_power_table_1_3()
2128 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL); radeon_atombios_parse_power_table_1_3()
2129 if (!rdev->pm.power_state) radeon_atombios_parse_power_table_1_3()
2133 rdev->pm.power_state[state_index].clock_info = radeon_atombios_parse_power_table_1_3()
2135 if (!rdev->pm.power_state[state_index].clock_info) radeon_atombios_parse_power_table_1_3()
2137 rdev->pm.power_state[state_index].num_clock_modes = 1; radeon_atombios_parse_power_table_1_3()
2138 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; radeon_atombios_parse_power_table_1_3()
2141 rdev->pm.power_state[state_index].clock_info[0].mclk = radeon_atombios_parse_power_table_1_3()
2143 rdev->pm.power_state[state_index].clock_info[0].sclk = radeon_atombios_parse_power_table_1_3()
2146 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || radeon_atombios_parse_power_table_1_3()
2147 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) radeon_atombios_parse_power_table_1_3()
2149 rdev->pm.power_state[state_index].pcie_lanes = radeon_atombios_parse_power_table_1_3()
2154 rdev->pm.power_state[state_index].clock_info[0].voltage.type = radeon_atombios_parse_power_table_1_3()
2156 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = radeon_atombios_parse_power_table_1_3()
2160 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = radeon_atombios_parse_power_table_1_3()
2163 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = radeon_atombios_parse_power_table_1_3()
2166 rdev->pm.power_state[state_index].clock_info[0].voltage.type = radeon_atombios_parse_power_table_1_3()
2168 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = radeon_atombios_parse_power_table_1_3()
2171 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; radeon_atombios_parse_power_table_1_3()
2176 rdev->pm.power_state[state_index].clock_info[0].mclk = radeon_atombios_parse_power_table_1_3()
2178 rdev->pm.power_state[state_index].clock_info[0].sclk = radeon_atombios_parse_power_table_1_3()
2181 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || radeon_atombios_parse_power_table_1_3()
2182 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) radeon_atombios_parse_power_table_1_3()
2184 rdev->pm.power_state[state_index].pcie_lanes = radeon_atombios_parse_power_table_1_3()
2190 rdev->pm.power_state[state_index].clock_info[0].voltage.type = radeon_atombios_parse_power_table_1_3()
2192 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = radeon_atombios_parse_power_table_1_3()
2196 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = radeon_atombios_parse_power_table_1_3()
2199 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = radeon_atombios_parse_power_table_1_3()
2202 rdev->pm.power_state[state_index].clock_info[0].voltage.type = radeon_atombios_parse_power_table_1_3()
2204 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = radeon_atombios_parse_power_table_1_3()
2207 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; radeon_atombios_parse_power_table_1_3()
2212 rdev->pm.power_state[state_index].clock_info[0].mclk = radeon_atombios_parse_power_table_1_3()
2214 rdev->pm.power_state[state_index].clock_info[0].sclk = radeon_atombios_parse_power_table_1_3()
2217 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || radeon_atombios_parse_power_table_1_3()
2218 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) radeon_atombios_parse_power_table_1_3()
2220 rdev->pm.power_state[state_index].pcie_lanes = radeon_atombios_parse_power_table_1_3()
2226 rdev->pm.power_state[state_index].clock_info[0].voltage.type = radeon_atombios_parse_power_table_1_3()
2228 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = radeon_atombios_parse_power_table_1_3()
2232 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = radeon_atombios_parse_power_table_1_3()
2235 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = radeon_atombios_parse_power_table_1_3()
2238 rdev->pm.power_state[state_index].clock_info[0].voltage.type = radeon_atombios_parse_power_table_1_3()
2240 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = radeon_atombios_parse_power_table_1_3()
2243 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = radeon_atombios_parse_power_table_1_3()
2245 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = radeon_atombios_parse_power_table_1_3()
2249 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; radeon_atombios_parse_power_table_1_3()
2256 if (rdev->pm.default_power_state_index == -1) { radeon_atombios_parse_power_table_1_3()
2257 rdev->pm.power_state[state_index - 1].type = radeon_atombios_parse_power_table_1_3()
2259 rdev->pm.default_power_state_index = state_index - 1; radeon_atombios_parse_power_table_1_3()
2260 rdev->pm.power_state[state_index - 1].default_clock_mode = radeon_atombios_parse_power_table_1_3()
2261 &rdev->pm.power_state[state_index - 1].clock_info[0]; radeon_atombios_parse_power_table_1_3()
2262 rdev->pm.power_state[state_index].flags &= radeon_atombios_parse_power_table_1_3()
2264 rdev->pm.power_state[state_index].misc = 0; radeon_atombios_parse_power_table_1_3()
2265 rdev->pm.power_state[state_index].misc2 = 0; radeon_atombios_parse_power_table_1_3()
2278 rdev->pm.no_fan = true; radeon_atombios_add_pplib_thermal_controller()
2279 rdev->pm.fan_pulses_per_revolution = radeon_atombios_add_pplib_thermal_controller()
2281 if (rdev->pm.fan_pulses_per_revolution) { radeon_atombios_add_pplib_thermal_controller()
2282 rdev->pm.fan_min_rpm = controller->ucFanMinRPM; radeon_atombios_add_pplib_thermal_controller()
2283 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM; radeon_atombios_add_pplib_thermal_controller()
2289 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; radeon_atombios_add_pplib_thermal_controller()
2294 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; radeon_atombios_add_pplib_thermal_controller()
2299 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; radeon_atombios_add_pplib_thermal_controller()
2304 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; radeon_atombios_add_pplib_thermal_controller()
2309 rdev->pm.int_thermal_type = THERMAL_TYPE_NI; radeon_atombios_add_pplib_thermal_controller()
2314 rdev->pm.int_thermal_type = THERMAL_TYPE_SI; radeon_atombios_add_pplib_thermal_controller()
2319 rdev->pm.int_thermal_type = THERMAL_TYPE_CI; radeon_atombios_add_pplib_thermal_controller()
2324 rdev->pm.int_thermal_type = THERMAL_TYPE_KV; radeon_atombios_add_pplib_thermal_controller()
2330 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; radeon_atombios_add_pplib_thermal_controller()
2336 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; radeon_atombios_add_pplib_thermal_controller()
2342 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; radeon_atombios_add_pplib_thermal_controller()
2349 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; radeon_atombios_add_pplib_thermal_controller()
2351 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); radeon_atombios_add_pplib_thermal_controller()
2352 if (rdev->pm.i2c_bus) { radeon_atombios_add_pplib_thermal_controller()
2357 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); radeon_atombios_add_pplib_thermal_controller()
2406 rdev->pm.power_state[state_index].misc = misc; radeon_atombios_parse_pplib_non_clock_info()
2407 rdev->pm.power_state[state_index].misc2 = misc2; radeon_atombios_parse_pplib_non_clock_info()
2408 rdev->pm.power_state[state_index].pcie_lanes = radeon_atombios_parse_pplib_non_clock_info()
2413 rdev->pm.power_state[state_index].type = radeon_atombios_parse_pplib_non_clock_info()
2417 rdev->pm.power_state[state_index].type = radeon_atombios_parse_pplib_non_clock_info()
2421 rdev->pm.power_state[state_index].type = radeon_atombios_parse_pplib_non_clock_info()
2426 rdev->pm.power_state[state_index].type = radeon_atombios_parse_pplib_non_clock_info()
2430 rdev->pm.power_state[state_index].flags = 0; radeon_atombios_parse_pplib_non_clock_info()
2432 rdev->pm.power_state[state_index].flags |= radeon_atombios_parse_pplib_non_clock_info()
2435 rdev->pm.power_state[state_index].type = radeon_atombios_parse_pplib_non_clock_info()
2437 rdev->pm.default_power_state_index = state_index; radeon_atombios_parse_pplib_non_clock_info()
2438 rdev->pm.power_state[state_index].default_clock_mode = radeon_atombios_parse_pplib_non_clock_info()
2439 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; radeon_atombios_parse_pplib_non_clock_info()
2442 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; radeon_atombios_parse_pplib_non_clock_info()
2443 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; radeon_atombios_parse_pplib_non_clock_info()
2444 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; radeon_atombios_parse_pplib_non_clock_info()
2445 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; radeon_atombios_parse_pplib_non_clock_info()
2455 rdev->pm.power_state[state_index].clock_info[j].mclk = radeon_atombios_parse_pplib_non_clock_info()
2457 rdev->pm.power_state[state_index].clock_info[j].sclk = radeon_atombios_parse_pplib_non_clock_info()
2460 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = radeon_atombios_parse_pplib_non_clock_info()
2463 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci = radeon_atombios_parse_pplib_non_clock_info()
2481 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; radeon_atombios_parse_pplib_clock_info()
2485 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; radeon_atombios_parse_pplib_clock_info()
2492 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; radeon_atombios_parse_pplib_clock_info()
2493 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; radeon_atombios_parse_pplib_clock_info()
2494 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = radeon_atombios_parse_pplib_clock_info()
2501 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; radeon_atombios_parse_pplib_clock_info()
2502 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; radeon_atombios_parse_pplib_clock_info()
2503 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = radeon_atombios_parse_pplib_clock_info()
2505 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = radeon_atombios_parse_pplib_clock_info()
2507 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = radeon_atombios_parse_pplib_clock_info()
2514 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; radeon_atombios_parse_pplib_clock_info()
2515 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; radeon_atombios_parse_pplib_clock_info()
2516 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = radeon_atombios_parse_pplib_clock_info()
2518 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = radeon_atombios_parse_pplib_clock_info()
2520 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = radeon_atombios_parse_pplib_clock_info()
2527 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; radeon_atombios_parse_pplib_clock_info()
2528 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; radeon_atombios_parse_pplib_clock_info()
2529 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = radeon_atombios_parse_pplib_clock_info()
2531 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = radeon_atombios_parse_pplib_clock_info()
2536 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { radeon_atombios_parse_pplib_clock_info()
2546 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, radeon_atombios_parse_pplib_clock_info()
2548 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; radeon_atombios_parse_pplib_clock_info()
2556 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) radeon_atombios_parse_pplib_clock_info()
2560 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || radeon_atombios_parse_pplib_clock_info()
2561 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) radeon_atombios_parse_pplib_clock_info()
2589 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * radeon_atombios_parse_power_table_4_5()
2591 if (!rdev->pm.power_state) radeon_atombios_parse_power_table_4_5()
2605 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * radeon_atombios_parse_power_table_4_5()
2609 if (!rdev->pm.power_state[i].clock_info) radeon_atombios_parse_power_table_4_5()
2625 rdev->pm.power_state[state_index].clock_info[0].mclk = radeon_atombios_parse_power_table_4_5()
2627 rdev->pm.power_state[state_index].clock_info[0].sclk = radeon_atombios_parse_power_table_4_5()
2631 rdev->pm.power_state[state_index].num_clock_modes = mode_index; radeon_atombios_parse_power_table_4_5()
2640 if (rdev->pm.power_state[i].num_clock_modes > 1) radeon_atombios_parse_power_table_4_5()
2641 rdev->pm.power_state[i].clock_info[0].flags |= radeon_atombios_parse_power_table_4_5()
2645 if (rdev->pm.default_power_state_index == -1) { radeon_atombios_parse_power_table_4_5()
2646 rdev->pm.power_state[0].type = radeon_atombios_parse_power_table_4_5()
2648 rdev->pm.default_power_state_index = 0; radeon_atombios_parse_power_table_4_5()
2649 rdev->pm.power_state[0].default_clock_mode = radeon_atombios_parse_power_table_4_5()
2650 &rdev->pm.power_state[0].clock_info[0]; radeon_atombios_parse_power_table_4_5()
2690 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * radeon_atombios_parse_power_table_6()
2692 if (!rdev->pm.power_state) radeon_atombios_parse_power_table_6()
2701 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * radeon_atombios_parse_power_table_6()
2705 if (!rdev->pm.power_state[i].clock_info) radeon_atombios_parse_power_table_6()
2719 rdev->pm.power_state[state_index].clock_info[0].mclk = radeon_atombios_parse_power_table_6()
2721 rdev->pm.power_state[state_index].clock_info[0].sclk = radeon_atombios_parse_power_table_6()
2725 rdev->pm.power_state[state_index].num_clock_modes = mode_index; radeon_atombios_parse_power_table_6()
2735 if (rdev->pm.power_state[i].num_clock_modes > 1) radeon_atombios_parse_power_table_6()
2736 rdev->pm.power_state[i].clock_info[0].flags |= radeon_atombios_parse_power_table_6()
2740 if (rdev->pm.default_power_state_index == -1) { radeon_atombios_parse_power_table_6()
2741 rdev->pm.power_state[0].type = radeon_atombios_parse_power_table_6()
2743 rdev->pm.default_power_state_index = 0; radeon_atombios_parse_power_table_6()
2744 rdev->pm.power_state[0].default_clock_mode = radeon_atombios_parse_power_table_6()
2745 &rdev->pm.power_state[0].clock_info[0]; radeon_atombios_parse_power_table_6()
2758 rdev->pm.default_power_state_index = -1; radeon_atombios_get_power_modes()
2781 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); radeon_atombios_get_power_modes()
2782 if (rdev->pm.power_state) { radeon_atombios_get_power_modes()
2783 rdev->pm.power_state[0].clock_info = radeon_atombios_get_power_modes()
2785 if (rdev->pm.power_state[0].clock_info) { radeon_atombios_get_power_modes()
2787 rdev->pm.power_state[state_index].type = radeon_atombios_get_power_modes()
2789 rdev->pm.power_state[state_index].num_clock_modes = 1; radeon_atombios_get_power_modes()
2790 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; radeon_atombios_get_power_modes()
2791 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; radeon_atombios_get_power_modes()
2792 rdev->pm.power_state[state_index].default_clock_mode = radeon_atombios_get_power_modes()
2793 &rdev->pm.power_state[state_index].clock_info[0]; radeon_atombios_get_power_modes()
2794 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; radeon_atombios_get_power_modes()
2795 rdev->pm.power_state[state_index].pcie_lanes = 16; radeon_atombios_get_power_modes()
2796 rdev->pm.default_power_state_index = state_index; radeon_atombios_get_power_modes()
2797 rdev->pm.power_state[state_index].flags = 0; radeon_atombios_get_power_modes()
2803 rdev->pm.num_power_states = state_index; radeon_atombios_get_power_modes()
2805 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; radeon_atombios_get_power_modes()
2806 rdev->pm.current_clock_mode_index = 0; radeon_atombios_get_power_modes()
2807 if (rdev->pm.default_power_state_index >= 0) radeon_atombios_get_power_modes()
2808 rdev->pm.current_vddc = radeon_atombios_get_power_modes()
2809 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; radeon_atombios_get_power_modes()
2811 rdev->pm.current_vddc = 0; radeon_atombios_get_power_modes()
3303 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; radeon_atom_get_voltage_evv()
3307 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == radeon_atom_get_voltage_evv()
3319 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); radeon_atom_get_voltage_evv()
H A Drv6xx_dpm.c46 struct rv6xx_power_info *pi = rdev->pm.dpm.priv; rv6xx_get_pi()
922 rdev->pm.dpm.voltage_response_time, rv6xx_program_voltage_timing_parameters()
926 rdev->pm.dpm.backbias_response_time, rv6xx_program_voltage_timing_parameters()
1186 if (rdev->pm.dpm.new_active_crtcs & 1) { rv6xx_program_display_gap()
1189 } else if (rdev->pm.dpm.new_active_crtcs & 2) { rv6xx_program_display_gap()
1299 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000); rv6xx_step_sw_voltage()
1549 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; rv6xx_dpm_enable()
1554 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) rv6xx_dpm_enable()
1616 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; rv6xx_dpm_disable()
1634 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) rv6xx_dpm_disable()
1646 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { rv6xx_dpm_disable()
1660 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; rv6xx_dpm_set_power_state()
1661 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; rv6xx_dpm_set_power_state()
1684 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) rv6xx_dpm_set_power_state()
1688 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) rv6xx_dpm_set_power_state()
1697 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) rv6xx_dpm_set_power_state()
1701 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) rv6xx_dpm_set_power_state()
1703 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000); rv6xx_dpm_set_power_state()
1721 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) { rv6xx_dpm_set_power_state()
1729 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) rv6xx_dpm_set_power_state()
1760 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s) rv6xx_setup_asic()
1762 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1) rv6xx_setup_asic()
1764 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1) rv6xx_setup_asic()
1812 rdev->pm.dpm.boot_ps = rps; rv6xx_parse_pplib_non_clock_info()
1814 rdev->pm.dpm.uvd_ps = rps; rv6xx_parse_pplib_non_clock_info()
1891 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * rv6xx_parse_power_table()
1893 if (!rdev->pm.dpm.ps) rv6xx_parse_power_table()
1910 kfree(rdev->pm.dpm.ps); rv6xx_parse_power_table()
1913 rdev->pm.dpm.ps[i].ps_priv = ps; rv6xx_parse_power_table()
1914 rv6xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], rv6xx_parse_power_table()
1923 &rdev->pm.dpm.ps[i], j, rv6xx_parse_power_table()
1928 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates; rv6xx_parse_power_table()
1942 rdev->pm.dpm.priv = pi; rv6xx_dpm_init()
1952 if (rdev->pm.dpm.voltage_response_time == 0) rv6xx_dpm_init()
1953 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; rv6xx_dpm_init()
1954 if (rdev->pm.dpm.backbias_response_time == 0) rv6xx_dpm_init()
1955 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; rv6xx_dpm_init()
1997 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)) rv6xx_dpm_init()
2031 struct radeon_ps *rps = rdev->pm.dpm.current_ps; rv6xx_dpm_debugfs_print_current_performance_level()
2056 struct radeon_ps *rps = rdev->pm.dpm.current_ps; rv6xx_dpm_get_current_sclk()
2079 struct radeon_ps *rps = rdev->pm.dpm.current_ps; rv6xx_dpm_get_current_mclk()
2103 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { rv6xx_dpm_fini()
2104 kfree(rdev->pm.dpm.ps[i].ps_priv); rv6xx_dpm_fini()
2106 kfree(rdev->pm.dpm.ps); rv6xx_dpm_fini()
2107 kfree(rdev->pm.dpm.priv); rv6xx_dpm_fini()
2112 struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps); rv6xx_dpm_get_sclk()
2122 struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps); rv6xx_dpm_get_mclk()
2156 rdev->pm.dpm.forced_level = level; rv6xx_dpm_force_performance_level()
H A Dkv_dpm.c251 struct kv_power_info *pi = rdev->pm.dpm.priv; kv_get_pi()
556 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; kv_convert_vid2_to_vid7()
578 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; kv_convert_vid7_to_vid2()
719 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; kv_program_bootup_state()
821 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; kv_populate_uvd_table()
894 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; kv_populate_vce_table()
955 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; kv_populate_samu_table()
1021 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; kv_populate_acp_table()
1080 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; kv_calculate_dfs_bypass_settings()
1280 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); kv_dpm_enable()
1290 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { kv_dpm_late_enable()
1329 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); kv_dpm_disable()
1427 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; kv_update_uvd_dpm()
1463 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; kv_get_vce_boot_level()
1479 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; kv_update_vce_dpm()
1520 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; kv_update_samu_dpm()
1551 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; kv_get_acp_boot_level()
1584 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; kv_update_acp_dpm()
1712 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; kv_set_valid_clock_range()
1832 rdev->pm.dpm.forced_level = level; kv_dpm_force_performance_level()
1840 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; kv_dpm_pre_set_power_state()
1860 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power); kv_dpm_set_power_state()
1987 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; kv_patch_voltage_values()
1989 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; kv_patch_voltage_values()
1991 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; kv_patch_voltage_values()
1993 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; kv_patch_voltage_values()
2107 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; kv_get_high_voltage_limit()
2148 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; kv_apply_state_adjust_rules()
2151 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; kv_apply_state_adjust_rules()
2154 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; kv_apply_state_adjust_rules()
2155 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; kv_apply_state_adjust_rules()
2181 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) kv_apply_state_adjust_rules()
2182 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; kv_apply_state_adjust_rules()
2243 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) || kv_apply_state_adjust_rules()
2285 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; kv_calculate_nbps_level_settings()
2302 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); kv_calculate_nbps_level_settings()
2352 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; kv_init_graphics_levels()
2473 rdev->pm.dpm.thermal.min_temp = low_temp; kv_set_thermal_temperature_range()
2474 rdev->pm.dpm.thermal.max_temp = high_temp; kv_set_thermal_temperature_range()
2547 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); kv_parse_sys_info_table()
2602 rdev->pm.dpm.boot_ps = rps; kv_parse_pplib_non_clock_info()
2606 rdev->pm.dpm.uvd_ps = rps; kv_parse_pplib_non_clock_info()
2663 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * kv_parse_power_table()
2665 if (!rdev->pm.dpm.ps) kv_parse_power_table()
2674 if (!rdev->pm.power_state[i].clock_info) kv_parse_power_table()
2678 kfree(rdev->pm.dpm.ps); kv_parse_power_table()
2681 rdev->pm.dpm.ps[i].ps_priv = ps; kv_parse_power_table()
2694 &rdev->pm.dpm.ps[i], k, kv_parse_power_table()
2698 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], kv_parse_power_table()
2703 rdev->pm.dpm.num_ps = state_array->ucNumEntries; kv_parse_power_table()
2708 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; kv_parse_power_table()
2713 rdev->pm.dpm.vce_states[i].sclk = sclk; kv_parse_power_table()
2714 rdev->pm.dpm.vce_states[i].mclk = 0; kv_parse_power_table()
2728 rdev->pm.dpm.priv = pi; kv_dpm_init()
2868 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { kv_dpm_fini()
2869 kfree(rdev->pm.dpm.ps[i].ps_priv); kv_dpm_fini()
2871 kfree(rdev->pm.dpm.ps); kv_dpm_fini()
2872 kfree(rdev->pm.dpm.priv); kv_dpm_fini()
H A Dsi_dpm.c1764 struct si_power_info *pi = rdev->pm.dpm.priv; si_get_pi()
1838 u32 p_limit1 = rdev->pm.dpm.tdp_limit; si_update_dte_from_pl2()
1839 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; si_update_dte_from_pl2()
2128 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) si_calculate_adjusted_tdp_limits()
2131 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; si_calculate_adjusted_tdp_limits()
2134 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; si_calculate_adjusted_tdp_limits()
2135 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); si_calculate_adjusted_tdp_limits()
2137 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; si_calculate_adjusted_tdp_limits()
2138 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; si_calculate_adjusted_tdp_limits()
2139 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) si_calculate_adjusted_tdp_limits()
2140 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; si_calculate_adjusted_tdp_limits()
2162 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; si_populate_smc_tdp_limits()
2175 rdev->pm.dpm.tdp_adjustment, si_populate_smc_tdp_limits()
2232 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); si_populate_smc_tdp_limits_2()
2234 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); si_populate_smc_tdp_limits_2()
2394 if (rdev->pm.dpm.sq_ramping_threshold == 0) si_populate_sq_ramping_values()
2416 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && si_populate_sq_ramping_values()
2535 &rdev->pm.dpm.dyn_state.cac_leakage_table; si_get_cac_std_voltage_max_min()
2672 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; si_initialize_smc_cac_tables()
2699 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; si_initialize_smc_cac_tables()
2963 if ((rdev->pm.dpm.new_active_crtc_count > 1) || si_apply_state_adjust_rules()
2972 if (rdev->pm.dpm.ac_power) si_apply_state_adjust_rules()
2973 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; si_apply_state_adjust_rules()
2975 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; si_apply_state_adjust_rules()
2981 if (rdev->pm.dpm.ac_power == false) { si_apply_state_adjust_rules()
2995 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, si_apply_state_adjust_rules()
2997 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, si_apply_state_adjust_rules()
2999 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, si_apply_state_adjust_rules()
3092 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, si_apply_state_adjust_rules()
3095 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, si_apply_state_adjust_rules()
3098 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, si_apply_state_adjust_rules()
3101 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, si_apply_state_adjust_rules()
3115 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) si_apply_state_adjust_rules()
3342 struct radeon_ps *rps = rdev->pm.dpm.current_ps; si_dpm_force_performance_level()
3366 rdev->pm.dpm.forced_level = level; si_dpm_force_performance_level()
3587 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; si_program_response_times()
3588 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; si_program_response_times()
3626 if (rdev->pm.dpm.new_active_crtc_count > 0) si_program_display_gap()
3631 if (rdev->pm.dpm.new_active_crtc_count > 1) si_program_display_gap()
3641 if ((rdev->pm.dpm.new_active_crtc_count > 0) && si_program_display_gap()
3642 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { si_program_display_gap()
3645 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) si_program_display_gap()
3662 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); si_program_display_gap()
3915 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, si_construct_voltage_tables()
3936 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, si_construct_voltage_tables()
4032 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { si_populate_smc_voltage_tables()
4094 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { si_get_std_voltage_value()
4095 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { si_get_std_voltage_value()
4096 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) si_get_std_voltage_value()
4099 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { si_get_std_voltage_value()
4101 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { si_get_std_voltage_value()
4103 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) si_get_std_voltage_value()
4105 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; si_get_std_voltage_value()
4108 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; si_get_std_voltage_value()
4114 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { si_get_std_voltage_value()
4116 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { si_get_std_voltage_value()
4118 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) si_get_std_voltage_value()
4120 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; si_get_std_voltage_value()
4123 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; si_get_std_voltage_value()
4129 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) si_get_std_voltage_value()
4130 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; si_get_std_voltage_value()
4382 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, si_populate_smc_initial_state()
4468 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, si_populate_smc_acpi_state()
4495 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, si_populate_smc_acpi_state()
4636 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; si_init_smc_table()
4645 switch (rdev->pm.int_thermal_type) { si_init_smc_table()
4658 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) si_init_smc_table()
4661 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { si_init_smc_table()
4666 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) si_init_smc_table()
4672 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) si_init_smc_table()
4675 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { si_init_smc_table()
4677 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; si_init_smc_table()
4943 (rdev->pm.dpm.new_active_crtc_count <= 2)) { si_convert_power_level_to_smc()
5008 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, si_convert_power_level_to_smc()
5098 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { si_is_state_ulv_compatible()
5100 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { si_is_state_ulv_compatible()
5102 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) si_is_state_ulv_compatible()
5260 if (rdev->pm.dpm.new_active_crtc_count == 0) si_upload_smc_data()
5264 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { si_upload_smc_data()
5842 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); si_patch_dependency_tables_based_on_leakage()
5844 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); si_patch_dependency_tables_based_on_leakage()
5846 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); si_patch_dependency_tables_based_on_leakage()
5923 rdev->pm.dpm.thermal.min_temp = low_temp; si_thermal_set_temperature_range()
5924 rdev->pm.dpm.thermal.max_temp = high_temp; si_thermal_set_temperature_range()
5963 rdev->pm.dpm.fan.ucode_fan_control = false; si_thermal_setup_fan_table()
5970 rdev->pm.dpm.fan.ucode_fan_control = false; si_thermal_setup_fan_table()
5974 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; si_thermal_setup_fan_table()
5978 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; si_thermal_setup_fan_table()
5979 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; si_thermal_setup_fan_table()
5981 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; si_thermal_setup_fan_table()
5982 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; si_thermal_setup_fan_table()
5987 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); si_thermal_setup_fan_table()
5988 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); si_thermal_setup_fan_table()
5989 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); si_thermal_setup_fan_table()
5996 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); si_thermal_setup_fan_table()
6006 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * si_thermal_setup_fan_table()
6022 rdev->pm.dpm.fan.ucode_fan_control = false; si_thermal_setup_fan_table()
6063 if (rdev->pm.no_fan) si_fan_ctrl_get_fan_speed_percent()
6090 if (rdev->pm.no_fan) si_fan_ctrl_set_fan_speed_percent()
6119 if (rdev->pm.dpm.fan.ucode_fan_control) si_fan_ctrl_set_mode()
6124 if (rdev->pm.dpm.fan.ucode_fan_control) si_fan_ctrl_set_mode()
6150 if (rdev->pm.no_fan)
6153 if (rdev->pm.fan_pulses_per_revolution == 0)
6171 if (rdev->pm.no_fan)
6174 if (rdev->pm.fan_pulses_per_revolution == 0)
6177 if ((speed < rdev->pm.fan_min_rpm) ||
6178 (speed > rdev->pm.fan_max_rpm))
6181 if (rdev->pm.dpm.fan.ucode_fan_control)
6214 if (rdev->pm.dpm.fan.ucode_fan_control) { si_thermal_start_smc_fan_control()
6224 if (rdev->pm.fan_pulses_per_revolution) { si_thermal_initialize()
6226 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); si_thermal_initialize()
6246 if (rdev->pm.dpm.fan.ucode_fan_control) { si_thermal_start_thermal_controller()
6264 if (!rdev->pm.no_fan) { si_thermal_stop_thermal_controller()
6275 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; si_dpm_enable()
6420 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; si_dpm_disable()
6444 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; si_dpm_pre_set_power_state()
6456 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; si_power_control_set_level()
6647 rdev->pm.dpm.boot_ps = rps; si_parse_pplib_non_clock_info()
6649 rdev->pm.dpm.uvd_ps = rps; si_parse_pplib_non_clock_info()
6721 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; si_parse_pplib_clock_info()
6722 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; si_parse_pplib_clock_info()
6723 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; si_parse_pplib_clock_info()
6724 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; si_parse_pplib_clock_info()
6760 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * si_parse_power_table()
6762 if (!rdev->pm.dpm.ps) si_parse_power_table()
6771 if (!rdev->pm.power_state[i].clock_info) si_parse_power_table()
6775 kfree(rdev->pm.dpm.ps); si_parse_power_table()
6778 rdev->pm.dpm.ps[i].ps_priv = ps; si_parse_power_table()
6779 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], si_parse_power_table()
6794 &rdev->pm.dpm.ps[i], k, si_parse_power_table()
6800 rdev->pm.dpm.num_ps = state_array->ucNumEntries; si_parse_power_table()
6817 rdev->pm.dpm.priv = si_pi; si_dpm_init()
6852 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = si_dpm_init()
6854 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { si_dpm_init()
6858 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; si_dpm_init()
6859 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; si_dpm_init()
6860 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; si_dpm_init()
6861 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; si_dpm_init()
6862 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; si_dpm_init()
6863 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; si_dpm_init()
6864 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; si_dpm_init()
6865 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; si_dpm_init()
6866 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; si_dpm_init()
6868 if (rdev->pm.dpm.voltage_response_time == 0) si_dpm_init()
6869 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; si_dpm_init()
6870 if (rdev->pm.dpm.backbias_response_time == 0) si_dpm_init()
6871 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; si_dpm_init()
6931 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) si_dpm_init()
6948 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; si_dpm_init()
6949 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; si_dpm_init()
6950 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; si_dpm_init()
6951 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; si_dpm_init()
6952 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; si_dpm_init()
6953 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; si_dpm_init()
6954 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; si_dpm_init()
6959 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || si_dpm_init()
6960 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) si_dpm_init()
6961 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = si_dpm_init()
6962 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; si_dpm_init()
6973 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { si_dpm_fini()
6974 kfree(rdev->pm.dpm.ps[i].ps_priv); si_dpm_fini()
6976 kfree(rdev->pm.dpm.ps); si_dpm_fini()
6977 kfree(rdev->pm.dpm.priv); si_dpm_fini()
6978 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); si_dpm_fini()
H A Dbtc_dpm.c1231 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values, btc_get_valid_mclk()
1238 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values, btc_get_valid_sclk()
1281 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) btc_adjust_clock_combinations()
1285 (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / btc_adjust_clock_combinations()
1286 rdev->pm.dpm.dyn_state.mclk_sclk_ratio); btc_adjust_clock_combinations()
1288 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) btc_adjust_clock_combinations()
1292 rdev->pm.dpm.dyn_state.sclk_mclk_delta); btc_adjust_clock_combinations()
1319 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { btc_apply_voltage_delta_rules()
1321 (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta)); btc_apply_voltage_delta_rules()
1325 if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { btc_apply_voltage_delta_rules()
1327 (*vddci - rdev->pm.dpm.dyn_state.vddc_vddci_delta)); btc_apply_voltage_delta_rules()
1639 switch (rdev->pm.int_thermal_type) { btc_init_smc_table()
1652 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) btc_init_smc_table()
1655 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) btc_init_smc_table()
1658 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) btc_init_smc_table()
2104 if ((rdev->pm.dpm.new_active_crtc_count > 1) || btc_apply_state_adjust_rules()
2110 if (rdev->pm.dpm.ac_power) btc_apply_state_adjust_rules()
2111 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; btc_apply_state_adjust_rules()
2113 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; btc_apply_state_adjust_rules()
2115 if (rdev->pm.dpm.ac_power == false) { btc_apply_state_adjust_rules()
2209 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, btc_apply_state_adjust_rules()
2211 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, btc_apply_state_adjust_rules()
2213 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, btc_apply_state_adjust_rules()
2215 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, btc_apply_state_adjust_rules()
2218 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, btc_apply_state_adjust_rules()
2220 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, btc_apply_state_adjust_rules()
2222 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, btc_apply_state_adjust_rules()
2224 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, btc_apply_state_adjust_rules()
2227 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, btc_apply_state_adjust_rules()
2229 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, btc_apply_state_adjust_rules()
2231 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, btc_apply_state_adjust_rules()
2233 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, btc_apply_state_adjust_rules()
2243 if ((ps->high.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) && btc_apply_state_adjust_rules()
2244 (ps->medium.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) && btc_apply_state_adjust_rules()
2245 (ps->low.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)) btc_apply_state_adjust_rules()
2250 if (ps->low.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) btc_apply_state_adjust_rules()
2252 if (ps->medium.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) btc_apply_state_adjust_rules()
2254 if (ps->high.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) btc_apply_state_adjust_rules()
2293 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; btc_dpm_pre_set_power_state()
2380 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; btc_dpm_enable()
2418 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) btc_dpm_enable()
2488 btc_update_current_ps(rdev, rdev->pm.dpm.boot_ps); btc_dpm_enable()
2510 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { btc_dpm_disable()
2529 btc_update_current_ps(rdev, rdev->pm.dpm.boot_ps); btc_dpm_disable()
2562 rdev->pm.dpm.priv = eg_pi; btc_dpm_init()
2584 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = btc_dpm_init()
2586 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { btc_dpm_init()
2590 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; btc_dpm_init()
2591 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; btc_dpm_init()
2592 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; btc_dpm_init()
2593 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; btc_dpm_init()
2594 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 800; btc_dpm_init()
2595 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; btc_dpm_init()
2596 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 800; btc_dpm_init()
2597 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; btc_dpm_init()
2598 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 800; btc_dpm_init()
2600 if (rdev->pm.dpm.voltage_response_time == 0) btc_dpm_init()
2601 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; btc_dpm_init()
2602 if (rdev->pm.dpm.backbias_response_time == 0) btc_dpm_init()
2603 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; btc_dpm_init()
2659 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) btc_dpm_init()
2698 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; btc_dpm_init()
2699 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; btc_dpm_init()
2700 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900; btc_dpm_init()
2701 rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk); btc_dpm_init()
2702 rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk; btc_dpm_init()
2703 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; btc_dpm_init()
2704 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; btc_dpm_init()
2707 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; btc_dpm_init()
2709 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 10000; btc_dpm_init()
2712 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || btc_dpm_init()
2713 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) btc_dpm_init()
2714 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = btc_dpm_init()
2715 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; btc_dpm_init()
2724 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { btc_dpm_fini()
2725 kfree(rdev->pm.dpm.ps[i].ps_priv); btc_dpm_fini()
2727 kfree(rdev->pm.dpm.ps); btc_dpm_fini()
2728 kfree(rdev->pm.dpm.priv); btc_dpm_fini()
2729 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); btc_dpm_fini()
H A Drv770_dpm.c57 struct rv7xx_power_info *pi = rdev->pm.dpm.priv; rv770_get_pi()
64 struct evergreen_power_info *pi = rdev->pm.dpm.priv; evergreen_get_pi()
1177 switch (rdev->pm.int_thermal_type) { rv770_init_smc_table()
1191 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) { rv770_init_smc_table()
1194 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT) rv770_init_smc_table()
1197 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT) rv770_init_smc_table()
1201 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) rv770_init_smc_table()
1347 if (rdev->pm.dpm.new_active_crtcs & 1) { rv770_program_display_gap()
1350 } else if (rdev->pm.dpm.new_active_crtcs & 2) { rv770_program_display_gap()
1499 rdev->pm.dpm.forced_level = level; rv770_dpm_force_performance_level()
1708 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; rv770_program_response_times()
1709 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; rv770_program_response_times()
1888 rdev->pm.dpm.thermal.min_temp = low_temp; rv770_set_thermal_temperature_range()
1889 rdev->pm.dpm.thermal.max_temp = high_temp; rv770_set_thermal_temperature_range()
1897 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; rv770_dpm_enable()
1926 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) rv770_dpm_enable()
1982 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { rv770_dpm_late_enable()
2017 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { rv770_dpm_disable()
2040 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; rv770_dpm_set_power_state()
2041 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; rv770_dpm_set_power_state()
2084 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
2109 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s) rv770_dpm_setup_asic()
2111 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1) rv770_dpm_setup_asic()
2113 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1) rv770_dpm_setup_asic()
2169 rdev->pm.dpm.boot_ps = rps; rv7xx_parse_pplib_non_clock_info()
2171 rdev->pm.dpm.uvd_ps = rps; rv7xx_parse_pplib_non_clock_info()
2260 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; rv7xx_parse_pplib_clock_info()
2261 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; rv7xx_parse_pplib_clock_info()
2262 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; rv7xx_parse_pplib_clock_info()
2263 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; rv7xx_parse_pplib_clock_info()
2285 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * rv7xx_parse_power_table()
2287 if (!rdev->pm.dpm.ps) rv7xx_parse_power_table()
2304 kfree(rdev->pm.dpm.ps); rv7xx_parse_power_table()
2307 rdev->pm.dpm.ps[i].ps_priv = ps; rv7xx_parse_power_table()
2308 rv7xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], rv7xx_parse_power_table()
2318 &rdev->pm.dpm.ps[i], j, rv7xx_parse_power_table()
2323 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates; rv7xx_parse_power_table()
2352 rdev->pm.dpm.priv = pi; rv770_dpm_init()
2368 if (rdev->pm.dpm.voltage_response_time == 0) rv770_dpm_init()
2369 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; rv770_dpm_init()
2370 if (rdev->pm.dpm.backbias_response_time == 0) rv770_dpm_init()
2371 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; rv770_dpm_init()
2409 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) rv770_dpm_init()
2468 struct radeon_ps *rps = rdev->pm.dpm.current_ps; rv770_dpm_debugfs_print_current_performance_level()
2497 struct radeon_ps *rps = rdev->pm.dpm.current_ps; rv770_dpm_get_current_sclk()
2519 struct radeon_ps *rps = rdev->pm.dpm.current_ps; rv770_dpm_get_current_mclk()
2543 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { rv770_dpm_fini()
2544 kfree(rdev->pm.dpm.ps[i].ps_priv); rv770_dpm_fini()
2546 kfree(rdev->pm.dpm.ps); rv770_dpm_fini()
2547 kfree(rdev->pm.dpm.priv); rv770_dpm_fini()
2552 struct rv7xx_ps *requested_state = rv770_get_ps(rdev->pm.dpm.requested_ps); rv770_dpm_get_sclk()
2562 struct rv7xx_ps *requested_state = rv770_get_ps(rdev->pm.dpm.requested_ps); rv770_dpm_get_mclk()
H A Drs780_dpm.c43 struct igp_power_info *pi = rdev->pm.dpm.priv; rs780_get_pi()
380 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); rs780_force_voltage()
407 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); rs780_force_fbdiv()
600 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; rs780_dpm_enable()
643 (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) { rs780_dpm_disable()
652 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; rs780_dpm_set_power_state()
653 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; rs780_dpm_set_power_state()
742 rdev->pm.dpm.boot_ps = rps; rs780_parse_pplib_non_clock_info()
744 rdev->pm.dpm.uvd_ps = rps; rs780_parse_pplib_non_clock_info()
807 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * rs780_parse_power_table()
809 if (!rdev->pm.dpm.ps) rs780_parse_power_table()
830 kfree(rdev->pm.dpm.ps); rs780_parse_power_table()
833 rdev->pm.dpm.ps[i].ps_priv = ps; rs780_parse_power_table()
834 rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], rs780_parse_power_table()
838 &rdev->pm.dpm.ps[i], rs780_parse_power_table()
842 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates; rs780_parse_power_table()
858 rdev->pm.dpm.priv = pi; rs780_dpm_init()
956 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { rs780_dpm_fini()
957 kfree(rdev->pm.dpm.ps[i].ps_priv); rs780_dpm_fini()
959 kfree(rdev->pm.dpm.ps); rs780_dpm_fini()
960 kfree(rdev->pm.dpm.priv); rs780_dpm_fini()
965 struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps); rs780_dpm_get_sclk()
983 struct radeon_ps *rps = rdev->pm.dpm.current_ps; rs780_dpm_debugfs_print_current_performance_level()
1030 struct radeon_ps *rps = rdev->pm.dpm.current_ps; rs780_dpm_force_performance_level()
1073 rdev->pm.dpm.forced_level = level; rs780_dpm_force_performance_level()
H A Devergreen.c1456 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; sumo_pm_init_profile()
1457 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; sumo_pm_init_profile()
1458 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; sumo_pm_init_profile()
1459 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; sumo_pm_init_profile()
1467 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; sumo_pm_init_profile()
1468 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; sumo_pm_init_profile()
1469 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; sumo_pm_init_profile()
1470 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; sumo_pm_init_profile()
1472 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; sumo_pm_init_profile()
1473 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; sumo_pm_init_profile()
1474 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; sumo_pm_init_profile()
1475 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; sumo_pm_init_profile()
1477 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; sumo_pm_init_profile()
1478 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; sumo_pm_init_profile()
1479 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; sumo_pm_init_profile()
1480 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; sumo_pm_init_profile()
1482 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; sumo_pm_init_profile()
1483 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; sumo_pm_init_profile()
1484 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; sumo_pm_init_profile()
1485 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; sumo_pm_init_profile()
1489 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; sumo_pm_init_profile()
1490 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; sumo_pm_init_profile()
1491 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; sumo_pm_init_profile()
1492 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = sumo_pm_init_profile()
1493 rdev->pm.power_state[idx].num_clock_modes - 1; sumo_pm_init_profile()
1495 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; sumo_pm_init_profile()
1496 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; sumo_pm_init_profile()
1497 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; sumo_pm_init_profile()
1498 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = sumo_pm_init_profile()
1499 rdev->pm.power_state[idx].num_clock_modes - 1; sumo_pm_init_profile()
1516 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; btc_pm_init_profile()
1517 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; btc_pm_init_profile()
1518 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; btc_pm_init_profile()
1519 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; btc_pm_init_profile()
1529 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; btc_pm_init_profile()
1530 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; btc_pm_init_profile()
1531 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; btc_pm_init_profile()
1532 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; btc_pm_init_profile()
1534 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; btc_pm_init_profile()
1535 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; btc_pm_init_profile()
1536 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; btc_pm_init_profile()
1537 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; btc_pm_init_profile()
1539 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; btc_pm_init_profile()
1540 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; btc_pm_init_profile()
1541 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; btc_pm_init_profile()
1542 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; btc_pm_init_profile()
1544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; btc_pm_init_profile()
1545 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; btc_pm_init_profile()
1546 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; btc_pm_init_profile()
1547 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; btc_pm_init_profile()
1549 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; btc_pm_init_profile()
1550 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; btc_pm_init_profile()
1551 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; btc_pm_init_profile()
1552 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; btc_pm_init_profile()
1554 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; btc_pm_init_profile()
1555 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; btc_pm_init_profile()
1556 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; btc_pm_init_profile()
1557 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; btc_pm_init_profile()
1561 * evergreen_pm_misc - set additional pm hw parameters callback.
1570 int req_ps_idx = rdev->pm.requested_power_state_index; evergreen_pm_misc()
1571 int req_cm_idx = rdev->pm.requested_clock_mode_index; evergreen_pm_misc()
1572 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; evergreen_pm_misc()
1579 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { evergreen_pm_misc()
1581 rdev->pm.current_vddc = voltage->voltage; evergreen_pm_misc()
1589 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && evergreen_pm_misc()
1591 rdev->pm.active_crtc_count && evergreen_pm_misc()
1592 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || evergreen_pm_misc()
1593 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) evergreen_pm_misc()
1594 voltage = &rdev->pm.power_state[req_ps_idx]. evergreen_pm_misc()
1595 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage; evergreen_pm_misc()
1600 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { evergreen_pm_misc()
1602 rdev->pm.current_vddci = voltage->vddci; evergreen_pm_misc()
2232 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { evergreen_program_watermarks()
2238 wm_high.yclk = rdev->pm.current_mclk * 10; evergreen_program_watermarks()
2239 wm_high.sclk = rdev->pm.current_sclk * 10; evergreen_program_watermarks()
2259 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { evergreen_program_watermarks()
2265 wm_low.yclk = rdev->pm.current_mclk * 10; evergreen_program_watermarks()
2266 wm_low.sclk = rdev->pm.current_sclk * 10; evergreen_program_watermarks()
5033 rdev->pm.vblank_sync = true; evergreen_irq_process()
5063 rdev->pm.vblank_sync = true; evergreen_irq_process()
5093 rdev->pm.vblank_sync = true; evergreen_irq_process()
5123 rdev->pm.vblank_sync = true; evergreen_irq_process()
5153 rdev->pm.vblank_sync = true; evergreen_irq_process()
5183 rdev->pm.vblank_sync = true; evergreen_irq_process()
5424 rdev->pm.dpm.thermal.high_to_low = false; evergreen_irq_process()
5429 rdev->pm.dpm.thermal.high_to_low = true; evergreen_irq_process()
5457 if (queue_thermal && rdev->pm.dpm_enabled) evergreen_irq_process()
5458 schedule_work(&rdev->pm.dpm.thermal.work); evergreen_irq_process()
5487 if (ASIC_IS_DCE5(rdev) && !rdev->pm.dpm_enabled) { evergreen_startup()
5627 if (rdev->pm.pm_method == PM_METHOD_DPM) evergreen_resume()
H A Dradeon_combios.c2643 rdev->pm.default_power_state_index = -1; radeon_combios_get_power_modes()
2646 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL); radeon_combios_get_power_modes()
2647 if (rdev->pm.power_state) { radeon_combios_get_power_modes()
2649 rdev->pm.power_state[0].clock_info = radeon_combios_get_power_modes()
2651 rdev->pm.power_state[1].clock_info = radeon_combios_get_power_modes()
2653 if (!rdev->pm.power_state[0].clock_info || radeon_combios_get_power_modes()
2654 !rdev->pm.power_state[1].clock_info) radeon_combios_get_power_modes()
2695 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); radeon_combios_get_power_modes()
2696 if (rdev->pm.i2c_bus) { radeon_combios_get_power_modes()
2701 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); radeon_combios_get_power_modes()
2712 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); radeon_combios_get_power_modes()
2713 if (rdev->pm.i2c_bus) { radeon_combios_get_power_modes()
2718 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); radeon_combios_get_power_modes()
2731 rdev->pm.power_state[state_index].num_clock_modes = 1; radeon_combios_get_power_modes()
2732 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); radeon_combios_get_power_modes()
2733 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); radeon_combios_get_power_modes()
2734 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || radeon_combios_get_power_modes()
2735 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) radeon_combios_get_power_modes()
2737 rdev->pm.power_state[state_index].type = radeon_combios_get_power_modes()
2742 rdev->pm.power_state[state_index].misc = misc; radeon_combios_get_power_modes()
2743 rdev->pm.power_state[state_index].misc2 = misc2; radeon_combios_get_power_modes()
2745 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; radeon_combios_get_power_modes()
2747 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = radeon_combios_get_power_modes()
2750 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = radeon_combios_get_power_modes()
2752 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; radeon_combios_get_power_modes()
2754 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = radeon_combios_get_power_modes()
2757 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); radeon_combios_get_power_modes()
2762 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = radeon_combios_get_power_modes()
2765 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); radeon_combios_get_power_modes()
2767 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; radeon_combios_get_power_modes()
2772 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; radeon_combios_get_power_modes()
2775 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; radeon_combios_get_power_modes()
2778 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; radeon_combios_get_power_modes()
2781 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; radeon_combios_get_power_modes()
2784 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; radeon_combios_get_power_modes()
2788 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; radeon_combios_get_power_modes()
2790 rdev->pm.power_state[state_index].pcie_lanes = radeon_combios_get_power_modes()
2792 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; radeon_combios_get_power_modes()
2803 rdev->pm.power_state[state_index].type = radeon_combios_get_power_modes()
2805 rdev->pm.power_state[state_index].num_clock_modes = 1; radeon_combios_get_power_modes()
2806 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; radeon_combios_get_power_modes()
2807 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; radeon_combios_get_power_modes()
2808 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; radeon_combios_get_power_modes()
2810 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) radeon_combios_get_power_modes()
2811 rdev->pm.power_state[state_index].clock_info[0].voltage = radeon_combios_get_power_modes()
2812 rdev->pm.power_state[0].clock_info[0].voltage; radeon_combios_get_power_modes()
2814 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; radeon_combios_get_power_modes()
2815 rdev->pm.power_state[state_index].pcie_lanes = 16; radeon_combios_get_power_modes()
2816 rdev->pm.power_state[state_index].flags = 0; radeon_combios_get_power_modes()
2817 rdev->pm.default_power_state_index = state_index; radeon_combios_get_power_modes()
2818 rdev->pm.num_power_states = state_index + 1; radeon_combios_get_power_modes()
2820 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; radeon_combios_get_power_modes()
2821 rdev->pm.current_clock_mode_index = 0; radeon_combios_get_power_modes()
2825 rdev->pm.default_power_state_index = state_index; radeon_combios_get_power_modes()
2826 rdev->pm.num_power_states = 0; radeon_combios_get_power_modes()
2828 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; radeon_combios_get_power_modes()
2829 rdev->pm.current_clock_mode_index = 0; radeon_combios_get_power_modes()
H A Dr100.c210 rdev->pm.dynpm_can_upclock = true; r100_pm_get_dynpm_state()
211 rdev->pm.dynpm_can_downclock = true; r100_pm_get_dynpm_state()
213 switch (rdev->pm.dynpm_planned_action) { r100_pm_get_dynpm_state()
215 rdev->pm.requested_power_state_index = 0; r100_pm_get_dynpm_state()
216 rdev->pm.dynpm_can_downclock = false; r100_pm_get_dynpm_state()
219 if (rdev->pm.current_power_state_index == 0) { r100_pm_get_dynpm_state()
220 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; r100_pm_get_dynpm_state()
221 rdev->pm.dynpm_can_downclock = false; r100_pm_get_dynpm_state()
223 if (rdev->pm.active_crtc_count > 1) { r100_pm_get_dynpm_state()
224 for (i = 0; i < rdev->pm.num_power_states; i++) { r100_pm_get_dynpm_state()
225 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) r100_pm_get_dynpm_state()
227 else if (i >= rdev->pm.current_power_state_index) { r100_pm_get_dynpm_state()
228 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; r100_pm_get_dynpm_state()
231 rdev->pm.requested_power_state_index = i; r100_pm_get_dynpm_state()
236 rdev->pm.requested_power_state_index = r100_pm_get_dynpm_state()
237 rdev->pm.current_power_state_index - 1; r100_pm_get_dynpm_state()
240 if ((rdev->pm.active_crtc_count > 0) && r100_pm_get_dynpm_state()
241 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & r100_pm_get_dynpm_state()
243 rdev->pm.requested_power_state_index++; r100_pm_get_dynpm_state()
247 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { r100_pm_get_dynpm_state()
248 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; r100_pm_get_dynpm_state()
249 rdev->pm.dynpm_can_upclock = false; r100_pm_get_dynpm_state()
251 if (rdev->pm.active_crtc_count > 1) { r100_pm_get_dynpm_state()
252 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { r100_pm_get_dynpm_state()
253 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) r100_pm_get_dynpm_state()
255 else if (i <= rdev->pm.current_power_state_index) { r100_pm_get_dynpm_state()
256 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; r100_pm_get_dynpm_state()
259 rdev->pm.requested_power_state_index = i; r100_pm_get_dynpm_state()
264 rdev->pm.requested_power_state_index = r100_pm_get_dynpm_state()
265 rdev->pm.current_power_state_index + 1; r100_pm_get_dynpm_state()
269 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; r100_pm_get_dynpm_state()
270 rdev->pm.dynpm_can_upclock = false; r100_pm_get_dynpm_state()
278 rdev->pm.requested_clock_mode_index = 0; r100_pm_get_dynpm_state()
281 rdev->pm.power_state[rdev->pm.requested_power_state_index]. r100_pm_get_dynpm_state()
282 clock_info[rdev->pm.requested_clock_mode_index].sclk, r100_pm_get_dynpm_state()
283 rdev->pm.power_state[rdev->pm.requested_power_state_index]. r100_pm_get_dynpm_state()
284 clock_info[rdev->pm.requested_clock_mode_index].mclk, r100_pm_get_dynpm_state()
285 rdev->pm.power_state[rdev->pm.requested_power_state_index]. r100_pm_get_dynpm_state()
301 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; r100_pm_init_profile()
302 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r100_pm_init_profile()
303 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; r100_pm_init_profile()
304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; r100_pm_init_profile()
306 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; r100_pm_init_profile()
307 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; r100_pm_init_profile()
308 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; r100_pm_init_profile()
309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; r100_pm_init_profile()
311 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; r100_pm_init_profile()
312 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; r100_pm_init_profile()
313 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; r100_pm_init_profile()
314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; r100_pm_init_profile()
316 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; r100_pm_init_profile()
317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r100_pm_init_profile()
318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; r100_pm_init_profile()
319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; r100_pm_init_profile()
321 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; r100_pm_init_profile()
322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r100_pm_init_profile()
323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; r100_pm_init_profile()
324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; r100_pm_init_profile()
326 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; r100_pm_init_profile()
327 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r100_pm_init_profile()
328 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; r100_pm_init_profile()
329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; r100_pm_init_profile()
331 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; r100_pm_init_profile()
332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; r100_pm_init_profile()
333 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; r100_pm_init_profile()
334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; r100_pm_init_profile()
338 * r100_pm_misc - set additional pm hw parameters callback.
347 int requested_index = rdev->pm.requested_power_state_index; r100_pm_misc()
348 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; r100_pm_misc()
427 rdev->asic->pm.set_pcie_lanes && r100_pm_misc()
429 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { r100_pm_misc()
783 rdev->pm.vblank_sync = true; r100_irq_process()
792 rdev->pm.vblank_sync = true; r100_irq_process()
3253 sclk_ff = rdev->pm.sclk; r100_bandwidth_update()
3254 mclk_ff = rdev->pm.mclk; r100_bandwidth_update()
H A Dni_dpm.c728 struct ni_power_info *pi = rdev->pm.dpm.priv; ni_get_pi()
795 if ((rdev->pm.dpm.new_active_crtc_count > 1) || ni_apply_state_adjust_rules()
801 if (rdev->pm.dpm.ac_power) ni_apply_state_adjust_rules()
802 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; ni_apply_state_adjust_rules()
804 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; ni_apply_state_adjust_rules()
806 if (rdev->pm.dpm.ac_power == false) { ni_apply_state_adjust_rules()
873 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, ni_apply_state_adjust_rules()
876 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, ni_apply_state_adjust_rules()
879 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, ni_apply_state_adjust_rules()
882 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, ni_apply_state_adjust_rules()
896 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) ni_apply_state_adjust_rules()
899 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) ni_apply_state_adjust_rules()
1012 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); ni_patch_dependency_tables_based_on_leakage()
1015 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); ni_patch_dependency_tables_based_on_leakage()
1075 rdev->pm.dpm.forced_level = level; ni_dpm_force_performance_level()
1228 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; ni_program_response_times()
1229 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; ni_program_response_times()
1346 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries && ni_get_std_voltage_value()
1347 ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)) ni_get_std_voltage_value()
1348 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; ni_get_std_voltage_value()
1438 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) ni_calculate_adjusted_tdp_limits()
1442 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; ni_calculate_adjusted_tdp_limits()
1443 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit + (*tdp_limit - rdev->pm.dpm.tdp_limit); ni_calculate_adjusted_tdp_limits()
1445 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; ni_calculate_adjusted_tdp_limits()
1446 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit - (rdev->pm.dpm.tdp_limit - *tdp_limit); ni_calculate_adjusted_tdp_limits()
1473 rdev->pm.dpm.tdp_adjustment, ni_populate_smc_tdp_limits()
1945 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; ni_init_smc_table()
1952 switch (rdev->pm.int_thermal_type) { ni_init_smc_table()
1965 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) ni_init_smc_table()
1968 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) ni_init_smc_table()
1971 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) ni_init_smc_table()
2478 rdev->pm.dpm.tdp_adjustment, ni_populate_power_containment_values()
2553 if (rdev->pm.dpm.sq_ramping_threshold == 0) ni_populate_sq_ramping_values()
2575 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && ni_populate_sq_ramping_values()
3098 &rdev->pm.dpm.dyn_state.cac_leakage_table; ni_init_simplified_leakage_table()
3165 ni_pi->cac_data.i_leakage = rdev->pm.dpm.cac_leakage; ni_initialize_smc_cac_tables()
3589 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; ni_dpm_enable()
3707 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; ni_dpm_disable()
3722 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { ni_dpm_disable()
3743 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; ni_power_control_set_level()
3768 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; ni_dpm_pre_set_power_state()
3915 rdev->pm.dpm.boot_ps = rps; ni_parse_pplib_non_clock_info()
3917 rdev->pm.dpm.uvd_ps = rps; ni_parse_pplib_non_clock_info()
3978 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; ni_parse_pplib_clock_info()
3979 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; ni_parse_pplib_clock_info()
3980 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; ni_parse_pplib_clock_info()
3981 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; ni_parse_pplib_clock_info()
4003 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * ni_parse_power_table()
4005 if (!rdev->pm.dpm.ps) ni_parse_power_table()
4022 kfree(rdev->pm.dpm.ps); ni_parse_power_table()
4025 rdev->pm.dpm.ps[i].ps_priv = ps; ni_parse_power_table()
4026 ni_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], ni_parse_power_table()
4036 &rdev->pm.dpm.ps[i], j, ni_parse_power_table()
4041 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates; ni_parse_power_table()
4056 rdev->pm.dpm.priv = ni_pi; ni_dpm_init()
4079 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = ni_dpm_init()
4081 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { ni_dpm_init()
4085 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; ni_dpm_init()
4086 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; ni_dpm_init()
4087 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; ni_dpm_init()
4088 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; ni_dpm_init()
4089 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; ni_dpm_init()
4090 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; ni_dpm_init()
4091 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; ni_dpm_init()
4092 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; ni_dpm_init()
4093 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; ni_dpm_init()
4097 if (rdev->pm.dpm.voltage_response_time == 0) ni_dpm_init()
4098 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; ni_dpm_init()
4099 if (rdev->pm.dpm.backbias_response_time == 0) ni_dpm_init()
4100 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; ni_dpm_init()
4163 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) ni_dpm_init()
4194 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3; ni_dpm_init()
4195 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; ni_dpm_init()
4196 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900; ni_dpm_init()
4197 rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk); ni_dpm_init()
4198 rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk; ni_dpm_init()
4199 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; ni_dpm_init()
4200 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; ni_dpm_init()
4201 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500; ni_dpm_init()
4258 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || ni_dpm_init()
4259 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) ni_dpm_init()
4260 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = ni_dpm_init()
4261 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; ni_dpm_init()
4270 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { ni_dpm_fini()
4271 kfree(rdev->pm.dpm.ps[i].ps_priv); ni_dpm_fini()
4273 kfree(rdev->pm.dpm.ps); ni_dpm_fini()
4274 kfree(rdev->pm.dpm.priv); ni_dpm_fini()
4275 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); ni_dpm_fini()
H A Dradeon_asic.c245 .pm = {
313 .pm = {
409 .pm = {
477 .pm = {
545 .pm = {
613 .pm = {
681 .pm = {
749 .pm = {
817 .pm = {
885 .pm = {
982 .pm = {
1068 .pm = {
1161 .pm = {
1267 .pm = {
1387 .pm = {
1481 .pm = {
1574 .pm = {
1722 .pm = {
1827 .pm = {
1962 .pm = {
2131 .pm = {
2244 .pm = {
2339 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; radeon_asic_init()
2340 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; radeon_asic_init()
2341 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; radeon_asic_init()
2342 rdev->asic->pm.set_memory_clock = NULL; radeon_asic_init()
2668 rdev->asic->pm.get_memory_clock = NULL; radeon_asic_init()
2669 rdev->asic->pm.set_memory_clock = NULL; radeon_asic_init()
H A Dtrinity_dpm.c355 struct trinity_power_info *pi = rdev->pm.dpm.priv; trinity_get_pi()
1044 rdev->pm.dpm.thermal.min_temp = low_temp; trinity_set_thermal_temperature_range()
1045 rdev->pm.dpm.thermal.max_temp = high_temp; trinity_set_thermal_temperature_range()
1107 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps); trinity_dpm_enable()
1120 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { trinity_dpm_late_enable()
1150 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { trinity_dpm_disable()
1155 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps); trinity_dpm_disable()
1210 rdev->pm.dpm.forced_level = level; trinity_dpm_force_performance_level()
1218 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; trinity_dpm_pre_set_power_state()
1239 trinity_dpm_bapm_enable(rdev, rdev->pm.dpm.ac_power); trinity_dpm_set_power_state()
1500 u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count; trinity_apply_state_adjust_rules()
1571 u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count; trinity_add_dccac_value()
1634 rdev->pm.dpm.boot_ps = rps; trinity_parse_pplib_non_clock_info()
1638 rdev->pm.dpm.uvd_ps = rps; trinity_parse_pplib_non_clock_info()
1695 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * trinity_parse_power_table()
1697 if (!rdev->pm.dpm.ps) trinity_parse_power_table()
1706 if (!rdev->pm.power_state[i].clock_info) trinity_parse_power_table()
1710 kfree(rdev->pm.dpm.ps); trinity_parse_power_table()
1713 rdev->pm.dpm.ps[i].ps_priv = ps; trinity_parse_power_table()
1726 &rdev->pm.dpm.ps[i], k, trinity_parse_power_table()
1730 trinity_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], trinity_parse_power_table()
1735 rdev->pm.dpm.num_ps = state_array->ucNumEntries; trinity_parse_power_table()
1875 rdev->pm.dpm.priv = pi; trinity_dpm_init()
1998 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { trinity_dpm_fini()
1999 kfree(rdev->pm.dpm.ps[i].ps_priv); trinity_dpm_fini()
2001 kfree(rdev->pm.dpm.ps); trinity_dpm_fini()
2002 kfree(rdev->pm.dpm.priv); trinity_dpm_fini()
H A Dcypress_dpm.c1622 switch (rdev->pm.int_thermal_type) { cypress_init_smc_table()
1635 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) cypress_init_smc_table()
1638 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) cypress_init_smc_table()
1641 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) cypress_init_smc_table()
1748 if (rdev->pm.dpm.new_active_crtc_count > 0) cypress_program_display_gap()
1753 if (rdev->pm.dpm.new_active_crtc_count > 1) cypress_program_display_gap()
1763 if ((rdev->pm.dpm.new_active_crtc_count > 0) && cypress_program_display_gap()
1764 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { cypress_program_display_gap()
1767 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) cypress_program_display_gap()
1780 cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); cypress_program_display_gap()
1807 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; cypress_dpm_enable()
1842 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) cypress_dpm_enable()
1918 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; cypress_dpm_disable()
1932 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { cypress_dpm_disable()
1957 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; cypress_dpm_set_power_state()
1958 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; cypress_dpm_set_power_state()
2031 rdev->pm.dpm.priv = eg_pi; cypress_dpm_init()
2050 if (rdev->pm.dpm.voltage_response_time == 0) cypress_dpm_init()
2051 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; cypress_dpm_init()
2052 if (rdev->pm.dpm.backbias_response_time == 0) cypress_dpm_init()
2053 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; cypress_dpm_init()
2101 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) cypress_dpm_init()
2146 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { cypress_dpm_fini()
2147 kfree(rdev->pm.dpm.ps[i].ps_priv); cypress_dpm_fini()
2149 kfree(rdev->pm.dpm.ps); cypress_dpm_fini()
2150 kfree(rdev->pm.dpm.priv); cypress_dpm_fini()
H A Dradeon_uvd.c827 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { radeon_uvd_idle_work_handler()
828 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd, radeon_uvd_idle_work_handler()
829 &rdev->pm.dpm.hd); radeon_uvd_idle_work_handler()
847 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { radeon_uvd_note_usage()
850 if ((rdev->pm.dpm.sd != sd) || radeon_uvd_note_usage()
851 (rdev->pm.dpm.hd != hd)) { radeon_uvd_note_usage()
852 rdev->pm.dpm.sd = sd; radeon_uvd_note_usage()
853 rdev->pm.dpm.hd = hd; radeon_uvd_note_usage()
860 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { radeon_uvd_note_usage()
H A Dsumo_dpm.c84 struct sumo_power_info *pi = rdev->pm.dpm.priv; sumo_get_pi()
1175 rdev->pm.dpm.thermal.min_temp = low_temp; sumo_set_thermal_temperature_range()
1176 rdev->pm.dpm.thermal.max_temp = high_temp; sumo_set_thermal_temperature_range()
1233 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps); sumo_dpm_enable()
1247 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { sumo_dpm_late_enable()
1273 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { sumo_dpm_disable()
1278 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps); sumo_dpm_disable()
1284 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; sumo_dpm_pre_set_power_state()
1423 rdev->pm.dpm.boot_ps = rps; sumo_parse_pplib_non_clock_info()
1427 rdev->pm.dpm.uvd_ps = rps; sumo_parse_pplib_non_clock_info()
1485 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * sumo_parse_power_table()
1487 if (!rdev->pm.dpm.ps) sumo_parse_power_table()
1496 if (!rdev->pm.power_state[i].clock_info) sumo_parse_power_table()
1500 kfree(rdev->pm.dpm.ps); sumo_parse_power_table()
1503 rdev->pm.dpm.ps[i].ps_priv = ps; sumo_parse_power_table()
1515 &rdev->pm.dpm.ps[i], k, sumo_parse_power_table()
1519 sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], sumo_parse_power_table()
1524 rdev->pm.dpm.num_ps = state_array->ucNumEntries; sumo_parse_power_table()
1749 rdev->pm.dpm.priv = pi; sumo_dpm_init()
1874 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { sumo_dpm_fini()
1875 kfree(rdev->pm.dpm.ps[i].ps_priv); sumo_dpm_fini()
1877 kfree(rdev->pm.dpm.ps); sumo_dpm_fini()
1878 kfree(rdev->pm.dpm.priv); sumo_dpm_fini()
1942 rdev->pm.dpm.forced_level = level; sumo_dpm_force_performance_level()
/linux-4.1.27/drivers/hid/
H A Dhid-prodikeys.c43 struct pcmidi_snd *pm; /* pcmidi device context */ member in struct:pk_device
48 struct pcmidi_snd *pm; member in struct:pcmidi_sustain
109 dbg_hid("pcmidi sysfs read channel=%u\n", pk->pm->midi_channel); show_channel()
111 return sprintf(buf, "%u (min:%u, max:%u)\n", pk->pm->midi_channel, show_channel()
126 pk->pm->midi_channel = channel; store_channel()
146 dbg_hid("pcmidi sysfs read sustain=%u\n", pk->pm->midi_sustain); show_sustain()
148 return sprintf(buf, "%u (off:%u, max:%u (ms))\n", pk->pm->midi_sustain, show_sustain()
163 pk->pm->midi_sustain = sustain; store_sustain()
164 pk->pm->midi_sustain_mode = store_sustain()
165 (0 == sustain || !pk->pm->midi_mode) ? 0 : 1; store_sustain()
185 dbg_hid("pcmidi sysfs read octave=%d\n", pk->pm->midi_octave); show_octave()
187 return sprintf(buf, "%d (min:%d, max:%d)\n", pk->pm->midi_octave, show_octave()
203 pk->pm->midi_octave = octave; store_octave()
217 static void pcmidi_send_note(struct pcmidi_snd *pm, pcmidi_send_note() argument
227 spin_lock_irqsave(&pm->rawmidi_in_lock, flags); pcmidi_send_note()
229 if (!pm->in_substream) pcmidi_send_note()
231 if (!test_bit(pm->in_substream->number, &pm->in_triggered)) pcmidi_send_note()
234 snd_rawmidi_receive(pm->in_substream, buffer, 3); pcmidi_send_note()
237 spin_unlock_irqrestore(&pm->rawmidi_in_lock, flags); pcmidi_send_note()
246 pcmidi_send_note(pms->pm, pms->status, pms->note, pms->velocity); pcmidi_sustained_note_release()
250 static void init_sustain_timers(struct pcmidi_snd *pm) init_sustain_timers() argument
256 pms = &pm->sustained_notes[i]; init_sustain_timers()
258 pms->pm = pm; init_sustain_timers()
264 static void stop_sustain_timers(struct pcmidi_snd *pm) stop_sustain_timers() argument
270 pms = &pm->sustained_notes[i]; stop_sustain_timers()
276 static int pcmidi_get_output_report(struct pcmidi_snd *pm) pcmidi_get_output_report() argument
278 struct hid_device *hdev = pm->pk->hdev; pcmidi_get_output_report()
294 pm->pcmidi_report6 = report; pcmidi_get_output_report()
301 static void pcmidi_submit_output_report(struct pcmidi_snd *pm, int state) pcmidi_submit_output_report() argument
303 struct hid_device *hdev = pm->pk->hdev; pcmidi_submit_output_report()
304 struct hid_report *report = pm->pcmidi_report6; pcmidi_submit_output_report()
311 static int pcmidi_handle_report1(struct pcmidi_snd *pm, u8 *data) pcmidi_handle_report1() argument
319 dbg_hid("pcmidi mode: %d\n", pm->midi_mode); pcmidi_handle_report1()
322 if (pm->midi_mode && bit_mask == 0x004000) { pcmidi_handle_report1()
324 pm->midi_octave--; pcmidi_handle_report1()
325 if (pm->midi_octave < -2) pcmidi_handle_report1()
326 pm->midi_octave = -2; pcmidi_handle_report1()
328 pm->midi_mode, pm->midi_octave); pcmidi_handle_report1()
332 else if (pm->midi_mode && bit_mask == 0x000004) { pcmidi_handle_report1()
334 pm->midi_sustain_mode ^= 0x1; pcmidi_handle_report1()
341 static int pcmidi_handle_report3(struct pcmidi_snd *pm, u8 *data, int size) pcmidi_handle_report3() argument
353 status = 128 + 16 + pm->midi_channel; /* 1001nnnn */ pcmidi_handle_report3()
355 (pm->midi_octave * 12); pcmidi_handle_report3()
359 status = 128 + pm->midi_channel; /* 1000nnnn */ pcmidi_handle_report3()
361 (pm->midi_octave*12); pcmidi_handle_report3()
363 if (pm->midi_sustain_mode) { pcmidi_handle_report3()
365 pms = &pm->sustained_notes[i]; pcmidi_handle_report3()
374 msecs_to_jiffies(pm->midi_sustain)); pcmidi_handle_report3()
380 pcmidi_send_note(pm, status, note, velocity); pcmidi_handle_report3()
386 static int pcmidi_handle_report4(struct pcmidi_snd *pm, u8 *data) pcmidi_handle_report4() argument
398 key = pm->last_key[bit_index]; pcmidi_handle_report4()
400 input_event(pm->input_ep82, EV_KEY, pcmidi_handle_report4()
401 pm->last_key[bit_index], 0); pcmidi_handle_report4()
402 pm->last_key[bit_index] = 0; pcmidi_handle_report4()
411 pm->fn_state ^= 0x000010; pcmidi_handle_report4()
412 if (pm->fn_state) pcmidi_handle_report4()
413 pcmidi_submit_output_report(pm, 0xc5); pcmidi_handle_report4()
415 pcmidi_submit_output_report(pm, 0xc6); pcmidi_handle_report4()
418 pcmidi_submit_output_report(pm, 0xc1); pcmidi_handle_report4()
419 pm->midi_mode ^= 0x01; pcmidi_handle_report4()
421 dbg_hid("pcmidi mode: %d\n", pm->midi_mode); pcmidi_handle_report4()
424 dbg_hid("pcmidi mode: %d\n", pm->midi_mode); pcmidi_handle_report4()
425 if (pm->midi_mode) { pcmidi_handle_report4()
426 pm->midi_octave++; pcmidi_handle_report4()
427 if (pm->midi_octave > 2) pcmidi_handle_report4()
428 pm->midi_octave = 2; pcmidi_handle_report4()
430 pm->midi_mode, pm->midi_octave); pcmidi_handle_report4()
491 input_event(pm->input_ep82, EV_KEY, key, 1); pcmidi_handle_report4()
492 pm->last_key[bit_index] = key; pcmidi_handle_report4()
500 struct pcmidi_snd *pm, unsigned report_id, u8 *data, int size) pcmidi_handle_report()
506 ret = pcmidi_handle_report1(pm, data); pcmidi_handle_report()
509 ret = pcmidi_handle_report3(pm, data, size); pcmidi_handle_report()
512 ret = pcmidi_handle_report4(pm, data); pcmidi_handle_report()
519 struct pcmidi_snd *pm, struct input_dev *input) pcmidi_setup_extra_keys()
544 if (pm->ifnum != 1) /* only set up ONCE for interace 1 */ pcmidi_setup_extra_keys()
547 pm->input_ep82 = input; pcmidi_setup_extra_keys()
550 pm->last_key[i] = 0; pcmidi_setup_extra_keys()
553 set_bit(*pkeys, pm->input_ep82->keybit); pcmidi_setup_extra_keys()
558 static int pcmidi_set_operational(struct pcmidi_snd *pm) pcmidi_set_operational() argument
560 if (pm->ifnum != 1) pcmidi_set_operational()
563 pcmidi_get_output_report(pm); pcmidi_set_operational()
564 pcmidi_submit_output_report(pm, 0xc1); pcmidi_set_operational()
575 struct pcmidi_snd *pm = substream->rmidi->private_data; pcmidi_in_open() local
578 pm->in_substream = substream; pcmidi_in_open()
590 struct pcmidi_snd *pm = substream->rmidi->private_data; pcmidi_in_trigger() local
594 pm->in_triggered = up; pcmidi_in_trigger()
603 static int pcmidi_snd_initialise(struct pcmidi_snd *pm) pcmidi_snd_initialise() argument
614 if (pm->ifnum != 1) pcmidi_snd_initialise()
627 err = snd_card_new(&pm->pk->hdev->dev, index[dev], id[dev], pcmidi_snd_initialise()
634 pm->card = card; pcmidi_snd_initialise()
637 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, pm, &ops); pcmidi_snd_initialise()
656 pm->rwmidi = rwmidi; pcmidi_snd_initialise()
659 rwmidi->private_data = pm; pcmidi_snd_initialise()
665 err = device_create_file(&pm->pk->hdev->dev, pcmidi_snd_initialise()
673 err = device_create_file(&pm->pk->hdev->dev, pcmidi_snd_initialise()
681 err = device_create_file(&pm->pk->hdev->dev, pcmidi_snd_initialise()
689 spin_lock_init(&pm->rawmidi_in_lock); pcmidi_snd_initialise()
691 init_sustain_timers(pm); pcmidi_snd_initialise()
692 pcmidi_set_operational(pm); pcmidi_snd_initialise()
706 stop_sustain_timers(pm); pcmidi_snd_initialise()
707 device_remove_file(&pm->pk->hdev->dev, sysfs_device_attr_octave); pcmidi_snd_initialise()
709 device_remove_file(&pm->pk->hdev->dev, sysfs_device_attr_sustain); pcmidi_snd_initialise()
711 device_remove_file(&pm->pk->hdev->dev, sysfs_device_attr_channel); pcmidi_snd_initialise()
713 if (pm->card) { pcmidi_snd_initialise()
714 snd_card_free(pm->card); pcmidi_snd_initialise()
715 pm->card = NULL; pcmidi_snd_initialise()
720 static int pcmidi_snd_terminate(struct pcmidi_snd *pm) pcmidi_snd_terminate() argument
722 if (pm->card) { pcmidi_snd_terminate()
723 stop_sustain_timers(pm); pcmidi_snd_terminate()
725 device_remove_file(&pm->pk->hdev->dev, pcmidi_snd_terminate()
727 device_remove_file(&pm->pk->hdev->dev, pcmidi_snd_terminate()
729 device_remove_file(&pm->pk->hdev->dev, pcmidi_snd_terminate()
732 snd_card_disconnect(pm->card); pcmidi_snd_terminate()
733 snd_card_free_when_closed(pm->card); pcmidi_snd_terminate()
761 struct pcmidi_snd *pm; pk_input_mapping() local
763 pm = pk->pm; pk_input_mapping()
766 1 == pm->ifnum) { pk_input_mapping()
767 pcmidi_setup_extra_keys(pm, hi->input); pk_input_mapping()
781 if (1 == pk->pm->ifnum) { pk_raw_event()
787 ret = pcmidi_handle_report(pk->pm, pk_raw_event()
803 struct pcmidi_snd *pm = NULL; pk_probe() local
813 pm = kzalloc(sizeof(*pm), GFP_KERNEL); pk_probe()
814 if (pm == NULL) { pk_probe()
820 pm->pk = pk; pk_probe()
821 pk->pm = pm; pk_probe()
822 pm->ifnum = ifnum; pk_probe()
842 ret = pcmidi_snd_initialise(pm); pk_probe()
850 kfree(pm); pk_probe()
860 struct pcmidi_snd *pm; pk_remove() local
862 pm = pk->pm; pk_remove()
863 if (pm) { pk_remove()
864 pcmidi_snd_terminate(pm); pk_remove()
865 kfree(pm); pk_remove()
499 pcmidi_handle_report( struct pcmidi_snd *pm, unsigned report_id, u8 *data, int size) pcmidi_handle_report() argument
518 pcmidi_setup_extra_keys( struct pcmidi_snd *pm, struct input_dev *input) pcmidi_setup_extra_keys() argument
/linux-4.1.27/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_packet_manager.c53 static void pm_calc_rlib_size(struct packet_manager *pm, pm_calc_rlib_size() argument
59 BUG_ON(!pm || !rlib_size || !over_subscription); pm_calc_rlib_size()
61 process_count = pm->dqm->processes_count; pm_calc_rlib_size()
62 queue_count = pm->dqm->queue_count; pm_calc_rlib_size()
86 static int pm_allocate_runlist_ib(struct packet_manager *pm, pm_allocate_runlist_ib() argument
94 BUG_ON(!pm); pm_allocate_runlist_ib()
95 BUG_ON(pm->allocated == true); pm_allocate_runlist_ib()
98 pm_calc_rlib_size(pm, rl_buffer_size, is_over_subscription); pm_allocate_runlist_ib()
100 retval = kfd_gtt_sa_allocate(pm->dqm->dev, *rl_buffer_size, pm_allocate_runlist_ib()
101 &pm->ib_buffer_obj); pm_allocate_runlist_ib()
108 *(void **)rl_buffer = pm->ib_buffer_obj->cpu_ptr; pm_allocate_runlist_ib()
109 *rl_gpu_buffer = pm->ib_buffer_obj->gpu_addr; pm_allocate_runlist_ib()
112 pm->allocated = true; pm_allocate_runlist_ib()
116 static int pm_create_runlist(struct packet_manager *pm, uint32_t *buffer, pm_create_runlist() argument
121 BUG_ON(!pm || !buffer || !ib); pm_create_runlist()
139 static int pm_create_map_process(struct packet_manager *pm, uint32_t *buffer, pm_create_map_process() argument
146 BUG_ON(!pm || !buffer || !qpd); pm_create_map_process()
179 static int pm_create_map_queue(struct packet_manager *pm, uint32_t *buffer, pm_create_map_queue() argument
184 BUG_ON(!pm || !buffer || !q); pm_create_map_queue()
236 static int pm_create_runlist_ib(struct packet_manager *pm, pm_create_runlist_ib() argument
250 BUG_ON(!pm || !queues || !rl_size_bytes || !rl_gpu_addr); pm_create_runlist_ib()
254 retval = pm_allocate_runlist_ib(pm, &rl_buffer, rl_gpu_addr, pm_create_runlist_ib()
263 pm->dqm->processes_count, pm->dqm->queue_count); pm_create_runlist_ib()
269 if (proccesses_mapped >= pm->dqm->processes_count) { list_for_each_entry()
271 pm_release_ib(pm); list_for_each_entry()
274 retval = pm_create_map_process(pm, &rl_buffer[rl_wptr], qpd); list_for_each_entry()
284 retval = pm_create_map_queue(pm, &rl_buffer[rl_wptr], list_for_each_entry()
295 retval = pm_create_map_queue(pm, list_for_each_entry()
307 pm_create_runlist(pm, &rl_buffer[rl_wptr], *rl_gpu_addr,
317 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm) pm_init() argument
321 pm->dqm = dqm; pm_init()
322 mutex_init(&pm->lock); pm_init()
323 pm->priv_queue = kernel_queue_init(dqm->dev, KFD_QUEUE_TYPE_HIQ); pm_init()
324 if (pm->priv_queue == NULL) { pm_init()
325 mutex_destroy(&pm->lock); pm_init()
328 pm->allocated = false; pm_init()
333 void pm_uninit(struct packet_manager *pm) pm_uninit() argument
335 BUG_ON(!pm); pm_uninit()
337 mutex_destroy(&pm->lock); pm_uninit()
338 kernel_queue_uninit(pm->priv_queue); pm_uninit()
341 int pm_send_set_resources(struct packet_manager *pm, pm_send_set_resources() argument
346 BUG_ON(!pm || !res); pm_send_set_resources()
350 mutex_lock(&pm->lock); pm_send_set_resources()
351 pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue, pm_send_set_resources()
355 mutex_unlock(&pm->lock); pm_send_set_resources()
378 pm->priv_queue->ops.submit_packet(pm->priv_queue); pm_send_set_resources()
380 mutex_unlock(&pm->lock); pm_send_set_resources()
385 int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues) pm_send_runlist() argument
392 BUG_ON(!pm || !dqm_queues); pm_send_runlist()
394 retval = pm_create_runlist_ib(pm, dqm_queues, &rl_gpu_ib_addr, pm_send_runlist()
402 mutex_lock(&pm->lock); pm_send_runlist()
404 retval = pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue, pm_send_runlist()
409 retval = pm_create_runlist(pm, rl_buffer, rl_gpu_ib_addr, pm_send_runlist()
414 pm->priv_queue->ops.submit_packet(pm->priv_queue); pm_send_runlist()
416 mutex_unlock(&pm->lock); pm_send_runlist()
421 pm->priv_queue->ops.rollback_packet(pm->priv_queue); pm_send_runlist()
423 mutex_unlock(&pm->lock); pm_send_runlist()
425 if (pm->allocated == true) pm_send_runlist()
426 pm_release_ib(pm); pm_send_runlist()
430 int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, pm_send_query_status() argument
436 BUG_ON(!pm || !fence_address); pm_send_query_status()
438 mutex_lock(&pm->lock); pm_send_query_status()
439 retval = pm->priv_queue->ops.acquire_packet_buffer( pm_send_query_status()
440 pm->priv_queue, pm_send_query_status()
460 pm->priv_queue->ops.submit_packet(pm->priv_queue); pm_send_query_status()
461 mutex_unlock(&pm->lock); pm_send_query_status()
466 mutex_unlock(&pm->lock); pm_send_query_status()
470 int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, pm_send_unmap_queue() argument
479 BUG_ON(!pm); pm_send_unmap_queue()
481 mutex_lock(&pm->lock); pm_send_unmap_queue()
482 retval = pm->priv_queue->ops.acquire_packet_buffer( pm_send_unmap_queue()
483 pm->priv_queue, pm_send_unmap_queue()
537 pm->priv_queue->ops.submit_packet(pm->priv_queue); pm_send_unmap_queue()
539 mutex_unlock(&pm->lock); pm_send_unmap_queue()
543 mutex_unlock(&pm->lock); pm_send_unmap_queue()
547 void pm_release_ib(struct packet_manager *pm) pm_release_ib() argument
549 BUG_ON(!pm); pm_release_ib()
551 mutex_lock(&pm->lock); pm_release_ib()
552 if (pm->allocated) { pm_release_ib()
553 kfd_gtt_sa_free(pm->dqm->dev, pm->ib_buffer_obj); pm_release_ib()
554 pm->allocated = false; pm_release_ib()
556 mutex_unlock(&pm->lock); pm_release_ib()
/linux-4.1.27/arch/sh/boards/mach-hp6xx/
H A DMakefile6 obj-$(CONFIG_PM) += pm.o pm_wakeup.o
/linux-4.1.27/arch/blackfin/mach-bf609/
H A DMakefile6 obj-$(CONFIG_PM) += pm.o dpm.o
/linux-4.1.27/arch/arm/mach-highbank/
H A DMakefile6 obj-$(CONFIG_PM_SLEEP) += pm.o
/linux-4.1.27/arch/arm/mach-mvebu/
H A DMakefile10 obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o pm.o pm-board.o
15 obj-$(CONFIG_MACH_KIRKWOOD) += kirkwood.o kirkwood-pm.o
/linux-4.1.27/sound/drivers/
H A Dportman2x4.c93 static int portman_free(struct portman *pm) portman_free() argument
95 kfree(pm); portman_free()
103 struct portman *pm; portman_create() local
107 pm = kzalloc(sizeof(struct portman), GFP_KERNEL); portman_create()
108 if (pm == NULL) portman_create()
112 spin_lock_init(&pm->reg_lock); portman_create()
113 pm->card = card; portman_create()
114 pm->pardev = pardev; portman_create()
116 *rchip = pm; portman_create()
196 static inline void portman_write_command(struct portman *pm, u8 value) portman_write_command() argument
198 parport_write_control(pm->pardev->port, value); portman_write_command()
201 static inline u8 portman_read_command(struct portman *pm) portman_read_command() argument
203 return parport_read_control(pm->pardev->port); portman_read_command()
206 static inline u8 portman_read_status(struct portman *pm) portman_read_status() argument
208 return parport_read_status(pm->pardev->port); portman_read_status()
211 static inline u8 portman_read_data(struct portman *pm) portman_read_data() argument
213 return parport_read_data(pm->pardev->port); portman_read_data()
216 static inline void portman_write_data(struct portman *pm, u8 value) portman_write_data() argument
218 parport_write_data(pm->pardev->port, value); portman_write_data()
221 static void portman_write_midi(struct portman *pm, portman_write_midi() argument
243 portman_write_command(pm, command); portman_write_midi()
249 portman_write_data(pm, mididata); portman_write_midi()
254 } while ((portman_read_status(pm) & TXEMPTY) != TXEMPTY); portman_write_midi()
261 portman_write_command(pm, command | STROBE); portman_write_midi()
268 while ((portman_read_status(pm) & ESTB) == 0) portman_write_midi()
272 portman_write_command(pm, command); portman_write_midi()
274 while ((portman_read_status(pm) & ESTB) == ESTB) portman_write_midi()
281 while ((portman_read_status(pm) & BUSY) == BUSY) portman_write_midi()
293 static int portman_read_midi(struct portman *pm, int port) portman_read_midi() argument
299 portman_write_data(pm, 0); /* Make sure edge is down. */ portman_read_midi()
303 portman_write_command(pm, cmdout); portman_read_midi()
305 while ((portman_read_status(pm) & ESTB) == ESTB) portman_read_midi()
311 if ((portman_read_status(pm) & RXAVAIL) == 0) portman_read_midi()
315 portman_write_command(pm, cmdout | STROBE); /* Write address+IE+Strobe. */ portman_read_midi()
317 while ((portman_read_status(pm) & ESTB) == 0) portman_read_midi()
321 midi_data = (portman_read_status(pm) & 128); portman_read_midi()
322 portman_write_data(pm, 1); /* Cause rising edge, which shifts data. */ portman_read_midi()
325 portman_write_data(pm, 0); /* Cause falling edge while data settles. */ portman_read_midi()
326 midi_data |= (portman_read_status(pm) >> 1) & 64; portman_read_midi()
327 portman_write_data(pm, 1); /* Cause rising edge, which shifts data. */ portman_read_midi()
330 portman_write_data(pm, 0); /* Cause falling edge while data settles. */ portman_read_midi()
331 midi_data |= (portman_read_status(pm) >> 2) & 32; portman_read_midi()
332 portman_write_data(pm, 1); /* Cause rising edge, which shifts data. */ portman_read_midi()
335 portman_write_data(pm, 0); /* Cause falling edge while data settles. */ portman_read_midi()
336 midi_data |= (portman_read_status(pm) >> 3) & 16; portman_read_midi()
337 portman_write_data(pm, 1); /* Cause rising edge, which shifts data. */ portman_read_midi()
340 portman_write_data(pm, 0); /* Cause falling edge while data settles. */ portman_read_midi()
341 midi_data |= (portman_read_status(pm) >> 4) & 8; portman_read_midi()
342 portman_write_data(pm, 1); /* Cause rising edge, which shifts data. */ portman_read_midi()
345 portman_write_data(pm, 0); /* Cause falling edge while data settles. */ portman_read_midi()
346 midi_data |= (portman_read_status(pm) >> 5) & 4; portman_read_midi()
347 portman_write_data(pm, 1); /* Cause rising edge, which shifts data. */ portman_read_midi()
350 portman_write_data(pm, 0); /* Cause falling edge while data settles. */ portman_read_midi()
351 midi_data |= (portman_read_status(pm) >> 6) & 2; portman_read_midi()
352 portman_write_data(pm, 1); /* Cause rising edge, which shifts data. */ portman_read_midi()
355 portman_write_data(pm, 0); /* Cause falling edge while data settles. */ portman_read_midi()
356 midi_data |= (portman_read_status(pm) >> 7) & 1; portman_read_midi()
357 portman_write_data(pm, 1); /* Cause rising edge, which shifts data. */ portman_read_midi()
358 portman_write_data(pm, 0); /* Return data clock low. */ portman_read_midi()
362 portman_write_command(pm, cmdout); /* Output saved address+IE. */ portman_read_midi()
365 while ((portman_read_status(pm) & ESTB) == ESTB) portman_read_midi()
375 static int portman_data_avail(struct portman *pm, int channel) portman_data_avail() argument
387 portman_write_command(pm, command); portman_data_avail()
389 if ((portman_read_status(pm) & RXAVAIL) == RXAVAIL) portman_data_avail()
400 static void portman_flush_input(struct portman *pm, unsigned char port) portman_flush_input() argument
421 portman_write_command(pm, command); portman_flush_input()
424 portman_write_command(pm, command | STROBE); portman_flush_input()
427 while ((portman_read_status(pm) & ESTB) == 0) portman_flush_input()
431 portman_write_data(pm, 0); portman_flush_input()
435 portman_write_data(pm, 1); portman_flush_input()
436 portman_write_data(pm, 0); portman_flush_input()
440 portman_write_command(pm, command | INT_EN); portman_flush_input()
443 while ((portman_read_status(pm) & ESTB) == ESTB) portman_flush_input()
501 static int portman_device_init(struct portman *pm) portman_device_init() argument
503 portman_flush_input(pm, 0); portman_device_init()
504 portman_flush_input(pm, 1); portman_device_init()
525 struct portman *pm = substream->rmidi->private_data; snd_portman_midi_input_trigger() local
528 spin_lock_irqsave(&pm->reg_lock, flags); snd_portman_midi_input_trigger()
530 pm->mode[substream->number] |= PORTMAN2X4_MODE_INPUT_TRIGGERED; snd_portman_midi_input_trigger()
532 pm->mode[substream->number] &= ~PORTMAN2X4_MODE_INPUT_TRIGGERED; snd_portman_midi_input_trigger()
533 spin_unlock_irqrestore(&pm->reg_lock, flags); snd_portman_midi_input_trigger()
539 struct portman *pm = substream->rmidi->private_data; snd_portman_midi_output_trigger() local
543 spin_lock_irqsave(&pm->reg_lock, flags); snd_portman_midi_output_trigger()
546 portman_write_midi(pm, substream->number, byte); snd_portman_midi_output_trigger()
548 spin_unlock_irqrestore(&pm->reg_lock, flags); snd_portman_midi_output_trigger()
566 struct portman *pm = card->private_data; snd_portman_rawmidi_create() local
578 rmidi->private_data = pm; snd_portman_rawmidi_create()
584 pm->rmidi = rmidi; snd_portman_rawmidi_create()
604 pm->midi_input[substream->number] = substream; snd_portman_rawmidi_create()
618 struct portman *pm = ((struct snd_card*)userdata)->private_data; snd_portman_interrupt() local
620 spin_lock(&pm->reg_lock); snd_portman_interrupt()
623 while ((portman_read_status(pm) & INT_REQ) == INT_REQ) { snd_portman_interrupt()
626 if (portman_data_avail(pm, 0)) { snd_portman_interrupt()
628 midivalue = portman_read_midi(pm, 0); snd_portman_interrupt()
630 if (pm->mode[0] & PORTMAN2X4_MODE_INPUT_TRIGGERED) snd_portman_interrupt()
631 snd_rawmidi_receive(pm->midi_input[0], snd_portman_interrupt()
637 if (portman_data_avail(pm, 1)) { snd_portman_interrupt()
639 midivalue = portman_read_midi(pm, 1); snd_portman_interrupt()
641 if (pm->mode[1] & PORTMAN2X4_MODE_INPUT_TRIGGERED) snd_portman_interrupt()
642 snd_rawmidi_receive(pm->midi_input[1], snd_portman_interrupt()
648 spin_unlock(&pm->reg_lock); snd_portman_interrupt()
719 struct portman *pm = card->private_data; snd_portman_card_private_free() local
720 struct pardevice *pardev = pm->pardev; snd_portman_card_private_free()
723 if (pm->pardev_claimed) snd_portman_card_private_free()
728 portman_free(pm); snd_portman_card_private_free()
737 struct portman *pm = NULL; snd_portman_probe() local
775 if ((err = portman_create(card, pardev, &pm)) < 0) { snd_portman_probe()
780 card->private_data = pm; snd_portman_probe()
794 pm->pardev_claimed = 1; snd_portman_probe()
797 if ((err = portman_device_init(pm)) < 0) snd_portman_probe()
/linux-4.1.27/drivers/scsi/
H A Dscsi_pm.c21 static int do_scsi_suspend(struct device *dev, const struct dev_pm_ops *pm) do_scsi_suspend() argument
23 return pm && pm->suspend ? pm->suspend(dev) : 0; do_scsi_suspend()
26 static int do_scsi_freeze(struct device *dev, const struct dev_pm_ops *pm) do_scsi_freeze() argument
28 return pm && pm->freeze ? pm->freeze(dev) : 0; do_scsi_freeze()
31 static int do_scsi_poweroff(struct device *dev, const struct dev_pm_ops *pm) do_scsi_poweroff() argument
33 return pm && pm->poweroff ? pm->poweroff(dev) : 0; do_scsi_poweroff()
36 static int do_scsi_resume(struct device *dev, const struct dev_pm_ops *pm) do_scsi_resume() argument
38 return pm && pm->resume ? pm->resume(dev) : 0; do_scsi_resume()
41 static int do_scsi_thaw(struct device *dev, const struct dev_pm_ops *pm) do_scsi_thaw() argument
43 return pm && pm->thaw ? pm->thaw(dev) : 0; do_scsi_thaw()
46 static int do_scsi_restore(struct device *dev, const struct dev_pm_ops *pm) do_scsi_restore() argument
48 return pm && pm->restore ? pm->restore(dev) : 0; do_scsi_restore()
54 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; scsi_dev_type_suspend() local
62 err = cb(dev, pm); scsi_dev_type_suspend()
73 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; scsi_dev_type_resume() local
76 err = cb(dev, pm); scsi_dev_type_resume()
218 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; sdev_runtime_suspend() local
222 if (pm && pm->runtime_suspend) { sdev_runtime_suspend()
226 err = pm->runtime_suspend(dev); sdev_runtime_suspend()
248 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; sdev_runtime_resume() local
251 if (pm && pm->runtime_resume) { sdev_runtime_resume()
253 err = pm->runtime_resume(dev); sdev_runtime_resume()
/linux-4.1.27/fs/hfs/
H A Dpart_tbl.c73 struct old_pmap *pm; hfs_part_find() local
76 pm = (struct old_pmap *)bh->b_data; hfs_part_find()
77 p = pm->pdEntry; hfs_part_find()
92 struct new_pmap *pm; hfs_part_find() local
94 pm = (struct new_pmap *)bh->b_data; hfs_part_find()
95 size = be32_to_cpu(pm->pmMapBlkCnt); hfs_part_find()
97 if (!memcmp(pm->pmPartType,"Apple_HFS", 9) && hfs_part_find()
99 *part_start += be32_to_cpu(pm->pmPyPartStart); hfs_part_find()
100 *part_size = be32_to_cpu(pm->pmPartBlkCnt); hfs_part_find()
105 bh = sb_bread512(sb, *part_start + HFS_PMAP_BLK + ++i, pm); hfs_part_find()
108 if (pm->pmSig != cpu_to_be16(HFS_NEW_PMAP_MAGIC)) hfs_part_find()
/linux-4.1.27/drivers/net/wireless/cw1200/
H A DMakefile12 cw1200_core-$(CONFIG_PM) += pm.o
H A Dpm.h29 int cw1200_pm_init(struct cw1200_pm_state *pm,
31 void cw1200_pm_deinit(struct cw1200_pm_state *pm);
36 void cw1200_pm_stay_awake(struct cw1200_pm_state *pm,
39 static inline void cw1200_pm_stay_awake(struct cw1200_pm_state *pm, cw1200_pm_stay_awake() argument
H A Dpm.c15 #include "pm.h"
99 int cw1200_pm_init(struct cw1200_pm_state *pm, cw1200_pm_init() argument
102 spin_lock_init(&pm->lock); cw1200_pm_init()
104 setup_timer(&pm->stay_awake, cw1200_pm_stay_awake_tmo, cw1200_pm_init()
105 (unsigned long)pm); cw1200_pm_init()
110 void cw1200_pm_deinit(struct cw1200_pm_state *pm) cw1200_pm_deinit() argument
112 del_timer_sync(&pm->stay_awake); cw1200_pm_deinit()
115 void cw1200_pm_stay_awake(struct cw1200_pm_state *pm, cw1200_pm_stay_awake() argument
119 spin_lock_bh(&pm->lock); cw1200_pm_stay_awake()
120 cur_tmo = pm->stay_awake.expires - jiffies; cw1200_pm_stay_awake()
121 if (!timer_pending(&pm->stay_awake) || cur_tmo < (long)tmo) cw1200_pm_stay_awake()
122 mod_timer(&pm->stay_awake, jiffies + tmo); cw1200_pm_stay_awake()
123 spin_unlock_bh(&pm->lock); cw1200_pm_stay_awake()
/linux-4.1.27/arch/blackfin/mach-common/
H A DMakefile9 obj-$(CONFIG_PM) += pm.o
/linux-4.1.27/kernel/irq/
H A DMakefile8 obj-$(CONFIG_PM_SLEEP) += pm.o
/linux-4.1.27/arch/frv/kernel/
H A DMakefile18 obj-$(CONFIG_PM) += pm.o cmode.o
19 obj-$(CONFIG_MB93093_PDK) += pm-mb93093.o
H A Dpm-mb93093.c14 #include <linux/pm.h>
/linux-4.1.27/arch/powerpc/kernel/
H A Dibmebus.c446 if (drv && drv->pm && drv->pm->prepare) ibmebus_bus_pm_prepare()
447 ret = drv->pm->prepare(dev); ibmebus_bus_pm_prepare()
456 if (drv && drv->pm && drv->pm->complete) ibmebus_bus_pm_complete()
457 drv->pm->complete(dev); ibmebus_bus_pm_complete()
470 if (drv->pm) { ibmebus_bus_pm_suspend()
471 if (drv->pm->suspend) ibmebus_bus_pm_suspend()
472 ret = drv->pm->suspend(dev); ibmebus_bus_pm_suspend()
488 if (drv->pm) { ibmebus_bus_pm_suspend_noirq()
489 if (drv->pm->suspend_noirq) ibmebus_bus_pm_suspend_noirq()
490 ret = drv->pm->suspend_noirq(dev); ibmebus_bus_pm_suspend_noirq()
504 if (drv->pm) { ibmebus_bus_pm_resume()
505 if (drv->pm->resume) ibmebus_bus_pm_resume()
506 ret = drv->pm->resume(dev); ibmebus_bus_pm_resume()
522 if (drv->pm) { ibmebus_bus_pm_resume_noirq()
523 if (drv->pm->resume_noirq) ibmebus_bus_pm_resume_noirq()
524 ret = drv->pm->resume_noirq(dev); ibmebus_bus_pm_resume_noirq()
549 if (drv->pm) { ibmebus_bus_pm_freeze()
550 if (drv->pm->freeze) ibmebus_bus_pm_freeze()
551 ret = drv->pm->freeze(dev); ibmebus_bus_pm_freeze()
567 if (drv->pm) { ibmebus_bus_pm_freeze_noirq()
568 if (drv->pm->freeze_noirq) ibmebus_bus_pm_freeze_noirq()
569 ret = drv->pm->freeze_noirq(dev); ibmebus_bus_pm_freeze_noirq()
583 if (drv->pm) { ibmebus_bus_pm_thaw()
584 if (drv->pm->thaw) ibmebus_bus_pm_thaw()
585 ret = drv->pm->thaw(dev); ibmebus_bus_pm_thaw()
601 if (drv->pm) { ibmebus_bus_pm_thaw_noirq()
602 if (drv->pm->thaw_noirq) ibmebus_bus_pm_thaw_noirq()
603 ret = drv->pm->thaw_noirq(dev); ibmebus_bus_pm_thaw_noirq()
617 if (drv->pm) { ibmebus_bus_pm_poweroff()
618 if (drv->pm->poweroff) ibmebus_bus_pm_poweroff()
619 ret = drv->pm->poweroff(dev); ibmebus_bus_pm_poweroff()
635 if (drv->pm) { ibmebus_bus_pm_poweroff_noirq()
636 if (drv->pm->poweroff_noirq) ibmebus_bus_pm_poweroff_noirq()
637 ret = drv->pm->poweroff_noirq(dev); ibmebus_bus_pm_poweroff_noirq()
651 if (drv->pm) { ibmebus_bus_pm_restore()
652 if (drv->pm->restore) ibmebus_bus_pm_restore()
653 ret = drv->pm->restore(dev); ibmebus_bus_pm_restore()
669 if (drv->pm) { ibmebus_bus_pm_restore_noirq()
670 if (drv->pm->restore_noirq) ibmebus_bus_pm_restore_noirq()
671 ret = drv->pm->restore_noirq(dev); ibmebus_bus_pm_restore_noirq()
724 .pm = IBMEBUS_BUS_PM_OPS_PTR,
/linux-4.1.27/arch/arm/mach-shmobile/
H A DMakefile9 obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o pm-sh73a0.o
11 obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o
13 obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o
49 obj-$(CONFIG_PM_RCAR) += pm-rcar.o
50 obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o
51 obj-$(CONFIG_ARCH_RCAR_GEN2) += pm-rcar-gen2.o
H A Dsuspend.c11 #include <linux/pm.h>
H A Dpm-r8a7779.c12 #include <linux/pm.h>
26 #include "pm-rcar.h"
H A Dpm-rmobile.c8 * based on pm-sh7372.c
21 #include <linux/pm.h>
27 #include "pm-rmobile.h"
407 pmd = of_get_child_by_name(np, "pm-domains"); rmobile_init_pm_domains()
409 pr_warn("%s lacks pm-domains node\n", np->full_name); rmobile_init_pm_domains()
H A Dsmp-r8a7790.c25 #include "pm-rcar.h"
/linux-4.1.27/drivers/pci/
H A Dpci-driver.c645 WARN(ret && drv->driver.pm, "driver %s device %04x:%04x\n", pci_has_legacy_pm_support()
664 if (drv && drv->pm && drv->pm->prepare) { pci_pm_prepare()
665 int error = drv->pm->prepare(dev); pci_pm_prepare()
684 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pci_pm_suspend() local
689 if (!pm) { pci_pm_suspend()
705 if (pm->suspend) { pci_pm_suspend()
709 error = pm->suspend(dev); pci_pm_suspend()
710 suspend_report_result(pm->suspend, error); pci_pm_suspend()
718 pm->suspend); pci_pm_suspend()
731 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pci_pm_suspend_noirq() local
736 if (!pm) { pci_pm_suspend_noirq()
741 if (pm->suspend_noirq) { pci_pm_suspend_noirq()
745 error = pm->suspend_noirq(dev); pci_pm_suspend_noirq()
746 suspend_report_result(pm->suspend_noirq, error); pci_pm_suspend_noirq()
754 pm->suspend_noirq); pci_pm_suspend_noirq()
796 if (drv && drv->pm && drv->pm->resume_noirq) pci_pm_resume_noirq()
797 error = drv->pm->resume_noirq(dev); pci_pm_resume_noirq()
805 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pci_pm_resume() local
820 if (pm) { pci_pm_resume()
821 if (pm->resume) pci_pm_resume()
822 error = pm->resume(dev); pci_pm_resume()
851 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pci_pm_freeze() local
856 if (!pm) { pci_pm_freeze()
870 if (pm->freeze) { pci_pm_freeze()
873 error = pm->freeze(dev); pci_pm_freeze()
874 suspend_report_result(pm->freeze, error); pci_pm_freeze()
893 if (drv && drv->pm && drv->pm->freeze_noirq) { pci_pm_freeze_noirq()
896 error = drv->pm->freeze_noirq(dev); pci_pm_freeze_noirq()
897 suspend_report_result(drv->pm->freeze_noirq, error); pci_pm_freeze_noirq()
930 if (drv && drv->pm && drv->pm->thaw_noirq) pci_pm_thaw_noirq()
931 error = drv->pm->thaw_noirq(dev); pci_pm_thaw_noirq()
939 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pci_pm_thaw() local
951 if (pm) { pci_pm_thaw()
952 if (pm->thaw) pci_pm_thaw()
953 error = pm->thaw(dev); pci_pm_thaw()
966 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pci_pm_poweroff() local
971 if (!pm) { pci_pm_poweroff()
980 if (pm->poweroff) { pci_pm_poweroff()
983 error = pm->poweroff(dev); pci_pm_poweroff()
984 suspend_report_result(pm->poweroff, error); pci_pm_poweroff()
1006 if (!drv || !drv->pm) { pci_pm_poweroff_noirq()
1011 if (drv->pm->poweroff_noirq) { pci_pm_poweroff_noirq()
1014 error = drv->pm->poweroff_noirq(dev); pci_pm_poweroff_noirq()
1015 suspend_report_result(drv->pm->poweroff_noirq, error); pci_pm_poweroff_noirq()
1055 if (drv && drv->pm && drv->pm->restore_noirq) pci_pm_restore_noirq()
1056 error = drv->pm->restore_noirq(dev); pci_pm_restore_noirq()
1064 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pci_pm_restore() local
1085 if (pm) { pci_pm_restore()
1086 if (pm->restore) pci_pm_restore()
1087 error = pm->restore(dev); pci_pm_restore()
1113 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pci_pm_runtime_suspend() local
1124 if (!pm || !pm->runtime_suspend) pci_pm_runtime_suspend()
1129 error = pm->runtime_suspend(dev); pci_pm_runtime_suspend()
1130 suspend_report_result(pm->runtime_suspend, error); pci_pm_runtime_suspend()
1142 pm->runtime_suspend); pci_pm_runtime_suspend()
1158 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pci_pm_runtime_resume() local
1167 if (!pm || !pm->runtime_resume) pci_pm_runtime_resume()
1175 rc = pm->runtime_resume(dev); pci_pm_runtime_resume()
1185 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; pci_pm_runtime_idle() local
1195 if (!pm) pci_pm_runtime_idle()
1198 if (pm->runtime_idle) pci_pm_runtime_idle()
1199 ret = pm->runtime_idle(dev); pci_pm_runtime_idle()
1407 .pm = PCI_PM_OPS_PTR,
/linux-4.1.27/fs/hfsplus/
H A Dpart_tbl.c70 static int hfs_parse_old_pmap(struct super_block *sb, struct old_pmap *pm, hfs_parse_old_pmap() argument
77 struct old_pmap_entry *p = &pm->pdEntry[i]; hfs_parse_old_pmap()
92 struct new_pmap *pm, sector_t *part_start, sector_t *part_size) hfs_parse_new_pmap()
95 int size = be32_to_cpu(pm->pmMapBlkCnt); hfs_parse_new_pmap()
101 if (!memcmp(pm->pmPartType, "Apple_HFS", 9) && hfs_parse_new_pmap()
103 *part_start += be32_to_cpu(pm->pmPyPartStart); hfs_parse_new_pmap()
104 *part_size = be32_to_cpu(pm->pmPartBlkCnt); hfs_parse_new_pmap()
111 pm = (struct new_pmap *)((u8 *)pm + HFSPLUS_SECTOR_SIZE); hfs_parse_new_pmap()
112 if ((u8 *)pm - (u8 *)buf >= buf_size) { hfs_parse_new_pmap()
115 buf, (void **)&pm, READ); hfs_parse_new_pmap()
119 } while (pm->pmSig == cpu_to_be16(HFS_NEW_PMAP_MAGIC)); hfs_parse_new_pmap()
91 hfs_parse_new_pmap(struct super_block *sb, void *buf, struct new_pmap *pm, sector_t *part_start, sector_t *part_size) hfs_parse_new_pmap() argument
/linux-4.1.27/drivers/ide/
H A Dide-pm.c83 struct request_pm_state *pm = rq->special; ide_complete_power_step() local
87 drive->name, pm->pm_step); ide_complete_power_step()
92 switch (pm->pm_step) { ide_complete_power_step()
94 if (pm->pm_state == PM_EVENT_FREEZE) ide_complete_power_step()
95 pm->pm_step = IDE_PM_COMPLETED; ide_complete_power_step()
97 pm->pm_step = IDE_PM_STANDBY; ide_complete_power_step()
100 pm->pm_step = IDE_PM_COMPLETED; ide_complete_power_step()
103 pm->pm_step = IDE_PM_IDLE; ide_complete_power_step()
106 pm->pm_step = IDE_PM_RESTORE_DMA; ide_complete_power_step()
113 struct request_pm_state *pm = rq->special; ide_start_power_step() local
116 switch (pm->pm_step) { ide_start_power_step()
140 pm->pm_step = IDE_PM_RESTORE_DMA; ide_start_power_step()
162 pm->pm_step = IDE_PM_COMPLETED; ide_start_power_step()
185 struct request_pm_state *pm = rq->special; ide_complete_pm_rq() local
189 if (pm->pm_step != IDE_PM_COMPLETED) ide_complete_pm_rq()
211 struct request_pm_state *pm = rq->special; ide_check_pm_state() local
214 pm->pm_step == IDE_PM_START_SUSPEND) ide_check_pm_state()
218 pm->pm_step == IDE_PM_START_RESUME) { ide_check_pm_state()
/linux-4.1.27/arch/mips/mti-malta/
H A Dmalta-reset.c10 #include <linux/pm.h>
13 #include <asm/mach-malta/malta-pm.h>
H A DMakefile13 obj-$(CONFIG_MIPS_MALTA_PM) += malta-pm.o
H A Dmalta-pm.c16 #include <asm/mach-malta/malta-pm.h>
67 pr_warn("malta-pm: failed to find reference to PCI bus\n"); malta_pm_setup()
76 pr_warn("malta-pm: failed to find PIIX4 PM\n"); malta_pm_setup()
83 pr_warn("malta-pm: failed to request PM IO registers (%d)\n", malta_pm_setup()
/linux-4.1.27/arch/arm/mach-prima2/
H A Dpm.h2 * arch/arm/mach-prima2/pm.h
H A Dsleep.S13 #include "pm.h"
/linux-4.1.27/arch/arm/mach-ux500/
H A DMakefile5 obj-y := cpu.o id.o timer.o pm.o
H A Dpm_domains.c53 { .compatible = "stericsson,ux500-pm-domains", },
/linux-4.1.27/arch/arm/mach-at91/
H A DMakefile17 obj-$(CONFIG_PM) += pm.o
/linux-4.1.27/arch/arm/mach-imx/
H A DMakefile8 obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
11 obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
12 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
14 imx5-pm-$(CONFIG_PM) += pm-imx5.o
15 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o clk-cpu.o $(imx5-pm-y)
98 obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
/linux-4.1.27/net/mac80211/
H A Dmesh_ps.c148 * @pm: the power mode to set
152 enum nl80211_mesh_power_mode pm) ieee80211_mps_set_sta_local_pm()
156 if (sta->local_pm == pm) ieee80211_mps_set_sta_local_pm()
160 pm, sta->sta.addr); ieee80211_mps_set_sta_local_pm()
162 sta->local_pm = pm; ieee80211_mps_set_sta_local_pm()
190 enum nl80211_mesh_power_mode pm; ieee80211_mps_set_frame_flags() local
201 pm = sta->local_pm; ieee80211_mps_set_frame_flags()
203 pm = sdata->u.mesh.nonpeer_pm; ieee80211_mps_set_frame_flags()
205 if (pm == NL80211_MESH_POWER_ACTIVE) ieee80211_mps_set_frame_flags()
216 pm == NL80211_MESH_POWER_DEEP_SLEEP) || ieee80211_mps_set_frame_flags()
233 enum nl80211_mesh_power_mode pm; ieee80211_mps_sta_status_update() local
246 pm = sta->peer_pm; ieee80211_mps_sta_status_update()
248 pm = sta->nonpeer_pm; ieee80211_mps_sta_status_update()
250 do_buffer = (pm != NL80211_MESH_POWER_ACTIVE); ieee80211_mps_sta_status_update()
277 enum nl80211_mesh_power_mode pm; mps_set_sta_peer_pm() local
292 pm = NL80211_MESH_POWER_DEEP_SLEEP; mps_set_sta_peer_pm()
294 pm = NL80211_MESH_POWER_LIGHT_SLEEP; mps_set_sta_peer_pm()
296 pm = NL80211_MESH_POWER_ACTIVE; mps_set_sta_peer_pm()
299 if (sta->peer_pm == pm) mps_set_sta_peer_pm()
303 sta->sta.addr, pm); mps_set_sta_peer_pm()
305 sta->peer_pm = pm; mps_set_sta_peer_pm()
313 enum nl80211_mesh_power_mode pm; mps_set_sta_nonpeer_pm() local
316 pm = NL80211_MESH_POWER_DEEP_SLEEP; mps_set_sta_nonpeer_pm()
318 pm = NL80211_MESH_POWER_ACTIVE; mps_set_sta_nonpeer_pm()
320 if (sta->nonpeer_pm == pm) mps_set_sta_nonpeer_pm()
324 sta->sta.addr, pm); mps_set_sta_nonpeer_pm()
326 sta->nonpeer_pm = pm; mps_set_sta_nonpeer_pm()
151 ieee80211_mps_set_sta_local_pm(struct sta_info *sta, enum nl80211_mesh_power_mode pm) ieee80211_mps_set_sta_local_pm() argument
H A DMakefile50 mac80211-$(CONFIG_PM) += pm.o
/linux-4.1.27/arch/mips/pci/
H A Dpci-alchemy.c42 unsigned long pm[12]; member in struct:alchemy_pci_context
312 ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); alchemy_pci_suspend()
313 ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; alchemy_pci_suspend()
314 ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); alchemy_pci_suspend()
315 ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); alchemy_pci_suspend()
316 ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); alchemy_pci_suspend()
317 ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); alchemy_pci_suspend()
318 ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); alchemy_pci_suspend()
319 ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); alchemy_pci_suspend()
320 ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); alchemy_pci_suspend()
321 ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); alchemy_pci_suspend()
322 ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); alchemy_pci_suspend()
323 ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); alchemy_pci_suspend()
334 __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); alchemy_pci_resume()
335 __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); alchemy_pci_resume()
336 __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); alchemy_pci_resume()
337 __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); alchemy_pci_resume()
338 __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); alchemy_pci_resume()
339 __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); alchemy_pci_resume()
340 __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); alchemy_pci_resume()
341 __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV); alchemy_pci_resume()
342 __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM); alchemy_pci_resume()
343 __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR); alchemy_pci_resume()
344 __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT); alchemy_pci_resume()
346 __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG); alchemy_pci_resume()
/linux-4.1.27/drivers/gpio/
H A Dgpio-amd8111.c72 void __iomem *pm; member in struct:amd_gpio
84 agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) & amd_gpio_request()
98 iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset)); amd_gpio_free()
108 temp = ioread8(agp->pm + AMD_REG_GPIO(offset)); amd_gpio_set()
110 iowrite8(temp, agp->pm + AMD_REG_GPIO(offset)); amd_gpio_set()
121 temp = ioread8(agp->pm + AMD_REG_GPIO(offset)); amd_gpio_get()
135 temp = ioread8(agp->pm + AMD_REG_GPIO(offset)); amd_gpio_dirout()
137 iowrite8(temp, agp->pm + AMD_REG_GPIO(offset)); amd_gpio_dirout()
152 temp = ioread8(agp->pm + AMD_REG_GPIO(offset)); amd_gpio_dirin()
154 iowrite8(temp, agp->pm + AMD_REG_GPIO(offset)); amd_gpio_dirin()
215 gp.pm = ioport_map(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
216 if (!gp.pm) {
232 ioport_unmap(gp.pm);
243 ioport_unmap(gp.pm); amd_gpio_exit()
H A Dgpio-ml-ioh.c45 u32 pm; member in struct:ioh_reg_comn
134 u32 pm; ioh_gpio_direction_output() local
139 pm = ioread32(&chip->reg->regs[chip->ch].pm) & ioh_gpio_direction_output()
141 pm |= (1 << nr); ioh_gpio_direction_output()
142 iowrite32(pm, &chip->reg->regs[chip->ch].pm); ioh_gpio_direction_output()
159 u32 pm; ioh_gpio_direction_input() local
163 pm = ioread32(&chip->reg->regs[chip->ch].pm) & ioh_gpio_direction_input()
165 pm &= ~(1 << nr); ioh_gpio_direction_input()
166 iowrite32(pm, &chip->reg->regs[chip->ch].pm); ioh_gpio_direction_input()
184 ioread32(&chip->reg->regs[chip->ch].pm); ioh_gpio_save_reg_conf()
210 &chip->reg->regs[chip->ch].pm); ioh_gpio_restore_reg_conf()
H A Dgpio-pch.c43 u32 pm; member in struct:pch_regs
137 u32 pm; pch_gpio_direction_output() local
150 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); pch_gpio_direction_output()
151 pm |= (1 << nr); pch_gpio_direction_output()
152 iowrite32(pm, &chip->reg->pm); pch_gpio_direction_output()
162 u32 pm; pch_gpio_direction_input() local
166 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); pch_gpio_direction_input()
167 pm &= ~(1 << nr); pch_gpio_direction_input()
168 iowrite32(pm, &chip->reg->pm); pch_gpio_direction_input()
183 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm); pch_gpio_save_reg_conf()
202 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm); pch_gpio_restore_reg_conf()
/linux-4.1.27/drivers/isdn/hardware/eicon/
H A Ddsp_tst.h45 #define dsp_make_address_ex(pm, address) ((word)((pm) ? (address) : (address) + 0x4000))
/linux-4.1.27/drivers/bus/
H A Dsimple-pm-bus.c40 { .compatible = "simple-pm-bus", },
49 .name = "simple-pm-bus",
/linux-4.1.27/net/8021q/
H A Dvlan_netlink.c182 struct vlan_priority_tci_mapping *pm; vlan_fill_info() local
221 for (pm = vlan->egress_priority_map[i]; pm; vlan_fill_info()
222 pm = pm->next) { vlan_fill_info()
223 if (!pm->vlan_qos) vlan_fill_info()
226 m.from = pm->priority; vlan_fill_info()
227 m.to = (pm->vlan_qos >> 13) & 0x7; vlan_fill_info()
/linux-4.1.27/arch/unicore32/kernel/
H A DMakefile18 obj-$(CONFIG_PUV3_PM) += pm.o sleep.o
H A Dpm.c2 * linux/arch/unicore32/kernel/pm.c
21 #include <mach/pm.h>
115 printk(KERN_ERR "failed to alloc memory for pm save\n"); puv3_pm_init()
/linux-4.1.27/include/linux/
H A Dpm-trace.h5 #include <asm/pm-trace.h>
/linux-4.1.27/include/uapi/linux/
H A Dhdlc.h4 * Copyright (C) 1999-2005 Krzysztof Halasa <khc@pm.waw.pl>
/linux-4.1.27/arch/arm/mach-sa1100/
H A DMakefile38 obj-$(CONFIG_PM) += pm.o sleep.o
H A Dhackkit.c76 .pm = hackkit_uart_pm,
99 * @state: pm state
100 * @oldstate: old pm state
/linux-4.1.27/arch/arm/mach-exynos/
H A DMakefile14 obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm.o sleep.o
/linux-4.1.27/drivers/net/fddi/skfp/
H A Dsmtdef.c167 struct fddi_mib_p *pm ; smt_init_mib() local
253 pm = mib->p ; smt_init_mib()
263 pm->fddiPORTIndex = port+INDEX_PORT ; smt_init_mib()
264 pm->fddiPORTHardwarePresent = TRUE ; smt_init_mib()
266 pm->fddiPORTLer_Alarm = DEFAULT_LEM_ALARM ; smt_init_mib()
267 pm->fddiPORTLer_Cutoff = DEFAULT_LEM_CUTOFF ; smt_init_mib()
273 pm->fddiPORTRequestedPaths[1] = 0 ; smt_init_mib()
274 pm->fddiPORTRequestedPaths[2] = 0 ; smt_init_mib()
275 pm->fddiPORTRequestedPaths[3] = 0 ; smt_init_mib()
276 pm->fddiPORTAvailablePaths = MIB_PATH_P ; smt_init_mib()
277 pm->fddiPORTPMDClass = MIB_PMDCLASS_MULTI ; smt_init_mib()
278 pm++ ; smt_init_mib()
/linux-4.1.27/arch/arm/plat-samsung/
H A Dpm-gpio.c2 /* linux/arch/arm/plat-s3c/pm-gpio.c
25 #include <plat/pm.h>
315 struct samsung_gpio_pm *pm = ourchip->pm; samsung_pm_save_gpio() local
317 if (pm == NULL || pm->save == NULL) samsung_pm_save_gpio()
318 S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); samsung_pm_save_gpio()
320 pm->save(ourchip); samsung_pm_save_gpio()
361 struct samsung_gpio_pm *pm = ourchip->pm; samsung_pm_resume_gpio() local
363 if (pm == NULL || pm->resume == NULL) samsung_pm_resume_gpio()
364 S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); samsung_pm_resume_gpio()
366 pm->resume(ourchip); samsung_pm_resume_gpio()
H A Dpm-debug.c23 #include <plat/pm-common.h>
26 #include <plat/pm.h>
27 #include <mach/pm-core.h>
H A Dwakeup-mask.c20 #include <plat/pm.h>
H A Dpm.c1 /* linux/arch/arm/plat-s3c/pm.c
37 #include <plat/pm.h>
38 #include <mach/pm-core.h>
/linux-4.1.27/drivers/hwmon/
H A Dadt7x10.h5 #include <linux/pm.h>
H A Dadt7410.c69 .pm = ADT7X10_DEV_PM_OPS,
/linux-4.1.27/drivers/staging/iio/addac/
H A Dadt7316.h13 #include <linux/pm.h>
/linux-4.1.27/drivers/of/
H A Dof_net.c24 const char *pm; of_get_phy_mode() local
27 err = of_property_read_string(np, "phy-mode", &pm); of_get_phy_mode()
29 err = of_property_read_string(np, "phy-connection-type", &pm); of_get_phy_mode()
34 if (!strcasecmp(pm, phy_modes(i))) of_get_phy_mode()
H A Dof_mtd.c37 const char *pm; of_get_nand_ecc_mode() local
40 err = of_property_read_string(np, "nand-ecc-mode", &pm); of_get_nand_ecc_mode()
45 if (!strcasecmp(pm, nand_ecc_modes[i])) of_get_nand_ecc_mode()
/linux-4.1.27/arch/sparc/kernel/
H A Dreboot.c8 #include <linux/pm.h>
H A Dpmc.c11 #include <linux/pm.h>
/linux-4.1.27/drivers/usb/host/
H A Dohci-tmio.c80 u16 pm; tmio_write_pm() local
85 pm = CCR_PM_GKEN | CCR_PM_CKRNEN | tmio_write_pm()
88 tmio_iowrite16(pm, tmio->ccr + CCR_PM); tmio_write_pm()
97 u16 pm; tmio_stop_hc() local
99 pm = CCR_PM_GKEN | CCR_PM_CKRNEN; tmio_stop_hc()
104 pm |= CCR_PM_USBPW3; tmio_stop_hc()
106 pm |= CCR_PM_USBPW2; tmio_stop_hc()
108 pm |= CCR_PM_USBPW1; tmio_stop_hc()
114 tmio_iowrite16(pm, tmio->ccr + CCR_PM); tmio_stop_hc()
/linux-4.1.27/include/linux/platform_data/
H A Dsa11x0-serial.h21 void (*pm)(struct uart_port *, u_int, u_int); member in struct:sa1100_port_fns
/linux-4.1.27/arch/sh/include/asm/
H A Drtc.h13 #define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
/linux-4.1.27/arch/mips/mti-sead3/
H A Dsead3-reset.c9 #include <linux/pm.h>
/linux-4.1.27/arch/arm/mach-s3c24xx/
H A Dpm.c1 /* linux/arch/arm/plat-s3c24xx/pm.c
24 * Parts based on arch/arm/mach-pxa/pm.c
47 #include <plat/pm.h>
51 #define PFX "s3c24xx-pm: "
H A Dpm-s3c2416.c1 /* linux/arch/arm/mach-s3c2416/pm.c
22 #include <plat/pm.h>
H A Dsimtec-pm.c1 /* linux/arch/arm/plat-s3c24xx/pm-simtec.c
34 #include <plat/pm.h>
H A Dmach-s3c2416-dt.c27 #include <plat/pm.h>
H A Dpm-h1940.S1 /* linux/arch/arm/mach-s3c2410/pm-h1940.S
H A Dpm-s3c2412.c1 /* linux/arch/arm/mach-s3c2412/pm.c
31 #include <plat/pm.h>
H A Ds3c2440.c37 #include <plat/pm.h>
H A Ds3c2442.c47 #include <plat/pm.h>
/linux-4.1.27/arch/arm/mach-s5pv210/
H A Dpm.c1 /* linux/arch/arm/mach-s5pv210/pm.c
8 * Based on arch/arm/mach-s3c2410/pm.c
25 #include <plat/pm-common.h>
47 /* issue the standby signal into the pm unit. Note, we s5pv210_cpu_suspend()
/linux-4.1.27/arch/arc/kernel/
H A Dreset.c12 #include <linux/pm.h>
/linux-4.1.27/kernel/power/
H A Dpoweroff.c10 #include <linux/pm.h>
/linux-4.1.27/lib/
H A Dpm-notifier-error-inject.c26 dir = notifier_err_inject_init("pm", notifier_err_inject_dir, err_inject_init()
/linux-4.1.27/fs/proc/
H A Dtask_mmu.c997 struct pagemapread *pm) add_to_pagemap()
999 pm->buffer[pm->pos++] = *pme; add_to_pagemap()
1000 if (pm->pos >= pm->len) add_to_pagemap()
1008 struct pagemapread *pm = walk->private; pagemap_pte_hole() local
1014 pagemap_entry_t pme = make_pme(PM_NOT_PRESENT(pm->v2)); pagemap_pte_hole()
1024 err = add_to_pagemap(addr, &pme, pm); pagemap_pte_hole()
1034 pme.pme |= PM_STATUS2(pm->v2, __PM_SOFT_DIRTY); pagemap_pte_hole()
1036 err = add_to_pagemap(addr, &pme, pm); pagemap_pte_hole()
1045 static void pte_to_pagemap_entry(pagemap_entry_t *pme, struct pagemapread *pm, pte_to_pagemap_entry() argument
1071 *pme = make_pme(PM_NOT_PRESENT(pm->v2) | PM_STATUS2(pm->v2, flags2)); pte_to_pagemap_entry()
1080 *pme = make_pme(PM_PFRAME(frame) | PM_STATUS2(pm->v2, flags2) | flags); pte_to_pagemap_entry()
1084 static void thp_pmd_to_pagemap_entry(pagemap_entry_t *pme, struct pagemapread *pm, thp_pmd_to_pagemap_entry() argument
1094 | PM_STATUS2(pm->v2, pmd_flags2) | PM_PRESENT); thp_pmd_to_pagemap_entry()
1096 *pme = make_pme(PM_NOT_PRESENT(pm->v2) | PM_STATUS2(pm->v2, pmd_flags2)); thp_pmd_to_pagemap_entry()
1099 static inline void thp_pmd_to_pagemap_entry(pagemap_entry_t *pme, struct pagemapread *pm, thp_pmd_to_pagemap_entry() argument
1109 struct pagemapread *pm = walk->private; pagemap_pte_range() local
1128 thp_pmd_to_pagemap_entry(&pme, pm, *pmd, offset, pmd_flags2); pagemap_pte_range()
1129 err = add_to_pagemap(addr, &pme, pm); pagemap_pte_range()
1148 pte_to_pagemap_entry(&pme, pm, vma, addr, *pte); pagemap_pte_range()
1149 err = add_to_pagemap(addr, &pme, pm); pagemap_pte_range()
1161 static void huge_pte_to_pagemap_entry(pagemap_entry_t *pme, struct pagemapread *pm, huge_pte_to_pagemap_entry() argument
1166 PM_STATUS2(pm->v2, flags2) | huge_pte_to_pagemap_entry()
1169 *pme = make_pme(PM_NOT_PRESENT(pm->v2) | huge_pte_to_pagemap_entry()
1170 PM_STATUS2(pm->v2, flags2)); huge_pte_to_pagemap_entry()
1178 struct pagemapread *pm = walk->private; pagemap_hugetlb_range() local
1191 huge_pte_to_pagemap_entry(&pme, pm, *pte, offset, flags2); pagemap_hugetlb_range()
1192 err = add_to_pagemap(addr, &pme, pm); pagemap_hugetlb_range()
1232 struct pagemapread pm; pagemap_read() local
1253 pm.v2 = soft_dirty_cleared; pagemap_read()
1254 pm.len = (PAGEMAP_WALK_SIZE >> PAGE_SHIFT); pagemap_read()
1255 pm.buffer = kmalloc(pm.len * PM_ENTRY_BYTES, GFP_TEMPORARY); pagemap_read()
1257 if (!pm.buffer) pagemap_read()
1271 pagemap_walk.private = &pm; pagemap_read()
1285 * user buffer is tracked in "pm", and the walk pagemap_read()
1293 pm.pos = 0; pagemap_read()
1303 len = min(count, PM_ENTRY_BYTES * pm.pos); pagemap_read()
1304 if (copy_to_user(buf, pm.buffer, len)) { pagemap_read()
1319 kfree(pm.buffer); pagemap_read()
996 add_to_pagemap(unsigned long addr, pagemap_entry_t *pme, struct pagemapread *pm) add_to_pagemap() argument
/linux-4.1.27/drivers/misc/mei/
H A Dpci-txe.c161 * For not wake-able HW runtime pm framework mei_txe_probe()
163 * Use domain runtime pm callbacks instead. mei_txe_probe()
376 * mei_txe_set_pm_domain - fill and set pm domain structure for device
384 if (pdev->dev.bus && pdev->dev.bus->pm) { mei_txe_set_pm_domain()
385 dev->pg_domain.ops = *pdev->dev.bus->pm; mei_txe_set_pm_domain()
396 * mei_txe_unset_pm_domain - clean pm domain structure for device
402 /* stop using pm callbacks if any */ mei_txe_unset_pm_domain()
429 .driver.pm = MEI_TXE_PM_OPS,
H A Dpci-me.c218 * For not wake-able HW runtime pm framework mei_me_probe()
220 * Use domain runtime pm callbacks instead. mei_me_probe()
426 * mei_me_set_pm_domain - fill and set pm domain structure for device
434 if (pdev->dev.bus && pdev->dev.bus->pm) { mei_me_set_pm_domain()
435 dev->pg_domain.ops = *pdev->dev.bus->pm; mei_me_set_pm_domain()
446 * mei_me_unset_pm_domain - clean pm domain structure for device
452 /* stop using pm callbacks if any */ mei_me_unset_pm_domain()
478 .driver.pm = MEI_ME_PM_OPS,
/linux-4.1.27/drivers/ata/
H A Dahci_platform.c17 #include <linux/pm.h>
90 .pm = &ahci_pm_ops,
H A Dahci_da850.c12 #include <linux/pm.h>
113 .pm = &ahci_da850_pm_ops,
/linux-4.1.27/drivers/pnp/
H A Ddriver.c166 if (pnp_drv->driver.pm && pnp_drv->driver.pm->suspend) { __pnp_bus_suspend()
167 error = pnp_drv->driver.pm->suspend(dev); __pnp_bus_suspend()
168 suspend_report_result(pnp_drv->driver.pm->suspend, error); __pnp_bus_suspend()
226 if (pnp_drv->driver.pm && pnp_drv->driver.pm->resume) { pnp_bus_resume()
227 error = pnp_drv->driver.pm->resume(dev); pnp_bus_resume()
258 .pm = &pnp_bus_dev_pm_ops,
/linux-4.1.27/arch/mips/kernel/
H A Dpm.c18 #include <asm/pm.h>
21 /* Used by PM helper macros in asm/pm.h */
H A Dreset.c11 #include <linux/pm.h>
H A DMakefile107 obj-$(CONFIG_CPU_PM) += pm.o
108 obj-$(CONFIG_MIPS_CPS_PM) += pm-cps.o
/linux-4.1.27/arch/arm/mach-s3c24xx/include/mach/
H A Dpm-core.h1 /* linux/arch/arm/mach-s3c2410/include/pm-core.h
7 * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c
/linux-4.1.27/sound/soc/codecs/
H A Dwmfw.h33 __le32 pm; member in struct:wmfw_adsp1_sizes
40 __le32 pm; member in struct:wmfw_adsp2_sizes
H A Dcs42xx8-i2c.c53 .pm = &cs42xx8_pm,
H A Dwm8804-i2c.c53 .pm = &wm8804_pm,
H A Dwm8804-spi.c46 .pm = &wm8804_pm,
/linux-4.1.27/arch/x86/platform/olpc/
H A Dolpc-xo1-pm.c18 #include <linux/pm.h>
26 #define DRV_NAME "olpc-xo1-pm"
144 else if (strcmp(pdev->name, "olpc-xo1-pm-acpi") == 0) xo1_pm_probe()
163 else if (strcmp(pdev->name, "olpc-xo1-pm-acpi") == 0) xo1_pm_remove()
180 .name = "olpc-xo1-pm-acpi",
/linux-4.1.27/arch/arm/mach-omap2/
H A DMakefile9 obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \
84 obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
90 omap-4-5-pm-common = pm44xx.o omap-mpuss-lowpower.o
91 obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
92 obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common)
93 obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-pm-common)
94 obj-$(CONFIG_PM_DEBUG) += pm-debug.o
H A Dpm-debug.c15 * Based on pm.c for omap2
33 #include "omap-pm.h"
38 #include "pm.h"
/linux-4.1.27/drivers/mtd/maps/
H A Dl440gx.c90 /* Setup the pm iobase resource init_l440gx()
97 pm_iobase->name = "pm iobase"; init_l440gx()
114 printk(KERN_WARNING "Could not allocate pm iobase resource\n"); init_l440gx()
/linux-4.1.27/drivers/power/reset/
H A Dat91-poweroff.c76 const char *pm; at91_poweroff_get_wakeup_mode() local
80 err = of_property_read_string(np, "atmel,wakeup-mode", &pm); at91_poweroff_get_wakeup_mode()
85 if (!strcasecmp(pm, shdwc_wakeup_modes[i])) at91_poweroff_get_wakeup_mode()
H A Dmsm-poweroff.c23 #include <linux/pm.h>
/linux-4.1.27/arch/arm/mach-davinci/
H A Dpm.c11 #include <linux/pm.h>
25 #include <mach/pm.h>
150 .name = "pm-davinci",
H A DMakefile39 obj-$(CONFIG_SUSPEND) += pm.o sleep.o
/linux-4.1.27/drivers/iio/common/hid-sensors/
H A Dhid-sensor-trigger.h22 #include <linux/pm.h>
/linux-4.1.27/drivers/pci/pcie/
H A Dportdrv_bus.c13 #include <linux/pm.h>
/linux-4.1.27/arch/x86/include/asm/
H A Dnmi.h5 #include <linux/pm.h>
H A Dtimer.h3 #include <linux/pm.h>
/linux-4.1.27/arch/sh/kernel/
H A Didle.c13 #include <linux/pm.h>
H A Dreboot.c1 #include <linux/pm.h>
/linux-4.1.27/arch/tile/kernel/
H A Dreboot.c18 #include <linux/pm.h>
/linux-4.1.27/arch/unicore32/include/mach/
H A Dpm.h2 * linux/arch/unicore/include/mach/pm.h
/linux-4.1.27/arch/mips/jz4740/
H A Dpm.c17 #include <linux/pm.h>
/linux-4.1.27/arch/mips/loongson1/common/
H A Dreset.c11 #include <linux/pm.h>
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A Dpm.h34 * accessing the LUBBOCK CPLD registers in arch/arm/mach-pxa/pm.c
/linux-4.1.27/arch/arm/mach-tegra/
H A Dpm-tegra20.c19 #include "pm.h"
H A Dpm-tegra30.c19 #include "pm.h"
H A Dcpuidle-tegra114.c28 #include "pm.h"
/linux-4.1.27/arch/arm/mach-mxs/
H A Dpm.c18 #include "pm.h"
/linux-4.1.27/sound/soc/au1x/
H A Ddb1000.c54 .pm = &snd_soc_pm_ops,
H A Dpsc.h24 unsigned long pm[2]; member in struct:au1xpsc_audio_data
/linux-4.1.27/include/linux/mmc/
H A Dpm.h2 * linux/include/linux/mmc/pm.h
/linux-4.1.27/drivers/net/wan/
H A Dhdlc_raw.c5 * Copyright (C) 1999 - 2006 Krzysztof Halasa <khc@pm.waw.pl>
112 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
H A Dhdlc_raw_eth.c5 * Copyright (C) 2002-2006 Krzysztof Halasa <khc@pm.waw.pl>
130 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
/linux-4.1.27/drivers/mfd/
H A Dwm831x-spi.c17 #include <linux/pm.h>
100 .pm = &wm831x_spi_pm,
H A Darizona.h18 #include <linux/pm.h>
/linux-4.1.27/drivers/ssb/
H A Dpcihost_wrapper.c14 #include <linux/pm.h>
129 driver->driver.pm = &ssb_pcihost_pm_ops; ssb_pcihost_register()
/linux-4.1.27/arch/arm/mach-pxa/
H A Dpm.c19 #include <mach/pm.h>
110 printk(KERN_ERR "failed to alloc memory for pm save\n"); pxa_pm_init()
/linux-4.1.27/arch/arm/mach-s3c64xx/
H A Dirq-pm.c1 /* arch/arm/plat-s3c64xx/irq-pm.c
32 #include <plat/pm.h>
H A Dpm.c1 /* linux/arch/arm/plat-s3c64xx/pm.c
26 #include <plat/pm.h>
244 /* since both s3c6400 and s3c6410 share the same sleep pm calls, we
268 /* issue the standby signal into the pm unit. Note, we s3c64xx_cpu_suspend()
/linux-4.1.27/arch/m68k/atari/
H A Dtime.c171 int pm = 0; atari_tt_hwclk() local
189 pm = 0x80; atari_tt_hwclk()
242 RTC_WRITE( RTC_HOURS, hour + pm); atari_tt_hwclk()
256 pm = 1; atari_tt_hwclk()
270 if (!pm && hour == 12) atari_tt_hwclk()
272 else if (pm && hour != 12) atari_tt_hwclk()
/linux-4.1.27/drivers/gpu/drm/i915/
H A Ddvo_ch7xxx.c249 uint8_t cdet, orig_pm, pm; ch7xxx_detect() local
253 pm = orig_pm; ch7xxx_detect()
254 pm &= ~CH7xxx_PM_FPD; ch7xxx_detect()
255 pm |= CH7xxx_PM_DVIL | CH7xxx_PM_DVIP; ch7xxx_detect()
257 ch7xxx_writeb(dvo, CH7xxx_PM, pm); ch7xxx_detect()
/linux-4.1.27/drivers/net/can/usb/peak_usb/
H A Dpcan_usb_pro.c102 static u8 *pcan_msg_init(struct pcan_usb_pro_msg *pm, void *buffer_addr, pcan_msg_init() argument
108 pm->u.rec_buffer = (u8 *)buffer_addr; pcan_msg_init()
109 pm->rec_buffer_size = pm->rec_buffer_len = buffer_size; pcan_msg_init()
110 pm->rec_ptr = pm->u.rec_buffer + PCAN_USBPRO_MSG_HEADER_LEN; pcan_msg_init()
112 return pm->rec_ptr; pcan_msg_init()
115 static u8 *pcan_msg_init_empty(struct pcan_usb_pro_msg *pm, pcan_msg_init_empty() argument
118 u8 *pr = pcan_msg_init(pm, buffer_addr, buffer_size); pcan_msg_init_empty()
121 pm->rec_buffer_len = PCAN_USBPRO_MSG_HEADER_LEN; pcan_msg_init_empty()
122 *pm->u.rec_cnt = 0; pcan_msg_init_empty()
130 static int pcan_msg_add_rec(struct pcan_usb_pro_msg *pm, u8 id, ...) pcan_msg_add_rec() argument
138 pc = pm->rec_ptr + 1; pcan_msg_add_rec()
193 len = pc - pm->rec_ptr; pcan_msg_add_rec()
195 *pm->u.rec_cnt = cpu_to_le32(le32_to_cpu(*pm->u.rec_cnt) + 1); pcan_msg_add_rec()
196 *pm->rec_ptr = id; pcan_msg_add_rec()
198 pm->rec_ptr = pc; pcan_msg_add_rec()
199 pm->rec_buffer_len += len; pcan_msg_add_rec()
/linux-4.1.27/drivers/base/
H A Dplatform.c883 if (drv->pm) { platform_pm_suspend()
884 if (drv->pm->suspend) platform_pm_suspend()
885 ret = drv->pm->suspend(dev); platform_pm_suspend()
901 if (drv->pm) { platform_pm_resume()
902 if (drv->pm->resume) platform_pm_resume()
903 ret = drv->pm->resume(dev); platform_pm_resume()
923 if (drv->pm) { platform_pm_freeze()
924 if (drv->pm->freeze) platform_pm_freeze()
925 ret = drv->pm->freeze(dev); platform_pm_freeze()
941 if (drv->pm) { platform_pm_thaw()
942 if (drv->pm->thaw) platform_pm_thaw()
943 ret = drv->pm->thaw(dev); platform_pm_thaw()
959 if (drv->pm) { platform_pm_poweroff()
960 if (drv->pm->poweroff) platform_pm_poweroff()
961 ret = drv->pm->poweroff(dev); platform_pm_poweroff()
977 if (drv->pm) { platform_pm_restore()
978 if (drv->pm->restore) platform_pm_restore()
979 ret = drv->pm->restore(dev); platform_pm_restore()
1000 .pm = &platform_dev_pm_ops,
/linux-4.1.27/drivers/spi/
H A Dspi-fsl-espi.c136 u8 pm; fsl_espi_setup_transfer() local
178 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4); fsl_espi_setup_transfer()
180 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. " fsl_espi_setup_transfer()
183 if (pm > 33) fsl_espi_setup_transfer()
184 pm = 33; fsl_espi_setup_transfer()
186 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4); fsl_espi_setup_transfer()
188 if (pm) fsl_espi_setup_transfer()
189 pm--; fsl_espi_setup_transfer()
190 if (pm < 2) fsl_espi_setup_transfer()
191 pm = 2; fsl_espi_setup_transfer()
193 cs->hw_mode |= CSMODE_PM(pm); fsl_espi_setup_transfer()
871 .pm = &espi_pm,
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Daddi_apci_1500.c59 unsigned int pm[2]; /* Pattern Mask */ member in struct:apci1500_private
308 z8536_write(dev, devpriv->pm[pa_trig] & 0xff, Z8536_PA_PM_REG); apci1500_di_inttrig_start()
313 z8536_write(dev, (devpriv->pm[pb_trig] >> 8) & 0xff, Z8536_PB_PM_REG); apci1500_di_inttrig_start()
318 if (devpriv->pm[pa_trig] & 0xff) { apci1500_di_inttrig_start()
337 if (devpriv->pm[pb_trig] & 0xff00) { apci1500_di_inttrig_start()
468 unsigned int pm = devpriv->pm[trig] & old_mask; apci1500_di_cfg_trig() local
486 pm = 0; apci1500_di_cfg_trig()
491 pm |= chan_mask; /* enable channels */ apci1500_di_cfg_trig()
497 pm |= chan_mask; /* enable channels */ apci1500_di_cfg_trig()
530 devpriv->pm[trig] = pm; apci1500_di_cfg_trig()
/linux-4.1.27/drivers/rtc/
H A Drtc-msm6242.c148 unsigned int pm = msm6242_read(priv, MSM6242_HOUR10) & msm6242_read_time() local
150 if (!pm && tm->tm_hour == 12) msm6242_read_time()
152 else if (pm && tm->tm_hour != 12) msm6242_read_time()
/linux-4.1.27/drivers/misc/lis3lv02d/
H A Dlis3lv02d_spi.c18 #include <linux/pm.h>
142 .pm = &lis3lv02d_spi_pm,
/linux-4.1.27/drivers/gpu/drm/bochs/
H A Dbochs_drv.c99 /* pm interface */
204 .driver.pm = &bochs_pm_ops,
/linux-4.1.27/drivers/input/keyboard/
H A Dipaq-micro-keys.c17 #include <linux/pm.h>
160 .pm = &micro_key_dev_pm_ops,
/linux-4.1.27/arch/arm/mach-s3c64xx/include/mach/
H A Dpm-core.h1 /* linux/arch/arm/mach-s3c64xx/include/mach/pm-core.h
8 * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
/linux-4.1.27/arch/arm/plat-samsung/include/plat/
H A Dpm.h1 /* arch/arm/plat-samsung/include/plat/pm.h
18 #include <plat/pm-common.h>
H A Dwakeup-mask.h30 * samsung_sync_wakemask - sync wakeup mask information for pm
/linux-4.1.27/tools/power/cpupower/debug/kernel/
H A Dcpufreq-test_tsc.c21 * linux-pm@vger.kernel.org
33 /*helper function to safely read acpi pm timesource*/ read_pmtmr()
/linux-4.1.27/drivers/crypto/ccp/
H A Dccp-ops.c1913 if (!ecc->u.pm.point_1.x || ccp_run_ecc_pm_cmd()
1914 (ecc->u.pm.point_1.x_len > CCP_ECC_MODULUS_BYTES) || ccp_run_ecc_pm_cmd()
1915 !ecc->u.pm.point_1.y || ccp_run_ecc_pm_cmd()
1916 (ecc->u.pm.point_1.y_len > CCP_ECC_MODULUS_BYTES)) ccp_run_ecc_pm_cmd()
1920 if (!ecc->u.pm.point_2.x || ccp_run_ecc_pm_cmd()
1921 (ecc->u.pm.point_2.x_len > CCP_ECC_MODULUS_BYTES) || ccp_run_ecc_pm_cmd()
1922 !ecc->u.pm.point_2.y || ccp_run_ecc_pm_cmd()
1923 (ecc->u.pm.point_2.y_len > CCP_ECC_MODULUS_BYTES)) ccp_run_ecc_pm_cmd()
1926 if (!ecc->u.pm.domain_a || ccp_run_ecc_pm_cmd()
1927 (ecc->u.pm.domain_a_len > CCP_ECC_MODULUS_BYTES)) ccp_run_ecc_pm_cmd()
1931 if (!ecc->u.pm.scalar || ccp_run_ecc_pm_cmd()
1932 (ecc->u.pm.scalar_len > CCP_ECC_MODULUS_BYTES)) ccp_run_ecc_pm_cmd()
1936 if (!ecc->u.pm.result.x || ccp_run_ecc_pm_cmd()
1937 (ecc->u.pm.result.x_len < CCP_ECC_MODULUS_BYTES) || ccp_run_ecc_pm_cmd()
1938 !ecc->u.pm.result.y || ccp_run_ecc_pm_cmd()
1939 (ecc->u.pm.result.y_len < CCP_ECC_MODULUS_BYTES)) ccp_run_ecc_pm_cmd()
1967 ccp_reverse_set_dm_area(&src, ecc->u.pm.point_1.x, ccp_run_ecc_pm_cmd()
1968 ecc->u.pm.point_1.x_len, ccp_run_ecc_pm_cmd()
1971 ccp_reverse_set_dm_area(&src, ecc->u.pm.point_1.y, ccp_run_ecc_pm_cmd()
1972 ecc->u.pm.point_1.y_len, ccp_run_ecc_pm_cmd()
1982 ccp_reverse_set_dm_area(&src, ecc->u.pm.point_2.x, ccp_run_ecc_pm_cmd()
1983 ecc->u.pm.point_2.x_len, ccp_run_ecc_pm_cmd()
1986 ccp_reverse_set_dm_area(&src, ecc->u.pm.point_2.y, ccp_run_ecc_pm_cmd()
1987 ecc->u.pm.point_2.y_len, ccp_run_ecc_pm_cmd()
1996 ccp_reverse_set_dm_area(&src, ecc->u.pm.domain_a, ccp_run_ecc_pm_cmd()
1997 ecc->u.pm.domain_a_len, ccp_run_ecc_pm_cmd()
2003 ccp_reverse_set_dm_area(&src, ecc->u.pm.scalar, ccp_run_ecc_pm_cmd()
2004 ecc->u.pm.scalar_len, ccp_run_ecc_pm_cmd()
2048 ccp_reverse_get_dm_area(&dst, ecc->u.pm.result.x, ccp_run_ecc_pm_cmd()
2051 ccp_reverse_get_dm_area(&dst, ecc->u.pm.result.y, ccp_run_ecc_pm_cmd()
/linux-4.1.27/drivers/mmc/host/
H A Ddw_mmc-k3.c89 .pm = &dw_mci_k3_pmops,
H A Dsdhci-cns3xxx.c104 .pm = SDHCI_PLTFM_PMOPS,
/linux-4.1.27/drivers/staging/iio/adc/
H A Dad7606_spi.c106 .pm = AD7606_SPI_PM_OPS,
/linux-4.1.27/drivers/staging/iio/magnetometer/
H A Dhmc5843_i2c.c93 .pm = HMC5843_PM_OPS,
H A Dhmc5843_spi.c88 .pm = HMC5843_PM_OPS,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/pm/
H A Dpriv.h3 #include <engine/pm.h>
/linux-4.1.27/drivers/hsi/clients/
H A Dnokia-modem.c32 static unsigned int pm = 1; variable
33 module_param(pm, int, 0400);
34 MODULE_PARM_DESC(pm,
188 if(pm) { nokia_modem_probe()
/linux-4.1.27/include/trace/events/
H A Drpm.h15 * runtime pm internal functions.
/linux-4.1.27/arch/s390/include/asm/
H A Dnmi.h38 __u32 pm : 1; /* 22 psw program mask and cc validity */ member in struct:mci
/linux-4.1.27/arch/sh/boards/mach-landisk/
H A Dsetup.c18 #include <linux/pm.h>
/linux-4.1.27/arch/mips/lantiq/falcon/
H A Dreset.c12 #include <linux/pm.h>
/linux-4.1.27/arch/mips/lasat/
H A Dreset.c21 #include <linux/pm.h>
/linux-4.1.27/arch/mips/loongson/common/
H A Dreset.c13 #include <linux/pm.h>
/linux-4.1.27/arch/mips/ralink/
H A Dreset.c11 #include <linux/pm.h>
/linux-4.1.27/arch/mips/sgi-ip27/
H A Dip27-reset.c18 #include <linux/pm.h>
/linux-4.1.27/arch/powerpc/include/asm/
H A Drtc.h42 #define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
/linux-4.1.27/arch/cris/kernel/
H A Dcrisksyms.c7 #include <linux/pm.h>
/linux-4.1.27/arch/m68k/include/asm/
H A Drtc.h28 #define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
/linux-4.1.27/arch/arm/mach-cns3xxx/
H A Ddevices.c20 #include "pm.h"
/linux-4.1.27/arch/arm/mach-dove/include/mach/
H A Dpm.h2 * arch/arm/mach-dove/include/mach/pm.h

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