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Searched refs:wr32 (Results 1 – 97 of 97) sorted by relevance

/linux-4.1.27/drivers/net/ethernet/intel/igb/
Digb_ptp.c145 wr32(E1000_SYSTIML, ts->tv_nsec); in igb_ptp_write_i210()
146 wr32(E1000_SYSTIMH, ts->tv_sec); in igb_ptp_write_i210()
224 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); in igb_ptp_adjfreq_82576()
250 wr32(E1000_TIMINCA, inca); in igb_ptp_adjfreq_82580()
403 wr32(E1000_TSSDP, tssdp); in igb_pin_extts()
404 wr32(E1000_CTRL, ctrl); in igb_pin_extts()
405 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_pin_extts()
455 wr32(E1000_TSSDP, tssdp); in igb_pin_perout()
456 wr32(E1000_CTRL, ctrl); in igb_pin_perout()
457 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_pin_perout()
[all …]
De1000_82575.c189 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_init_phy_params_82575()
472 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); in igb_set_sfp_media_type_82575()
518 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_set_sfp_media_type_82575()
640 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_get_invariants_82575()
846 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); in igb_get_phy_id_82575()
878 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_get_phy_id_82575()
1027 wr32(E1000_82580_PHY_POWER_MGMT, data); in igb_set_d0_lplu_state_82580()
1071 wr32(E1000_82580_PHY_POWER_MGMT, data); in igb_set_d3_lplu_state_82580()
1155 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_acquire_swfw_sync_82575()
1180 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_release_swfw_sync_82575()
[all …]
De1000_mac.c323 wr32(E1000_RAL(index), rar_low); in igb_rar_set()
325 wr32(E1000_RAH(index), rar_high); in igb_rar_set()
631 wr32(E1000_FCT, FLOW_CONTROL_TYPE); in igb_setup_link()
632 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); in igb_setup_link()
633 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); in igb_setup_link()
635 wr32(E1000_FCTTV, hw->fc.pause_time); in igb_setup_link()
661 wr32(E1000_TCTL, tctl); in igb_config_collision_dist()
695 wr32(E1000_FCRTL, fcrtl); in igb_set_fc_watermarks()
696 wr32(E1000_FCRTH, fcrth); in igb_set_fc_watermarks()
805 wr32(E1000_CTRL, ctrl); in igb_force_mac_fc()
[all …]
Digb_main.c598 wr32(E1000_I2CPARAMS, i2cctl); in igb_set_i2c_data()
623 wr32(E1000_I2CPARAMS, i2cctl); in igb_set_i2c_clk()
897 wr32(E1000_CTRL_EXT, tmp); in igb_configure_msix()
914 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | in igb_configure_msix()
922 wr32(E1000_IVAR_MISC, tmp); in igb_configure_msix()
1154 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); in igb_set_interrupt_capability()
1485 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1486 wr32(E1000_EIMC, adapter->eims_enable_mask); in igb_irq_disable()
1488 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1491 wr32(E1000_IAM, 0); in igb_irq_disable()
[all …]
De1000_i210.c84 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI); in igb_get_hw_semaphore_i210()
168 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_acquire_swfw_sync_i210()
192 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_release_swfw_sync_i210()
270 wr32(E1000_SRWR, eewr); in igb_write_nvm_srwr()
698 wr32(E1000_EECD, flup); in igb_update_flash_i210()
856 wr32(E1000_MDICNFG, reg_val); in igb_pll_workaround_i210()
877 wr32(E1000_CTRL, ctrl|E1000_CTRL_PHY_RST); in igb_pll_workaround_i210()
881 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_pll_workaround_i210()
883 wr32(E1000_WUC, 0); in igb_pll_workaround_i210()
885 wr32(E1000_EEARBC_I210, reg_val); in igb_pll_workaround_i210()
[all …]
De1000_nvm.c39 wr32(E1000_EECD, *eecd); in igb_raise_eec_clk()
54 wr32(E1000_EECD, *eecd); in igb_lower_eec_clk()
85 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
97 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
184 wr32(E1000_EECD, eecd | E1000_EECD_REQ); in igb_acquire_nvm()
197 wr32(E1000_EECD, eecd); in igb_acquire_nvm()
219 wr32(E1000_EECD, eecd); in igb_standby_nvm()
223 wr32(E1000_EECD, eecd); in igb_standby_nvm()
261 wr32(E1000_EECD, eecd); in igb_release_nvm()
282 wr32(E1000_EECD, eecd); in igb_ready_nvm_eeprom()
[all …]
De1000_mbx.c249 wr32(E1000_MBVFICR, mask); in igb_check_for_bit_pf()
307 wr32(E1000_VFLRE, (1 << vf_number)); in igb_check_for_rst_pf()
327 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_PFU); in igb_obtain_mbx_lock_pf()
366 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_STS); in igb_write_mbx_pf()
403 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_ACK); in igb_read_mbx_pf()
Digb_ethtool.c1204 wr32(reg, (_test[pat] & write)); in reg_pattern_test()
1224 wr32(reg, write & mask); in reg_set_and_check()
1288 wr32(E1000_STATUS, toggle); in igb_reg_test()
1298 wr32(E1000_STATUS, before); in igb_reg_test()
1416 wr32(E1000_IMC, ~0); in igb_intr_test()
1460 wr32(E1000_ICR, ~0); in igb_intr_test()
1462 wr32(E1000_IMC, mask); in igb_intr_test()
1463 wr32(E1000_ICS, mask); in igb_intr_test()
1482 wr32(E1000_ICR, ~0); in igb_intr_test()
1484 wr32(E1000_IMS, mask); in igb_intr_test()
[all …]
De1000_regs.h372 #define wr32(reg, val) \ macro
384 wr32((reg) + ((offset) << 2), (value))
De1000_phy.c155 wr32(E1000_MDIC, mdic); in igb_read_phy_reg_mdic()
212 wr32(E1000_MDIC, mdic); in igb_write_phy_reg_mdic()
261 wr32(E1000_I2CCMD, i2ccmd); in igb_read_phy_reg_i2c()
318 wr32(E1000_I2CCMD, i2ccmd); in igb_write_phy_reg_i2c()
370 wr32(E1000_I2CCMD, i2ccmd); in igb_read_sfp_data_byte()
1394 wr32(E1000_CTRL, ctrl); in igb_phy_force_speed_duplex_setup()
2096 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); in igb_phy_hw_reset()
2101 wr32(E1000_CTRL, ctrl); in igb_phy_hw_reset()
/linux-4.1.27/drivers/net/ethernet/intel/i40e/
Di40e_hmc.h131 wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
132 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
133 wr32((hw), I40E_PFHMC_SDCMD, val3); \
150 wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
151 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
152 wr32((hw), I40E_PFHMC_SDCMD, val3); \
162 wr32((hw), I40E_PFHMC_PDINV, \
Di40e_adminq.c308 wr32(hw, hw->aq.asq.head, 0); in i40e_config_asq_regs()
309 wr32(hw, hw->aq.asq.tail, 0); in i40e_config_asq_regs()
312 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
314 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
315 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
337 wr32(hw, hw->aq.arq.head, 0); in i40e_config_arq_regs()
338 wr32(hw, hw->aq.arq.tail, 0); in i40e_config_arq_regs()
341 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
343 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
344 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
[all …]
Di40e_ptp.c92 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); in i40e_ptp_write()
93 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); in i40e_ptp_write()
145 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); in i40e_ptp_adjfreq()
146 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); in i40e_ptp_adjfreq()
418 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); in i40e_ptp_set_increment()
419 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); in i40e_ptp_set_increment()
532 wr32(hw, I40E_PRTTSYN_CTL0, regval); in i40e_ptp_set_timestamp_mode()
539 wr32(hw, I40E_PFINT_ICR0_ENA, regval); in i40e_ptp_set_timestamp_mode()
552 wr32(hw, I40E_PRTTSYN_CTL1, regval); in i40e_ptp_set_timestamp_mode()
686 wr32(hw, I40E_PRTTSYN_CTL0, regval); in i40e_ptp_init()
[all …]
Di40e_virtchnl_pf.c168 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id), reg); in i40e_vc_disable_vf()
280 wr32(hw, reg_idx, I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK); in i40e_config_irq_link_list()
305 wr32(hw, reg_idx, reg); in i40e_config_irq_link_list()
342 wr32(hw, reg_idx, reg); in i40e_config_irq_link_list()
411 wr32(hw, I40E_QTX_CTL(pf_queue_id), qtx_ctl); in i40e_config_vsi_tx_queue()
591 wr32(hw, I40E_VSILAN_QBASE(vf->lan_vsi_id), in i40e_enable_vf_mappings()
596 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_id), reg); in i40e_enable_vf_mappings()
602 wr32(hw, I40E_VPLAN_QTABLE(total_queue_pairs, vf->vf_id), reg); in i40e_enable_vf_mappings()
618 wr32(hw, I40E_VSILAN_QTABLE(j, vf->lan_vsi_id), reg); in i40e_enable_vf_mappings()
637 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_id), 0); in i40e_disable_vf_mappings()
[all …]
Di40e_diag.c46 wr32(hw, reg, (pat & mask)); in i40e_diag_reg_pattern_test()
56 wr32(hw, reg, orig_val); in i40e_diag_reg_pattern_test()
Di40e_main.c2522 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl); in i40e_configure_tx_ring()
2814 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1), in i40e_vsi_configure_msix()
2818 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1), in i40e_vsi_configure_msix()
2822 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp); in i40e_vsi_configure_msix()
2831 wr32(hw, I40E_QINT_RQCTL(qp), val); in i40e_vsi_configure_msix()
2845 wr32(hw, I40E_QINT_TQCTL(qp), val); in i40e_vsi_configure_msix()
2863 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ in i40e_enable_misc_int_causes()
2878 wr32(hw, I40E_PFINT_ICR0_ENA, val); in i40e_enable_misc_int_causes()
2881 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | in i40e_enable_misc_int_causes()
2885 wr32(hw, I40E_PFINT_STAT_CTL0, 0); in i40e_enable_misc_int_causes()
[all …]
Di40e_lan_hmc.c510 wr32(hw, I40E_GLHMC_LANTXBASE(hmc_fn_id), in i40e_configure_lan_hmc()
512 wr32(hw, I40E_GLHMC_LANTXCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
516 wr32(hw, I40E_GLHMC_LANRXBASE(hmc_fn_id), in i40e_configure_lan_hmc()
518 wr32(hw, I40E_GLHMC_LANRXCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
522 wr32(hw, I40E_GLHMC_FCOEDDPBASE(hmc_fn_id), in i40e_configure_lan_hmc()
524 wr32(hw, I40E_GLHMC_FCOEDDPCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
528 wr32(hw, I40E_GLHMC_FCOEFBASE(hmc_fn_id), in i40e_configure_lan_hmc()
530 wr32(hw, I40E_GLHMC_FCOEFCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
Di40e_osdep.h46 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg))) macro
Di40e_common.c721 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); in i40e_pre_tx_queue_cfg()
923 wr32(hw, I40E_PFGEN_CTRL, in i40e_pf_reset()
988 wr32(hw, I40E_PFINT_ICR0_ENA, 0); in i40e_clear_hw()
991 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); in i40e_clear_hw()
995 wr32(hw, I40E_PFINT_LNKLST0, val); in i40e_clear_hw()
997 wr32(hw, I40E_PFINT_LNKLSTN(i), val); in i40e_clear_hw()
1000 wr32(hw, I40E_VPINT_LNKLST0(i), val); in i40e_clear_hw()
1002 wr32(hw, I40E_VPINT_LNKLSTN(i), val); in i40e_clear_hw()
1019 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); in i40e_clear_hw()
1025 wr32(hw, I40E_QINT_TQCTL(i), 0); in i40e_clear_hw()
[all …]
Di40e_ethtool.c1528 wr32(&pf->hw, I40E_PFINT_DYN_CTL0, in i40e_intr_test()
1777 wr32(hw, I40E_PFINT_ITRN(0, vector - 1), q_vector->rx.itr); in i40e_set_coalesce()
1779 wr32(hw, I40E_PFINT_ITRN(1, vector - 1), q_vector->tx.itr); in i40e_set_coalesce()
2079 wr32(hw, I40E_PFQF_HENA(0), (u32)hena); in i40e_set_rss_hash_opt()
2080 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); in i40e_set_rss_hash_opt()
2508 wr32(hw, I40E_PFQF_HLUT(i), reg_val); in i40e_set_rxfh()
2517 wr32(hw, I40E_PFQF_HKEY(i), reg_val); in i40e_set_rxfh()
Di40e_txrx.c867 wr32(&vsi->back->hw, in i40e_force_wb()
956 wr32(hw, reg_addr, q_vector->rx.itr); in i40e_update_dynamic_itr()
962 wr32(hw, reg_addr, q_vector->tx.itr); in i40e_update_dynamic_itr()
1911 wr32(hw, I40E_QINT_RQCTL(0), qval); in i40e_napi_poll()
1915 wr32(hw, I40E_QINT_TQCTL(0), qval); in i40e_napi_poll()
Di40e_fcoe.c301 wr32(hw, I40E_PFQF_HENA(1), val); in i40e_init_pf_fcoe()
323 wr32(hw, I40E_GLFCOE_RCTL, val); in i40e_init_pf_fcoe()
Di40e_nvm.c194 wr32(hw, I40E_GLNVM_SRCTL, sr_reg); in i40e_read_nvm_word_srctl()
Di40e_debugfs.c1522 wr32(&pf->hw, address, value); in i40e_dbg_command_write()
/linux-4.1.27/drivers/net/ethernet/intel/i40evf/
Di40e_hmc.h131 wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
132 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
133 wr32((hw), I40E_PFHMC_SDCMD, val3); \
150 wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
151 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
152 wr32((hw), I40E_PFHMC_SDCMD, val3); \
162 wr32((hw), I40E_PFHMC_PDINV, \
Di40e_adminq.c306 wr32(hw, hw->aq.asq.head, 0); in i40e_config_asq_regs()
307 wr32(hw, hw->aq.asq.tail, 0); in i40e_config_asq_regs()
310 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
312 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
313 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
335 wr32(hw, hw->aq.arq.head, 0); in i40e_config_arq_regs()
336 wr32(hw, hw->aq.arq.tail, 0); in i40e_config_arq_regs()
339 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
341 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
342 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
[all …]
Di40evf_ethtool.c354 wr32(hw, I40E_VFINT_ITRN1(0, i), q_vector->rx.itr); in i40evf_set_coalesce()
356 wr32(hw, I40E_VFINT_ITRN1(1, i), q_vector->tx.itr); in i40evf_set_coalesce()
559 wr32(hw, I40E_VFQF_HENA(0), (u32)hena); in i40evf_set_rss_hash_opt()
560 wr32(hw, I40E_VFQF_HENA(1), (u32)(hena >> 32)); in i40evf_set_rss_hash_opt()
685 wr32(hw, I40E_VFQF_HLUT(i), hlut_val); in i40evf_set_rxfh()
Di40evf_main.c187 wr32(hw, I40E_VFINT_DYN_CTL01, 0); in i40evf_misc_irq_disable()
203 wr32(hw, I40E_VFINT_DYN_CTL01, I40E_VFINT_DYN_CTL01_INTENA_MASK | in i40evf_misc_irq_enable()
205 wr32(hw, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA_ADMINQ_MASK); in i40evf_misc_irq_enable()
224 wr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), 0); in i40evf_irq_disable()
243 wr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), in i40evf_irq_enable_queues()
267 wr32(hw, I40E_VFINT_DYN_CTL01, dyn_ctl); in i40evf_fire_sw_int()
275 wr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), dyn_ctl); in i40evf_fire_sw_int()
315 wr32(hw, I40E_VFINT_DYN_CTL01, val); in i40evf_msix_aq()
1452 wr32(hw, I40E_VFQF_HKEY(i), rss_key[i]); in i40evf_configure_rss()
1456 wr32(hw, I40E_VFQF_HENA(0), (u32)hena); in i40evf_configure_rss()
[all …]
Di40e_osdep.h45 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg))) macro
Di40e_txrx.c379 wr32(&vsi->back->hw, in i40e_force_wb()
468 wr32(hw, reg_addr, q_vector->rx.itr); in i40e_update_dynamic_itr()
474 wr32(hw, reg_addr, q_vector->tx.itr); in i40e_update_dynamic_itr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/ce/
Dgf100.c59 .wr32 = _nvkm_falcon_context_wr32,
151 .wr32 = _nvkm_falcon_wr32,
164 .wr32 = _nvkm_falcon_wr32,
Dgt215.c60 .wr32 = _nvkm_falcon_context_wr32,
150 .wr32 = _nvkm_falcon_wr32,
Dgk104.c53 .wr32 = _nvkm_engctx_wr32,
Dgm204.c53 .wr32 = _nvkm_engctx_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/vp/
Dg84.c52 .wr32 = _nvkm_engctx_wr32,
91 .wr32 = _nvkm_xtensa_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/bsp/
Dg84.c52 .wr32 = _nvkm_engctx_wr32,
91 .wr32 = _nvkm_xtensa_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msvld/
Dg98.c56 .wr32 = _nvkm_falcon_context_wr32,
108 .wr32 = _nvkm_falcon_wr32,
Dgk104.c54 .wr32 = _nvkm_falcon_context_wr32,
107 .wr32 = _nvkm_falcon_wr32,
Dgf100.c54 .wr32 = _nvkm_falcon_context_wr32,
107 .wr32 = _nvkm_falcon_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/
Dgk104.c54 .wr32 = _nvkm_falcon_context_wr32,
107 .wr32 = _nvkm_falcon_wr32,
Dg98.c55 .wr32 = _nvkm_falcon_context_wr32,
107 .wr32 = _nvkm_falcon_wr32,
Dgf100.c54 .wr32 = _nvkm_falcon_context_wr32,
107 .wr32 = _nvkm_falcon_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msppp/
Dg98.c55 .wr32 = _nvkm_falcon_context_wr32,
107 .wr32 = _nvkm_falcon_wr32,
Dgf100.c54 .wr32 = _nvkm_falcon_context_wr32,
107 .wr32 = _nvkm_falcon_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sec/
Dg98.c59 .wr32 = _nvkm_falcon_context_wr32,
147 .wr32 = _nvkm_falcon_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
Dg84.c68 .wr32 = _nvkm_gpuobj_wr32,
90 .wr32 = _nvkm_engctx_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dnv10.c110 .wr32 = _nvkm_fifo_channel_wr32,
133 .wr32 = _nvkm_fifo_context_wr32,
Dnv17.c117 .wr32 = _nvkm_fifo_channel_wr32,
140 .wr32 = _nvkm_fifo_context_wr32,
Dnv40.c236 .wr32 = _nvkm_fifo_channel_wr32,
259 .wr32 = _nvkm_fifo_context_wr32,
Dg84.c336 .wr32 = _nvkm_fifo_channel_wr32,
348 .wr32 = _nvkm_fifo_channel_wr32,
413 .wr32 = _nvkm_fifo_context_wr32,
Dnv50.c362 .wr32 = _nvkm_fifo_channel_wr32,
374 .wr32 = _nvkm_fifo_channel_wr32,
446 .wr32 = _nvkm_fifo_context_wr32,
Dnv04.c251 .wr32 = _nvkm_fifo_channel_wr32,
292 .wr32 = _nvkm_fifo_context_wr32,
Dgf100.c301 .wr32 = _nvkm_fifo_channel_wr32,
365 .wr32 = _nvkm_fifo_context_wr32,
Dgk104.c334 .wr32 = _nvkm_fifo_channel_wr32,
397 .wr32 = _nvkm_fifo_context_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv50.c70 .wr32 = _nvkm_gpuobj_wr32,
114 .wr32 = _nvkm_mpeg_context_wr32,
Dg84.c57 .wr32 = _nvkm_mpeg_context_wr32,
Dnv44.c85 .wr32 = _nvkm_mpeg_context_wr32,
Dnv31.c105 .wr32 = _nvkm_gpuobj_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dnv04.c101 .wr32 = nv04_instobj_wr32,
190 .wr32 = nv04_instmem_wr32,
Dnv40.c133 .wr32 = nv40_instmem_wr32,
Dnv50.c126 .wr32 = nv50_instobj_wr32,
Dgk20a.c375 .wr32 = gk20a_instobj_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxgk20a.c40 .wr32 = _nvkm_gr_context_wr32,
Dctxgk110b.c81 .wr32 = _nvkm_gr_context_wr32,
Dctxgf104.c91 .wr32 = _nvkm_gr_context_wr32,
Dctxgm206.c61 .wr32 = _nvkm_gr_context_wr32,
Dctxgf110.c342 .wr32 = _nvkm_gr_context_wr32,
Dctxgf119.c510 .wr32 = _nvkm_gr_context_wr32,
Dctxgk208.c542 .wr32 = _nvkm_gr_context_wr32,
Dctxgk110.c820 .wr32 = _nvkm_gr_context_wr32,
Dnv2a.c82 .wr32 = _nvkm_gr_context_wr32,
Dctxgf108.c787 .wr32 = _nvkm_gr_context_wr32,
Dnv25.c115 .wr32 = _nvkm_gr_context_wr32,
Dnv35.c116 .wr32 = _nvkm_gr_context_wr32,
Dnv34.c116 .wr32 = _nvkm_gr_context_wr32,
Dnv40.c86 .wr32 = _nvkm_gpuobj_wr32,
197 .wr32 = _nvkm_gr_context_wr32,
Dctxgf117.c264 .wr32 = _nvkm_gr_context_wr32,
Dctxgm204.c1032 .wr32 = _nvkm_gr_context_wr32,
Dnv30.c118 .wr32 = _nvkm_gr_context_wr32,
Dctxgk104.c1002 .wr32 = _nvkm_gr_context_wr32,
Dctxgm107.c1006 .wr32 = _nvkm_gr_context_wr32,
Dnv50.c82 .wr32 = _nvkm_gpuobj_wr32,
169 .wr32 = _nvkm_gr_context_wr32,
Dnv20.c149 .wr32 = _nvkm_gr_context_wr32,
Dctxgf100.c1373 .wr32 = _nvkm_gr_context_wr32,
Dnv04.c981 .wr32 = _nvkm_gpuobj_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/
Dobject.h100 void (*wr32)(struct nvkm_object *, u64 offset, u32 data); member
179 nv_ofuncs(obj)->wr32(obj, addr, data); in nv_wo32()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/core/
Dramht.c85 .wr32 = _nvkm_gpuobj_wr32,
Dgpuobj.c196 pfuncs->wr32(gpuobj->parent, addr, data); in _nvkm_gpuobj_wr32()
208 .wr32 = _nvkm_gpuobj_wr32,
Dioctl.c294 if (ret = -ENODEV, ofuncs->wr32) { in nvkm_ioctl_wr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
Dbase.c101 .wr32 = nvkm_barobj_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dgf110.c354 .base.wr32 = nv50_disp_chan_wr32,
448 .base.wr32 = nv50_disp_chan_wr32,
529 .base.wr32 = nv50_disp_chan_wr32,
600 .base.wr32 = nv50_disp_chan_wr32,
617 .base.wr32 = nv50_disp_chan_wr32,
Dnv50.c583 .base.wr32 = nv50_disp_chan_wr32,
685 .base.wr32 = nv50_disp_chan_wr32,
775 .base.wr32 = nv50_disp_chan_wr32,
893 .base.wr32 = nv50_disp_chan_wr32,
941 .base.wr32 = nv50_disp_chan_wr32,
1281 .wr32 = _nvkm_engctx_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
Di2c_.fuc293 call(wr32)
300 call(wr32)
Dmacros.fuc245 */ call(wr32)
Dkernel.fuc70 wr32:
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dbase.c204 .wr32 = nvkm_bios_wr32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/device/
Dbase.c277 .wr32 = nvkm_devobj_wr32,