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Searched refs:writel_relaxed (Results 1 – 200 of 286) sorted by relevance

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/linux-4.1.27/drivers/phy/
Dphy-qcom-apq8064-sata.c104 writel_relaxed(0x01, base + SATA_PHY_SER_CTRL); in qcom_apq8064_sata_phy_init()
105 writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0); in qcom_apq8064_sata_phy_init()
110 writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0); in qcom_apq8064_sata_phy_init()
111 writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); in qcom_apq8064_sata_phy_init()
112 writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); in qcom_apq8064_sata_phy_init()
113 writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0); in qcom_apq8064_sata_phy_init()
114 writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2); in qcom_apq8064_sata_phy_init()
117 writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG); in qcom_apq8064_sata_phy_init()
118 writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG); in qcom_apq8064_sata_phy_init()
120 writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0); in qcom_apq8064_sata_phy_init()
[all …]
Dphy-qcom-ufs-qmp-20nm.c97 writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); in ufs_qcom_phy_qmp_20nm_power_control()
110 writel_relaxed(0x0A, phy->mmio + in ufs_qcom_phy_qmp_20nm_power_control()
112 writel_relaxed(0x08, phy->mmio + in ufs_qcom_phy_qmp_20nm_power_control()
122 writel_relaxed(0x0A, phy->mmio + in ufs_qcom_phy_qmp_20nm_power_control()
124 writel_relaxed(0x02, phy->mmio + in ufs_qcom_phy_qmp_20nm_power_control()
133 writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); in ufs_qcom_phy_qmp_20nm_power_control()
145 writel_relaxed(val & UFS_PHY_TX_LANE_ENABLE_MASK, in ufs_qcom_phy_qmp_20nm_set_tx_lane_enable()
157 writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START); in ufs_qcom_phy_qmp_20nm_start_serdes()
Dphy-qcom-ipq806x-sata.c69 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
76 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0); in qcom_ipq806x_sata_phy_init()
85 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1); in qcom_ipq806x_sata_phy_init()
90 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2); in qcom_ipq806x_sata_phy_init()
95 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
100 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
111 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
124 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_exit()
Dphy-hix5hd2-sata.c89 writel_relaxed(val, priv->base + SATA_PHY0_CTLL); in hix5hd2_sata_phy_init()
92 writel_relaxed(val, priv->base + SATA_PHY0_CTLL); in hix5hd2_sata_phy_init()
99 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL1); in hix5hd2_sata_phy_init()
106 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL2); in hix5hd2_sata_phy_init()
114 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); in hix5hd2_sata_phy_init()
121 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); in hix5hd2_sata_phy_init()
127 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); in hix5hd2_sata_phy_init()
Dphy-qcom-ufs-qmp-14nm.c76 writel_relaxed(val ? 0x1 : 0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); in ufs_qcom_phy_qmp_14nm_power_control()
100 writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START); in ufs_qcom_phy_qmp_14nm_start_serdes()
Dphy-qcom-ufs.c48 writel_relaxed(tbl_A[i].cfg_value, in ufs_qcom_phy_calibrate()
66 writel_relaxed(tbl_B[i].cfg_value, in ufs_qcom_phy_calibrate()
501 writel_relaxed(temp, phy->dev_ref_clk_ctrl_mmio); in ufs_qcom_phy_dev_ref_clk_ctrl()
/linux-4.1.27/arch/arm/mach-hisi/
Dhotplug.c86 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
91 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN); in set_cpu_hi3620()
96 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
99 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); in set_cpu_hi3620()
103 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
110 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
115 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
120 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
123 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS); in set_cpu_hi3620()
127 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
[all …]
Dplatsmp.c31 writel_relaxed(virt_to_phys(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
112 writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */ in hix5hd2_set_scu_boot_addr()
113 writel_relaxed(jump_addr, virt + 4); /* pc jump phy address */ in hix5hd2_set_scu_boot_addr()
148 writel_relaxed(0xe51ff004, virt); in hip01_set_boot_addr()
149 writel_relaxed(jump_addr, virt + 4); in hip01_set_boot_addr()
172 writel_relaxed(remap_reg_value, ctrl_base + REG_SC_CTRL); in hip01_boot_secondary()
Dplatmcpm.c91 writel_relaxed(data, fabric + FAB_SF_MODE); in hip04_set_snoop_filter()
116 writel_relaxed(data, sys_dreq); in hip04_mcpm_power_up()
125 writel_relaxed(data, sys_dreq); in hip04_mcpm_power_up()
214 writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster)); in hip04_mcpm_wait_for_powerdown()
365 writel_relaxed(hip04_boot_method[0], relocation); in hip04_mcpm_init()
366 writel_relaxed(0xa5a5a5a5, relocation + 4); /* magic number */ in hip04_mcpm_init()
367 writel_relaxed(virt_to_phys(mcpm_entry_point), relocation + 8); in hip04_mcpm_init()
368 writel_relaxed(0, relocation + 12); in hip04_mcpm_init()
/linux-4.1.27/drivers/crypto/ux500/cryp/
Dcryp.c147 writel_relaxed(cr_for_kse, &device_data->base->cr); in cryp_set_configuration()
218 writel_relaxed(key_value.key_value_left, in cryp_configure_key_values()
220 writel_relaxed(key_value.key_value_right, in cryp_configure_key_values()
224 writel_relaxed(key_value.key_value_left, in cryp_configure_key_values()
226 writel_relaxed(key_value.key_value_right, in cryp_configure_key_values()
230 writel_relaxed(key_value.key_value_left, in cryp_configure_key_values()
232 writel_relaxed(key_value.key_value_right, in cryp_configure_key_values()
236 writel_relaxed(key_value.key_value_left, in cryp_configure_key_values()
238 writel_relaxed(key_value.key_value_right, in cryp_configure_key_values()
265 writel_relaxed(init_vector_value.init_value_left, in cryp_configure_init_vector()
[all …]
Dcryp_p.h24 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
27 writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\
34 writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \
Dcryp_irq.c28 writel_relaxed(i, &device_data->base->imsc); in cryp_enable_irq_src()
39 writel_relaxed(i, &device_data->base->imsc); in cryp_disable_irq_src()
/linux-4.1.27/drivers/clocksource/
Dtimer-atlas7.c59 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7, in sirfsoc_timer_count_disable()
66 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3, in sirfsoc_timer_count_enable()
77 writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); in sirfsoc_timer_interrupt()
92 writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | in sirfsoc_timer_read()
109 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 + in sirfsoc_timer_set_next_event()
111 writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 + in sirfsoc_timer_set_next_event()
147 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); in sirfsoc_clocksource_resume()
149 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], in sirfsoc_clocksource_resume()
151 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], in sirfsoc_clocksource_resume()
154 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | in sirfsoc_clocksource_resume()
[all …]
Dtimer-prima2.c68 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); in sirfsoc_timer_interrupt()
81 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, in sirfsoc_timer_read()
95 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, in sirfsoc_timer_set_next_event()
99 writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0); in sirfsoc_timer_set_next_event()
100 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, in sirfsoc_timer_set_next_event()
116 writel_relaxed(val | BIT(0), in sirfsoc_timer_set_mode()
120 writel_relaxed(val & ~BIT(0), in sirfsoc_timer_set_mode()
133 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, in sirfsoc_clocksource_suspend()
147 writel_relaxed(sirfsoc_timer_reg_val[i], in sirfsoc_clocksource_resume()
150 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], in sirfsoc_clocksource_resume()
[all …]
Dasm9260_timer.c117 writel_relaxed(delta, priv.base + HW_MR0); in asm9260_timer_set_next_event()
119 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_next_event()
127 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG); in asm9260_timer_set_mode()
132 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), in asm9260_timer_set_mode()
135 writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0); in asm9260_timer_set_mode()
137 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_mode()
141 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), in asm9260_timer_set_mode()
163 writel_relaxed(BM_IR_MR0, priv.base + HW_IR); in asm9260_timer_interrupt()
197 writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR); in asm9260_timer_init()
199 writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR); in asm9260_timer_init()
[all …]
Dtime-efm32.c59 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_mode()
60 writel_relaxed(ddata->periodic_top, ddata->base + TIMERn_TOP); in efm32_clock_event_set_mode()
61 writel_relaxed(TIMERn_CTRL_PRESC_1024 | in efm32_clock_event_set_mode()
65 writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD); in efm32_clock_event_set_mode()
69 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_mode()
70 writel_relaxed(TIMERn_CTRL_PRESC_1024 | in efm32_clock_event_set_mode()
79 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_mode()
93 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_next_event()
94 writel_relaxed(evt, ddata->base + TIMERn_CNT); in efm32_clock_event_set_next_event()
95 writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD); in efm32_clock_event_set_next_event()
[all …]
Dcadence_ttc_timer.c123 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
125 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); in ttc_set_interval()
133 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
217 writel_relaxed(ctrl_reg, in ttc_set_mode()
224 writel_relaxed(ctrl_reg, in ttc_set_mode()
294 writel_relaxed(ttccs->scale_clk_ctrl_reg_new, in ttc_rate_change_clocksource_cb()
304 writel_relaxed(ttccs->scale_clk_ctrl_reg_new, in ttc_rate_change_clocksource_cb()
314 writel_relaxed(ttccs->scale_clk_ctrl_reg_old, in ttc_rate_change_clocksource_cb()
363 writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); in ttc_setup_clocksource()
364 writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, in ttc_setup_clocksource()
[all …]
Dqcom-timer.c55 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_interrupt()
67 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_set_next_event()
69 writel_relaxed(ctrl, event_base + TIMER_CLEAR); in msm_timer_set_next_event()
70 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); in msm_timer_set_next_event()
76 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); in msm_timer_set_next_event()
99 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_set_mode()
226 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE); in msm_timer_init()
282 writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL); in msm_dt_timer_init()
Drockchip_timer.c51 writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG); in rk_timer_disable()
57 writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags, in rk_timer_enable()
65 writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0); in rk_timer_update_counter()
66 writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1); in rk_timer_update_counter()
72 writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS); in rk_timer_interrupt_clear()
Dbcm2835_timer.c77 writel_relaxed(readl_relaxed(system_clock) + event, in bcm2835_time_set_next_event()
87 writel_relaxed(timer->match_mask, timer->control); in bcm2835_time_interrupt()
Darm_arch_timer.c86 writel_relaxed(val, timer->base + CNTP_CTL); in arch_timer_reg_write()
89 writel_relaxed(val, timer->base + CNTP_TVAL); in arch_timer_reg_write()
96 writel_relaxed(val, timer->base + CNTV_CTL); in arch_timer_reg_write()
99 writel_relaxed(val, timer->base + CNTV_TVAL); in arch_timer_reg_write()
Dtimer-keystone.c59 writel_relaxed(val, timer.base + rg); in keystone_timer_writel()
Dtegra20_timer.c60 writel_relaxed(value, timer_reg_base + (reg))
Dpxa_timer.c53 #define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg))
/linux-4.1.27/arch/arm/mach-ks8695/
Dtime.c69 writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); in ks8695_set_mode()
72 writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); in ks8695_set_mode()
73 writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); in ks8695_set_mode()
77 writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); in ks8695_set_mode()
91 writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); in ks8695_set_next_event()
94 writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); in ks8695_set_next_event()
95 writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); in ks8695_set_next_event()
99 writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); in ks8695_set_next_event()
137 writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); in ks8695_timer_setup()
166 writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); in ks8695_restart()
[all …]
/linux-4.1.27/drivers/mmc/host/
Dmmci_qcom_dml.c68 writel_relaxed(config, base + DML_CONFIG); in dml_start_xfer()
71 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE); in dml_start_xfer()
74 writel_relaxed(data->blocks * data->blksz, in dml_start_xfer()
79 writel_relaxed(config, base + DML_CONFIG); in dml_start_xfer()
81 writel_relaxed(1, base + DML_PRODUCER_START); in dml_start_xfer()
88 writel_relaxed(config, base + DML_CONFIG); in dml_start_xfer()
92 writel_relaxed(config, base + DML_CONFIG); in dml_start_xfer()
94 writel_relaxed(1, base + DML_CONSUMER_START); in dml_start_xfer()
137 writel_relaxed(1, base + DML_SW_RESET); in dml_hw_init()
158 writel_relaxed(config, base + DML_CONFIG); in dml_hw_init()
[all …]
Dsdhci-msm.c108 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); in msm_config_cm_dll_phase()
122 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); in msm_config_cm_dll_phase()
125 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) in msm_config_cm_dll_phase()
136 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); in msm_config_cm_dll_phase()
284 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); in msm_cm_dll_set_freq()
301 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) in msm_init_cm_dll()
305 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) in msm_init_cm_dll()
309 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) in msm_init_cm_dll()
314 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) in msm_init_cm_dll()
318 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) in msm_init_cm_dll()
[all …]
Dsdhci-st.c136 writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL); in st_mmcss_set_static_delay()
137 writel_relaxed(ST_TOP_MMC_DLY_MAX, in st_mmcss_set_static_delay()
164 writel_relaxed(ST_MMC_CCONFIG_1_DEFAULT, in st_mmcss_cconfig()
184 writel_relaxed(cconf2, host->ioaddr + ST_MMC_CCONFIG_REG_2); in st_mmcss_cconfig()
190 writel_relaxed(ST_MMC_GP_OUTPUT_CD, in st_mmcss_cconfig()
217 writel_relaxed(cconf3, host->ioaddr + ST_MMC_CCONFIG_REG_3); in st_mmcss_cconfig()
218 writel_relaxed(cconf4, host->ioaddr + ST_MMC_CCONFIG_REG_4); in st_mmcss_cconfig()
219 writel_relaxed(cconf5, host->ioaddr + ST_MMC_CCONFIG_REG_5); in st_mmcss_cconfig()
227 writel_relaxed(ST_TOP_MMC_DYN_DLY_CONF, ioaddr + ST_TOP_MMC_DLY_CTRL); in st_mmcss_set_dll()
228 writel_relaxed(ST_TOP_MMC_TX_DLL_STEP_DLY_VALID, in st_mmcss_set_dll()
Datmel-mci-regs.h147 writel_relaxed((value), (port)->regs + reg)
/linux-4.1.27/arch/arm/mach-qcom/
Dplatsmp.c83 writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL); in scss_release_secondary()
84 writel_relaxed(0, base + SCSS_CPU1CORE_RESET); in scss_release_secondary()
85 writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP); in scss_release_secondary()
128 writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL); in kpssv1_release_secondary()
134 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
136 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
141 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
146 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
151 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
156 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
[all …]
/linux-4.1.27/drivers/irqchip/
Dirq-gic-common.c50 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); in gic_configure_irq()
61 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); in gic_configure_irq()
66 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); in gic_configure_irq()
83 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG, in gic_dist_config()
90 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); in gic_dist_config()
97 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_dist_config()
112 writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR); in gic_cpu_config()
113 writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET); in gic_cpu_config()
119 writel_relaxed(GICD_INT_DEF_PRI_X4, in gic_cpu_config()
Dirq-sirfsoc.c72 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0); in sirfsoc_irq_init()
73 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_init()
75 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0); in sirfsoc_irq_init()
76 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1); in sirfsoc_irq_init()
109 writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0); in sirfsoc_irq_resume()
110 writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); in sirfsoc_irq_resume()
111 writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0); in sirfsoc_irq_resume()
112 writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_resume()
Dirq-tegra.c98 writel_relaxed(mask, base + reg); in tegra_ictlr_write_mask()
161 writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); in tegra_ictlr_suspend()
164 writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR); in tegra_ictlr_suspend()
167 writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET); in tegra_ictlr_suspend()
183 writel_relaxed(lic->cpu_iep[i], in tegra_ictlr_resume()
185 writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR); in tegra_ictlr_resume()
186 writel_relaxed(lic->cpu_ier[i], in tegra_ictlr_resume()
188 writel_relaxed(lic->cop_iep[i], in tegra_ictlr_resume()
190 writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); in tegra_ictlr_resume()
191 writel_relaxed(lic->cop_ier[i], in tegra_ictlr_resume()
[all …]
Dirq-hip04.c99 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR + in hip04_mask_irq()
109 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET + in hip04_unmask_irq()
116 writel_relaxed(hip04_irq(d), hip04_cpu_base(d) + GIC_CPU_EOI); in hip04_eoi_irq()
165 writel_relaxed(val | bit, reg); in hip04_irq_set_affinity()
186 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); in hip04_handle_irq()
232 writel_relaxed(0, base + GIC_DIST_CTRL); in hip04_irq_dist_init()
240 writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3)); in hip04_irq_dist_init()
244 writel_relaxed(1, base + GIC_DIST_CTRL); in hip04_irq_dist_init()
271 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); in hip04_irq_cpu_init()
272 writel_relaxed(1, base + GIC_CPU_CTRL); in hip04_irq_cpu_init()
[all …]
Dirq-gic.c146 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); in gic_poke_irq()
167 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); in gic_eoi_irq()
257 writel_relaxed(val | bit, reg); in gic_set_affinity()
279 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); in gic_handle_irq()
376 writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up()
387 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); in gic_dist_init()
396 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); in gic_dist_init()
400 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); in gic_dist_init()
427 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); in gic_cpu_init()
438 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); in gic_cpu_if_down()
[all …]
Dirq-clps711x.c100 writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hwirq].eoi); in clps711x_intc_eoi()
111 writel_relaxed(tmp, intmr); in clps711x_intc_mask()
122 writel_relaxed(tmp, intmr); in clps711x_intc_unmask()
150 writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hw].eoi); in clps711x_intc_irq_map()
181 writel_relaxed(0, clps711x_intc->intmr[0]); in _clps711x_intc_init()
182 writel_relaxed(0, clps711x_intc->intmr[1]); in _clps711x_intc_init()
183 writel_relaxed(0, clps711x_intc->intmr[2]); in _clps711x_intc_init()
Dirq-dw-apb-ictl.c60 writel_relaxed(~0, gc->reg_base + ct->regs.enable); in dw_apb_ictl_resume()
61 writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask); in dw_apb_ictl_resume()
112 writel_relaxed(~0, iobase + APB_INT_MASK_L); in dw_apb_ictl_init()
113 writel_relaxed(~0, iobase + APB_INT_MASK_H); in dw_apb_ictl_init()
114 writel_relaxed(~0, iobase + APB_INT_ENABLE_L); in dw_apb_ictl_init()
115 writel_relaxed(~0, iobase + APB_INT_ENABLE_H); in dw_apb_ictl_init()
Dirq-nvic.c103 writel_relaxed(~0, gc->reg_base + NVIC_ICER); in nvic_of_init()
108 writel_relaxed(0, nvic_base + NVIC_IPR + i); in nvic_of_init()
Dirq-mmp.c76 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
84 writel_relaxed(r, data->reg_mask); in icu_mask_ack_irq()
100 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
103 writel_relaxed(r, data->reg_mask); in icu_mask_irq()
119 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_unmask_irq()
122 writel_relaxed(r, data->reg_mask); in icu_unmask_irq()
Dirq-gic-v3.c175 writel_relaxed(val, rbase + GICR_WAKER); in gic_enable_redist()
225 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); in gic_poke_irq()
379 writel_relaxed(0, base + GICD_CTLR); in gic_dist_init()
389 writel_relaxed(~0, base + GICD_IGROUPR + i / 8); in gic_dist_init()
394 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, in gic_dist_init()
495 writel_relaxed(~0, rbase + GICR_IGROUPR0); in gic_cpu_init()
Dirq-bcm2835.c103 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); in armctrl_mask_irq()
108 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]); in armctrl_unmask_irq()
/linux-4.1.27/drivers/video/fbdev/mmp/hw/
Dmmp_ctrl.c55 writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR); in ctrl_handle_irq()
139 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); in dmafetch_set_fmt()
152 writel_relaxed(win->pitch[0], &regs->v_pitch_yc); in overlay_set_win()
153 writel_relaxed(win->pitch[2] << 16 | in overlay_set_win()
156 writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->v_size); in overlay_set_win()
157 writel_relaxed((win->ydst << 16) | win->xdst, &regs->v_size_z); in overlay_set_win()
158 writel_relaxed(win->ypos << 16 | win->xpos, &regs->v_start); in overlay_set_win()
160 writel_relaxed(win->pitch[0], &regs->g_pitch); in overlay_set_win()
162 writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->g_size); in overlay_set_win()
163 writel_relaxed((win->ydst << 16) | win->xdst, &regs->g_size_z); in overlay_set_win()
[all …]
Dmmp_spi.c51 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); in lcd_spi_write()
55 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
58 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
61 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
87 writel_relaxed(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
89 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); in lcd_spi_write()
113 writel_relaxed(IOPAD_DUMB18SPI | in lcd_spi_setup()
/linux-4.1.27/drivers/net/ethernet/hisilicon/
Dhix5hd2_gmac.c265 writel_relaxed(val, priv->ctrl_base); in hix5hd2_config_port()
267 writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port()
274 writel_relaxed(val, priv->base + PORT_MODE); in hix5hd2_config_port()
275 writel_relaxed(0, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port()
276 writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL); in hix5hd2_config_port()
281 writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth()
282 writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH); in hix5hd2_set_desc_depth()
283 writel_relaxed(0, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth()
285 writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN); in hix5hd2_set_desc_depth()
286 writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH); in hix5hd2_set_desc_depth()
[all …]
Dhip04_eth.c219 writel_relaxed(val, priv->base + GE_PORT_MODE); in hip04_config_port()
222 writel_relaxed(val, priv->base + GE_DUPLEX_TYPE); in hip04_config_port()
225 writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG); in hip04_config_port()
246 writel_relaxed(val, priv->base + PPE_CFG_STS_MODE); in hip04_config_fifo()
253 writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN); in hip04_config_fifo()
264 writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG); in hip04_config_fifo()
267 writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG); in hip04_config_fifo()
270 writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG); in hip04_config_fifo()
273 writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG); in hip04_config_fifo()
276 writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG); in hip04_config_fifo()
[all …]
Dhip04_mdio.c57 writel_relaxed(val, priv->base + MDIO_CMD_REG); in hip04_mdio_read()
87 writel_relaxed(value, priv->base + MDIO_WDATA_REG); in hip04_mdio_write()
89 writel_relaxed(val, priv->base + MDIO_CMD_REG); in hip04_mdio_write()
/linux-4.1.27/arch/arm/mach-prima2/
Drtciobrg.c56 writel_relaxed(0x00, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE); in __sirfsoc_rtc_iobrg_readl()
57 writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR); in __sirfsoc_rtc_iobrg_readl()
58 writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL); in __sirfsoc_rtc_iobrg_readl()
83 writel_relaxed(0xf1, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE); in sirfsoc_rtc_iobrg_pre_writel()
84 writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR); in sirfsoc_rtc_iobrg_pre_writel()
86 writel_relaxed(val, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); in sirfsoc_rtc_iobrg_pre_writel()
97 writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL); in sirfsoc_rtc_iobrg_writel()
/linux-4.1.27/arch/arm/mach-shmobile/
Dpm-rcar-gen2.c96 writel_relaxed(bar, p + CA15BAR); in rcar_gen2_pm_init()
97 writel_relaxed(bar | 0x10, p + CA15BAR); in rcar_gen2_pm_init()
100 writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | in rcar_gen2_pm_init()
104 writel_relaxed(bar, p + CA7BAR); in rcar_gen2_pm_init()
105 writel_relaxed(bar | 0x10, p + CA7BAR); in rcar_gen2_pm_init()
108 writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | in rcar_gen2_pm_init()
Dplatsmp-apmu.c40 writel_relaxed(BIT(bit), p + WUPCR_OFFS); in apmu_power_on()
52 writel_relaxed(3, p + CPUNCR_OFFS(bit)); in apmu_power_off()
/linux-4.1.27/drivers/soc/ti/
Dknav_dma.c156 writel_relaxed(v, &chan->reg_chan->mode); in chan_start()
157 writel_relaxed(DMA_ENABLE, &chan->reg_chan->control); in chan_start()
161 writel_relaxed(cfg->u.tx.priority, &chan->reg_tx_sched->prio); in chan_start()
179 writel_relaxed(v, &chan->reg_rx_flow->control); in chan_start()
180 writel_relaxed(0, &chan->reg_rx_flow->tags); in chan_start()
181 writel_relaxed(0, &chan->reg_rx_flow->tag_sel); in chan_start()
185 writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[0]); in chan_start()
189 writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[1]); in chan_start()
191 writel_relaxed(0, &chan->reg_rx_flow->thresh[0]); in chan_start()
192 writel_relaxed(0, &chan->reg_rx_flow->thresh[1]); in chan_start()
[all …]
Dknav_qmss_acc.c90 writel_relaxed(mask, pdsp->intd + offset); in knav_acc_set_notify()
130 writel_relaxed(1, pdsp->intd + ACC_INTD_OFFSET_COUNT(channel)); in knav_acc_int_handler()
132 writel_relaxed(ACC_CHANNEL_INT_BASE + channel, in knav_acc_int_handler()
203 writel_relaxed(1, pdsp->intd + ACC_INTD_OFFSET_COUNT(channel)); in knav_acc_int_handler()
206 writel_relaxed(ACC_CHANNEL_INT_BASE + channel, in knav_acc_int_handler()
299 writel_relaxed(cmd->timer_config, &pdsp->acc_command->timer_config); in knav_acc_write()
300 writel_relaxed(cmd->queue_num, &pdsp->acc_command->queue_num); in knav_acc_write()
301 writel_relaxed(cmd->list_phys, &pdsp->acc_command->list_phys); in knav_acc_write()
302 writel_relaxed(cmd->queue_mask, &pdsp->acc_command->queue_mask); in knav_acc_write()
303 writel_relaxed(cmd->command, &pdsp->acc_command->command); in knav_acc_write()
Dknav_qmss_queue.c493 writel_relaxed(0, &inst->qmgr->reg_push[id].ptr_size_thresh); in knav_queue_flush()
624 writel_relaxed(val, &qh->reg_push[0].ptr_size_thresh); in knav_queue_push()
1030 writel_relaxed(region->dma_start, &regs->base); in knav_queue_setup_region()
1031 writel_relaxed(region->link_index, &regs->start_index); in knav_queue_setup_region()
1032 writel_relaxed(hw_desc_size << 16 | hw_num_desc, in knav_queue_setup_region()
1171 writel_relaxed(block->phys, &qmgr->reg_config->link_ram_base0); in knav_queue_setup_link_ram()
1172 writel_relaxed(block->size, &qmgr->reg_config->link_ram_size0); in knav_queue_setup_link_ram()
1180 writel_relaxed(block->phys, &qmgr->reg_config->link_ram_base1); in knav_queue_setup_link_ram()
1254 writel_relaxed(THRESH_GTE | 1, in knav_setup_queue_range()
1256 writel_relaxed(0, in knav_setup_queue_range()
[all …]
/linux-4.1.27/drivers/i2c/busses/
Di2c-st.c202 writel_relaxed(readl_relaxed(reg) | mask, reg); in st_i2c_set_bits()
207 writel_relaxed(readl_relaxed(reg) & ~mask, reg); in st_i2c_clr_bits()
283 writel_relaxed(val, i2c_dev->base + SSC_CLR); in st_i2c_hw_config()
287 writel_relaxed(val, i2c_dev->base + SSC_CTL); in st_i2c_hw_config()
294 writel_relaxed(val, i2c_dev->base + SSC_BRG); in st_i2c_hw_config()
297 writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG); in st_i2c_hw_config()
300 writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C); in st_i2c_hw_config()
304 writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD); in st_i2c_hw_config()
308 writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP); in st_i2c_hw_config()
312 writel_relaxed(val, i2c_dev->base + SSC_START_HOLD); in st_i2c_hw_config()
[all …]
Di2c-hix5hd2.c106 writel_relaxed(val, priv->regs + HIX5I2C_ICR); in hix5hd2_i2c_clr_pend_irq()
113 writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR); in hix5hd2_i2c_clr_all_irq()
118 writel_relaxed(0, priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_disable_irq()
123 writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL, in hix5hd2_i2c_enable_irq()
134 writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate()
139 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H); in hix5hd2_i2c_drv_setrate()
140 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L); in hix5hd2_i2c_drv_setrate()
143 writel_relaxed(val, priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate()
198 writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM); in hix5hd2_rw_handle_stop()
208 writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM); in hix5hd2_read_handle()
[all …]
/linux-4.1.27/drivers/spi/
Dspi-qup.c190 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
191 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
195 writel_relaxed(cur_state, controller->base + QUP_STATE); in spi_qup_set_state()
273 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); in spi_qup_fifo_write()
395 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
396 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
397 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
498 writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
499 writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
501 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
[all …]
Dspi-st-ssc4.c117 writel_relaxed(word, spi_st->base + SSC_TBUF); in ssc_write_tx_fifo()
175 writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL); in spi_st_transfer_one()
188 writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN); in spi_st_transfer_one()
195 writel_relaxed(ctl, spi_st->base + SSC_CTL); in spi_st_transfer_one()
253 writel_relaxed(sscbrg, spi_st->base + SSC_BRG); in spi_st_setup()
289 writel_relaxed(var, spi_st->base + SSC_CTL); in spi_st_setup()
310 writel_relaxed(0x0, spi_st->base + SSC_IEN); in spi_st_irq()
366 writel_relaxed(0x0, spi_st->base + SSC_I2C); in spi_st_probe()
369 writel_relaxed(var, spi_st->base + SSC_CTL); in spi_st_probe()
374 writel_relaxed(var, spi_st->base + SSC_CTL); in spi_st_probe()
[all …]
Dspi-rockchip.c206 writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR); in spi_enable_chip()
211 writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR); in spi_set_clk()
237 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR); in get_fifo_len()
242 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR); in get_fifo_len()
292 writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER); in rockchip_spi_set_cs()
354 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); in rockchip_spi_pio_writer()
547 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); in rockchip_spi_config()
549 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1); in rockchip_spi_config()
550 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR); in rockchip_spi_config()
551 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); in rockchip_spi_config()
[all …]
Dspi-omap2-mcspi.c158 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
173 writel_relaxed(val, cs->base + idx); in mcspi_write_cs_reg()
346 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_restore_ctx()
683 writel_relaxed(*tx++, tx_reg); in omap2_mcspi_txrx_pio()
730 writel_relaxed(*tx++, tx_reg); in omap2_mcspi_txrx_pio()
777 writel_relaxed(*tx++, tx_reg); in omap2_mcspi_txrx_pio()
1151 writel_relaxed(0, cs->base in omap2_mcspi_work()
1506 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_resume()
1508 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_resume()
/linux-4.1.27/drivers/watchdog/
Dsa1100_wdt.c57 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_open()
58 writel_relaxed(OSSR_M3, OSSR); in sa1100dog_open()
59 writel_relaxed(OWER_WME, OWER); in sa1100dog_open()
60 writel_relaxed(readl_relaxed(OIER) | OIER_E3, OIER); in sa1100dog_open()
83 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_write()
117 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_ioctl()
132 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_ioctl()
Dsp805_wdt.c140 writel_relaxed(UNLOCK, wdt->base + WDTLOCK); in wdt_config()
141 writel_relaxed(wdt->load_val, wdt->base + WDTLOAD); in wdt_config()
144 writel_relaxed(INT_MASK, wdt->base + WDTINTCLR); in wdt_config()
145 writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + in wdt_config()
149 writel_relaxed(LOCK, wdt->base + WDTLOCK); in wdt_config()
176 writel_relaxed(UNLOCK, wdt->base + WDTLOCK); in wdt_disable()
177 writel_relaxed(0, wdt->base + WDTCONTROL); in wdt_disable()
178 writel_relaxed(LOCK, wdt->base + WDTLOCK); in wdt_disable()
Domap_wdt.c73 writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); in omap_wdt_reload()
86 writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR); in omap_wdt_enable()
90 writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR); in omap_wdt_enable()
100 writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ in omap_wdt_disable()
104 writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ in omap_wdt_disable()
119 writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR); in omap_wdt_set_timer()
146 writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL); in omap_wdt_start()
Dbcm2835_wdt.c53 writel_relaxed(PM_PASSWORD | (SECS_TO_WDOG_TICKS(wdog->timeout) & in bcm2835_wdt_start()
56 writel_relaxed(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | in bcm2835_wdt_start()
68 writel_relaxed(PM_PASSWORD | PM_RSTC_RESET, wdt->base + PM_RSTC); in bcm2835_wdt_stop()
/linux-4.1.27/drivers/gpio/
Dgpio-pxa.c244 writel_relaxed(value, base + GPDR_OFFSET); in pxa_gpio_direction_input()
257 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); in pxa_gpio_direction_output()
266 writel_relaxed(tmp, base + GPDR_OFFSET); in pxa_gpio_direction_output()
280 writel_relaxed(1 << offset, gpio_chip_base(chip) + in pxa_gpio_set()
354 writel_relaxed(grer, c->regbase + GRER_OFFSET); in update_edge_detect()
355 writel_relaxed(gfer, c->regbase + GFER_OFFSET); in update_edge_detect()
382 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
384 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
420 writel_relaxed(gedr, c->regbase + GEDR_OFFSET); in pxa_gpio_demux_handler()
438 writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); in pxa_ack_muxed_gpio()
[all …]
Dgpio-omap.c109 writel_relaxed(l, reg); in omap_set_gpio_direction()
129 writel_relaxed(l, reg); in omap_set_gpio_dataout_reg()
145 writel_relaxed(l, reg); in omap_set_gpio_dataout_mask()
172 writel_relaxed(l, base + reg); in omap_gpio_rmw()
181 writel_relaxed(bank->dbck_enable_mask, in omap_gpio_dbck_enable()
194 writel_relaxed(0, bank->base + bank->regs->debounce_en); in omap_gpio_dbck_disable()
231 writel_relaxed(debounce, reg); in omap2_set_gpio_debounce()
242 writel_relaxed(val, reg); in omap2_set_gpio_debounce()
281 writel_relaxed(bank->context.debounce_en, in omap_clear_gpio_debounce()
286 writel_relaxed(bank->context.debounce, bank->base + in omap_clear_gpio_debounce()
[all …]
Dgpio-mvebu.c211 writel_relaxed(u, mvebu_gpioreg_out(mvchip)); in mvebu_gpio_set()
244 writel_relaxed(u, mvebu_gpioreg_blink(mvchip)); in mvebu_gpio_blink()
265 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); in mvebu_gpio_direction_input()
292 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); in mvebu_gpio_direction_output()
315 writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip)); in mvebu_gpio_irq_ack()
329 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip)); in mvebu_gpio_edge_irq_mask()
343 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip)); in mvebu_gpio_edge_irq_unmask()
357 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); in mvebu_gpio_level_irq_mask()
371 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); in mvebu_gpio_level_irq_unmask()
432 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); in mvebu_gpio_irq_set_type()
[all …]
Dgpio-davinci.c95 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
99 writel_relaxed(temp, &g->dir); in __davinci_direction()
140 writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data); in davinci_gpio_set()
293 writel_relaxed(mask, &g->clr_falling); in gpio_irq_disable()
294 writel_relaxed(mask, &g->clr_rising); in gpio_irq_disable()
308 writel_relaxed(mask, &g->set_falling); in gpio_irq_enable()
310 writel_relaxed(mask, &g->set_rising); in gpio_irq_enable()
353 writel_relaxed(status, &g->intstat); in gpio_irq_handler()
406 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) in gpio_irq_type_unbanked()
408 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) in gpio_irq_type_unbanked()
[all …]
Dgpio-zynq.c206 writel_relaxed(state, gpio->base_addr + reg_offset); in zynq_gpio_set_value()
234 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
263 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
268 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
290 writel_relaxed(BIT(bank_pin_num), in zynq_gpio_irq_mask()
310 writel_relaxed(BIT(bank_pin_num), in zynq_gpio_irq_unmask()
329 writel_relaxed(BIT(bank_pin_num), in zynq_gpio_irq_ack()
418 writel_relaxed(int_type, in zynq_gpio_set_irq_type()
420 writel_relaxed(int_pol, in zynq_gpio_set_irq_type()
422 writel_relaxed(int_any, in zynq_gpio_set_irq_type()
[all …]
Dgpio-spear-spics.c80 writel_relaxed(tmp, spics->base + spics->perip_cfg); in spics_set_value()
105 writel_relaxed(tmp, spics->base + spics->perip_cfg); in spics_request()
120 writel_relaxed(tmp, spics->base + spics->perip_cfg); in spics_free()
/linux-4.1.27/arch/arm/mach-imx/
Dgpc.c59 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | in imx_gpc_set_arm_power_up_timing()
65 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | in imx_gpc_set_arm_power_down_timing()
71 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); in imx_gpc_set_arm_power_in_lpm()
85 writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4); in imx_gpc_pre_suspend()
98 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); in imx_gpc_post_resume()
124 writel_relaxed(~0, reg_imr1 + i * 4); in imx_gpc_mask_all()
135 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); in imx_gpc_restore_all()
146 writel_relaxed(val, reg); in imx_gpc_hwirq_unmask()
157 writel_relaxed(val, reg); in imx_gpc_hwirq_mask()
267 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); in imx_gpc_init()
[all …]
Dsrc.c63 writel_relaxed(val, src_base + SRC_SCR); in imx_src_reset_module()
95 writel_relaxed(val, src_base + SRC_SCR); in imx_enable_cpu()
102 writel_relaxed(virt_to_phys(jump_addr), in imx_set_cpu_jump()
115 writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); in imx_set_cpu_arg()
140 writel_relaxed(val, src_base + SRC_SCR); in imx_src_init()
Dclk-pfd.c46 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); in clk_pfd_enable()
55 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); in clk_pfd_disable()
106 writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR); in clk_pfd_set_rate()
107 writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET); in clk_pfd_set_rate()
Dclk-pllv3.c80 writel_relaxed(val, pll->base); in clk_pllv3_prepare()
95 writel_relaxed(val, pll->base); in clk_pllv3_unprepare()
132 writel_relaxed(val, pll->base); in clk_pllv3_set_rate()
186 writel_relaxed(val, pll->base); in clk_pllv3_sys_set_rate()
256 writel_relaxed(val, pll->base); in clk_pllv3_av_set_rate()
257 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); in clk_pllv3_av_set_rate()
258 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); in clk_pllv3_av_set_rate()
Dpm-imx6.c205 writel_relaxed(val, ccm_base + CGPR); in imx6q_set_int_mem_clk_lpm()
222 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
249 writel_relaxed(val, ccm_base + CLPCR); in imx6q_enable_wb()
255 writel_relaxed(val, ccm_base + CCR); in imx6q_enable_wb()
317 writel_relaxed(val, ccm_base + CLPCR); in imx6q_set_lpm()
Dmmdc.c51 writel_relaxed(val, reg); in imx_mmdc_probe()
Dsystem.c123 writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); in imx_init_l2cache()
Dplatsmp.c121 writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1); in ls1021a_smp_prepare_cpus()
Dclk-imx6sl.c155 writel_relaxed(val, anatop_base + PLL_ARM); in imx6sl_enable_pll_arm()
159 writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM); in imx6sl_enable_pll_arm()
177 writel_relaxed(arm_div_for_wait, ccm_base + CACRR); in imx6sl_set_wait_clk()
179 writel_relaxed(saved_arm_div, ccm_base + CACRR); in imx6sl_set_wait_clk()
/linux-4.1.27/arch/arm/mach-omap2/
Dsram.c67 writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ in is_sram_locked()
68 writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */ in is_sram_locked()
69 writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */ in is_sram_locked()
72 writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */ in is_sram_locked()
73 writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */ in is_sram_locked()
74 writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */ in is_sram_locked()
75 writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2); in is_sram_locked()
76 writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0); in is_sram_locked()
Domap-wakeupgen.c71 writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 + in wakeupgen_writel()
77 writel_relaxed(val, sar_base + offset + (idx * 4)); in sar_writel()
222 writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET); in omap4_irq_save_context()
224 writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET); in omap4_irq_save_context()
228 writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET); in omap4_irq_save_context()
230 writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET); in omap4_irq_save_context()
235 writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET); in omap4_irq_save_context()
255 writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET); in omap5_irq_save_context()
257 writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET); in omap5_irq_save_context()
262 writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); in omap5_irq_save_context()
[all …]
Domap4-common.c57 writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL); in gic_dist_disable()
63 writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL); in gic_dist_enable()
83 writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT); in gic_timer_retrigger()
85 writel_relaxed(1, twd_base + TWD_TIMER_COUNTER); in gic_timer_retrigger()
87 writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL); in gic_timer_retrigger()
Domap-mpuss-lowpower.c124 writel_relaxed(addr, pm_info->wkup_sar_addr); in set_cpu_wakeup_addr()
150 writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr); in scu_pwrst_prepare()
189 writel_relaxed(save_state, pm_info->l2x0_sar_addr); in l2x0_pwrst_prepare()
202 writel_relaxed(l2x0_saved_regs.aux_ctrl, in save_l2x0_context()
204 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, in save_l2x0_context()
424 writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0, in omap4_mpuss_init()
Domap-smp.c103 writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0); in omap4_boot_secondary()
236 writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup), in omap4_smp_prepare_cpus()
239 writel_relaxed(virt_to_phys(omap5_secondary_startup), in omap4_smp_prepare_cpus()
Dwd_timer.c52 writel_relaxed(0xAAAA, base + OMAP_WDT_SPR); in omap2_wd_timer_disable()
56 writel_relaxed(0x5555, base + OMAP_WDT_SPR); in omap2_wd_timer_disable()
Dsdrc2xxx.c106 writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP); in omap2xxx_sdrc_reprogram()
108 writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP); in omap2xxx_sdrc_reprogram()
Dsdrc.h34 writel_relaxed(val, OMAP_SDRC_REGADDR(reg)); in sdrc_write_reg()
46 writel_relaxed(val, OMAP_SMS_REGADDR(reg)); in sms_write_reg()
Domap-hotplug.c42 writel_relaxed(0, base + OMAP_AUX_CORE_BOOT_0); in omap4_cpu_die()
Dprcm_mpu44xx.c38 writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); in omap4_prcm_mpu_write_inst_reg()
Domap_phy_internal.c62 writel_relaxed(PHY_PD, ctrl_base + CONTROL_DEV_CONF); in omap4430_phy_power_down()
Dcm2xxx_3xxx.h60 writel_relaxed(val, cm_base + module + idx); in omap2_cm_write_mod_reg()
Dcontrol.c210 writel_relaxed(val, omap2_ctrl_base + offset); in omap_ctrl_writel()
242 writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); in omap3_ctrl_write_boot_mode()
305 writel_relaxed(0x0, (v_addr + offset)); in omap3_clear_scratchpad_contents()
Dprminst44xx.c73 writel_relaxed(val, _prm_bases[part] + inst + idx); in omap4_prminst_write_inst_reg()
Dprm2xxx_3xxx.h63 writel_relaxed(val, prm_base + module + idx); in omap2_prm_write_mod_reg()
/linux-4.1.27/drivers/mfd/
Dmcp-sa11x0.c56 writel_relaxed(m->mccr0, MCCR0(m)); in mcp_sa11x0_set_telecom_divisor()
68 writel_relaxed(m->mccr0, MCCR0(m)); in mcp_sa11x0_set_audio_divisor()
84 writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m)); in mcp_sa11x0_write()
111 writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m)); in mcp_sa11x0_read()
133 writel_relaxed(m->mccr0, MCCR0(m)); in mcp_sa11x0_enable()
141 writel_relaxed(m->mccr0, MCCR0(m)); in mcp_sa11x0_disable()
211 writel_relaxed(-1, MCSR(m)); in mcp_sa11x0_probe()
212 writel_relaxed(m->mccr1, MCCR1(m)); in mcp_sa11x0_probe()
213 writel_relaxed(m->mccr0, MCCR0(m)); in mcp_sa11x0_probe()
279 writel_relaxed(m->mccr1, MCCR1(m)); in mcp_sa11x0_resume()
[all …]
Dqcom_rpm.c397 writel_relaxed(buf[i], RPM_REQ_REG(rpm, res->target_id + i)); in qcom_rpm_write()
401 writel_relaxed(sel_mask[i], in qcom_rpm_write()
405 writel_relaxed(BIT(state), RPM_CTRL_REG(rpm, RPM_REQUEST_CONTEXT)); in qcom_rpm_write()
430 writel_relaxed(0, RPM_CTRL_REG(rpm, RPM_ACK_SELECTOR + i)); in qcom_rpm_ack_interrupt()
/linux-4.1.27/drivers/pinctrl/
Dpinctrl-at91.c365 writel_relaxed(mask, pio + PIO_IDR); in at91_mux_disable_interrupt()
376 writel_relaxed(mask, pio + PIO_PPDDR); in at91_mux_set_pullup()
378 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); in at91_mux_set_pullup()
388 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); in at91_mux_set_multidrive()
393 writel_relaxed(mask, pio + PIO_ASR); in at91_mux_set_A_periph()
398 writel_relaxed(mask, pio + PIO_BSR); in at91_mux_set_B_periph()
404 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, in at91_mux_pio3_set_A_periph()
406 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, in at91_mux_pio3_set_A_periph()
412 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, in at91_mux_pio3_set_B_periph()
414 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, in at91_mux_pio3_set_B_periph()
[all …]
/linux-4.1.27/arch/arm/kernel/
Dsmp_twd.c48 writel_relaxed(DIV_ROUND_CLOSEST(twd_timer_rate, HZ), in twd_set_mode()
61 writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL); in twd_set_mode()
71 writel_relaxed(evt, twd_base + TWD_TIMER_COUNTER); in twd_set_next_event()
72 writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL); in twd_set_next_event()
86 writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT); in twd_timer_ack()
214 writel_relaxed(0x1, twd_base + TWD_TIMER_CONTROL); in twd_calibrate_rate()
217 writel_relaxed(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER); in twd_calibrate_rate()
280 writel_relaxed(0, twd_base + TWD_TIMER_CONTROL); in twd_timer_setup()
293 writel_relaxed(0, twd_base + TWD_TIMER_CONTROL); in twd_timer_setup()
Dsmp_scu.c49 writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30); in scu_enable()
65 writel_relaxed(scu_ctrl, scu_base + SCU_CTRL); in scu_enable()
Dio.c22 writel_relaxed(value, reg); in atomic_io_modify_relaxed()
/linux-4.1.27/drivers/hsi/controllers/
Domap_ssi_port.c267 writel_relaxed(d_addr, gdd + SSI_GDD_CDSA_REG(lch)); in ssi_start_dma()
268 writel_relaxed(s_addr, gdd + SSI_GDD_CSSA_REG(lch)); in ssi_start_dma()
275 writel_relaxed(tmp, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG); in ssi_start_dma()
463 writel_relaxed(SSI_MODE_SLEEP, sst + SSI_SST_MODE_REG); in ssi_setup()
464 writel_relaxed(SSI_MODE_SLEEP, ssr + SSI_SSR_MODE_REG); in ssi_setup()
468 writel_relaxed(31, sst + SSI_SST_FRAMESIZE_REG); in ssi_setup()
469 writel_relaxed(div, sst + SSI_SST_DIVISOR_REG); in ssi_setup()
470 writel_relaxed(cl->tx_cfg.num_hw_channels, sst + SSI_SST_CHANNELS_REG); in ssi_setup()
471 writel_relaxed(cl->tx_cfg.arb_mode, sst + SSI_SST_ARBMODE_REG); in ssi_setup()
472 writel_relaxed(cl->tx_cfg.mode, sst + SSI_SST_MODE_REG); in ssi_setup()
[all …]
Domap_ssi.c191 writel_relaxed(SSI_WAKE(0), in ssi_waketest()
194 writel_relaxed(SSI_WAKE(0), in ssi_waketest()
215 writel_relaxed(val, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG); in ssi_gdd_complete()
243 writel_relaxed(val, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); in ssi_gdd_complete()
265 writel_relaxed(status_reg, sys + SSI_GDD_MPU_IRQ_STATUS_REG); in ssi_gdd_tasklet()
417 writel_relaxed(SSI_SOFTRESET, omap_ssi->sys + SSI_SYSCONFIG_REG); in ssi_hw_init()
429 writel_relaxed(SSI_SWRESET, omap_ssi->gdd + SSI_GDD_GRST_REG); in ssi_hw_init()
435 writel_relaxed(val, omap_ssi->sys + SSI_SYSCONFIG_REG); in ssi_hw_init()
437 writel_relaxed(SSI_CLK_AUTOGATING_ON, omap_ssi->sys + SSI_GDD_GCR_REG); in ssi_hw_init()
584 writel_relaxed(omap_ssi->gdd_gcr, omap_ssi->gdd + SSI_GDD_GCR_REG); in omap_ssi_runtime_resume()
/linux-4.1.27/drivers/media/rc/
Dir-hix5hd2.c94 writel_relaxed(0x01, priv->base + IR_ENABLE); in hix5hd2_ir_config()
112 writel_relaxed(val, priv->base + IR_CONFIG); in hix5hd2_ir_config()
114 writel_relaxed(0x00, priv->base + IR_INTM); in hix5hd2_ir_config()
116 writel_relaxed(0x01, priv->base + IR_START); in hix5hd2_ir_config()
154 writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC); in hix5hd2_ir_rx_interrupt()
183 writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC); in hix5hd2_ir_rx_interrupt()
185 writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC); in hix5hd2_ir_rx_interrupt()
310 writel_relaxed(0x01, priv->base + IR_ENABLE); in hix5hd2_ir_resume()
311 writel_relaxed(0x00, priv->base + IR_INTM); in hix5hd2_ir_resume()
312 writel_relaxed(0xff, priv->base + IR_INTC); in hix5hd2_ir_resume()
[all …]
/linux-4.1.27/arch/arm/mach-pxa/
Dreset.c81 writel_relaxed(OWER_WME, OWER); in do_hw_reset()
82 writel_relaxed(OSSR_M3, OSSR); in do_hw_reset()
84 writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3); in do_hw_reset()
90 writel_relaxed(MDREFR_SLFRSH, MDREFR); in do_hw_reset()
/linux-4.1.27/drivers/clk/hisilicon/
Dclk-hix5hd2.c179 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
181 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
186 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare()
191 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare()
196 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare()
208 writel_relaxed(val, clk->ctrl_reg); in clk_ether_unprepare()
224 writel_relaxed(val, clk->ctrl_reg); in clk_complex_enable()
229 writel_relaxed(val, clk->phy_reg); in clk_complex_enable()
242 writel_relaxed(val, clk->ctrl_reg); in clk_complex_disable()
247 writel_relaxed(val, clk->phy_reg); in clk_complex_disable()
Dclkgate-separated.c58 writel_relaxed(reg, sclk->enable); in clkgate_separated_enable()
75 writel_relaxed(reg, sclk->enable + CLKGATE_SEPERATED_DISABLE); in clkgate_separated_disable()
Dclk-hi3620.c383 writel_relaxed(val, mclk->clken_reg); in mmc_clk_set_timing()
387 writel_relaxed(val, mclk->sam_reg); in mmc_clk_set_timing()
391 writel_relaxed(val, mclk->drv_reg); in mmc_clk_set_timing()
395 writel_relaxed(val, mclk->div_reg); in mmc_clk_set_timing()
399 writel_relaxed(val, mclk->clken_reg); in mmc_clk_set_timing()
/linux-4.1.27/drivers/clk/mxs/
Dclk-imx28.c79 writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR); in mxs_saif_clkmux_select()
80 writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET); in mxs_saif_clkmux_select()
90 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); in clk_misc_init()
93 writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET); in clk_misc_init()
96 writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR); in clk_misc_init()
101 writel_relaxed(val, SAIF0); in clk_misc_init()
105 writel_relaxed(val, SAIF1); in clk_misc_init()
110 writel_relaxed(val, ENET); in clk_misc_init()
116 writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR); in clk_misc_init()
125 writel_relaxed(val, FRAC0); in clk_misc_init()
Dclk-pll.c43 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
54 writel_relaxed(1 << pll->power, pll->base + CLR); in clk_pll_unprepare()
61 writel_relaxed(1 << 31, pll->base + CLR); in clk_pll_enable()
70 writel_relaxed(1 << 31, pll->base + SET); in clk_pll_disable()
Dclk-imx23.c56 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); in clk_misc_init()
59 writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR); in clk_misc_init()
64 writel_relaxed(val, SAIF); in clk_misc_init()
70 writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR); in clk_misc_init()
76 writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR); in clk_misc_init()
77 writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET); in clk_misc_init()
Dclk-ref.c42 writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR); in clk_ref_enable()
51 writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET); in clk_ref_disable()
113 writel_relaxed(val, ref->reg); in clk_ref_set_rate()
Dclk-frac.c98 writel_relaxed(val, frac->reg); in clk_frac_set_rate()
/linux-4.1.27/drivers/clk/tegra/
Dclk-periph-gate.c34 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
36 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
41 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
88 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
89 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
91 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
Dclk-pll-out.c55 writel_relaxed(val, pll_out->reg); in clk_pll_out_enable()
77 writel_relaxed(val, pll_out->reg); in clk_pll_out_disable()
Dclk-tegra114.c997 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra114_utmi_param_configure()
1015 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
1022 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1027 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
1036 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1043 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1352 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); in tegra114_clock_tune_cpu_trimmers_high()
1379 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); in tegra114_clock_tune_cpu_trimmers_low()
1401 writel_relaxed(r, clk_base + CPU_FINETRIM_R); in tegra114_clock_tune_cpu_trimmers_init()
1410 writel_relaxed(dr, clk_base + CPU_FINETRIM_DR); in tegra114_clock_tune_cpu_trimmers_init()
[all …]
Dclk-super.c106 writel_relaxed(val, mux->reg); in clk_super_set_parent()
115 writel_relaxed(val, mux->reg); in clk_super_set_parent()
Dclk.c155 writel_relaxed(BIT(id % 32), in tegra_clk_rst_assert()
164 writel_relaxed(BIT(id % 32), in tegra_clk_rst_deassert()
Dclk-tegra-pmc.c117 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); in tegra_pmc_clk_init()
Dclk-tegra124.c1057 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra124_utmi_param_configure()
1075 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
1082 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra124_utmi_param_configure()
1087 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
1096 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra124_utmi_param_configure()
1103 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra124_utmi_param_configure()
/linux-4.1.27/drivers/hwtracing/coresight/
Dcoresight-etb10.c118 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); in etb_enable_hw()
121 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG); in etb_enable_hw()
124 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); in etb_enable_hw()
126 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); in etb_enable_hw()
128 writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG); in etb_enable_hw()
129 writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER, in etb_enable_hw()
132 writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG); in etb_enable_hw()
165 writel_relaxed(ffcr, drvdata->base + ETB_FFCR); in etb_disable_hw()
168 writel_relaxed(ffcr, drvdata->base + ETB_FFCR); in etb_disable_hw()
177 writel_relaxed(0x0, drvdata->base + ETB_CTL_REG); in etb_disable_hw()
[all …]
Dcoresight-tmc.c153 writel_relaxed(ffcr, drvdata->base + TMC_FFCR); in tmc_flush_and_stop()
155 writel_relaxed(ffcr, drvdata->base + TMC_FFCR); in tmc_flush_and_stop()
169 writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL); in tmc_enable_hw()
174 writel_relaxed(0x0, drvdata->base + TMC_CTL); in tmc_disable_hw()
184 writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); in tmc_etb_enable_hw()
185 writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | in tmc_etb_enable_hw()
190 writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG); in tmc_etb_enable_hw()
205 writel_relaxed(drvdata->size / 4, drvdata->base + TMC_RSZ); in tmc_etr_enable_hw()
206 writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); in tmc_etr_enable_hw()
210 writel_relaxed(axictl, drvdata->base + TMC_AXICTL); in tmc_etr_enable_hw()
[all …]
Dcoresight-priv.h42 writel_relaxed(0x0, addr + CORESIGHT_LAR); in CS_LOCK()
49 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR); in CS_UNLOCK()
Dcoresight-funnel.c60 writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL); in funnel_enable_hw()
61 writel_relaxed(drvdata->priority, drvdata->base + FUNNEL_PRICTL); in funnel_enable_hw()
90 writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL); in funnel_disable_hw()
Dcoresight-tpiu.c92 writel_relaxed(0x0, drvdata->base + TPIU_FFCR); in tpiu_disable_hw()
94 writel_relaxed(FFCR_FON_MAN, drvdata->base + TPIU_FFCR); in tpiu_disable_hw()
/linux-4.1.27/drivers/dma/
Dsirf-dma.c130 writel_relaxed(sdesc->width, sdma->base + SIRFSOC_DMA_WIDTH_0 + in sirfsoc_dma_execute()
132 writel_relaxed(cid | (schan->mode << SIRFSOC_DMA_MODE_CTRL_BIT) | in sirfsoc_dma_execute()
135 writel_relaxed(sdesc->xlen, sdma->base + cid * 0x10 + in sirfsoc_dma_execute()
137 writel_relaxed(sdesc->ylen, sdma->base + cid * 0x10 + in sirfsoc_dma_execute()
139 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) | in sirfsoc_dma_execute()
168 writel_relaxed(1 << ch, sdma->base + SIRFSOC_DMA_CH_INT); in sirfsoc_dma_irq()
311 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) & in sirfsoc_dma_terminate_all()
313 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL) in sirfsoc_dma_terminate_all()
317 writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_INT_EN_CLR); in sirfsoc_dma_terminate_all()
318 writel_relaxed((1 << cid) | 1 << (cid + 16), in sirfsoc_dma_terminate_all()
[all …]
Dqcom_bam_dma.c430 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_RST)); in bam_reset_channel()
431 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_RST)); in bam_reset_channel()
459 writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)), in bam_chan_init_hw()
461 writel_relaxed(BAM_DESC_FIFO_SIZE, in bam_chan_init_hw()
465 writel_relaxed(P_DEFAULT_IRQS_EN, in bam_chan_init_hw()
471 writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); in bam_chan_init_hw()
481 writel_relaxed(val, bam_addr(bdev, bchan->id, BAM_P_CTRL)); in bam_chan_init_hw()
548 writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); in bam_free_chan()
551 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_IRQ_EN)); in bam_free_chan()
699 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_HALT)); in bam_pause()
[all …]
Dk3dma.c122 writel_relaxed(val, phy->base + CX_CFG); in k3_dma_pause_dma()
126 writel_relaxed(val, phy->base + CX_CFG); in k3_dma_pause_dma()
137 writel_relaxed(val, d->base + INT_TC1_RAW); in k3_dma_terminate_chan()
138 writel_relaxed(val, d->base + INT_ERR1_RAW); in k3_dma_terminate_chan()
139 writel_relaxed(val, d->base + INT_ERR2_RAW); in k3_dma_terminate_chan()
144 writel_relaxed(hw->lli, phy->base + CX_LLI); in k3_dma_set_desc()
145 writel_relaxed(hw->count, phy->base + CX_CNT); in k3_dma_set_desc()
146 writel_relaxed(hw->saddr, phy->base + CX_SRC); in k3_dma_set_desc()
147 writel_relaxed(hw->daddr, phy->base + CX_DST); in k3_dma_set_desc()
148 writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG); in k3_dma_set_desc()
[all …]
Dste_dma40_ll.c342 writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0); in d40_log_lli_lcpa_write()
343 writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1); in d40_log_lli_lcpa_write()
344 writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2); in d40_log_lli_lcpa_write()
345 writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3); in d40_log_lli_lcpa_write()
355 writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02); in d40_log_lli_lcla_write()
356 writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13); in d40_log_lli_lcla_write()
357 writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02); in d40_log_lli_lcla_write()
358 writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13); in d40_log_lli_lcla_write()
Dimx-sdma.c499 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
500 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
501 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
529 writel_relaxed(ret, sdma->regs + SDMA_H_INTR); in sdma_run_channel0()
536 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
585 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_enable()
597 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_disable()
675 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); in sdma_int_handler()
848 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); in sdma_disable_channel()
923 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); in sdma_set_channel_priority()
[all …]
Dsa11x0-dma.c216 writel_relaxed(sg->addr, base + dbsx); in sa11x0_dma_start_sg()
217 writel_relaxed(sg->len, base + dbtx); in sa11x0_dma_start_sg()
264 writel_relaxed(dcsr & (DCSR_ERROR | DCSR_DONEA | DCSR_DONEB), in sa11x0_dma_irq()
320 writel_relaxed(DCSR_RUN | DCSR_STRTA | DCSR_STRTB, in sa11x0_dma_start_txd()
322 writel_relaxed(txd->ddar, p->base + DMA_DDAR); in sa11x0_dma_start_txd()
926 writel_relaxed(DCSR_RUN | DCSR_IE | DCSR_ERROR | in sa11x0_dma_probe()
929 writel_relaxed(0, p->base + DMA_DDAR); in sa11x0_dma_probe()
1049 writel_relaxed(txd->ddar, p->base + DMA_DDAR); in sa11x0_dma_resume()
1051 writel_relaxed(p->dbs[0], p->base + DMA_DBSA); in sa11x0_dma_resume()
1052 writel_relaxed(p->dbt[0], p->base + DMA_DBTA); in sa11x0_dma_resume()
[all …]
Ds3c24xx-dma.c475 writel_relaxed((cdata->chansel << 1) | in s3c24xx_dma_start_next_sg()
488 writel_relaxed(0, phy->base + S3C24XX_DMAREQSEL); in s3c24xx_dma_start_next_sg()
491 writel_relaxed(dsg->src_addr, phy->base + S3C24XX_DISRC); in s3c24xx_dma_start_next_sg()
492 writel_relaxed(txd->disrcc, phy->base + S3C24XX_DISRCC); in s3c24xx_dma_start_next_sg()
493 writel_relaxed(dsg->dst_addr, phy->base + S3C24XX_DIDST); in s3c24xx_dma_start_next_sg()
494 writel_relaxed(txd->didstc, phy->base + S3C24XX_DIDSTC); in s3c24xx_dma_start_next_sg()
495 writel_relaxed(dcon, phy->base + S3C24XX_DCON); in s3c24xx_dma_start_next_sg()
Dmv_xor.c90 writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan)); in mv_chan_set_next_descriptor()
97 writel_relaxed(val, XOR_INTR_MASK(chan)); in mv_chan_unmask_interrupts()
114 writel_relaxed(val, XOR_INTR_CAUSE(chan)); in mv_xor_device_clear_eoc_cause()
120 writel_relaxed(val, XOR_INTR_CAUSE(chan)); in mv_xor_device_clear_err_status()
153 writel_relaxed(config, XOR_CONFIG(chan)); in mv_set_mode()
/linux-4.1.27/arch/arm/mach-mvebu/
Dkirkwood-pm.c32 writel_relaxed(~0, memory_pm_ctrl); in kirkwood_low_power()
35 writel_relaxed(0x7, ddr_operation_base); in kirkwood_low_power()
44 writel_relaxed(mem_pm_ctrl, memory_pm_ctrl); in kirkwood_low_power()
/linux-4.1.27/arch/arm/mm/
Dcache-l2x0.c80 writel_relaxed(val, base + reg); in l2c_write_sec()
95 writel_relaxed(l2x0_way_mask, reg); in __l2c_op_way()
104 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + in l2c_unlock()
106 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + in l2c_unlock()
143 writel_relaxed(0, base + sync_reg_offset); in l2c_enable()
185 writel_relaxed(0, base + sync_reg_offset); in __l2c210_cache_sync()
192 writel_relaxed(start, reg); in __l2c210_op_pa_range()
203 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); in l2c210_inv_range()
209 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); in l2c210_inv_range()
278 writel_relaxed(0, base + L2X0_CACHE_SYNC); in __l2c220_cache_sync()
[all …]
/linux-4.1.27/drivers/clk/mmp/
Dclk-apbc.c53 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
65 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
78 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
100 writel_relaxed(data, apbc->base); in clk_apbc_unprepare()
112 writel_relaxed(data, apbc->base); in clk_apbc_unprepare()
Dclk-apmu.c40 writel_relaxed(data, apmu->base); in clk_apmu_enable()
58 writel_relaxed(data, apmu->base); in clk_apmu_disable()
/linux-4.1.27/drivers/video/fbdev/omap2/dss/
Dpll.c268 writel_relaxed(l, base + PLL_CONFIGURATION1); in dss_pll_write_config_type_a()
277 writel_relaxed(l, base + PLL_CONFIGURATION3); in dss_pll_write_config_type_a()
302 writel_relaxed(l, base + PLL_CONFIGURATION2); in dss_pll_write_config_type_a()
304 writel_relaxed(1, base + PLL_GO); /* PLL_GO */ in dss_pll_write_config_type_a()
325 writel_relaxed(l, base + PLL_CONFIGURATION2); in dss_pll_write_config_type_a()
351 writel_relaxed(l, base + PLL_CONFIGURATION1); in dss_pll_write_config_type_b()
365 writel_relaxed(l, base + PLL_CONFIGURATION2); in dss_pll_write_config_type_b()
369 writel_relaxed(l, base + PLL_CONFIGURATION3); in dss_pll_write_config_type_b()
374 writel_relaxed(l, base + PLL_CONFIGURATION4); in dss_pll_write_config_type_b()
376 writel_relaxed(1, base + PLL_GO); /* PLL_GO */ in dss_pll_write_config_type_b()
Dvideo-pll.c34 writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
/linux-4.1.27/drivers/iommu/
Darm-smmu.c534 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); in __arm_smmu_tlb_sync()
563 writel_relaxed(ARM_SMMU_CB_ASID(cfg), in arm_smmu_tlb_inv_context()
567 writel_relaxed(ARM_SMMU_CB_VMID(cfg), in arm_smmu_tlb_inv_context()
590 writel_relaxed(iova, reg); in arm_smmu_tlb_inv_range_nosync()
607 writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg); in arm_smmu_tlb_inv_range_nosync()
689 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); in arm_smmu_context_fault()
743 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); in arm_smmu_init_context_bank()
761 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); in arm_smmu_init_context_bank()
766 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); in arm_smmu_init_context_bank()
769 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); in arm_smmu_init_context_bank()
[all …]
/linux-4.1.27/drivers/gpu/drm/armada/
Darmada_crtc.c100 writel_relaxed(val | regs->val, reg); in armada_drm_crtc_update_regs()
145 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL); in armada_drm_crtc_update()
382 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH); in armada_drm_crtc_irq()
383 writel_relaxed(dcrtc->v[i].spu_v_h_total, in armada_drm_crtc_irq()
389 writel_relaxed(val, base + LCD_SPU_ADV_REG); in armada_drm_crtc_irq()
393 writel_relaxed(dcrtc->cursor_hw_pos, in armada_drm_crtc_irq()
395 writel_relaxed(dcrtc->cursor_hw_sz, in armada_drm_crtc_irq()
427 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_irq()
539 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL); in armada_drm_crtc_mode_set()
665 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | in armada_drm_crtc_disable()
[all …]
Darmada_overlay.c53 writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y); in armada_ovl_update_attr()
54 writel_relaxed(prop->colorkey_ug, dcrtc->base + LCD_SPU_COLORKEY_U); in armada_ovl_update_attr()
55 writel_relaxed(prop->colorkey_vb, dcrtc->base + LCD_SPU_COLORKEY_V); in armada_ovl_update_attr()
57 writel_relaxed(prop->brightness << 16 | prop->contrast, in armada_ovl_update_attr()
60 writel_relaxed(prop->saturation << 16, in armada_ovl_update_attr()
62 writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE); in armada_ovl_update_attr()
139 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN); in armada_plane_update()
142 writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN); in armada_plane_update()
145 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN); in armada_plane_update()
Darmada_drm.h29 writel_relaxed(v, ptr); in armada_updatel()
/linux-4.1.27/arch/arm/mach-vexpress/
Ddcscb.c51 writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cpu_powerup()
67 writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cluster_powerup()
80 writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cpu_powerdown_prepare()
92 writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cluster_powerdown_prepare()
Dspc.c142 writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK); in ve_spc_global_wakeup_irq()
175 writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK); in ve_spc_cpu_wakeup_irq()
197 writel_relaxed(addr, baseaddr); in ve_spc_set_resume_addr()
218 writel_relaxed(enable, info->baseaddr + pwdrn_reg); in ve_spc_powerdown()
/linux-4.1.27/drivers/input/keyboard/
Dspear-keyboard.c97 writel_relaxed(0, kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
121 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
122 writel_relaxed(1, kbd->io_base + STATUS_REG); in spear_kbd_open()
127 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
140 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_close()
323 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_suspend()
327 writel_relaxed(mode_ctl_reg & ~MODE_CTL_START_SCAN, in spear_kbd_suspend()
365 writel_relaxed(kbd->mode_ctl_reg, kbd->io_base + MODE_CTL_REG); in spear_kbd_resume()
/linux-4.1.27/drivers/mailbox/
Dmailbox-altera.c95 writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_rx_intmask()
107 writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_tx_intmask()
117 writel_relaxed(MBOX_MAGIC, mbox->mbox_base + MAILBOX_PTR_REG); in altera_mbox_is_sender()
121 writel_relaxed(0, mbox->mbox_base + MAILBOX_PTR_REG); in altera_mbox_is_sender()
238 writel_relaxed(udata[MBOX_PTR], mbox->mbox_base + MAILBOX_PTR_REG); in altera_mbox_send_data()
239 writel_relaxed(udata[MBOX_CMD], mbox->mbox_base + MAILBOX_CMD_REG); in altera_mbox_send_data()
281 writel_relaxed(~0, mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_shutdown()
Darm_mhu.c63 writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS); in mhu_rx_interrupt()
81 writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS); in mhu_send_data()
93 writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS); in mhu_startup()
/linux-4.1.27/arch/arm/mach-spear/
Dspear13xx.c41 writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL); in spear13xx_l2x0_init()
47 writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); in spear13xx_l2x0_init()
48 writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); in spear13xx_l2x0_init()
Drestart.c29 writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES); in spear_restart()
/linux-4.1.27/arch/arm/mach-bcm/
Dboard_bcm2835.c63 writel_relaxed(10 | PM_PASSWORD, wdt_regs + PM_WDOG); in bcm2835_restart()
67 writel_relaxed(val, wdt_regs + PM_RSTC); in bcm2835_restart()
90 writel_relaxed(val, wdt_regs + PM_RSTS); in bcm2835_power_off()
Dbcm_kona_smc.c151 writel_relaxed(data->arg0, args++); in __bcm_kona_smc()
152 writel_relaxed(data->arg1, args++); in __bcm_kona_smc()
153 writel_relaxed(data->arg2, args++); in __bcm_kona_smc()
Dplatsmp-brcmstb.c135 writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg); in cpu_rst_cfg_set()
141 writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs); in cpu_set_boot_addr()
142 writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs); in cpu_set_boot_addr()
Dkona_smp.c178 writel_relaxed(boot_val, boot_reg); in bcm_boot_secondary()
/linux-4.1.27/drivers/thermal/
Drockchip_thermal.c244 writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_HIGH), in rk_tsadcv2_initialize()
247 writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_LOW), in rk_tsadcv2_initialize()
250 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); in rk_tsadcv2_initialize()
251 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, in rk_tsadcv2_initialize()
253 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, in rk_tsadcv2_initialize()
255 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, in rk_tsadcv2_initialize()
264 writel_relaxed(val & TSADCV2_INT_PD_CLEAR, regs + TSADCV2_INT_PD); in rk_tsadcv2_irq_ack()
277 writel_relaxed(val, regs + TSADCV2_AUTO_CON); in rk_tsadcv2_control()
299 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn)); in rk_tsadcv2_tshut_temp()
303 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON); in rk_tsadcv2_tshut_temp()
[all …]
Dspear_thermal.c67 writel_relaxed(actual_mask & ~stdev->flags, stdev->thermal_base); in spear_thermal_suspend()
91 writel_relaxed(actual_mask | stdev->flags, stdev->thermal_base); in spear_thermal_resume()
138 writel_relaxed(stdev->flags, stdev->thermal_base); in spear_thermal_probe()
171 writel_relaxed(actual_mask & ~stdev->flags, stdev->thermal_base); in spear_thermal_exit()
/linux-4.1.27/arch/arm/mach-ux500/
Dcache-l2x0.c28 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE + in ux500_l2x0_unlock()
30 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE + in ux500_l2x0_unlock()
/linux-4.1.27/drivers/clk/ti/
Dfapll.c102 writel_relaxed(v, fd->base); in ti_fapll_set_bypass()
113 writel_relaxed(v, fd->base); in ti_fapll_clear_bypass()
142 writel_relaxed(v, fd->base); in ti_fapll_enable()
154 writel_relaxed(v, fd->base); in ti_fapll_disable()
262 writel_relaxed(v, fd->base); in ti_fapll_set_rate()
286 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); in ti_fapll_synth_enable()
297 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); in ti_fapll_synth_disable()
402 writel_relaxed(v, synth->freq); in ti_fapll_synth_set_frac_rate()
475 writel_relaxed(v, synth->div); in ti_fapll_synth_set_rate()
/linux-4.1.27/arch/arm/mach-highbank/
Dsysregs.h44 writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu)); in highbank_set_core_pwr()
53 writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu)); in highbank_clear_core_pwr()
/linux-4.1.27/arch/arm/mach-picoxcell/
Dcommon.c74 writel_relaxed(WDT_CTRL_REG_EN_MASK, wdt_regs + WDT_CTRL_REG_OFFS); in picoxcell_wdt_restart()
75 writel_relaxed(0, wdt_regs + WDT_TIMEOUT_REG_OFFS); in picoxcell_wdt_restart()
/linux-4.1.27/drivers/pinctrl/spear/
Dpinctrl-plgpio.c95 writel_relaxed(val | (1 << offset), reg_off); in plgpio_reg_set()
104 writel_relaxed(val & ~(1 << offset), reg_off); in plgpio_reg_reset()
345 writel_relaxed(val | (1 << offset), reg_off); in plgpio_irq_set_type()
347 writel_relaxed(val & ~(1 << offset), reg_off); in plgpio_irq_set_type()
379 writel_relaxed(~pending, plgpio->base + plgpio->regs.mis + in plgpio_irq_handler()
682 writel_relaxed(plgpio->csave_regs[i].wdata, plgpio->regs.wdata + in plgpio_resume()
684 writel_relaxed(plgpio->csave_regs[i].dir, plgpio->regs.dir + in plgpio_resume()
688 writel_relaxed(plgpio->csave_regs[i].eit, in plgpio_resume()
691 writel_relaxed(plgpio->csave_regs[i].ie, plgpio->regs.ie + off); in plgpio_resume()
694 writel_relaxed(plgpio->csave_regs[i].enb, in plgpio_resume()
/linux-4.1.27/drivers/clk/berlin/
Dberlin2-div.c104 writel_relaxed(reg, div->base + map->gate_offs); in berlin2_div_enable()
123 writel_relaxed(reg, div->base + map->gate_offs); in berlin2_div_disable()
144 writel_relaxed(reg, div->base + map->pll_switch_offs); in berlin2_div_set_parent()
151 writel_relaxed(reg, div->base + map->pll_select_offs); in berlin2_div_set_parent()
Dberlin2-avpll.c146 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
161 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_disable()
244 writel_relaxed(reg, ch->base + VCO_CTRL10); in berlin2_avpll_channel_enable()
256 writel_relaxed(reg, ch->base + VCO_CTRL10); in berlin2_avpll_channel_disable()
/linux-4.1.27/drivers/bus/
Domap_l3_noc.c151 writel_relaxed(clear, l3_targ_stderr); in l3_handle_target()
215 writel_relaxed(mask_val, mask_reg); in l3_interrupt_handler()
333 writel_relaxed(mask_val, mask_regx); in l3_resume_noirq()
339 writel_relaxed(mask_val, mask_regx); in l3_resume_noirq()
Domap-ocp2scp.c80 writel_relaxed(reg, regs + OCP2SCP_TIMING); in omap_ocp2scp_probe()
/linux-4.1.27/drivers/video/fbdev/
Dsa1100fb.c796 writel_relaxed(fbi->reg_lccr3, fbi->base + LCCR3); in sa1100fb_enable_controller()
797 writel_relaxed(fbi->reg_lccr2, fbi->base + LCCR2); in sa1100fb_enable_controller()
798 writel_relaxed(fbi->reg_lccr1, fbi->base + LCCR1); in sa1100fb_enable_controller()
799 writel_relaxed(fbi->reg_lccr0 & ~LCCR0_LEN, fbi->base + LCCR0); in sa1100fb_enable_controller()
800 writel_relaxed(fbi->dbar1, fbi->base + DBAR1); in sa1100fb_enable_controller()
801 writel_relaxed(fbi->dbar2, fbi->base + DBAR2); in sa1100fb_enable_controller()
802 writel_relaxed(fbi->reg_lccr0 | LCCR0_LEN, fbi->base + LCCR0); in sa1100fb_enable_controller()
829 writel_relaxed(~0, fbi->base + LCSR); in sa1100fb_disable_controller()
833 writel_relaxed(lccr0, fbi->base + LCCR0); in sa1100fb_disable_controller()
835 writel_relaxed(lccr0, fbi->base + LCCR0); in sa1100fb_disable_controller()
[all …]
/linux-4.1.27/drivers/crypto/ux500/hash/
Dhash_alg.h99 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
102 writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name)
105 writel_relaxed(((readl(reg) & ~(mask)) | \
/linux-4.1.27/arch/arm/plat-omap/include/plat/
Ddmtimer.h296 writel_relaxed(val, timer->func_base + (reg & 0xff)); in __omap_dm_timer_write()
388 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat); in __omap_dm_timer_stop()
402 writel_relaxed(value, timer->irq_ena); in __omap_dm_timer_int_enable()
415 writel_relaxed(value, timer->irq_stat); in __omap_dm_timer_write_status()
/linux-4.1.27/drivers/mtd/nand/
Dfsmc_nand.c386 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC)); in fsmc_cmd_ctrl()
429 writel_relaxed(value | FSMC_DEVWID_16, in fsmc_nand_setup()
432 writel_relaxed(value | FSMC_DEVWID_8, in fsmc_nand_setup()
435 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar, in fsmc_nand_setup()
437 writel_relaxed(thiz | thold | twait | tset, in fsmc_nand_setup()
439 writel_relaxed(thiz | thold | twait | tset, in fsmc_nand_setup()
453 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256, in fsmc_enable_hwecc()
455 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN, in fsmc_enable_hwecc()
457 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN, in fsmc_enable_hwecc()
639 writel_relaxed(p[i], chip->IO_ADDR_W); in fsmc_write_buf()
Datmel_nand_ecc.h133 writel_relaxed((value), (addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
/linux-4.1.27/drivers/cpufreq/
Dkirkwood-cpufreq.c65 writel_relaxed(reg, priv.base); in kirkwood_cpufreq_target()
82 writel_relaxed(reg, priv.base); in kirkwood_cpufreq_target()
/linux-4.1.27/arch/arm/mach-spear/include/mach/
Duncompress.h30 writel_relaxed(c, base + UART01x_DR); in putc()
/linux-4.1.27/arch/arm/mach-mmp/
Ddevices.c93 writel_relaxed(reg, base + offset); in u2o_set()
104 writel_relaxed(reg, base + offset); in u2o_clear()
111 writel_relaxed(value, base + offset); in u2o_write()
/linux-4.1.27/arch/m68k/include/asm/
Dio.h13 #define writel_relaxed(b, addr) writel(b, addr) macro
/linux-4.1.27/drivers/usb/phy/
Dphy-mxs-usb.c244 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, in __mxs_phy_disconnect_line()
262 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, in __mxs_phy_disconnect_line()
411 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET); in mxs_phy_set_wakeup()
413 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR); in mxs_phy_set_wakeup()
/linux-4.1.27/drivers/mtd/lpddr/
Dlpddr2_nvm.c149 writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18, in ow_enable()
151 writel_relaxed(0x01, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA); in ow_enable()
164 writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18, in ow_disable()
166 writel_relaxed(0x02, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA); in ow_disable()
DKconfig22 # ARM dependency is only for writel_relaxed()
/linux-4.1.27/drivers/iio/adc/
Drockchip_saradc.c74 writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC); in rockchip_saradc_read_raw()
84 writel_relaxed(0, info->regs + SARADC_CTRL); in rockchip_saradc_read_raw()
116 writel_relaxed(0, info->regs + SARADC_CTRL); in rockchip_saradc_isr()
/linux-4.1.27/drivers/clk/spear/
Dclk-vco-pll.c160 writel_relaxed(val, pll->vco->cfg_reg); in clk_pll_set_rate()
247 writel_relaxed(val, vco->mode_reg); in clk_vco_set_rate()
261 writel_relaxed(val, vco->cfg_reg); in clk_vco_set_rate()
Dclk-frac-synth.c111 writel_relaxed(val, frac->reg); in clk_frac_set_rate()
Dclk-gpt-synth.c100 writel_relaxed(val, gpt->reg); in clk_gpt_set_rate()
/linux-4.1.27/drivers/power/reset/
Dhisi-reboot.c30 writel_relaxed(0xdeadbeef, base + reboot_offset); in hisi_restart_handler()
/linux-4.1.27/arch/arm/mach-tegra/
Dirq.c58 writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL); in tegra_gic_notifier()
/linux-4.1.27/drivers/pwm/
Dpwm-spear.c74 writel_relaxed(val, chip->mmio_base + (num << 4) + offset); in spear_pwm_writel()
217 writel_relaxed(val, pc->mmio_base + PWMMCR); in spear_pwm_probe()
Dpwm-rockchip.c75 writel_relaxed(val, pc->base + pc->data->regs.ctrl); in rockchip_pwm_set_enable_v1()
98 writel_relaxed(val, pc->base + pc->data->regs.ctrl); in rockchip_pwm_set_enable_v2()
Dpwm-atmel.c81 writel_relaxed(val, chip->base + offset); in atmel_pwm_writel()
98 writel_relaxed(val, chip->base + base + offset); in atmel_pwm_ch_writel()
/linux-4.1.27/drivers/rtc/
Drtc-digicolor.c91 writel_relaxed(val, rtc->regs + DC_RTC_REFERENCE); in dc_rtc_write()
146 writel_relaxed(alarm_time - reference, rtc->regs + DC_RTC_ALARM); in dc_rtc_set_alarm()
/linux-4.1.27/arch/nios2/include/asm/
Dio.h26 #define writel_relaxed(x, addr) writel(x, addr) macro
/linux-4.1.27/arch/arm/mach-axxia/
Dplatsmp.c28 writel_relaxed(virt_to_phys(secondary_startup), virt); in write_release_addr()
/linux-4.1.27/arch/arm64/include/asm/
Dio.h127 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) macro
142 #define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
/linux-4.1.27/drivers/clk/shmobile/
Dclk-emev2.c42 writel_relaxed(value, smu_base + offs); in emev2_smu_write()
/linux-4.1.27/drivers/tty/serial/
Dmsm_serial.h131 writel_relaxed(val, port->membase + off); in msm_write()
/linux-4.1.27/drivers/spmi/
Dspmi-pmic-arb.c179 writel_relaxed(val, dev->wr_base + offset); in pmic_arb_base_write()
185 writel_relaxed(val, dev->rd_base + offset); in pmic_arb_set_rd_cmd()
488 writel_relaxed(1 << irq, pa->intr + pa->ver_ops->irq_clear(apid)); in qpnpint_irq_ack()
508 writel_relaxed(status, pa->intr + in qpnpint_irq_mask()
529 writel_relaxed(status | SPMI_PIC_ACC_ENABLE_BIT, in qpnpint_irq_unmask()
/linux-4.1.27/include/linux/clk/
Dat91_pmc.h26 writel_relaxed(value, at91_pmc_base + field)
/linux-4.1.27/arch/arm/mach-dove/
Dirq.c62 writel_relaxed(u, PMU_INTERRUPT_CAUSE); in pmu_irq_ack()
/linux-4.1.27/drivers/clk/samsung/
Dclk-exynos5440.c104 writel_relaxed(val, reg_base + 0xcc); in exynos5440_clk_restart_notify()
Dclk-s3c2410-dclk.c182 writel_relaxed(dclk_con, s3c24xx_dclk->base); in s3c24xx_dclk_update_cmp()
228 writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base); in s3c24xx_dclk_resume()
/linux-4.1.27/drivers/net/ethernet/cadence/
Dmacb.h433 writel_relaxed((value), (port)->regs + MACB_##reg)
437 writel_relaxed((value), (port)->regs + GEM_##reg)
441 writel_relaxed((value), (queue)->bp->regs + (queue)->reg)
/linux-4.1.27/arch/m32r/include/asm/
Dio.h167 #define writel_relaxed writel macro
/linux-4.1.27/arch/sh/include/asm/
Dio.h45 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c)) macro
55 #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
/linux-4.1.27/drivers/clk/rockchip/
Dclk-pll.c208 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, in rockchip_rk3066_pll_set_rate()
211 writel_relaxed(HIWORD_UPDATE(rate->bwadj, RK3066_PLLCON2_BWADJ_MASK, in rockchip_rk3066_pll_set_rate()
/linux-4.1.27/arch/arm/include/asm/
Dio.h304 #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) macro
312 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
/linux-4.1.27/drivers/soc/qcom/
Dqcom_gsbi.c197 writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci, in gsbi_probe()

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