| /linux-4.1.27/drivers/pci/host/ |
| H A D | pcie-iproc-platform.c | 27 #include "pcie-iproc.h"
31 struct iproc_pcie *pcie; iproc_pcie_pltfm_probe() local
38 pcie = devm_kzalloc(&pdev->dev, sizeof(struct iproc_pcie), GFP_KERNEL); iproc_pcie_pltfm_probe()
39 if (!pcie) iproc_pcie_pltfm_probe()
42 pcie->dev = &pdev->dev; iproc_pcie_pltfm_probe()
43 platform_set_drvdata(pdev, pcie); iproc_pcie_pltfm_probe()
47 dev_err(pcie->dev, "unable to obtain controller resources\n"); iproc_pcie_pltfm_probe()
51 pcie->base = devm_ioremap(pcie->dev, reg.start, resource_size(®)); iproc_pcie_pltfm_probe()
52 if (!pcie->base) { iproc_pcie_pltfm_probe()
53 dev_err(pcie->dev, "unable to map controller registers\n"); iproc_pcie_pltfm_probe()
58 pcie->phy = devm_phy_get(&pdev->dev, "pcie-phy"); iproc_pcie_pltfm_probe()
59 if (IS_ERR(pcie->phy)) { iproc_pcie_pltfm_probe()
60 if (PTR_ERR(pcie->phy) == -EPROBE_DEFER) iproc_pcie_pltfm_probe()
62 pcie->phy = NULL; iproc_pcie_pltfm_probe()
67 dev_err(pcie->dev, iproc_pcie_pltfm_probe()
72 pcie->resources = &res; iproc_pcie_pltfm_probe()
74 ret = iproc_pcie_setup(pcie); iproc_pcie_pltfm_probe()
76 dev_err(pcie->dev, "PCIe controller setup failed\n"); iproc_pcie_pltfm_probe()
85 struct iproc_pcie *pcie = platform_get_drvdata(pdev); iproc_pcie_pltfm_remove() local
87 return iproc_pcie_remove(pcie); iproc_pcie_pltfm_remove()
91 { .compatible = "brcm,iproc-pcie", },
98 .name = "iproc-pcie",
|
| H A D | pci-layerscape.c | 27 #include "pcie-designware.h"
54 struct ls_pcie *pcie = to_ls_pcie(pp); ls_pcie_link_up() local
56 regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state); ls_pcie_link_up()
67 struct ls_pcie *pcie = to_ls_pcie(pp); ls_pcie_host_init() local
86 val = ioread32(pcie->dbi + PCIE_STRFMR1); ls_pcie_host_init()
88 iowrite32(val, pcie->dbi + PCIE_STRFMR1); ls_pcie_host_init()
96 static int ls_add_pcie_port(struct ls_pcie *pcie) ls_add_pcie_port() argument
101 pp = &pcie->pp; ls_add_pcie_port()
102 pp->dev = pcie->dev; ls_add_pcie_port()
103 pp->dbi_base = pcie->dbi; ls_add_pcie_port()
118 struct ls_pcie *pcie; ls_pcie_probe() local
123 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); ls_pcie_probe()
124 if (!pcie) ls_pcie_probe()
127 pcie->dev = &pdev->dev; ls_pcie_probe()
130 pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base); ls_pcie_probe()
131 if (IS_ERR(pcie->dbi)) { ls_pcie_probe()
133 return PTR_ERR(pcie->dbi); ls_pcie_probe()
136 pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, ls_pcie_probe()
137 "fsl,pcie-scfg"); ls_pcie_probe()
138 if (IS_ERR(pcie->scfg)) { ls_pcie_probe()
140 return PTR_ERR(pcie->scfg); ls_pcie_probe()
144 "fsl,pcie-scfg", index, 2); ls_pcie_probe()
147 pcie->index = index[1]; ls_pcie_probe()
149 ret = ls_add_pcie_port(pcie); ls_pcie_probe()
153 platform_set_drvdata(pdev, pcie); ls_pcie_probe()
159 { .compatible = "fsl,ls1021a-pcie" },
166 .name = "layerscape-pcie",
|
| H A D | pci-tegra.c | 10 * Bits taken from arch/arm/mach-dove/pcie.c
309 struct tegra_pcie *pcie; member in struct:tegra_pcie_port
328 static inline void afi_writel(struct tegra_pcie *pcie, u32 value, afi_writel() argument
331 writel(value, pcie->afi + offset); afi_writel()
334 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) afi_readl() argument
336 return readl(pcie->afi + offset); afi_readl()
339 static inline void pads_writel(struct tegra_pcie *pcie, u32 value, pads_writel() argument
342 writel(value, pcie->pads + offset); pads_writel()
345 static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) pads_readl() argument
347 return readl(pcie->pads + offset); pads_readl()
382 static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie, tegra_pcie_bus_alloc() argument
387 phys_addr_t cs = pcie->cs->start; tegra_pcie_bus_alloc()
414 dev_err(pcie->dev, "ioremap_page_range() failed: %d\n", tegra_pcie_bus_alloc()
433 static void __iomem *tegra_pcie_bus_map(struct tegra_pcie *pcie, tegra_pcie_bus_map() argument
438 list_for_each_entry(bus, &pcie->buses, list) tegra_pcie_bus_map()
442 bus = tegra_pcie_bus_alloc(pcie, busnr); tegra_pcie_bus_map()
446 list_add_tail(&bus->list, &pcie->buses); tegra_pcie_bus_map()
455 struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata); tegra_pcie_conf_address() local
462 list_for_each_entry(port, &pcie->ports, list) { tegra_pcie_conf_address()
469 addr = tegra_pcie_bus_map(pcie, bus->number); tegra_pcie_conf_address()
471 dev_err(pcie->dev, tegra_pcie_conf_address()
516 value = afi_readl(port->pcie, ctrl); tegra_pcie_port_reset()
518 afi_writel(port->pcie, value, ctrl); tegra_pcie_port_reset()
522 value = afi_readl(port->pcie, ctrl); tegra_pcie_port_reset()
524 afi_writel(port->pcie, value, ctrl); tegra_pcie_port_reset()
529 const struct tegra_pcie_soc_data *soc = port->pcie->soc_data; tegra_pcie_port_enable()
534 value = afi_readl(port->pcie, ctrl); tegra_pcie_port_enable()
542 afi_writel(port->pcie, value, ctrl); tegra_pcie_port_enable()
549 const struct tegra_pcie_soc_data *soc = port->pcie->soc_data; tegra_pcie_port_disable()
554 value = afi_readl(port->pcie, ctrl); tegra_pcie_port_disable()
556 afi_writel(port->pcie, value, ctrl); tegra_pcie_port_disable()
559 value = afi_readl(port->pcie, ctrl); tegra_pcie_port_disable()
565 afi_writel(port->pcie, value, ctrl); tegra_pcie_port_disable()
570 struct tegra_pcie *pcie = port->pcie; tegra_pcie_port_free() local
572 devm_iounmap(pcie->dev, port->base); tegra_pcie_port_free()
573 devm_release_mem_region(pcie->dev, port->regs.start, tegra_pcie_port_free()
576 devm_kfree(pcie->dev, port); tegra_pcie_port_free()
598 struct tegra_pcie *pcie = sys_to_pcie(sys); tegra_pcie_setup() local
601 err = devm_request_resource(pcie->dev, &pcie->all, &pcie->mem); tegra_pcie_setup()
605 err = devm_request_resource(pcie->dev, &pcie->all, &pcie->prefetch); tegra_pcie_setup()
609 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); tegra_pcie_setup()
610 pci_add_resource_offset(&sys->resources, &pcie->prefetch, tegra_pcie_setup()
612 pci_add_resource(&sys->resources, &pcie->busn); tegra_pcie_setup()
614 pci_ioremap_io(pcie->pio.start, pcie->io.start); tegra_pcie_setup()
621 struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata); tegra_pcie_map_irq() local
628 irq = pcie->irq; tegra_pcie_map_irq()
635 struct tegra_pcie *pcie = sys_to_pcie(sys); tegra_pcie_scan_bus() local
638 bus = pci_create_root_bus(pcie->dev, sys->busnr, &tegra_pcie_ops, sys, tegra_pcie_scan_bus()
667 struct tegra_pcie *pcie = arg; tegra_pcie_isr() local
670 code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; tegra_pcie_isr()
671 signature = afi_readl(pcie, AFI_INTR_SIGNATURE); tegra_pcie_isr()
672 afi_writel(pcie, 0, AFI_INTR_CODE); tegra_pcie_isr()
685 dev_dbg(pcie->dev, "%s, signature: %08x\n", err_msg[code], tegra_pcie_isr()
688 dev_err(pcie->dev, "%s, signature: %08x\n", err_msg[code], tegra_pcie_isr()
693 u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff; tegra_pcie_isr()
697 dev_dbg(pcie->dev, " FPCI address: %10llx\n", address); tegra_pcie_isr()
699 dev_err(pcie->dev, " FPCI address: %10llx\n", address); tegra_pcie_isr()
713 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) tegra_pcie_setup_translations() argument
719 size = resource_size(pcie->cs); tegra_pcie_setup_translations()
720 axi_address = pcie->cs->start; tegra_pcie_setup_translations()
721 afi_writel(pcie, axi_address, AFI_AXI_BAR0_START); tegra_pcie_setup_translations()
722 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); tegra_pcie_setup_translations()
723 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0); tegra_pcie_setup_translations()
727 size = resource_size(&pcie->io); tegra_pcie_setup_translations()
728 axi_address = pcie->io.start; tegra_pcie_setup_translations()
729 afi_writel(pcie, axi_address, AFI_AXI_BAR1_START); tegra_pcie_setup_translations()
730 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); tegra_pcie_setup_translations()
731 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1); tegra_pcie_setup_translations()
734 fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; tegra_pcie_setup_translations()
735 size = resource_size(&pcie->prefetch); tegra_pcie_setup_translations()
736 axi_address = pcie->prefetch.start; tegra_pcie_setup_translations()
737 afi_writel(pcie, axi_address, AFI_AXI_BAR2_START); tegra_pcie_setup_translations()
738 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); tegra_pcie_setup_translations()
739 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2); tegra_pcie_setup_translations()
742 fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; tegra_pcie_setup_translations()
743 size = resource_size(&pcie->mem); tegra_pcie_setup_translations()
744 axi_address = pcie->mem.start; tegra_pcie_setup_translations()
745 afi_writel(pcie, axi_address, AFI_AXI_BAR3_START); tegra_pcie_setup_translations()
746 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); tegra_pcie_setup_translations()
747 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3); tegra_pcie_setup_translations()
750 afi_writel(pcie, 0, AFI_AXI_BAR4_START); tegra_pcie_setup_translations()
751 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); tegra_pcie_setup_translations()
752 afi_writel(pcie, 0, AFI_FPCI_BAR4); tegra_pcie_setup_translations()
754 afi_writel(pcie, 0, AFI_AXI_BAR5_START); tegra_pcie_setup_translations()
755 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); tegra_pcie_setup_translations()
756 afi_writel(pcie, 0, AFI_FPCI_BAR5); tegra_pcie_setup_translations()
759 afi_writel(pcie, PHYS_OFFSET, AFI_CACHE_BAR0_ST); tegra_pcie_setup_translations()
760 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); tegra_pcie_setup_translations()
761 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); tegra_pcie_setup_translations()
762 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); tegra_pcie_setup_translations()
765 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); tegra_pcie_setup_translations()
766 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); tegra_pcie_setup_translations()
767 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); tegra_pcie_setup_translations()
768 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); tegra_pcie_setup_translations()
771 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) tegra_pcie_pll_wait() argument
773 const struct tegra_pcie_soc_data *soc = pcie->soc_data; tegra_pcie_pll_wait()
779 value = pads_readl(pcie, soc->pads_pll_ctl); tegra_pcie_pll_wait()
787 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) tegra_pcie_phy_enable() argument
789 const struct tegra_pcie_soc_data *soc = pcie->soc_data; tegra_pcie_phy_enable()
794 pads_writel(pcie, 0x0, PADS_CTL_SEL); tegra_pcie_phy_enable()
797 value = pads_readl(pcie, PADS_CTL); tegra_pcie_phy_enable()
799 pads_writel(pcie, value, PADS_CTL); tegra_pcie_phy_enable()
805 value = pads_readl(pcie, soc->pads_pll_ctl); tegra_pcie_phy_enable()
808 pads_writel(pcie, value, soc->pads_pll_ctl); tegra_pcie_phy_enable()
811 value = pads_readl(pcie, soc->pads_pll_ctl); tegra_pcie_phy_enable()
813 pads_writel(pcie, value, soc->pads_pll_ctl); tegra_pcie_phy_enable()
818 value = pads_readl(pcie, soc->pads_pll_ctl); tegra_pcie_phy_enable()
820 pads_writel(pcie, value, soc->pads_pll_ctl); tegra_pcie_phy_enable()
824 pads_writel(pcie, value, PADS_REFCLK_CFG0); tegra_pcie_phy_enable()
826 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); tegra_pcie_phy_enable()
829 err = tegra_pcie_pll_wait(pcie, 500); tegra_pcie_phy_enable()
831 dev_err(pcie->dev, "PLL failed to lock: %d\n", err); tegra_pcie_phy_enable()
836 value = pads_readl(pcie, PADS_CTL); tegra_pcie_phy_enable()
838 pads_writel(pcie, value, PADS_CTL); tegra_pcie_phy_enable()
841 value = pads_readl(pcie, PADS_CTL); tegra_pcie_phy_enable()
843 pads_writel(pcie, value, PADS_CTL); tegra_pcie_phy_enable()
848 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) tegra_pcie_enable_controller() argument
850 const struct tegra_pcie_soc_data *soc = pcie->soc_data; tegra_pcie_enable_controller()
856 if (pcie->phy) { tegra_pcie_enable_controller()
857 value = afi_readl(pcie, AFI_PLLE_CONTROL); tegra_pcie_enable_controller()
860 afi_writel(pcie, value, AFI_PLLE_CONTROL); tegra_pcie_enable_controller()
865 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); tegra_pcie_enable_controller()
868 value = afi_readl(pcie, AFI_PCIE_CONFIG); tegra_pcie_enable_controller()
870 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config; tegra_pcie_enable_controller()
872 list_for_each_entry(port, &pcie->ports, list) tegra_pcie_enable_controller()
875 afi_writel(pcie, value, AFI_PCIE_CONFIG); tegra_pcie_enable_controller()
878 value = afi_readl(pcie, AFI_FUSE); tegra_pcie_enable_controller()
880 afi_writel(pcie, value, AFI_FUSE); tegra_pcie_enable_controller()
882 value = afi_readl(pcie, AFI_FUSE); tegra_pcie_enable_controller()
884 afi_writel(pcie, value, AFI_FUSE); tegra_pcie_enable_controller()
887 if (!pcie->phy) tegra_pcie_enable_controller()
888 err = tegra_pcie_phy_enable(pcie); tegra_pcie_enable_controller()
890 err = phy_power_on(pcie->phy); tegra_pcie_enable_controller()
893 dev_err(pcie->dev, "failed to power on PHY: %d\n", err); tegra_pcie_enable_controller()
898 reset_control_deassert(pcie->pcie_xrst); tegra_pcie_enable_controller()
901 value = afi_readl(pcie, AFI_CONFIGURATION); tegra_pcie_enable_controller()
903 afi_writel(pcie, value, AFI_CONFIGURATION); tegra_pcie_enable_controller()
912 afi_writel(pcie, value, AFI_AFI_INTR_ENABLE); tegra_pcie_enable_controller()
913 afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE); tegra_pcie_enable_controller()
916 afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK); tegra_pcie_enable_controller()
919 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); tegra_pcie_enable_controller()
924 static void tegra_pcie_power_off(struct tegra_pcie *pcie) tegra_pcie_power_off() argument
930 err = phy_power_off(pcie->phy); tegra_pcie_power_off()
932 dev_warn(pcie->dev, "failed to power off PHY: %d\n", err); tegra_pcie_power_off()
934 reset_control_assert(pcie->pcie_xrst); tegra_pcie_power_off()
935 reset_control_assert(pcie->afi_rst); tegra_pcie_power_off()
936 reset_control_assert(pcie->pex_rst); tegra_pcie_power_off()
940 err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); tegra_pcie_power_off()
942 dev_warn(pcie->dev, "failed to disable regulators: %d\n", err); tegra_pcie_power_off()
945 static int tegra_pcie_power_on(struct tegra_pcie *pcie) tegra_pcie_power_on() argument
947 const struct tegra_pcie_soc_data *soc = pcie->soc_data; tegra_pcie_power_on()
950 reset_control_assert(pcie->pcie_xrst); tegra_pcie_power_on()
951 reset_control_assert(pcie->afi_rst); tegra_pcie_power_on()
952 reset_control_assert(pcie->pex_rst); tegra_pcie_power_on()
957 err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies); tegra_pcie_power_on()
959 dev_err(pcie->dev, "failed to enable regulators: %d\n", err); tegra_pcie_power_on()
962 pcie->pex_clk, tegra_pcie_power_on()
963 pcie->pex_rst); tegra_pcie_power_on()
965 dev_err(pcie->dev, "powerup sequence failed: %d\n", err); tegra_pcie_power_on()
969 reset_control_deassert(pcie->afi_rst); tegra_pcie_power_on()
971 err = clk_prepare_enable(pcie->afi_clk); tegra_pcie_power_on()
973 dev_err(pcie->dev, "failed to enable AFI clock: %d\n", err); tegra_pcie_power_on()
978 err = clk_prepare_enable(pcie->cml_clk); tegra_pcie_power_on()
980 dev_err(pcie->dev, "failed to enable CML clock: %d\n", tegra_pcie_power_on()
986 err = clk_prepare_enable(pcie->pll_e); tegra_pcie_power_on()
988 dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err); tegra_pcie_power_on()
995 static int tegra_pcie_clocks_get(struct tegra_pcie *pcie) tegra_pcie_clocks_get() argument
997 const struct tegra_pcie_soc_data *soc = pcie->soc_data; tegra_pcie_clocks_get()
999 pcie->pex_clk = devm_clk_get(pcie->dev, "pex"); tegra_pcie_clocks_get()
1000 if (IS_ERR(pcie->pex_clk)) tegra_pcie_clocks_get()
1001 return PTR_ERR(pcie->pex_clk); tegra_pcie_clocks_get()
1003 pcie->afi_clk = devm_clk_get(pcie->dev, "afi"); tegra_pcie_clocks_get()
1004 if (IS_ERR(pcie->afi_clk)) tegra_pcie_clocks_get()
1005 return PTR_ERR(pcie->afi_clk); tegra_pcie_clocks_get()
1007 pcie->pll_e = devm_clk_get(pcie->dev, "pll_e"); tegra_pcie_clocks_get()
1008 if (IS_ERR(pcie->pll_e)) tegra_pcie_clocks_get()
1009 return PTR_ERR(pcie->pll_e); tegra_pcie_clocks_get()
1012 pcie->cml_clk = devm_clk_get(pcie->dev, "cml"); tegra_pcie_clocks_get()
1013 if (IS_ERR(pcie->cml_clk)) tegra_pcie_clocks_get()
1014 return PTR_ERR(pcie->cml_clk); tegra_pcie_clocks_get()
1020 static int tegra_pcie_resets_get(struct tegra_pcie *pcie) tegra_pcie_resets_get() argument
1022 pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex"); tegra_pcie_resets_get()
1023 if (IS_ERR(pcie->pex_rst)) tegra_pcie_resets_get()
1024 return PTR_ERR(pcie->pex_rst); tegra_pcie_resets_get()
1026 pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi"); tegra_pcie_resets_get()
1027 if (IS_ERR(pcie->afi_rst)) tegra_pcie_resets_get()
1028 return PTR_ERR(pcie->afi_rst); tegra_pcie_resets_get()
1030 pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x"); tegra_pcie_resets_get()
1031 if (IS_ERR(pcie->pcie_xrst)) tegra_pcie_resets_get()
1032 return PTR_ERR(pcie->pcie_xrst); tegra_pcie_resets_get()
1037 static int tegra_pcie_get_resources(struct tegra_pcie *pcie) tegra_pcie_get_resources() argument
1039 struct platform_device *pdev = to_platform_device(pcie->dev); tegra_pcie_get_resources()
1043 err = tegra_pcie_clocks_get(pcie); tegra_pcie_get_resources()
1049 err = tegra_pcie_resets_get(pcie); tegra_pcie_get_resources()
1055 pcie->phy = devm_phy_optional_get(pcie->dev, "pcie"); tegra_pcie_get_resources()
1056 if (IS_ERR(pcie->phy)) { tegra_pcie_get_resources()
1057 err = PTR_ERR(pcie->phy); tegra_pcie_get_resources()
1062 err = phy_init(pcie->phy); tegra_pcie_get_resources()
1068 err = tegra_pcie_power_on(pcie); tegra_pcie_get_resources()
1075 pcie->pads = devm_ioremap_resource(&pdev->dev, pads); tegra_pcie_get_resources()
1076 if (IS_ERR(pcie->pads)) { tegra_pcie_get_resources()
1077 err = PTR_ERR(pcie->pads); tegra_pcie_get_resources()
1082 pcie->afi = devm_ioremap_resource(&pdev->dev, afi); tegra_pcie_get_resources()
1083 if (IS_ERR(pcie->afi)) { tegra_pcie_get_resources()
1084 err = PTR_ERR(pcie->afi); tegra_pcie_get_resources()
1095 pcie->cs = devm_request_mem_region(pcie->dev, res->start, tegra_pcie_get_resources()
1097 if (!pcie->cs) { tegra_pcie_get_resources()
1109 pcie->irq = err; tegra_pcie_get_resources()
1111 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie); tegra_pcie_get_resources()
1120 tegra_pcie_power_off(pcie); tegra_pcie_get_resources()
1124 static int tegra_pcie_put_resources(struct tegra_pcie *pcie) tegra_pcie_put_resources() argument
1128 if (pcie->irq > 0) tegra_pcie_put_resources()
1129 free_irq(pcie->irq, pcie); tegra_pcie_put_resources()
1131 tegra_pcie_power_off(pcie); tegra_pcie_put_resources()
1133 err = phy_exit(pcie->phy); tegra_pcie_put_resources()
1135 dev_err(pcie->dev, "failed to teardown PHY: %d\n", err); tegra_pcie_put_resources()
1173 struct tegra_pcie *pcie = data; tegra_pcie_msi_irq() local
1174 struct tegra_msi *msi = &pcie->msi; tegra_pcie_msi_irq()
1178 unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4); tegra_pcie_msi_irq()
1186 afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4); tegra_pcie_msi_irq()
1193 dev_info(pcie->dev, "unhandled MSI\n"); tegra_pcie_msi_irq()
1199 dev_info(pcie->dev, "unexpected MSI\n"); tegra_pcie_msi_irq()
1203 reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4); tegra_pcie_msi_irq()
1277 static int tegra_pcie_enable_msi(struct tegra_pcie *pcie) tegra_pcie_enable_msi() argument
1279 struct platform_device *pdev = to_platform_device(pcie->dev); tegra_pcie_enable_msi()
1280 const struct tegra_pcie_soc_data *soc = pcie->soc_data; tegra_pcie_enable_msi()
1281 struct tegra_msi *msi = &pcie->msi; tegra_pcie_enable_msi()
1288 msi->chip.dev = pcie->dev; tegra_pcie_enable_msi()
1292 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR, tegra_pcie_enable_msi()
1308 tegra_msi_irq_chip.name, pcie); tegra_pcie_enable_msi()
1318 afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST); tegra_pcie_enable_msi()
1319 afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST); tegra_pcie_enable_msi()
1321 afi_writel(pcie, 1, AFI_MSI_BAR_SZ); tegra_pcie_enable_msi()
1324 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0); tegra_pcie_enable_msi()
1325 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1); tegra_pcie_enable_msi()
1326 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2); tegra_pcie_enable_msi()
1327 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3); tegra_pcie_enable_msi()
1328 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4); tegra_pcie_enable_msi()
1329 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5); tegra_pcie_enable_msi()
1330 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6); tegra_pcie_enable_msi()
1331 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7); tegra_pcie_enable_msi()
1334 reg = afi_readl(pcie, AFI_INTR_MASK); tegra_pcie_enable_msi()
1336 afi_writel(pcie, reg, AFI_INTR_MASK); tegra_pcie_enable_msi()
1345 static int tegra_pcie_disable_msi(struct tegra_pcie *pcie) tegra_pcie_disable_msi() argument
1347 struct tegra_msi *msi = &pcie->msi; tegra_pcie_disable_msi()
1352 value = afi_readl(pcie, AFI_INTR_MASK); tegra_pcie_disable_msi()
1354 afi_writel(pcie, value, AFI_INTR_MASK); tegra_pcie_disable_msi()
1357 afi_writel(pcie, 0, AFI_MSI_EN_VEC0); tegra_pcie_disable_msi()
1358 afi_writel(pcie, 0, AFI_MSI_EN_VEC1); tegra_pcie_disable_msi()
1359 afi_writel(pcie, 0, AFI_MSI_EN_VEC2); tegra_pcie_disable_msi()
1360 afi_writel(pcie, 0, AFI_MSI_EN_VEC3); tegra_pcie_disable_msi()
1361 afi_writel(pcie, 0, AFI_MSI_EN_VEC4); tegra_pcie_disable_msi()
1362 afi_writel(pcie, 0, AFI_MSI_EN_VEC5); tegra_pcie_disable_msi()
1363 afi_writel(pcie, 0, AFI_MSI_EN_VEC6); tegra_pcie_disable_msi()
1364 afi_writel(pcie, 0, AFI_MSI_EN_VEC7); tegra_pcie_disable_msi()
1369 free_irq(msi->irq, pcie); tegra_pcie_disable_msi()
1382 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes, tegra_pcie_get_xbar_config() argument
1385 struct device_node *np = pcie->dev->of_node; tegra_pcie_get_xbar_config()
1387 if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { tegra_pcie_get_xbar_config()
1390 dev_info(pcie->dev, "4x1, 1x1 configuration\n"); tegra_pcie_get_xbar_config()
1395 dev_info(pcie->dev, "2x1, 1x1 configuration\n"); tegra_pcie_get_xbar_config()
1399 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { tegra_pcie_get_xbar_config()
1402 dev_info(pcie->dev, "4x1, 2x1 configuration\n"); tegra_pcie_get_xbar_config()
1407 dev_info(pcie->dev, "2x3 configuration\n"); tegra_pcie_get_xbar_config()
1412 dev_info(pcie->dev, "4x1, 1x2 configuration\n"); tegra_pcie_get_xbar_config()
1416 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { tegra_pcie_get_xbar_config()
1419 dev_info(pcie->dev, "single-mode configuration\n"); tegra_pcie_get_xbar_config()
1424 dev_info(pcie->dev, "dual-mode configuration\n"); tegra_pcie_get_xbar_config()
1462 static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie) tegra_pcie_get_legacy_regulators() argument
1464 struct device_node *np = pcie->dev->of_node; tegra_pcie_get_legacy_regulators()
1466 if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) tegra_pcie_get_legacy_regulators()
1467 pcie->num_supplies = 3; tegra_pcie_get_legacy_regulators()
1468 else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) tegra_pcie_get_legacy_regulators()
1469 pcie->num_supplies = 2; tegra_pcie_get_legacy_regulators()
1471 if (pcie->num_supplies == 0) { tegra_pcie_get_legacy_regulators()
1472 dev_err(pcie->dev, "device %s not supported in legacy mode\n", tegra_pcie_get_legacy_regulators()
1477 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, tegra_pcie_get_legacy_regulators()
1478 sizeof(*pcie->supplies), tegra_pcie_get_legacy_regulators()
1480 if (!pcie->supplies) tegra_pcie_get_legacy_regulators()
1483 pcie->supplies[0].supply = "pex-clk"; tegra_pcie_get_legacy_regulators()
1484 pcie->supplies[1].supply = "vdd"; tegra_pcie_get_legacy_regulators()
1486 if (pcie->num_supplies > 2) tegra_pcie_get_legacy_regulators()
1487 pcie->supplies[2].supply = "avdd"; tegra_pcie_get_legacy_regulators()
1489 return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies, tegra_pcie_get_legacy_regulators()
1490 pcie->supplies); tegra_pcie_get_legacy_regulators()
1502 static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask) tegra_pcie_get_regulators() argument
1504 struct device_node *np = pcie->dev->of_node; tegra_pcie_get_regulators()
1507 if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { tegra_pcie_get_regulators()
1508 pcie->num_supplies = 7; tegra_pcie_get_regulators()
1510 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, tegra_pcie_get_regulators()
1511 sizeof(*pcie->supplies), tegra_pcie_get_regulators()
1513 if (!pcie->supplies) tegra_pcie_get_regulators()
1516 pcie->supplies[i++].supply = "avddio-pex"; tegra_pcie_get_regulators()
1517 pcie->supplies[i++].supply = "dvddio-pex"; tegra_pcie_get_regulators()
1518 pcie->supplies[i++].supply = "avdd-pex-pll"; tegra_pcie_get_regulators()
1519 pcie->supplies[i++].supply = "hvdd-pex"; tegra_pcie_get_regulators()
1520 pcie->supplies[i++].supply = "hvdd-pex-pll-e"; tegra_pcie_get_regulators()
1521 pcie->supplies[i++].supply = "vddio-pex-ctl"; tegra_pcie_get_regulators()
1522 pcie->supplies[i++].supply = "avdd-pll-erefe"; tegra_pcie_get_regulators()
1523 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { tegra_pcie_get_regulators()
1534 pcie->num_supplies = 4 + (need_pexa ? 2 : 0) + tegra_pcie_get_regulators()
1537 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, tegra_pcie_get_regulators()
1538 sizeof(*pcie->supplies), tegra_pcie_get_regulators()
1540 if (!pcie->supplies) tegra_pcie_get_regulators()
1543 pcie->supplies[i++].supply = "avdd-pex-pll"; tegra_pcie_get_regulators()
1544 pcie->supplies[i++].supply = "hvdd-pex"; tegra_pcie_get_regulators()
1545 pcie->supplies[i++].supply = "vddio-pex-ctl"; tegra_pcie_get_regulators()
1546 pcie->supplies[i++].supply = "avdd-plle"; tegra_pcie_get_regulators()
1549 pcie->supplies[i++].supply = "avdd-pexa"; tegra_pcie_get_regulators()
1550 pcie->supplies[i++].supply = "vdd-pexa"; tegra_pcie_get_regulators()
1554 pcie->supplies[i++].supply = "avdd-pexb"; tegra_pcie_get_regulators()
1555 pcie->supplies[i++].supply = "vdd-pexb"; tegra_pcie_get_regulators()
1557 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { tegra_pcie_get_regulators()
1558 pcie->num_supplies = 5; tegra_pcie_get_regulators()
1560 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, tegra_pcie_get_regulators()
1561 sizeof(*pcie->supplies), tegra_pcie_get_regulators()
1563 if (!pcie->supplies) tegra_pcie_get_regulators()
1566 pcie->supplies[0].supply = "avdd-pex"; tegra_pcie_get_regulators()
1567 pcie->supplies[1].supply = "vdd-pex"; tegra_pcie_get_regulators()
1568 pcie->supplies[2].supply = "avdd-pex-pll"; tegra_pcie_get_regulators()
1569 pcie->supplies[3].supply = "avdd-plle"; tegra_pcie_get_regulators()
1570 pcie->supplies[4].supply = "vddio-pex-clk"; tegra_pcie_get_regulators()
1573 if (of_regulator_bulk_available(pcie->dev->of_node, pcie->supplies, tegra_pcie_get_regulators()
1574 pcie->num_supplies)) tegra_pcie_get_regulators()
1575 return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies, tegra_pcie_get_regulators()
1576 pcie->supplies); tegra_pcie_get_regulators()
1583 dev_info(pcie->dev, "using legacy DT binding for power supplies\n"); tegra_pcie_get_regulators()
1585 devm_kfree(pcie->dev, pcie->supplies); tegra_pcie_get_regulators()
1586 pcie->num_supplies = 0; tegra_pcie_get_regulators()
1588 return tegra_pcie_get_legacy_regulators(pcie); tegra_pcie_get_regulators()
1591 static int tegra_pcie_parse_dt(struct tegra_pcie *pcie) tegra_pcie_parse_dt() argument
1593 const struct tegra_pcie_soc_data *soc = pcie->soc_data; tegra_pcie_parse_dt()
1594 struct device_node *np = pcie->dev->of_node, *port; tegra_pcie_parse_dt()
1602 memset(&pcie->all, 0, sizeof(pcie->all)); tegra_pcie_parse_dt()
1603 pcie->all.flags = IORESOURCE_MEM; tegra_pcie_parse_dt()
1604 pcie->all.name = np->full_name; tegra_pcie_parse_dt()
1605 pcie->all.start = ~0; tegra_pcie_parse_dt()
1606 pcie->all.end = 0; tegra_pcie_parse_dt()
1609 dev_err(pcie->dev, "missing \"ranges\" property\n"); tegra_pcie_parse_dt()
1620 memcpy(&pcie->pio, &res, sizeof(res)); tegra_pcie_parse_dt()
1621 pcie->pio.name = np->full_name; tegra_pcie_parse_dt()
1631 pcie->io.start = range.cpu_addr; tegra_pcie_parse_dt()
1632 pcie->io.end = range.cpu_addr + range.size - 1; tegra_pcie_parse_dt()
1633 pcie->io.flags = IORESOURCE_MEM; tegra_pcie_parse_dt()
1634 pcie->io.name = "I/O"; tegra_pcie_parse_dt()
1636 memcpy(&res, &pcie->io, sizeof(res)); tegra_pcie_parse_dt()
1641 memcpy(&pcie->prefetch, &res, sizeof(res)); tegra_pcie_parse_dt()
1642 pcie->prefetch.name = "prefetchable"; tegra_pcie_parse_dt()
1644 memcpy(&pcie->mem, &res, sizeof(res)); tegra_pcie_parse_dt()
1645 pcie->mem.name = "non-prefetchable"; tegra_pcie_parse_dt()
1650 if (res.start <= pcie->all.start) tegra_pcie_parse_dt()
1651 pcie->all.start = res.start; tegra_pcie_parse_dt()
1653 if (res.end >= pcie->all.end) tegra_pcie_parse_dt()
1654 pcie->all.end = res.end; tegra_pcie_parse_dt()
1657 err = devm_request_resource(pcie->dev, &iomem_resource, &pcie->all); tegra_pcie_parse_dt()
1661 err = of_pci_parse_bus_range(np, &pcie->busn); tegra_pcie_parse_dt()
1663 dev_err(pcie->dev, "failed to parse ranges property: %d\n", tegra_pcie_parse_dt()
1665 pcie->busn.name = np->name; tegra_pcie_parse_dt()
1666 pcie->busn.start = 0; tegra_pcie_parse_dt()
1667 pcie->busn.end = 0xff; tegra_pcie_parse_dt()
1668 pcie->busn.flags = IORESOURCE_BUS; tegra_pcie_parse_dt()
1679 dev_err(pcie->dev, "failed to parse address: %d\n", for_each_child_of_node()
1687 dev_err(pcie->dev, "invalid port number: %d\n", index); for_each_child_of_node()
1695 dev_err(pcie->dev, "failed to parse # of lanes: %d\n", for_each_child_of_node()
1701 dev_err(pcie->dev, "invalid # of lanes: %u\n", value); for_each_child_of_node()
1715 rp = devm_kzalloc(pcie->dev, sizeof(*rp), GFP_KERNEL); for_each_child_of_node()
1721 dev_err(pcie->dev, "failed to parse address: %d\n", for_each_child_of_node()
1729 rp->pcie = pcie; for_each_child_of_node()
1731 rp->base = devm_ioremap_resource(pcie->dev, &rp->regs); for_each_child_of_node()
1735 list_add_tail(&rp->list, &pcie->ports); for_each_child_of_node()
1738 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
1740 dev_err(pcie->dev, "invalid lane configuration\n");
1744 err = tegra_pcie_get_regulators(pcie, mask);
1781 dev_err(port->pcie->dev, "link %u down, retrying\n", tegra_pcie_port_check_link()
1804 static int tegra_pcie_enable(struct tegra_pcie *pcie) tegra_pcie_enable() argument
1809 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { tegra_pcie_enable()
1810 dev_info(pcie->dev, "probing port %u, using %u lanes\n", tegra_pcie_enable()
1818 dev_info(pcie->dev, "link %u down, ignoring\n", port->index); tegra_pcie_enable()
1827 hw.msi_ctrl = &pcie->msi.chip; tegra_pcie_enable()
1831 hw.private_data = (void **)&pcie; tegra_pcie_enable()
1837 pci_common_init_dev(pcie->dev, &hw); tegra_pcie_enable()
1879 { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie_data },
1880 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie_data },
1881 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie_data },
1888 struct tegra_pcie *pcie = s->private; tegra_pcie_ports_seq_start() local
1890 if (list_empty(&pcie->ports)) tegra_pcie_ports_seq_start()
1895 return seq_list_start(&pcie->ports, *pos); tegra_pcie_ports_seq_start()
1900 struct tegra_pcie *pcie = s->private; tegra_pcie_ports_seq_next() local
1902 return seq_list_next(v, &pcie->ports, pos); tegra_pcie_ports_seq_next()
1952 struct tegra_pcie *pcie = inode->i_private; tegra_pcie_ports_open() local
1961 s->private = pcie; tegra_pcie_ports_open()
1974 static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie) tegra_pcie_debugfs_init() argument
1978 pcie->debugfs = debugfs_create_dir("pcie", NULL); tegra_pcie_debugfs_init()
1979 if (!pcie->debugfs) tegra_pcie_debugfs_init()
1982 file = debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs, tegra_pcie_debugfs_init()
1983 pcie, &tegra_pcie_ports_ops); tegra_pcie_debugfs_init()
1990 debugfs_remove_recursive(pcie->debugfs); tegra_pcie_debugfs_init()
1991 pcie->debugfs = NULL; tegra_pcie_debugfs_init()
1998 struct tegra_pcie *pcie; tegra_pcie_probe() local
2005 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); tegra_pcie_probe()
2006 if (!pcie) tegra_pcie_probe()
2009 INIT_LIST_HEAD(&pcie->buses); tegra_pcie_probe()
2010 INIT_LIST_HEAD(&pcie->ports); tegra_pcie_probe()
2011 pcie->soc_data = match->data; tegra_pcie_probe()
2012 pcie->dev = &pdev->dev; tegra_pcie_probe()
2014 err = tegra_pcie_parse_dt(pcie); tegra_pcie_probe()
2020 err = tegra_pcie_get_resources(pcie); tegra_pcie_probe()
2026 err = tegra_pcie_enable_controller(pcie); tegra_pcie_probe()
2031 tegra_pcie_setup_translations(pcie); tegra_pcie_probe()
2034 err = tegra_pcie_enable_msi(pcie); tegra_pcie_probe()
2043 err = tegra_pcie_enable(pcie); tegra_pcie_probe()
2050 err = tegra_pcie_debugfs_init(pcie); tegra_pcie_probe()
2056 platform_set_drvdata(pdev, pcie); tegra_pcie_probe()
2061 tegra_pcie_disable_msi(pcie); tegra_pcie_probe()
2063 tegra_pcie_put_resources(pcie); tegra_pcie_probe()
2069 .name = "tegra-pcie",
|
| H A D | pcie-iproc.c | 31 #include "pcie-iproc.h"
75 struct iproc_pcie *pcie = sys_to_pcie(sys); iproc_pcie_map_cfg_bus() local
86 pcie->base + CFG_IND_ADDR_OFFSET); iproc_pcie_map_cfg_bus()
87 return (pcie->base + CFG_IND_DATA_OFFSET); iproc_pcie_map_cfg_bus()
99 writel(val, pcie->base + CFG_ADDR_OFFSET); iproc_pcie_map_cfg_bus()
101 return (pcie->base + CFG_DATA_OFFSET); iproc_pcie_map_cfg_bus()
110 static void iproc_pcie_reset(struct iproc_pcie *pcie) iproc_pcie_reset() argument
119 writel(val, pcie->base + CLK_CONTROL_OFFSET); iproc_pcie_reset()
122 writel(val, pcie->base + CLK_CONTROL_OFFSET); iproc_pcie_reset()
126 static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus) iproc_pcie_check_link() argument
136 dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type); iproc_pcie_check_link()
176 dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN"); iproc_pcie_check_link()
181 static void iproc_pcie_enable(struct iproc_pcie *pcie) iproc_pcie_enable() argument
183 writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN); iproc_pcie_enable()
186 int iproc_pcie_setup(struct iproc_pcie *pcie) iproc_pcie_setup() argument
191 if (!pcie || !pcie->dev || !pcie->base) iproc_pcie_setup()
194 if (pcie->phy) { iproc_pcie_setup()
195 ret = phy_init(pcie->phy); iproc_pcie_setup()
197 dev_err(pcie->dev, "unable to initialize PCIe PHY\n"); iproc_pcie_setup()
201 ret = phy_power_on(pcie->phy); iproc_pcie_setup()
203 dev_err(pcie->dev, "unable to power on PCIe PHY\n"); iproc_pcie_setup()
209 iproc_pcie_reset(pcie); iproc_pcie_setup()
211 pcie->sysdata.private_data = pcie; iproc_pcie_setup()
213 bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, iproc_pcie_setup()
214 &pcie->sysdata, pcie->resources); iproc_pcie_setup()
216 dev_err(pcie->dev, "unable to create PCI root bus\n"); iproc_pcie_setup()
220 pcie->root_bus = bus; iproc_pcie_setup()
222 ret = iproc_pcie_check_link(pcie, bus); iproc_pcie_setup()
224 dev_err(pcie->dev, "no PCIe EP device detected\n"); iproc_pcie_setup()
228 iproc_pcie_enable(pcie); iproc_pcie_setup()
242 if (pcie->phy) iproc_pcie_setup()
243 phy_power_off(pcie->phy); iproc_pcie_setup()
245 if (pcie->phy) iproc_pcie_setup()
246 phy_exit(pcie->phy); iproc_pcie_setup()
252 int iproc_pcie_remove(struct iproc_pcie *pcie) iproc_pcie_remove() argument
254 pci_stop_root_bus(pcie->root_bus); iproc_pcie_remove()
255 pci_remove_root_bus(pcie->root_bus); iproc_pcie_remove()
257 if (pcie->phy) { iproc_pcie_remove()
258 phy_power_off(pcie->phy); iproc_pcie_remove()
259 phy_exit(pcie->phy); iproc_pcie_remove()
|
| H A D | pcie-rcar.c | 6 * arch/sh/drivers/pci/pcie-sh7786.c
31 #define DRV_NAME "rcar-pcie"
143 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val, rcar_pci_write_reg() argument
146 writel(val, pcie->base + reg); rcar_pci_write_reg()
149 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie, rcar_pci_read_reg() argument
152 return readl(pcie->base + reg); rcar_pci_read_reg()
160 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) rcar_rmw32() argument
163 u32 val = rcar_pci_read_reg(pcie, where & ~3); rcar_rmw32()
167 rcar_pci_write_reg(pcie, val, where & ~3); rcar_rmw32()
170 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) rcar_read_conf() argument
173 u32 val = rcar_pci_read_reg(pcie, where & ~3); rcar_read_conf()
179 static int rcar_pcie_config_access(struct rcar_pcie *pcie, rcar_pcie_config_access() argument
210 *data = rcar_pci_read_reg(pcie, PCICONF(index)); rcar_pcie_config_access()
214 pcie->root_bus_nr = *data & 0xff; rcar_pcie_config_access()
216 rcar_pci_write_reg(pcie, *data, PCICONF(index)); rcar_pcie_config_access()
222 if (pcie->root_bus_nr < 0) rcar_pcie_config_access()
226 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); rcar_pcie_config_access()
229 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | rcar_pcie_config_access()
233 if (bus->parent->number == pcie->root_bus_nr) rcar_pcie_config_access()
234 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR); rcar_pcie_config_access()
236 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR); rcar_pcie_config_access()
239 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) rcar_pcie_config_access()
243 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & rcar_pcie_config_access()
248 *data = rcar_pci_read_reg(pcie, PCIECDR); rcar_pcie_config_access()
250 rcar_pci_write_reg(pcie, *data, PCIECDR); rcar_pcie_config_access()
253 rcar_pci_write_reg(pcie, 0, PCIECCTLR); rcar_pcie_config_access()
261 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata); rcar_pcie_read_conf() local
264 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ, rcar_pcie_read_conf()
276 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n", rcar_pcie_read_conf()
286 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata); rcar_pcie_write_conf() local
290 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ, rcar_pcie_write_conf()
295 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n", rcar_pcie_write_conf()
309 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE, rcar_pcie_write_conf()
320 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie) rcar_pcie_setup_window() argument
322 struct resource *res = &pcie->res[win]; rcar_pcie_setup_window()
329 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win)); rcar_pcie_setup_window()
337 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win)); rcar_pcie_setup_window()
344 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win)); rcar_pcie_setup_window()
345 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F, rcar_pcie_setup_window()
353 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win)); rcar_pcie_setup_window()
358 struct rcar_pcie *pcie = sys_to_pcie(sys); rcar_pcie_setup() local
362 pcie->root_bus_nr = -1; rcar_pcie_setup()
367 res = &pcie->res[i]; rcar_pcie_setup()
371 rcar_pcie_setup_window(i, pcie); rcar_pcie_setup()
379 pci_add_resource(&sys->resources, &pcie->busn); rcar_pcie_setup()
390 static void rcar_pcie_enable(struct rcar_pcie *pcie) rcar_pcie_enable() argument
392 struct platform_device *pdev = to_platform_device(pcie->dev); rcar_pcie_enable()
395 rcar_pci.private_data = (void **)&pcie; rcar_pcie_enable()
397 rcar_pci.msi_ctrl = &pcie->msi.chip; rcar_pcie_enable()
403 static int phy_wait_for_ack(struct rcar_pcie *pcie) phy_wait_for_ack() argument
408 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) phy_wait_for_ack()
414 dev_err(pcie->dev, "Access to PCIe phy timed out\n"); phy_wait_for_ack()
419 static void phy_write_reg(struct rcar_pcie *pcie, phy_write_reg() argument
431 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); phy_write_reg()
432 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); phy_write_reg()
435 phy_wait_for_ack(pcie); phy_write_reg()
438 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); phy_write_reg()
439 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); phy_write_reg()
442 phy_wait_for_ack(pcie); phy_write_reg()
445 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie) rcar_pcie_wait_for_dl() argument
450 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE)) rcar_pcie_wait_for_dl()
459 static int rcar_pcie_hw_init(struct rcar_pcie *pcie) rcar_pcie_hw_init() argument
464 rcar_pci_write_reg(pcie, 0, PCIETCTLR); rcar_pcie_hw_init()
467 rcar_pci_write_reg(pcie, 1, PCIEMSR); rcar_pcie_hw_init()
474 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1); rcar_pcie_hw_init()
480 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); rcar_pcie_hw_init()
481 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); rcar_pcie_hw_init()
484 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); rcar_pcie_hw_init()
485 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), rcar_pcie_hw_init()
487 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, rcar_pcie_hw_init()
491 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, rcar_pcie_hw_init()
495 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); rcar_pcie_hw_init()
498 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); rcar_pcie_hw_init()
501 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); rcar_pcie_hw_init()
505 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); rcar_pcie_hw_init()
508 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); rcar_pcie_hw_init()
511 err = rcar_pcie_wait_for_dl(pcie); rcar_pcie_hw_init()
516 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); rcar_pcie_hw_init()
523 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie) rcar_pcie_hw_init_h1() argument
528 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); rcar_pcie_hw_init_h1()
529 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); rcar_pcie_hw_init_h1()
530 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); rcar_pcie_hw_init_h1()
531 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); rcar_pcie_hw_init_h1()
532 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); rcar_pcie_hw_init_h1()
533 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); rcar_pcie_hw_init_h1()
534 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); rcar_pcie_hw_init_h1()
535 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); rcar_pcie_hw_init_h1()
536 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); rcar_pcie_hw_init_h1()
537 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); rcar_pcie_hw_init_h1()
538 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); rcar_pcie_hw_init_h1()
539 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); rcar_pcie_hw_init_h1()
541 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); rcar_pcie_hw_init_h1()
542 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); rcar_pcie_hw_init_h1()
543 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); rcar_pcie_hw_init_h1()
546 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR)) rcar_pcie_hw_init_h1()
547 return rcar_pcie_hw_init(pcie); rcar_pcie_hw_init_h1()
581 struct rcar_pcie *pcie = data; rcar_pcie_msi_irq() local
582 struct rcar_msi *msi = &pcie->msi; rcar_pcie_msi_irq()
585 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); rcar_pcie_msi_irq()
596 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR); rcar_pcie_msi_irq()
603 dev_info(pcie->dev, "unhandled MSI\n"); rcar_pcie_msi_irq()
606 dev_dbg(pcie->dev, "unexpected MSI\n"); rcar_pcie_msi_irq()
610 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); rcar_pcie_msi_irq()
620 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip); rcar_msi_setup_irq() local
637 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; rcar_msi_setup_irq()
638 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); rcar_msi_setup_irq()
676 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie) rcar_pcie_enable_msi() argument
678 struct platform_device *pdev = to_platform_device(pcie->dev); rcar_pcie_enable_msi()
679 struct rcar_msi *msi = &pcie->msi; rcar_pcie_enable_msi()
685 msi->chip.dev = pcie->dev; rcar_pcie_enable_msi()
689 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR, rcar_pcie_enable_msi()
699 rcar_msi_irq_chip.name, pcie); rcar_pcie_enable_msi()
707 rcar_msi_irq_chip.name, pcie); rcar_pcie_enable_msi()
717 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR); rcar_pcie_enable_msi()
718 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR); rcar_pcie_enable_msi()
721 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER); rcar_pcie_enable_msi()
731 struct rcar_pcie *pcie) rcar_pcie_get_resources()
740 pcie->clk = devm_clk_get(&pdev->dev, "pcie"); rcar_pcie_get_resources()
741 if (IS_ERR(pcie->clk)) { rcar_pcie_get_resources()
742 dev_err(pcie->dev, "cannot get platform clock\n"); rcar_pcie_get_resources()
743 return PTR_ERR(pcie->clk); rcar_pcie_get_resources()
745 err = clk_prepare_enable(pcie->clk); rcar_pcie_get_resources()
749 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus"); rcar_pcie_get_resources()
750 if (IS_ERR(pcie->bus_clk)) { rcar_pcie_get_resources()
751 dev_err(pcie->dev, "cannot get pcie bus clock\n"); rcar_pcie_get_resources()
752 err = PTR_ERR(pcie->bus_clk); rcar_pcie_get_resources()
755 err = clk_prepare_enable(pcie->bus_clk); rcar_pcie_get_resources()
761 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n"); rcar_pcie_get_resources()
765 pcie->msi.irq1 = i; rcar_pcie_get_resources()
769 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n"); rcar_pcie_get_resources()
773 pcie->msi.irq2 = i; rcar_pcie_get_resources()
775 pcie->base = devm_ioremap_resource(&pdev->dev, &res); rcar_pcie_get_resources()
776 if (IS_ERR(pcie->base)) { rcar_pcie_get_resources()
777 err = PTR_ERR(pcie->base); rcar_pcie_get_resources()
784 clk_disable_unprepare(pcie->bus_clk); rcar_pcie_get_resources()
786 clk_disable_unprepare(pcie->clk); rcar_pcie_get_resources()
791 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, rcar_pcie_inbound_ranges() argument
830 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx)); rcar_pcie_inbound_ranges()
831 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx)); rcar_pcie_inbound_ranges()
832 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx)); rcar_pcie_inbound_ranges()
834 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1)); rcar_pcie_inbound_ranges()
835 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1)); rcar_pcie_inbound_ranges()
836 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1)); rcar_pcie_inbound_ranges()
843 dev_err(pcie->dev, "Failed to map inbound regions!\n"); rcar_pcie_inbound_ranges()
870 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie, rcar_pcie_parse_map_dma_ranges() argument
884 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", rcar_pcie_parse_map_dma_ranges()
887 err = rcar_pcie_inbound_ranges(pcie, &range, &index); rcar_pcie_parse_map_dma_ranges()
896 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
897 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
898 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
905 struct rcar_pcie *pcie; rcar_pcie_probe() local
913 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); rcar_pcie_probe()
914 if (!pcie) rcar_pcie_probe()
917 pcie->dev = &pdev->dev; rcar_pcie_probe()
918 platform_set_drvdata(pdev, pcie); rcar_pcie_probe()
921 if (of_pci_parse_bus_range(pdev->dev.of_node, &pcie->busn)) { rcar_pcie_probe()
931 err = rcar_pcie_get_resources(pdev, pcie); rcar_pcie_probe()
939 &pcie->res[win++]); rcar_pcie_probe()
947 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node); rcar_pcie_probe()
952 err = rcar_pcie_enable_msi(pcie); rcar_pcie_probe()
961 of_id = of_match_device(rcar_pcie_of_match, pcie->dev); rcar_pcie_probe()
967 err = hw_init_fn(pcie); rcar_pcie_probe()
973 data = rcar_pci_read_reg(pcie, MACSR); rcar_pcie_probe()
976 rcar_pcie_enable(pcie); rcar_pcie_probe()
730 rcar_pcie_get_resources(struct platform_device *pdev, struct rcar_pcie *pcie) rcar_pcie_get_resources() argument
|
| H A D | pci-mvebu.c | 127 struct mvebu_pcie *pcie; member in struct:mvebu_pcie_port
332 dev_err(&port->pcie->pdev->dev, mvebu_pcie_add_windows()
369 dev_WARN(&port->pcie->pdev->dev, mvebu_pcie_handle_iobase_change()
383 port->iowin_base = port->pcie->io.start + iobase; mvebu_pcie_handle_iobase_change()
616 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie, mvebu_pcie_find_port() argument
622 for (i = 0; i < pcie->nports; i++) { mvebu_pcie_find_port()
623 struct mvebu_pcie_port *port = &pcie->ports[i]; mvebu_pcie_find_port()
640 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); mvebu_pcie_wr_conf() local
644 port = mvebu_pcie_find_port(pcie, bus, devfn); mvebu_pcie_wr_conf()
677 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); mvebu_pcie_rd_conf() local
681 port = mvebu_pcie_find_port(pcie, bus, devfn); mvebu_pcie_rd_conf()
723 struct mvebu_pcie *pcie = sys_to_pcie(sys); mvebu_pcie_setup() local
726 pcie->mem.name = "PCI MEM"; mvebu_pcie_setup()
727 pcie->realio.name = "PCI I/O"; mvebu_pcie_setup()
729 if (request_resource(&iomem_resource, &pcie->mem)) mvebu_pcie_setup()
732 if (resource_size(&pcie->realio) != 0) { mvebu_pcie_setup()
733 if (request_resource(&ioport_resource, &pcie->realio)) { mvebu_pcie_setup()
734 release_resource(&pcie->mem); mvebu_pcie_setup()
737 pci_add_resource_offset(&sys->resources, &pcie->realio, mvebu_pcie_setup()
740 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); mvebu_pcie_setup()
741 pci_add_resource(&sys->resources, &pcie->busn); mvebu_pcie_setup()
743 for (i = 0; i < pcie->nports; i++) { mvebu_pcie_setup()
744 struct mvebu_pcie_port *port = &pcie->ports[i]; mvebu_pcie_setup()
756 struct mvebu_pcie *pcie = sys_to_pcie(sys); mvebu_pcie_scan_bus() local
759 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr, mvebu_pcie_scan_bus()
799 static void mvebu_pcie_enable(struct mvebu_pcie *pcie) mvebu_pcie_enable() argument
806 hw.msi_ctrl = pcie->msi; mvebu_pcie_enable()
810 hw.private_data = (void **)&pcie; mvebu_pcie_enable()
888 static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie) mvebu_pcie_msi_enable() argument
892 msi_node = of_parse_phandle(pcie->pdev->dev.of_node, mvebu_pcie_msi_enable()
897 pcie->msi = of_pci_find_msi_chip_by_node(msi_node); mvebu_pcie_msi_enable()
899 if (pcie->msi) mvebu_pcie_msi_enable()
900 pcie->msi->dev = &pcie->pdev->dev; mvebu_pcie_msi_enable()
905 struct mvebu_pcie *pcie; mvebu_pcie_suspend() local
908 pcie = dev_get_drvdata(dev); mvebu_pcie_suspend()
909 for (i = 0; i < pcie->nports; i++) { mvebu_pcie_suspend()
910 struct mvebu_pcie_port *port = pcie->ports + i; mvebu_pcie_suspend()
919 struct mvebu_pcie *pcie; mvebu_pcie_resume() local
922 pcie = dev_get_drvdata(dev); mvebu_pcie_resume()
923 for (i = 0; i < pcie->nports; i++) { mvebu_pcie_resume()
924 struct mvebu_pcie_port *port = pcie->ports + i; mvebu_pcie_resume()
934 struct mvebu_pcie *pcie; mvebu_pcie_probe() local
939 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie), mvebu_pcie_probe()
941 if (!pcie) mvebu_pcie_probe()
944 pcie->pdev = pdev; mvebu_pcie_probe()
945 platform_set_drvdata(pdev, pcie); mvebu_pcie_probe()
948 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem); mvebu_pcie_probe()
949 if (resource_size(&pcie->mem) == 0) { mvebu_pcie_probe()
954 mvebu_mbus_get_pcie_io_aperture(&pcie->io); mvebu_pcie_probe()
956 if (resource_size(&pcie->io) != 0) { mvebu_pcie_probe()
957 pcie->realio.flags = pcie->io.flags; mvebu_pcie_probe()
958 pcie->realio.start = PCIBIOS_MIN_IO; mvebu_pcie_probe()
959 pcie->realio.end = min_t(resource_size_t, mvebu_pcie_probe()
961 resource_size(&pcie->io)); mvebu_pcie_probe()
963 pcie->realio = pcie->io; mvebu_pcie_probe()
966 ret = of_pci_parse_bus_range(np, &pcie->busn); mvebu_pcie_probe()
980 pcie->ports = devm_kzalloc(&pdev->dev, i * mvebu_pcie_probe()
983 if (!pcie->ports) mvebu_pcie_probe()
988 struct mvebu_pcie_port *port = &pcie->ports[i]; mvebu_pcie_probe()
994 port->pcie = pcie; mvebu_pcie_probe()
996 if (of_property_read_u32(child, "marvell,pcie-port", mvebu_pcie_probe()
999 "ignoring PCIe DT node, missing pcie-port property\n"); mvebu_pcie_probe()
1003 if (of_property_read_u32(child, "marvell,pcie-lane", mvebu_pcie_probe()
1007 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d", mvebu_pcie_probe()
1022 if (resource_size(&pcie->io) != 0) mvebu_pcie_probe()
1037 "pcie%d.%d-reset", port->port, port->lane); mvebu_pcie_probe()
1081 pcie->nports = i; mvebu_pcie_probe()
1084 pci_ioremap_io(i, pcie->io.start + i); mvebu_pcie_probe()
1086 mvebu_pcie_msi_enable(pcie); mvebu_pcie_probe()
1087 mvebu_pcie_enable(pcie); mvebu_pcie_probe()
1089 platform_set_drvdata(pdev, pcie); mvebu_pcie_probe()
1095 { .compatible = "marvell,armada-xp-pcie", },
1096 { .compatible = "marvell,armada-370-pcie", },
1097 { .compatible = "marvell,dove-pcie", },
1098 { .compatible = "marvell,kirkwood-pcie", },
1110 .name = "mvebu-pcie",
|
| H A D | pcie-iproc.h | 39 int iproc_pcie_setup(struct iproc_pcie *pcie);
40 int iproc_pcie_remove(struct iproc_pcie *pcie);
|
| H A D | pci-exynos.c | 27 #include "pcie-designware.h"
105 static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg) exynos_elb_writel() argument
107 writel(val, pcie->elbi_base + reg); exynos_elb_writel()
110 static inline u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg) exynos_elb_readl() argument
112 return readl(pcie->elbi_base + reg); exynos_elb_readl()
115 static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg) exynos_phy_writel() argument
117 writel(val, pcie->phy_base + reg); exynos_phy_writel()
120 static inline u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg) exynos_phy_readl() argument
122 return readl(pcie->phy_base + reg); exynos_phy_readl()
125 static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg) exynos_blk_writel() argument
127 writel(val, pcie->block_base + reg); exynos_blk_writel()
130 static inline u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg) exynos_blk_readl() argument
132 return readl(pcie->block_base + reg); exynos_blk_readl()
515 IRQF_SHARED, "exynos-pcie", pp); exynos_add_pcie_port()
531 "exynos-pcie", pp); exynos_add_pcie_port()
571 exynos_pcie->clk = devm_clk_get(&pdev->dev, "pcie"); exynos_pcie_probe()
573 dev_err(&pdev->dev, "Failed to get pcie rc clock\n"); exynos_pcie_probe()
582 dev_err(&pdev->dev, "Failed to get pcie bus clock\n"); exynos_pcie_probe()
636 { .compatible = "samsung,exynos5440-pcie", },
644 .name = "exynos-pcie",
|
| H A D | pcie-spear13xx.c | 26 #include "pcie-designware.h"
285 "spear1340-pcie", pp); spear13xx_add_pcie_port()
316 spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy"); spear13xx_pcie_probe()
322 dev_err(dev, "couldn't get pcie-phy\n"); spear13xx_pcie_probe()
330 dev_err(dev, "couldn't get clk for pcie\n"); spear13xx_pcie_probe()
335 dev_err(dev, "couldn't enable clk for pcie\n"); spear13xx_pcie_probe()
352 if (of_property_read_bool(np, "st,pcie-is-gen1")) spear13xx_pcie_probe()
369 { .compatible = "st,spear1340-pcie", },
377 .name = "spear-pcie",
|
| H A D | pci-dra7xx.c | 2 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
27 #include "pcie-designware.h"
75 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset) dra7xx_pcie_readl() argument
77 return readl(pcie->base + offset); dra7xx_pcie_readl()
80 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, dra7xx_pcie_writel() argument
83 writel(value, pcie->base + offset); dra7xx_pcie_writel()
294 "dra7-pcie-msi", pp); dra7xx_add_pcie_port()
346 IRQF_SHARED, "dra7xx-pcie-main", dra7xx); dra7xx_pcie_probe()
368 snprintf(name, sizeof(name), "pcie-phy%d", i); dra7xx_pcie_probe()
441 { .compatible = "ti,dra7-pcie", },
449 .name = "dra7-pcie",
|
| H A D | pci-imx6.c | 30 #include "pcie-designware.h"
38 struct clk *pcie; member in struct:imx6_pcie
272 ret = clk_prepare_enable(imx6_pcie->pcie); imx6_pcie_deassert_core_reset()
274 dev_err(pp->dev, "unable to enable pcie clock\n"); imx6_pcie_deassert_core_reset()
318 /* configure constant input signal to the pcie ctrl and phy */ imx6_pcie_init_phy()
538 "mx6-pcie-msi", pp); imx6_add_pcie_port()
607 imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie"); imx6_pcie_probe()
608 if (IS_ERR(imx6_pcie->pcie)) { imx6_pcie_probe()
610 "pcie clock source missing or invalid\n"); imx6_pcie_probe()
611 return PTR_ERR(imx6_pcie->pcie); imx6_pcie_probe()
639 { .compatible = "fsl,imx6q-pcie", },
646 .name = "imx6q-pcie",
|
| H A D | pci-keystone.c | 8 * Implementation based on pci-exynos.c and pcie-designware.c
29 #include "pcie-designware.h"
32 #define DRIVER_NAME "keystone-pcie"
329 .compatible = "ti,keystone-pcie",
362 phy = devm_phy_get(dev, "pcie-phy"); ks_pcie_probe()
380 ks_pcie->clk = devm_clk_get(dev, "pcie"); ks_pcie_probe()
382 dev_err(dev, "Failed to get pcie rc clock\n"); ks_pcie_probe()
404 .name = "keystone-pcie",
|
| H A D | pci-xgene.c | 355 dev_warn(port->dev, "invalid pcie dma-range config\n"); xgene_pcie_setup_ib_reg()
516 {.compatible = "apm,xgene-pcie",},
522 .name = "xgene-pcie",
|
| H A D | pcie-xilinx.c | 780 "xilinx-pcie", port); xilinx_pcie_parse_dt()
874 { .compatible = "xlnx,axi-pcie-host-1.00.a", },
880 .name = "xilinx-pcie",
|
| H A D | pci-keystone-dw.c | 23 #include "pcie-designware.h"
491 * We set these same and is used in pcie rd/wr_other_conf ks_dw_pcie_host_init()
|
| H A D | pcie-designware.c | 26 #include "pcie-designware.h"
|
| /linux-4.1.27/drivers/net/wireless/iwlwifi/ |
| H A D | Makefile | 9 iwlwifi-objs += pcie/drv.o pcie/rx.o pcie/tx.o pcie/trans.o
|
| /linux-4.1.27/arch/powerpc/platforms/85xx/ |
| H A D | common.c | 35 { .compatible = "fsl,mpc8548-pcie", },
36 { .compatible = "fsl,p1022-pcie", },
37 { .compatible = "fsl,p1010-pcie", },
38 { .compatible = "fsl,p1023-pcie", },
39 { .compatible = "fsl,p4080-pcie", },
40 { .compatible = "fsl,qoriq-pcie-v2.4", },
41 { .compatible = "fsl,qoriq-pcie-v2.3", },
42 { .compatible = "fsl,qoriq-pcie-v2.2", },
|
| H A D | corenet_generic.c | 103 .compatible = "fsl,p4080-pcie",
106 .compatible = "fsl,qoriq-pcie-v2.2",
109 .compatible = "fsl,qoriq-pcie-v2.3",
112 .compatible = "fsl,qoriq-pcie-v2.4",
115 .compatible = "fsl,qoriq-pcie-v3.0",
|
| H A D | ge_imp3a.c | 94 of_device_is_compatible(np, "fsl,mpc8548-pcie") || ge_imp3a_pci_assign_primary()
95 of_device_is_compatible(np, "fsl,p2020-pcie")) { ge_imp3a_pci_assign_primary()
|
| H A D | mpc85xx_cds.c | 299 of_device_is_compatible(np, "fsl,mpc8548-pcie")) && mpc85xx_cds_pci_assign_primary()
|
| /linux-4.1.27/drivers/firmware/efi/ |
| H A D | cper.c | 353 static void cper_print_pcie(const char *pfx, const struct cper_sec_pcie *pcie, cper_print_pcie() argument
356 if (pcie->validation_bits & CPER_PCIE_VALID_PORT_TYPE) cper_print_pcie()
357 printk("%s""port_type: %d, %s\n", pfx, pcie->port_type, cper_print_pcie()
358 pcie->port_type < ARRAY_SIZE(pcie_port_type_strs) ? cper_print_pcie()
359 pcie_port_type_strs[pcie->port_type] : "unknown"); cper_print_pcie()
360 if (pcie->validation_bits & CPER_PCIE_VALID_VERSION) cper_print_pcie()
362 pcie->version.major, pcie->version.minor); cper_print_pcie()
363 if (pcie->validation_bits & CPER_PCIE_VALID_COMMAND_STATUS) cper_print_pcie()
365 pcie->command, pcie->status); cper_print_pcie()
366 if (pcie->validation_bits & CPER_PCIE_VALID_DEVICE_ID) { cper_print_pcie()
369 pcie->device_id.segment, pcie->device_id.bus, cper_print_pcie()
370 pcie->device_id.device, pcie->device_id.function); cper_print_pcie()
372 pcie->device_id.slot >> CPER_PCIE_SLOT_SHIFT); cper_print_pcie()
374 pcie->device_id.secondary_bus); cper_print_pcie()
376 pcie->device_id.vendor_id, pcie->device_id.device_id); cper_print_pcie()
377 p = pcie->device_id.class_code; cper_print_pcie()
380 if (pcie->validation_bits & CPER_PCIE_VALID_SERIAL_NUMBER) cper_print_pcie()
382 pcie->serial_number.lower, pcie->serial_number.upper); cper_print_pcie()
383 if (pcie->validation_bits & CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS) cper_print_pcie()
386 pfx, pcie->bridge.secondary_status, pcie->bridge.control); cper_print_pcie()
422 struct cper_sec_pcie *pcie = (void *)(gdata + 1); cper_estatus_print_section() local
424 if (gdata->error_data_length >= sizeof(*pcie)) cper_estatus_print_section()
425 cper_print_pcie(newpfx, pcie, gdata); cper_estatus_print_section()
|
| /linux-4.1.27/drivers/pinctrl/ |
| H A D | pinctrl-tegra-xusb.c | 714 PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
715 PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
716 PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
717 PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
718 PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
747 "pcie-0",
748 "pcie-1",
749 "pcie-2",
750 "pcie-3",
751 "pcie-4",
756 "pcie-0",
757 "pcie-1",
758 "pcie-2",
759 "pcie-3",
760 "pcie-4",
765 "pcie-0",
766 "pcie-1",
767 "pcie-2",
768 "pcie-3",
769 "pcie-4",
777 "pcie-0",
778 "pcie-1",
779 "pcie-2",
780 "pcie-3",
781 "pcie-4",
796 TEGRA124_FUNCTION(pcie),
849 TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
850 TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
851 TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
852 TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
853 TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
|
| H A D | pinctrl-tegra20.c | 1931 FUNCTION(pcie),
|
| H A D | pinctrl-tegra30.c | 2063 FUNCTION(pcie),
|
| /linux-4.1.27/drivers/pci/hotplug/ |
| H A D | pciehp_acpi.c | 47 "Slot detection mode: pcie, acpi, auto\n"
48 " pcie - Use PCIe based slot detection\n"
51 " slot ids are found. Otherwise, use pcie option\n");
66 if (!strcmp(pciehp_detect_mode, "pcie")) parse_detect_mode()
|
| H A D | pciehp_hpc.c | 46 return ctrl->pcie->port; ctrl_dev()
82 int retval, irq = ctrl->pcie->irq; pciehp_request_irq()
104 free_irq(ctrl->pcie->irq, ctrl); pciehp_free_irq()
308 found = pci_bus_check_dev(ctrl->pcie->port->subordinate, pciehp_check_link_status()
319 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); pciehp_check_link_status()
357 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); pciehp_get_attention_status()
383 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); pciehp_get_power_status()
448 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); pciehp_set_attention_status()
461 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, pciehp_green_led_on()
475 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, pciehp_green_led_off()
489 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, pciehp_green_led_blink()
509 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, pciehp_power_on_slot()
525 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, pciehp_power_off_slot()
642 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); pcie_enable_notification()
655 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); pcie_disable_notification()
684 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); pciehp_reset_slot()
688 pci_reset_bridge_secondary_bus(ctrl->pcie->port); pciehp_reset_slot()
693 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); pciehp_reset_slot()
753 struct pci_dev *pdev = ctrl->pcie->port; dbg_ctrl()
812 ctrl->pcie = dev; pcie_init()
|
| H A D | pciehp.h | 62 dev_printk(KERN_DEBUG, &ctrl->pcie->device, \
66 dev_err(&ctrl->pcie->device, format, ## arg)
68 dev_info(&ctrl->pcie->device, format, ## arg)
70 dev_warn(&ctrl->pcie->device, format, ## arg)
91 struct pcie_device *pcie; /* PCI Express port service */ member in struct:controller
|
| H A D | pciehp_pci.c | 40 struct pci_dev *bridge = p_slot->ctrl->pcie->port; pciehp_configure_device()
82 struct pci_bus *parent = p_slot->ctrl->pcie->port->subordinate; pciehp_unconfigure_device()
|
| H A D | pciehp_ctrl.c | 207 struct pci_bus *parent = ctrl->pcie->port->subordinate; board_added()
303 pci_domain_nr(p_slot->ctrl->pcie->port->subordinate), pciehp_power_thread()
304 p_slot->ctrl->pcie->port->subordinate->number); pciehp_power_thread()
315 pci_domain_nr(p_slot->ctrl->pcie->port->subordinate), pciehp_power_thread()
316 p_slot->ctrl->pcie->port->subordinate->number); pciehp_power_thread()
|
| H A D | pciehp_core.c | 133 pci_domain_nr(ctrl->pcie->port->subordinate), init_slot()
134 ctrl->pcie->port->subordinate->number, PSN(ctrl)); init_slot()
136 ctrl->pcie->port->subordinate, 0, name); init_slot()
|
| H A D | acpiphp_glue.c | 450 /* quirk, or pcie could set it already */ check_hotplug_bridge()
|
| /linux-4.1.27/arch/powerpc/sysdev/ |
| H A D | fsl_pci.c | 182 /* atmu setup for fsl pci/pcie controller */ setup_pci_atmu()
636 struct mpc83xx_pcie_priv *pcie = hose->dn->data; mpc83xx_pcie_remap_cfg() local
648 return pcie->cfg_type0 + offset; mpc83xx_pcie_remap_cfg()
650 if (pcie->dev_base == dev_base) mpc83xx_pcie_remap_cfg()
653 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); mpc83xx_pcie_remap_cfg()
655 pcie->dev_base = dev_base; mpc83xx_pcie_remap_cfg()
657 return pcie->cfg_type1 + offset; mpc83xx_pcie_remap_cfg()
681 struct mpc83xx_pcie_priv *pcie; mpc83xx_pcie_setup() local
685 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); mpc83xx_pcie_setup()
686 if (!pcie) mpc83xx_pcie_setup()
689 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); mpc83xx_pcie_setup()
690 if (!pcie->cfg_type0) mpc83xx_pcie_setup()
693 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); mpc83xx_pcie_setup()
700 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); mpc83xx_pcie_setup()
701 if (!pcie->cfg_type1) mpc83xx_pcie_setup()
705 hose->dn->data = pcie; mpc83xx_pcie_setup()
709 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); mpc83xx_pcie_setup()
710 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); mpc83xx_pcie_setup()
717 iounmap(pcie->cfg_type0); mpc83xx_pcie_setup()
719 kfree(pcie); mpc83xx_pcie_setup()
788 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { mpc83xx_add_bridge()
820 struct mpc83xx_pcie_priv *pcie = hose->dn->data; fsl_pci_immrbar_base() local
825 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; fsl_pci_immrbar_base()
1018 { .compatible = "fsl,mpc8548-pcie", },
1020 { .compatible = "fsl,mpc8641-pcie", },
1021 { .compatible = "fsl,qoriq-pcie", },
1022 { .compatible = "fsl,qoriq-pcie-v2.1", },
1023 { .compatible = "fsl,qoriq-pcie-v2.2", },
1024 { .compatible = "fsl,qoriq-pcie-v2.3", },
1025 { .compatible = "fsl,qoriq-pcie-v2.4", },
1026 { .compatible = "fsl,qoriq-pcie-v3.0", },
1032 { .compatible = "fsl,p1022-pcie", },
1033 { .compatible = "fsl,p4080-pcie", },
|
| H A D | mpic_u3msi.c | 100 if (of_device_is_compatible(hose->dn, "u4-pcie") || find_u4_magic_addr()
101 of_device_is_compatible(hose->dn, "U4-pcie")) find_u4_magic_addr()
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| H A D | dart_iommu.c | 338 if (of_device_is_compatible(np, "U4-pcie") || dart_device_on_pcie()
339 of_device_is_compatible(np, "u4-pcie")) { dart_device_on_pcie()
|
| H A D | ppc4xx_pci.c | 1060 /* Return the number of pcie port */ apm821xx_pciex_core_init()
1650 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x" ppc4xx_pciex_read_config()
1690 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x" ppc4xx_pciex_write_config()
|
| /linux-4.1.27/arch/arm/plat-orion/include/plat/ |
| H A D | pcie.h | 2 * arch/arm/plat-orion/include/plat/pcie.h
|
| /linux-4.1.27/drivers/net/wireless/mwifiex/ |
| H A D | pcie.c | 29 #include "pcie.h"
85 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_ok_to_access_hw()
202 card->pcie.firmware = data->firmware; mwifiex_pcie_probe()
203 card->pcie.reg = data->reg; mwifiex_pcie_probe()
204 card->pcie.blksz_fw_dl = data->blksz_fw_dl; mwifiex_pcie_probe()
205 card->pcie.tx_buf_size = data->tx_buf_size; mwifiex_pcie_probe()
206 card->pcie.can_dump_fw = data->can_dump_fw; mwifiex_pcie_probe()
207 card->pcie.can_ext_scan = data->can_ext_scan; mwifiex_pcie_probe()
381 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pm_wakeup_card()
460 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_init_txq_ring()
490 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_init_rxq_ring()
595 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_cleanup_txq_ring()
633 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_cleanup_rxq_ring()
695 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_create_txbd_ring()
740 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_delete_txbd_ring()
763 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_create_rxbd_ring()
807 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_delete_rxbd_ring()
830 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_create_evtbd_ring()
870 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_delete_evtbd_ring()
1014 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_send_data_complete()
1106 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_send_data()
1233 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_process_recv_data()
1376 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_send_boot_cmd()
1440 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_init_fw_port()
1459 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_send_cmd()
1571 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_process_cmd_complete()
1672 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_process_event_ready()
1759 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_event_complete()
1840 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_prog_fw_w_helper()
1918 tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) / mwifiex_prog_fw_w_helper()
1919 card->pcie.blksz_fw_dl; mwifiex_prog_fw_w_helper()
1926 skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl); mwifiex_prog_fw_w_helper()
1977 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_check_fw_status()
2231 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_rdwr_firmware()
2266 const struct mwifiex_pcie_card_reg *creg = card->pcie.reg; mwifiex_pcie_fw_dump_work()
2274 if (!card->pcie.can_dump_fw) mwifiex_pcie_fw_dump_work()
2411 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_init()
2521 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_cleanup()
2564 adapter->tx_buf_size = card->pcie.tx_buf_size; mwifiex_register_dev()
2567 strcpy(adapter->fw_name, card->pcie.firmware); mwifiex_register_dev()
2568 adapter->ext_scan = card->pcie.can_ext_scan; mwifiex_register_dev()
2588 reg = card->pcie.reg; mwifiex_unregister_dev()
|
| H A D | pcie.h | 254 struct mwifiex_pcie_device pcie; member in struct:pcie_service_card
292 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_txbd_empty()
317 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; mwifiex_pcie_txbd_not_full()
|
| H A D | main.h | 44 #include "pcie.h"
|
| /linux-4.1.27/drivers/pci/pcie/ |
| H A D | portdrv_core.c | 327 struct pcie_device *pcie; pcie_device_init() local
330 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL); pcie_device_init()
331 if (!pcie) pcie_device_init()
333 pcie->port = pdev; pcie_device_init()
334 pcie->irq = irq; pcie_device_init()
335 pcie->service = service; pcie_device_init()
338 device = &pcie->device; pcie_device_init()
340 device->release = release_pcie_device; /* callback to free pcie dev */ pcie_device_init()
341 dev_set_name(device, "%s:pcie%02x", pcie_device_init()
|
| H A D | aspm.c | 2 * File: drivers/pci/pcie/aspm.c
65 * Endpoint acceptable latencies. A pcie downstream port only
551 * It is called after the pcie and its children devices are scanned.
|
| /linux-4.1.27/arch/sh/drivers/pci/ |
| H A D | ops-sh7786.c | 15 #include "pcie-sh7786.h"
119 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x " sh7786_pcie_read()
146 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x " sh7786_pcie_write()
|
| H A D | pcie-sh7786.c | 22 #include "pcie-sh7786.h"
221 snprintf(fclk_name, sizeof(fclk_name), "pcie%d_fck", port->index); pcie_clk_init()
|
| /linux-4.1.27/arch/arm/mach-dove/ |
| H A D | pcie.c | 2 * arch/arm/mach-dove/pcie.c
19 #include <plat/pcie.h>
188 struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0")); add_pcie_port()
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| H A D | common.c | 121 orion_clkdev_add("0", "pcie", pex0); dove_clk_init()
122 orion_clkdev_add("1", "pcie", pex1); dove_clk_init()
|
| /linux-4.1.27/arch/arm/mach-mvebu/ |
| H A D | mvebu-soc-id.c | 42 { .compatible = "marvell,armada-xp-pcie", },
43 { .compatible = "marvell,armada-370-pcie", },
44 { .compatible = "marvell,kirkwood-pcie" },
|
| /linux-4.1.27/drivers/gpu/drm/radeon/ |
| H A D | radeon_gart.c | 61 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
92 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
120 * (pcie r4xx, r5xx+). These asics require the
145 * by the memory manager (pcie r4xx, r5xx+). These asics require the
189 * Unpin the GART page table in vram (pcie r4xx, r5xx+).
214 * (pcie r4xx, r5xx+). These asics require the gart table to
|
| H A D | si_dpm.h | 162 /* pcie gen */
|
| H A D | radeon_agp.c | 158 /* chips with the agp to pcie bridge don't have the AGP_STATUS register radeon_agp_init()
|
| H A D | radeon_acpi.c | 575 * @perf_req: requested perf level (pcie gen speed)
579 * change the pcie gen speed (all asics).
|
| H A D | radeon_acpi.h | 339 * BYTE - adapter id (0: iGPU, 1-n: dGPU ordered by pcie bus number) } structure
|
| H A D | radeon_pm.c | 214 /* voltage, pcie lanes, etc.*/ radeon_set_power_state()
236 /* voltage, pcie lanes, etc.*/ radeon_set_power_state()
|
| H A D | rs600.c | 297 /* set pcie lanes */ rs600_pm_misc()
|
| H A D | rv6xx_dpm.c | 1855 /* fix up pcie gen2 */ rv6xx_parse_pplib_clock_info()
|
| H A D | rv770.c | 1689 /* enable pcie gen2 link */ rv770_startup()
|
| H A D | ni.c | 1985 /* enable pcie gen2 link */ cayman_startup()
|
| H A D | r600_cp.c | 2217 /* XXX turn off pcie gart */ r600_do_init_cp()
|
| H A D | radeon_cp.c | 1060 DRM_DEBUG("programming pcie %08X %08lX %08X\n", radeon_set_pciegart()
|
| H A D | ci_dpm.c | 5919 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n", ci_dpm_print_power_state()
|
| H A D | r100.c | 343 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
424 /* set pcie lanes */ r100_pm_misc()
|
| H A D | r600.c | 2996 /* enable pcie gen2 link */ r600_startup()
4345 DRM_ERROR("invalid pcie lane request: %d\n", lanes); r600_set_pcie_lanes()
|
| H A D | radeon.h | 1313 int pcie_lanes; /* pcie lanes */
|
| H A D | evergreen.c | 5475 /* enable pcie gen2 link */ evergreen_startup()
|
| H A D | ni_dpm.c | 4292 printk("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", ni_dpm_print_power_state()
|
| H A D | si.c | 6873 /* enable pcie gen2/3 link */ si_startup()
|
| H A D | si_dpm.c | 6998 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", si_dpm_debugfs_print_current_performance_level()
|
| H A D | cik.c | 8486 /* enable pcie gen2/3 link */ cik_startup()
|
| /linux-4.1.27/arch/mips/lantiq/xway/ |
| H A D | sysctrl.c | 369 clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY); ltq_soc_init()
370 clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK); ltq_soc_init()
371 clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI); ltq_soc_init()
372 clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI); ltq_soc_init()
373 clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL); ltq_soc_init()
374 clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); ltq_soc_init()
|
| /linux-4.1.27/drivers/net/ethernet/myricom/myri10ge/ |
| H A D | myri10ge_mcp_gen_header.h | 8 #define MCP_TYPE_PCIE 0x70636965 /* "PCIE" pcie-only MCP */
|
| H A D | myri10ge_mcp.h | 338 * throttle_factor = 256 * pcie-raw-speed / tx_speed
339 * tx_speed = 256 * pcie-raw-speed / throttle_factor
341 * For PCI-E x8: pcie-raw-speed == 16Gb/s
342 * For PCI-E x4: pcie-raw-speed == 8Gb/s
|
| /linux-4.1.27/drivers/pinctrl/mvebu/ |
| H A D | pinctrl-armada-370.c | 116 MPP_FUNCTION(0x2, "pcie", "clkreq0"),
123 MPP_FUNCTION(0x2, "pcie", "clkreq1"),
277 MPP_FUNCTION(0x2, "pcie", "clkreq1"),
306 MPP_FUNCTION(0x5, "pcie", "clkreq1")),
324 MPP_FUNCTION(0x5, "pcie", "clkreq0"),
351 MPP_FUNCTION(0x4, "pcie", "rst-out"),
363 MPP_FUNCTION(0x4, "pcie", "clkreq0"),
|
| H A D | pinctrl-armada-xp.c | 242 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)),
249 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS)),
261 MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)),
268 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)),
287 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)),
|
| H A D | pinctrl-orion.c | 79 MPP_VAR_FUNCTION(0x0, "pcie", "rstout", V_ALL),
|
| /linux-4.1.27/drivers/bcma/ |
| H A D | driver_mips.c | 353 struct bcma_device *cpu, *pcie, *i2s; bcma_fix_i2s_irqflag() local
363 pcie = bcma_find_core(bus, BCMA_CORE_PCIE); bcma_fix_i2s_irqflag()
365 if (cpu && pcie && i2s && bcma_fix_i2s_irqflag()
367 bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 && bcma_fix_i2s_irqflag()
370 bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504); bcma_fix_i2s_irqflag()
|
| H A D | driver_pci_host.c | 65 * one external pcie device is present). bcma_get_cfgspace_addr()
|
| /linux-4.1.27/arch/powerpc/platforms/pseries/ |
| H A D | pci.c | 128 "ibm,pcie-link-speed-stats", pseries_root_bridge_prepare()
137 pr_debug("no ibm,pcie-link-speed-stats property\n"); pseries_root_bridge_prepare()
|
| /linux-4.1.27/arch/powerpc/platforms/83xx/ |
| H A D | misc.c | 141 for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie") mpc83xx_setup_pci()
|
| /linux-4.1.27/arch/powerpc/platforms/86xx/ |
| H A D | sbc8641d.c | 98 { .compatible = "fsl,mpc8641-pcie", },
|
| H A D | mpc86xx_hpcn.c | 134 { .compatible = "fsl,mpc8641-pcie", },
|
| H A D | gef_ppc9a.c | 219 { .compatible = "fsl,mpc8641-pcie", },
|
| H A D | gef_sbc310.c | 206 { .compatible = "fsl,mpc8641-pcie", },
|
| H A D | gef_sbc610.c | 196 { .compatible = "fsl,mpc8641-pcie", },
|
| H A D | mpc8610_hpcd.c | 96 { .compatible = "fsl,mpc8641-pcie", }, mpc8610_suspend_init()
|
| /linux-4.1.27/arch/mips/ralink/ |
| H A D | mt7620.c | 70 FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
71 FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
89 GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
176 FUNC("pcie", 3, 11, 1),
|
| /linux-4.1.27/drivers/net/wireless/brcm80211/brcmfmac/ |
| H A D | pcie.c | 37 #include "pcie.h"
48 #define BRCMF_PCIE_43602_FW_NAME "brcm/brcmfmac43602-pcie.bin"
49 #define BRCMF_PCIE_43602_NVRAM_NAME "brcm/brcmfmac43602-pcie.txt"
50 #define BRCMF_PCIE_4356_FW_NAME "brcm/brcmfmac4356-pcie.bin"
51 #define BRCMF_PCIE_4356_NVRAM_NAME "brcm/brcmfmac4356-pcie.txt"
52 #define BRCMF_PCIE_43570_FW_NAME "brcm/brcmfmac43570-pcie.bin"
53 #define BRCMF_PCIE_43570_NVRAM_NAME "brcm/brcmfmac43570-pcie.txt"
1239 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; brcmf_pcie_wowl_config()
1580 struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie; brcmf_pcie_setup()
1683 bus->bus_priv.pcie = pcie_bus_dev; brcmf_pcie_probe()
1726 devinfo = bus->bus_priv.pcie->devinfo; brcmf_pcie_remove()
1734 kfree(bus->bus_priv.pcie); brcmf_pcie_remove()
1765 devinfo = bus->bus_priv.pcie->devinfo; brcmf_pcie_suspend()
1814 devinfo = bus->bus_priv.pcie->devinfo; brcmf_pcie_resume()
1830 devinfo = bus->bus_priv.pcie->devinfo; brcmf_pcie_resume()
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| H A D | bus.h | 123 struct brcmf_pciedev *pcie; member in union:brcmf_bus::__anon7802
|
| H A D | core.c | 35 #include "pcie.h"
|
| /linux-4.1.27/drivers/phy/ |
| H A D | phy-ti-pipe3.c | 225 if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) { ti_pipe3_init()
257 of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) ti_pipe3_exit()
311 if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) { ti_pipe3_probe()
355 if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) { ti_pipe3_probe()
584 .compatible = "ti,phy-pipe3-pcie",
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| H A D | phy-miphy365x.c | 459 (!strncmp(name, "pcie", 4) && type == PHY_TYPE_PCIE))) miphy365x_get_addr()
531 of_property_read_bool(phynode, "st,pcie-tx-pol-inv"); miphy365x_of_probe()
|
| H A D | phy-omap-control.c | 264 .compatible = "ti,control-phy-pcie",
|
| H A D | phy-miphy28lp.c | 241 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
968 dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base); miphy28lp_init_pcie()
|
| /linux-4.1.27/drivers/thunderbolt/ |
| H A D | tb.c | 152 /* scan for pcie devices at depth 1*/ tb_activate_pcie_devices()
270 "hotplug: activating pcie devices\n"); tb_handle_hotplug()
426 * the pcie links need some time to get going. thunderbolt_resume()
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| /linux-4.1.27/drivers/net/ethernet/atheros/atl1e/ |
| H A D | atl1e_hw.c | 286 /* pcie flow control mode change */ atl1e_init_pcie()
400 * pcie serdes link may be down ! atl1e_phy_commit()
411 "pcie linkdown at least for 25ms\n"); atl1e_phy_commit()
415 netdev_err(adapter->netdev, "pcie linkup after %d ms\n", i); atl1e_phy_commit()
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| H A D | atl1e_main.c | 1316 "pcie phy linkdown %x\n", status); atl1e_intr()
2175 /* pcie patch */ atl1e_suspend()
2187 /* pcie patch */ atl1e_suspend()
|
| /linux-4.1.27/include/xen/interface/io/ |
| H A D | pciif.h | 93 /*used for pcie aer handling*/
|
| /linux-4.1.27/arch/powerpc/kernel/ |
| H A D | of_platform.c | 103 { .type = "pcie", },
|
| H A D | pci_of_scan.c | 145 dev->needs_freset = 0; /* pcie fundamental reset required */ of_create_pci_dev()
|
| /linux-4.1.27/drivers/net/ethernet/emulex/benet/ |
| H A D | be_cmds.c | 3542 struct be_pcie_res_desc *pcie; be_get_pcie_desc() local
3548 pcie = (struct be_pcie_res_desc *)hdr; be_get_pcie_desc()
3549 if (pcie->pf_num == devfn) be_get_pcie_desc()
3550 return pcie; be_get_pcie_desc()
3658 struct be_pcie_res_desc *pcie; be_cmd_get_profile_config() local
3697 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param, be_cmd_get_profile_config()
3699 if (pcie) be_cmd_get_profile_config()
3700 res->max_vfs = le16_to_cpu(pcie->num_vfs); be_cmd_get_profile_config()
3780 static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie) be_reset_pcie_desc() argument
3782 memset(pcie, 0, sizeof(*pcie)); be_reset_pcie_desc()
3783 pcie->sriov_state = 0xFF; be_reset_pcie_desc()
3784 pcie->pf_state = 0xFF; be_reset_pcie_desc()
3785 pcie->pf_type = 0xFF; be_reset_pcie_desc()
3786 pcie->num_vfs = 0xFFFF; be_reset_pcie_desc()
3888 struct be_pcie_res_desc pcie; be_cmd_set_sriov_config() member in struct:__anon6439
3893 be_reset_pcie_desc(&desc.pcie); be_cmd_set_sriov_config()
3894 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1; be_cmd_set_sriov_config()
3895 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1; be_cmd_set_sriov_config()
3896 desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT); be_cmd_set_sriov_config()
3897 desc.pcie.pf_num = adapter->pdev->devfn; be_cmd_set_sriov_config()
3898 desc.pcie.sriov_state = num_vfs ? 1 : 0; be_cmd_set_sriov_config()
3899 desc.pcie.num_vfs = cpu_to_le16(num_vfs); be_cmd_set_sriov_config()
|
| /linux-4.1.27/arch/mips/pci/ |
| H A D | pci-bcm63xx.c | 155 pcie_clk = clk_get(NULL, "pcie"); bcm63xx_register_pcie()
181 /* set device bus/func for the pcie device */ bcm63xx_register_pcie()
|
| H A D | pcie-octeon.c | 773 /* Wait until pcie resets the ports. */ __cvmx_pcie_rc_initialize_gen1()
805 /* Wait until pcie resets the ports. */ __cvmx_pcie_rc_initialize_gen1()
1215 pr_notice("PCIE : init for pcie analyzer.\n"); __cvmx_pcie_rc_initialize_gen2()
1274 /* Wait until pcie resets the ports. */ __cvmx_pcie_rc_initialize_gen2()
1454 /* Above was cvmx-pcie.c, below original pcie.c */
1696 pr_err(" pcie cfg_read retries failed. retry_cnt=%d\n", octeon_pcie_read_config()
|
| /linux-4.1.27/arch/arm/plat-orion/ |
| H A D | pcie.c | 2 * arch/arm/plat-orion/pcie.c
15 #include <plat/pcie.h>
|
| /linux-4.1.27/arch/arm/mach-mv78xx0/ |
| H A D | pcie.c | 2 * arch/arm/mach-mv78xx0/pcie.c
17 #include <plat/pcie.h>
|
| /linux-4.1.27/drivers/misc/ |
| H A D | spear13xx_pcie_gadget.c | 24 #include <mach/pcie.h>
788 "pcie gadget interrupt IRQ%d already claimed\n", irq); spear_pcie_gadget_probe()
801 * init basic pcie application registers spear_pcie_gadget_probe()
862 .name = "pcie-gadget-spear",
869 MODULE_ALIAS("platform:pcie-gadget-spear");
|
| /linux-4.1.27/drivers/infiniband/hw/qib/ |
| H A D | qib_pcie.c | 117 "Unable to enable pcie error reporting: %d\n", qib_pcie_init()
175 * void because none of the core pcie cleanup returns are void
326 * Check against expected pcie width and complain if "wrong" qib_pcie_params()
346 * Setup pcie interrupt stuff again after a reset. I'd like to just call
452 * to move all the pcie code out of the chip-specific driver code.
|
| H A D | qib_iba6120.c | 3555 * Do remaining pcie setup and save pcie values in dd. qib_init_iba6120_funcs()
|
| H A D | qib_iba7220.c | 4599 * Do remaining pcie setup and save pcie values in dd. qib_init_iba7220_funcs()
|
| /linux-4.1.27/arch/tile/kernel/ |
| H A D | pci.c | 90 sprintf(filename, "pcie/%d/config%d", controller_id, config_type); tile_pcie_open()
109 sprintf(filename, "pcie/%d/ctl", controller_id); tile_init_irqs()
186 sprintf(name, "pcie/%d/mem", i); tile_pci_init()
|
| /linux-4.1.27/drivers/scsi/qla2xxx/ |
| H A D | qla_nx2.h | 38 * eliminated by the pcie bar and bar select before presentation
39 * over pcie. */
|
| H A D | qla_nx.h | 375 /* window 1 pcie slot */
474 * eliminated by the pcie bar and bar select before presentation
475 * over pcie. */
|
| /linux-4.1.27/include/linux/bcma/ |
| H A D | bcma_driver_pci.h | 56 #define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
57 #define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
|
| /linux-4.1.27/arch/arm/mach-imx/ |
| H A D | clk-imx6sx.c | 73 "ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core",
219 /* FIXME 100Mhz is used for pcie ref for all imx6 pcie, excepted imx6q */ imx6sx_clocks_init()
516 /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */ imx6sx_clocks_init()
518 pr_err("Failed to set pcie bus parent clk.\n"); imx6sx_clocks_init()
520 pr_err("Failed to set pcie parent clk.\n"); imx6sx_clocks_init()
|
| /linux-4.1.27/drivers/clk/tegra/ |
| H A D | clk-tegra30.c | 654 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
655 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
1146 /* pcie */ tegra30_periph_clk_init()
1147 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, tegra30_periph_clk_init()
|
| H A D | clk-tegra-periph.c | 544 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
|
| /linux-4.1.27/drivers/scsi/qla4xxx/ |
| H A D | ql4_nx.h | 399 /* window 1 pcie slot */
499 * eliminated by the pcie bar and bar select before presentation
500 * over pcie. */
|
| /linux-4.1.27/drivers/soc/tegra/ |
| H A D | pmc.c | 867 [TEGRA_POWERGATE_PCIE] = "pcie",
886 [TEGRA_POWERGATE_PCIE] = "pcie",
955 [TEGRA_POWERGATE_PCIE] = "pcie",
|
| /linux-4.1.27/drivers/media/pci/smipcie/ |
| H A D | smipcie.h | 277 /* pcie */
|
| /linux-4.1.27/drivers/pci/pcie/aer/ |
| H A D | aerdrv_errprint.c | 2 * drivers/pci/pcie/aer/aerdrv_errprint.c
|
| H A D | aerdrv_core.c | 2 * drivers/pci/pcie/aer/aerdrv_core.c
791 * @dev: pointer to AER pcie device
|
| H A D | aerdrv.c | 2 * drivers/pci/pcie/aer/aerdrv.c
|
| /linux-4.1.27/drivers/clk/berlin/ |
| H A D | bg2q.c | 288 { "pcie", "perif", 22 },
|
| /linux-4.1.27/arch/mips/bcm63xx/ |
| H A D | clk.c | 381 if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie")) clk_get()
|
| /linux-4.1.27/arch/arm/mach-shmobile/ |
| H A D | clock-r8a7779.c | 161 CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
|
| /linux-4.1.27/drivers/net/ethernet/atheros/alx/ |
| H A D | reg.h | 97 /* bit13: enable pcie clk switch in L1 state */
121 /* bit5: wakeup without pcie clk */
|
| H A D | hw.c | 580 /* mask some pcie error bits */ alx_reset_pcie()
|
| /linux-4.1.27/arch/powerpc/platforms/maple/ |
| H A D | pci.c | 524 } else if (of_device_is_compatible(dev, "u4-pcie")) { maple_add_bridge()
591 if ((of_device_is_compatible(np, "u4-pcie") || maple_pci_init()
|
| /linux-4.1.27/drivers/net/wireless/ath/ath9k/ |
| H A D | ar9002_hw.c | 321 /* set bit 19 to allow forcing of pcie core into L1 state */ ar9002_hw_configpcipowersave()
|
| H A D | ar9003_hw.c | 1031 /* set bit 19 to allow forcing of pcie core into L1 state */ ar9003_hw_configpcipowersave()
|
| /linux-4.1.27/drivers/staging/comedi/drivers/ |
| H A D | cb_pcimdas.c | 41 * http://www.mccdaq.com/PDFs/Manuals/pcie-das1602-16.pdf
|
| H A D | ni_pcimio.c | 815 .name = "pcie-6251",
872 .name = "pcie-6259",
|
| /linux-4.1.27/arch/x86/pci/ |
| H A D | sta2x11-fixup.c | 269 * At boot we must set up the mappings for the pcie-to-amba bridge.
|
| /linux-4.1.27/drivers/xen/xen-pciback/ |
| H A D | pciback_ops.c | 284 * as well as pcie aer front end ack. We use a new work_queue to schedule
|
| /linux-4.1.27/drivers/clk/spear/ |
| H A D | spear1310_clock.c | 745 clk_register_clkdev(clk, NULL, "b1000000.pcie"); spear1310_clk_init()
751 clk_register_clkdev(clk, NULL, "b1800000.pcie"); spear1310_clk_init()
757 clk_register_clkdev(clk, NULL, "b4000000.pcie"); spear1310_clk_init()
|
| H A D | spear1340_clock.c | 842 clk_register_clkdev(clk, NULL, "b1000000.pcie"); spear1340_clk_init()
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| /linux-4.1.27/drivers/bus/ |
| H A D | mvebu-mbus.c | 1123 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg)); mvebu_mbus_get_pcie_resources()
1130 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg)); mvebu_mbus_get_pcie_resources()
1191 /* Get optional pcie-{mem,io}-aperture properties */ mvebu_mbus_dt_init()
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| /linux-4.1.27/drivers/net/ethernet/sun/ |
| H A D | niu.h | 2965 #define NIU_QGC_LP_MDL_STR "SUNW,pcie-qgc"
2966 #define NIU_2XGF_LP_MDL_STR "SUNW,pcie-2xgf"
2967 #define NIU_QGC_PEM_MDL_STR "SUNW,pcie-qgc-pem"
2968 #define NIU_2XGF_PEM_MDL_STR "SUNW,pcie-2xgf-pem"
2971 #define NIU_MARAMBA_MDL_STR "SUNW,pcie-neptune"
2972 #define NIU_FOXXY_MDL_STR "SUNW,pcie-rfem"
2973 #define NIU_2XGF_MRVL_MDL_STR "SysKonnect,pcie-2xgf"
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| /linux-4.1.27/drivers/net/ethernet/atheros/atlx/ |
| H A D | atl1.c | 687 /* pcie serdes link may be down! */ atl1_phy_reset()
689 dev_dbg(&pdev->dev, "pcie phy link down\n"); atl1_phy_reset()
701 "pcie link down at least 25ms\n"); atl1_phy_reset()
1653 /* pcie flow control mode change */ atl1_pcie_patch()
2526 "pcie phy link down %x\n", status); atl1_intr()
2538 "pcie DMA r/w error (status = 0x%x)\n", atl1_intr()
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| H A D | atl2.c | 1581 /* pcie patch */ atl2_suspend()
1599 /* pcie patch */ atl2_suspend()
1618 /* pcie patch */ atl2_suspend()
2661 /* pcie serdes link may be down ! */ atl2_phy_commit()
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| /linux-4.1.27/drivers/scsi/csiostor/ |
| H A D | csio_mb.c | 279 ldst_cmd->u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1); csio_mb_ldst()
280 ldst_cmd->u.pcie.ctrl_to_fn = csio_mb_ldst()
282 ldst_cmd->u.pcie.r = (uint8_t)reg; csio_mb_ldst()
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| /linux-4.1.27/drivers/net/wireless/ath/ath10k/ |
| H A D | pci.c | 1569 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); ath10k_pci_init_config()
1575 ath10k_err(ar, "Invalid pcie state addr\n"); ath10k_pci_init_config()
1631 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); ath10k_pci_init_config()
1642 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); ath10k_pci_init_config()
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| /linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192se/ |
| H A D | fw.c | 376 firmware->pfwheader->fwpriv.hci_sel = 1;/* pcie */ rtl92s_download_fw()
|
| /linux-4.1.27/arch/arm/mach-orion5x/ |
| H A D | pci.c | 20 #include <plat/pcie.h>
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| /linux-4.1.27/drivers/pinctrl/spear/ |
| H A D | pinctrl-spear1340.c | 1823 /* pad multiplexing for pcie device */
1850 .name = "pcie",
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| /linux-4.1.27/arch/powerpc/platforms/cell/ |
| H A D | iommu.c | 1151 /* If we can find a pcie-endpoint in the device tree assume that setup_iommu_fixed()
1156 pciep = of_find_node_by_type(NULL, "pcie-endpoint"); setup_iommu_fixed()
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| /linux-4.1.27/arch/powerpc/platforms/powermac/ |
| H A D | pci.c | 817 } else if (of_device_is_compatible(dev, "u4-pcie")) { pmac_add_bridge()
1240 of_device_is_compatible(node, "u4-pcie") || pmac_pci_probe_mode()
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| /linux-4.1.27/drivers/iommu/ |
| H A D | iommu.c | 570 * space is quite small (especially since we're really only looking at pcie
|
| /linux-4.1.27/drivers/net/ethernet/chelsio/cxgb4/ |
| H A D | cxgb4_main.c | 3058 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1); t4_read_pcie_cfg4()
3059 ldst_cmd.u.pcie.ctrl_to_fn = t4_read_pcie_cfg4()
3061 ldst_cmd.u.pcie.r = reg; t4_read_pcie_cfg4()
3069 val = ntohl(ldst_cmd.u.pcie.data[0]); t4_read_pcie_cfg4()
|
| H A D | t4fw_api.h | 818 } pcie; member in union:fw_ldst_cmd::fw_ldst
|
| /linux-4.1.27/drivers/net/ethernet/intel/ixgbe/ |
| H A D | ixgbe_82598.c | 175 * Then set pcie completion timeout
|
| /linux-4.1.27/drivers/net/ethernet/qlogic/qlge/ |
| H A D | qlge_mpi.c | 98 * we are the lower of the 2 NIC pcie functions, or if
|
| H A D | qlge_main.c | 4484 /* Find the pcie function number for the other NIC
|
| /linux-4.1.27/drivers/net/ethernet/atheros/atl1c/ |
| H A D | atl1c_hw.h | 183 #define PM_CTRL_CLK_SWH_L1 BIT(13) /* en pcie clk sw in L1 */
|
| H A D | atl1c_main.c | 145 * Mask some pcie error bits atl1c_reset_pcie()
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| /linux-4.1.27/arch/ia64/sn/pci/ |
| H A D | tioce_provider.c | 252 * tioce_alloc_map - Given a coretalk address, map it to pcie bus address
|
| /linux-4.1.27/drivers/net/wireless/brcm80211/brcmsmac/ |
| H A D | dma.c | 618 /* add offset for pcie with DMA64 bus */ dma_attach()
|
| /linux-4.1.27/drivers/clk/samsung/ |
| H A D | clk-exynos4.c | 1057 GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
|
| /linux-4.1.27/arch/tile/include/hv/ |
| H A D | hypervisor.h | 1609 * (say, "pcie"). If there is more than one instance of a device, the
1610 * base name is followed by a slash and a device number (say, "pcie/0").
1614 * includes a trailing "/ctl" (say, "pcie/0/ctl").
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| /linux-4.1.27/drivers/net/wireless/rtlwifi/ |
| H A D | wifi.h | 2583 *intf_ops : for diff interrface usb/pcie
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| /linux-4.1.27/drivers/pci/ |
| H A D | probe.c | 1686 /* only one slot has pcie device */ pci_scan_slot()
|
| H A D | quirks.c | 3148 * The thunderbolt controller consists of a pcie switch with downstream
|
| /linux-4.1.27/arch/arm/mach-omap2/ |
| H A D | omap_hwmod_7xx_data.c | 1470 .name = "pcie",
|
| /linux-4.1.27/drivers/net/ethernet/intel/e1000e/ |
| H A D | netdev.c | 5032 /* disable TSO for pcie and 10/100 speeds, to avoid e1000_watchdog_task()
|
| /linux-4.1.27/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_main.c | 7872 * causing all hw-to-host pcie transactions to timeout. If this happened we want
|