| /linux-4.1.27/drivers/scsi/ |
| H A D | osst_detect.h | 4 {"OnStream", "DP-", "", "osst"}, \
|
| H A D | st.c | 237 {"OnStream", "DP-", "", "osst"}, \
|
| /linux-4.1.27/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_dcb.c | 129 DP(NETIF_MSG_LINK, "local_mib.error %x\n", error); bnx2x_dump_dcbx_drv_param()
132 DP(NETIF_MSG_LINK, bnx2x_dump_dcbx_drv_param()
135 DP(NETIF_MSG_LINK, bnx2x_dump_dcbx_drv_param()
139 DP(NETIF_MSG_LINK, bnx2x_dump_dcbx_drv_param()
144 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.pri_en_bitmap %x\n", bnx2x_dump_dcbx_drv_param()
146 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.pfc_caps %x\n", bnx2x_dump_dcbx_drv_param()
148 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.enabled %x\n", bnx2x_dump_dcbx_drv_param()
151 DP(BNX2X_MSG_DCB, "dcbx_features.app.default_pri %x\n", bnx2x_dump_dcbx_drv_param()
153 DP(BNX2X_MSG_DCB, "dcbx_features.app.tc_supported %x\n", bnx2x_dump_dcbx_drv_param()
155 DP(BNX2X_MSG_DCB, "dcbx_features.app.enabled %x\n", bnx2x_dump_dcbx_drv_param()
158 DP(BNX2X_MSG_DCB, bnx2x_dump_dcbx_drv_param()
161 DP(BNX2X_MSG_DCB, bnx2x_dump_dcbx_drv_param()
164 DP(BNX2X_MSG_DCB, bnx2x_dump_dcbx_drv_param()
198 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_APP_ERROR\n"); bnx2x_dcbx_get_ap_feature()
201 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_APP_MISMATCH\n"); bnx2x_dcbx_get_ap_feature()
204 DP(BNX2X_MSG_DCB, "DCBX_REMOTE_APP_TLV_NOT_FOUND\n"); bnx2x_dcbx_get_ap_feature()
236 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_APP_DISABLED\n"); bnx2x_dcbx_get_ap_feature()
255 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_ETS_ERROR\n"); bnx2x_dcbx_get_ets_feature()
258 DP(BNX2X_MSG_DCB, "DCBX_REMOTE_ETS_TLV_NOT_FOUND\n"); bnx2x_dcbx_get_ets_feature()
271 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_ETS_ENABLE\n"); bnx2x_dcbx_get_ets_feature()
286 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_ETS_DISABLED\n"); bnx2x_dcbx_get_ets_feature()
299 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_PFC_ERROR\n"); bnx2x_dcbx_get_pfc_feature()
302 DP(BNX2X_MSG_DCB, "DCBX_REMOTE_PFC_TLV_NOT_FOUND\n"); bnx2x_dcbx_get_pfc_feature()
310 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_PFC_DISABLED\n"); bnx2x_dcbx_get_pfc_feature()
334 DP(BNX2X_MSG_DCB, bnx2x_dcbx_map_nw()
437 DP(BNX2X_MSG_DCB, "STOP TRAFFIC\n"); bnx2x_dcbx_stop_hw_tx()
463 DP(BNX2X_MSG_DCB, "START TRAFFIC\n"); bnx2x_dcbx_resume_hw_tx()
599 DP(BNX2X_MSG_DCB, "dcbx_remote_mib_offset 0x%x\n", bnx2x_dcbx_read_shmem_remote_mib()
628 DP(BNX2X_MSG_DCB, "dcbx_neg_res_offset 0x%x\n", dcbx_neg_res_offset); bnx2x_dcbx_read_shmem_neg_results()
703 DP(BNX2X_MSG_DCB, bnx2x_dcbx_update_tc_mapping()
721 DP(BNX2X_MSG_DCB, "BNX2X_DCBX_STATE_NEG_RECEIVED\n"); bnx2x_dcbx_set_params()
770 DP(BNX2X_MSG_DCB, "BNX2X_DCBX_STATE_TX_PAUSED\n"); bnx2x_dcbx_set_params()
779 DP(BNX2X_MSG_DCB, "BNX2X_DCBX_STATE_TX_RELEASED\n"); bnx2x_dcbx_set_params()
870 DP(BNX2X_MSG_DCB, "pg_bw_tbl[%d] = %02x\n", bnx2x_dcbx_admin_mib_updated_params()
878 DP(BNX2X_MSG_DCB, "pri_pg_tbl[%d] = %02x\n", bnx2x_dcbx_admin_mib_updated_params()
930 DP(BNX2X_MSG_DCB, "DCB state [%s:%s]\n", bnx2x_dcbx_set_state()
1008 DP(BNX2X_MSG_DCB, "dcb_state %d bp->port.pmf %d\n", bnx2x_dcbx_init()
1016 DP(BNX2X_MSG_DCB, "dcbx_lldp_params_offset 0x%x\n", bnx2x_dcbx_init()
1049 DP(BNX2X_MSG_DCB, bnx2x_dcbx_print_cos_params()
1051 DP(BNX2X_MSG_DCB, bnx2x_dcbx_print_cos_params()
1056 DP(BNX2X_MSG_DCB, bnx2x_dcbx_print_cos_params()
1060 DP(BNX2X_MSG_DCB, bnx2x_dcbx_print_cos_params()
1064 DP(BNX2X_MSG_DCB, bnx2x_dcbx_print_cos_params()
1068 DP(BNX2X_MSG_DCB, bnx2x_dcbx_print_cos_params()
1074 DP(BNX2X_MSG_DCB, bnx2x_dcbx_print_cos_params()
1078 DP(BNX2X_MSG_DCB, bnx2x_dcbx_print_cos_params()
1125 DP(BNX2X_MSG_DCB, bnx2x_dcbx_get_num_pg_traf_type()
1793 DP(BNX2X_MSG_DCB, "COS %d PAUSABLE prijoinmask 0x%x\n", bnx2x_dcbx_fill_cos_params()
1796 DP(BNX2X_MSG_DCB, bnx2x_dcbx_fill_cos_params()
1813 DP(BNX2X_MSG_DCB, "set_configuration_ets_pg[%d] = 0x%x\n", bnx2x_dcbx_get_ets_pri_pg_tbl()
1911 DP(BNX2X_MSG_DCB, "state = %d\n", bp->dcb_state); bnx2x_dcbnl_get_state()
1918 DP(BNX2X_MSG_DCB, "state = %s\n", state ? "on" : "off"); bnx2x_dcbnl_set_state()
1923 DP(BNX2X_MSG_DCB, "Can not set dcbx to enabled while it is disabled in nvm\n"); bnx2x_dcbnl_set_state()
1935 DP(BNX2X_MSG_DCB, "GET-PERM-ADDR\n"); bnx2x_dcbnl_get_perm_hw_addr()
1952 DP(BNX2X_MSG_DCB, "prio[%d] = %d\n", prio, pgid); bnx2x_dcbnl_set_pg_tccfg_tx()
1977 DP(BNX2X_MSG_DCB, "pgid[%d] = %d\n", pgid, bw_pct); bnx2x_dcbnl_set_pg_bwgcfg_tx()
1991 DP(BNX2X_MSG_DCB, "Nothing to set; No RX support\n"); bnx2x_dcbnl_set_pg_tccfg_rx()
1998 DP(BNX2X_MSG_DCB, "Nothing to set; No RX support\n"); bnx2x_dcbnl_set_pg_bwgcfg_rx()
2006 DP(BNX2X_MSG_DCB, "prio = %d\n", prio); bnx2x_dcbnl_get_pg_tccfg_tx()
2032 DP(BNX2X_MSG_DCB, "pgid = %d\n", pgid); bnx2x_dcbnl_get_pg_bwgcfg_tx()
2047 DP(BNX2X_MSG_DCB, "Nothing to get; No RX support\n"); bnx2x_dcbnl_get_pg_tccfg_rx()
2056 DP(BNX2X_MSG_DCB, "Nothing to get; No RX support\n"); bnx2x_dcbnl_get_pg_bwgcfg_rx()
2065 DP(BNX2X_MSG_DCB, "prio[%d] = %d\n", prio, setting); bnx2x_dcbnl_set_pfc_cfg()
2082 DP(BNX2X_MSG_DCB, "prio = %d\n", prio); bnx2x_dcbnl_get_pfc_cfg()
2096 DP(BNX2X_MSG_DCB, "SET-ALL\n"); bnx2x_dcbnl_set_all()
2112 DP(BNX2X_MSG_DCB, "set_dcbx_params done\n"); bnx2x_dcbnl_set_all()
2154 DP(BNX2X_MSG_DCB, "DCB disabled\n"); bnx2x_dcbnl_get_cap()
2158 DP(BNX2X_MSG_DCB, "capid %d:%x\n", capid, *cap); bnx2x_dcbnl_get_cap()
2167 DP(BNX2X_MSG_DCB, "tcid %d\n", tcid); bnx2x_dcbnl_get_numtcs()
2185 DP(BNX2X_MSG_DCB, "DCB disabled\n"); bnx2x_dcbnl_get_numtcs()
2195 DP(BNX2X_MSG_DCB, "num tcs = %d; Not supported\n", num); bnx2x_dcbnl_set_numtcs()
2202 DP(BNX2X_MSG_DCB, "state = %d\n", bp->dcbx_local_feat.pfc.enabled); bnx2x_dcbnl_get_pfc_state()
2213 DP(BNX2X_MSG_DCB, "state = %s\n", state ? "on" : "off"); bnx2x_dcbnl_set_pfc_state()
2308 DP(BNX2X_MSG_DCB, "app_type %d, app_id %x, prio bitmap %d\n", bnx2x_dcbnl_set_app_up()
2312 DP(BNX2X_MSG_DCB, "dcbnl call not valid\n"); bnx2x_dcbnl_set_app_up()
2322 DP(BNX2X_MSG_DCB, "Wrong ID type\n"); bnx2x_dcbnl_set_app_up()
2344 DP(BNX2X_MSG_DCB, "state = %02x\n", state); bnx2x_dcbnl_set_dcbx()
2374 DP(BNX2X_MSG_DCB, "featid %d\n", featid); bnx2x_dcbnl_get_featcfg()
2408 DP(BNX2X_MSG_DCB, "DCB disabled\n"); bnx2x_dcbnl_get_featcfg()
2421 DP(BNX2X_MSG_DCB, "featid = %d flags = %02x\n", featid, flags); bnx2x_dcbnl_set_featcfg()
2449 DP(BNX2X_MSG_DCB, "dcbnl call not valid\n"); bnx2x_dcbnl_set_featcfg()
2462 DP(BNX2X_MSG_DCB, "APP-INFO\n"); bnx2x_peer_appinfo()
2481 DP(BNX2X_MSG_DCB, "APP-TABLE\n"); bnx2x_peer_apptable()
|
| H A D | bnx2x_ethtool.c | 244 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" bnx2x_get_vf_settings()
328 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" bnx2x_get_settings()
349 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" bnx2x_set_settings()
373 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
382 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
403 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
422 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
437 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); bnx2x_set_settings()
447 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); bnx2x_set_settings()
456 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); bnx2x_set_settings()
462 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
516 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
526 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
540 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
550 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
562 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
569 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
580 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
587 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
598 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
607 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_settings()
617 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); bnx2x_set_settings()
626 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" bnx2x_set_settings()
999 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", bnx2x_get_dump_flag()
1023 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); bnx2x_get_dump_data()
1093 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); bnx2x_set_wol()
1099 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); bnx2x_set_wol()
1205 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_acquire_nvram_lock()
1237 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_release_nvram_lock()
1314 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_nvram_read_dword()
1327 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_nvram_read()
1334 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_nvram_read()
1414 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_get_eeprom()
1419 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" bnx2x_get_eeprom()
1439 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_get_module_eeprom()
1462 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); bnx2x_get_module_eeprom()
1487 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); bnx2x_get_module_eeprom()
1502 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_get_module_info()
1516 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); bnx2x_get_module_info()
1529 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); bnx2x_get_module_info()
1582 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_nvram_write_dword()
1597 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_nvram_write1()
1649 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_nvram_write()
1656 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_nvram_write()
1713 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_set_eeprom()
1718 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" bnx2x_set_eeprom()
1728 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_set_eeprom()
1842 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_ringparam()
1847 DP(BNX2X_MSG_IOV, bnx2x_set_ringparam()
1853 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_ringparam()
1863 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); bnx2x_set_ringparam()
1893 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" bnx2x_get_pauseparam()
1906 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" bnx2x_set_pauseparam()
1923 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); bnx2x_set_pauseparam()
1942 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_pauseparam()
2009 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); bnx2x_get_eee()
2046 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); bnx2x_set_eee()
2053 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); bnx2x_set_eee()
2060 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_eee()
2066 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_eee()
2073 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_eee()
2216 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_test_registers()
2265 DP(BNX2X_MSG_ETHTOOL, bnx2x_test_registers()
2320 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_test_memory()
2338 DP(BNX2X_MSG_ETHTOOL, bnx2x_test_memory()
2353 DP(BNX2X_MSG_ETHTOOL, bnx2x_test_memory()
2374 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); bnx2x_wait_for_link()
2381 DP(BNX2X_MSG_ETHTOOL, bnx2x_wait_for_link()
2413 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); bnx2x_run_loopback()
2434 DP(BNX2X_MSG_ETHTOOL, bnx2x_run_loopback()
2440 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); bnx2x_run_loopback()
2449 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); bnx2x_run_loopback()
2464 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); bnx2x_run_loopback()
2605 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); bnx2x_test_loopback()
2611 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); bnx2x_test_loopback()
2636 DP(BNX2X_MSG_ETHTOOL, bnx2x_test_ext_loopback()
2646 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); bnx2x_test_ext_loopback()
2683 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_nvram_crc()
2718 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_test_nvram_dir()
2775 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); bnx2x_test_nvram_dirs()
2802 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_test_nvram_tbl()
2838 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); bnx2x_test_nvram()
2845 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_test_nvram()
2851 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_test_nvram()
2857 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); bnx2x_test_nvram()
2867 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_test_nvram()
2888 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_test_intr()
2909 DP(BNX2X_MSG_IOV, bnx2x_self_test()
2921 DP(BNX2X_MSG_ETHTOOL, bnx2x_self_test()
2937 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n"); bnx2x_self_test()
2957 DP(BNX2X_MSG_ETHTOOL, bnx2x_self_test()
2992 DP(BNX2X_MSG_ETHTOOL, bnx2x_self_test()
3190 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, bnx2x_set_phys_id()
3270 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); bnx2x_get_rxnfc()
3279 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_rss_flags()
3289 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_rss_flags()
3308 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_rss_flags()
3315 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_rss_flags()
3326 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_rss_flags()
3344 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_rss_flags()
3363 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); bnx2x_set_rxnfc()
3478 DP(BNX2X_MSG_ETHTOOL, bnx2x_set_channels()
3484 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n"); bnx2x_set_channels()
3494 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); bnx2x_set_channels()
3500 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); bnx2x_set_channels()
|
| H A D | bnx2x_link.c | 265 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); bnx2x_check_lfa()
306 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", bnx2x_check_lfa()
315 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", bnx2x_check_lfa()
324 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", bnx2x_check_lfa()
335 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", bnx2x_check_lfa()
348 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", bnx2x_check_lfa()
361 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, bnx2x_check_lfa()
378 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); bnx2x_get_epio()
395 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); bnx2x_set_epio()
398 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); bnx2x_set_epio()
449 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); bnx2x_ets_e2e3a0_disabled()
754 DP(NETIF_MSG_LINK, bnx2x_ets_e3b0_disabled()
782 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); bnx2x_ets_disabled()
915 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" bnx2x_ets_e3b0_get_total_bw()
931 DP(NETIF_MSG_LINK, bnx2x_ets_e3b0_get_total_bw()
935 DP(NETIF_MSG_LINK, bnx2x_ets_e3b0_get_total_bw()
971 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " bnx2x_ets_e3b0_sp_pri_to_cos_set()
977 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " bnx2x_ets_e3b0_sp_pri_to_cos_set()
1063 DP(NETIF_MSG_LINK, bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1077 DP(NETIF_MSG_LINK, bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1106 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1154 DP(NETIF_MSG_LINK, bnx2x_ets_e3b0_config()
1160 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " bnx2x_ets_e3b0_config()
1172 DP(NETIF_MSG_LINK, bnx2x_ets_e3b0_config()
1206 DP(NETIF_MSG_LINK, bnx2x_ets_e3b0_config()
1211 DP(NETIF_MSG_LINK, bnx2x_ets_e3b0_config()
1222 DP(NETIF_MSG_LINK, bnx2x_ets_e3b0_config()
1233 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); bnx2x_ets_e3b0_config()
1242 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); bnx2x_ets_bw_limit_common()
1291 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); bnx2x_ets_bw_limit()
1296 DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); bnx2x_ets_bw_limit()
1320 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); bnx2x_ets_strict()
1445 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n", bnx2x_set_mdio_clk()
1499 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); bnx2x_emac_init()
1501 DP(NETIF_MSG_LINK, "EMAC timeout!\n"); bnx2x_emac_init()
1567 DP(NETIF_MSG_LINK, "enabling UMAC\n"); bnx2x_umac_enable()
1590 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", bnx2x_umac_enable()
1608 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n"); bnx2x_umac_enable()
1669 DP(NETIF_MSG_LINK, bnx2x_xmac_init()
1682 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); bnx2x_xmac_init()
1693 DP(NETIF_MSG_LINK, bnx2x_xmac_init()
1698 DP(NETIF_MSG_LINK, bnx2x_xmac_init()
1732 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); bnx2x_set_xmac_rxtx()
1747 DP(NETIF_MSG_LINK, "enabling XMAC\n"); bnx2x_xmac_enable()
1784 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); bnx2x_xmac_enable()
1820 DP(NETIF_MSG_LINK, "enabling EMAC\n"); bnx2x_emac_enable()
1835 DP(NETIF_MSG_LINK, "XGXS\n"); bnx2x_emac_enable()
1842 DP(NETIF_MSG_LINK, "SerDes\n"); bnx2x_emac_enable()
1888 DP(NETIF_MSG_LINK, "PFC is enabled\n"); bnx2x_emac_enable()
2008 DP(NETIF_MSG_LINK, "PFC is enabled\n"); bnx2x_update_pfc_bmac2()
2022 DP(NETIF_MSG_LINK, "PFC is disabled\n"); bnx2x_update_pfc_bmac2()
2048 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); bnx2x_update_pfc_bmac2()
2138 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); bnx2x_update_pfc_nig()
2247 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); bnx2x_update_pfc()
2257 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); bnx2x_update_pfc()
2287 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); bnx2x_bmac1_enable()
2308 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); bnx2x_bmac1_enable()
2350 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); bnx2x_bmac2_enable()
2490 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); bnx2x_pbf_update()
2499 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", bnx2x_pbf_update()
2527 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", bnx2x_pbf_update()
2533 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", bnx2x_pbf_update()
2624 DP(NETIF_MSG_LINK, "write phy register failed\n"); bnx2x_cl22_write()
2661 DP(NETIF_MSG_LINK, "read phy register failed\n"); bnx2x_cl22_read()
2705 DP(NETIF_MSG_LINK, "read phy register failed\n"); bnx2x_cl45_read()
2727 DP(NETIF_MSG_LINK, "read phy register failed\n"); bnx2x_cl45_read()
2781 DP(NETIF_MSG_LINK, "write phy register failed\n"); bnx2x_cl45_write()
2802 DP(NETIF_MSG_LINK, "write phy register failed\n"); bnx2x_cl45_write()
2921 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); bnx2x_eee_set_timers()
2986 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); bnx2x_eee_advertise()
2990 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); bnx2x_eee_advertise()
3029 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); bnx2x_eee_an_resolve()
3037 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); bnx2x_eee_an_resolve()
3045 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); bnx2x_eee_an_resolve()
3053 DP(NETIF_MSG_LINK, "EEE is active\n"); bnx2x_eee_an_resolve()
3083 DP(NETIF_MSG_LINK, "Setting BSC switch\n"); bnx2x_bsc_module_sel()
3100 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", bnx2x_bsc_read()
3131 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", bnx2x_bsc_read()
3155 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); bnx2x_bsc_read()
3334 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); bnx2x_serdes_deassert()
3369 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); bnx2x_xgxs_deassert()
3420 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); bnx2x_calc_ieee_aneg_adv()
3456 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," set_phy_vars()
3487 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); bnx2x_ext_phy_set_pause()
3569 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); bnx2x_ext_phy_update_adv_fc()
3638 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n"); bnx2x_warpcore_enable_AN_KR2()
3676 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n"); bnx2x_disable_kr2()
3692 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); bnx2x_warpcore_set_lpi_passthrough()
3730 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); bnx2x_warpcore_enable_AN_KR()
3752 DP(NETIF_MSG_LINK, "Advertize 1G\n"); bnx2x_warpcore_enable_AN_KR()
3766 DP(NETIF_MSG_LINK, "Advertize 10G\n"); bnx2x_warpcore_enable_AN_KR()
3804 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); bnx2x_warpcore_enable_AN_KR()
4196 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); bnx2x_warpcore_set_sgmii_speed()
4211 DP(NETIF_MSG_LINK, bnx2x_warpcore_set_sgmii_speed()
4222 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", bnx2x_warpcore_set_sgmii_speed()
4226 DP(NETIF_MSG_LINK, " (readback) %x\n", val16); bnx2x_warpcore_set_sgmii_speed()
4336 DP(NETIF_MSG_LINK, bnx2x_get_mod_abs_int_cfg()
4425 DP(NETIF_MSG_LINK, "0x%x retry left\n", bnx2x_warpcore_config_runtime()
4446 DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); bnx2x_warpcore_config_sfi()
4449 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); bnx2x_warpcore_config_sfi()
4467 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); bnx2x_sfp_e3_set_transmitter()
4487 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " bnx2x_warpcore_config_init()
4498 DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); bnx2x_warpcore_config_init()
4508 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); bnx2x_warpcore_config_init()
4516 DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); bnx2x_warpcore_config_init()
4520 DP(NETIF_MSG_LINK, "1G Fiber\n"); bnx2x_warpcore_config_init()
4523 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); bnx2x_warpcore_config_init()
4553 DP(NETIF_MSG_LINK, "Speed not supported yet\n"); bnx2x_warpcore_config_init()
4556 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); bnx2x_warpcore_config_init()
4566 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n"); bnx2x_warpcore_config_init()
4571 DP(NETIF_MSG_LINK, bnx2x_warpcore_config_init()
4580 DP(NETIF_MSG_LINK, "Exit config init\n"); bnx2x_warpcore_config_init()
4644 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", bnx2x_set_warpcore_loopback()
4692 DP(NETIF_MSG_LINK, "phy link up\n"); bnx2x_sync_link()
4772 DP(NETIF_MSG_LINK, "phy link down\n"); bnx2x_sync_link()
4829 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); bnx2x_link_status_update()
4850 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", bnx2x_link_status_update()
4852 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", bnx2x_link_status_update()
4916 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); bnx2x_reset_unicore()
4976 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", bnx2x_set_parallel_detection()
4986 DP(NETIF_MSG_LINK, "XGXS\n"); bnx2x_set_parallel_detection()
5147 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); bnx2x_program_serdes()
5217 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); bnx2x_restart_autoneg()
5238 DP(NETIF_MSG_LINK, bnx2x_restart_autoneg()
5300 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", bnx2x_initialize_sgmii_process()
5338 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", bnx2x_direct_parallel_detect_used()
5349 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", bnx2x_direct_parallel_detect_used()
5383 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); bnx2x_update_adv_fc()
5397 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); bnx2x_update_adv_fc()
5428 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); bnx2x_flow_ctrl_resolve()
5436 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); bnx2x_check_fallback_to_cl37()
5444 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." bnx2x_check_fallback_to_cl37()
5462 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " bnx2x_check_fallback_to_cl37()
5478 DP(NETIF_MSG_LINK, "No CL37 FSM were received. " bnx2x_check_fallback_to_cl37()
5496 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); bnx2x_check_fallback_to_cl37()
5523 DP(NETIF_MSG_LINK, "phy link up\n"); bnx2x_get_link_speed_duplex()
5564 DP(NETIF_MSG_LINK, bnx2x_get_link_speed_duplex()
5584 DP(NETIF_MSG_LINK, bnx2x_get_link_speed_duplex()
5590 DP(NETIF_MSG_LINK, "phy link down\n"); bnx2x_get_link_speed_duplex()
5598 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", bnx2x_get_link_speed_duplex()
5622 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", bnx2x_link_settings_status()
5672 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", bnx2x_link_settings_status()
5701 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", bnx2x_warpcore_read_status()
5710 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); bnx2x_warpcore_read_status()
5783 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); bnx2x_warpcore_read_status()
5798 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", bnx2x_warpcore_read_status()
5848 DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); bnx2x_emac_program()
5873 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", bnx2x_emac_program()
5929 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); bnx2x_xgxs_config_init()
5938 DP(NETIF_MSG_LINK, "not SGMII, AN\n"); bnx2x_xgxs_config_init()
5955 DP(NETIF_MSG_LINK, "SGMII\n"); bnx2x_xgxs_config_init()
6023 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); bnx2x_wait_reset_complete()
6041 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); bnx2x_link_int_enable()
6046 DP(NETIF_MSG_LINK, "enabled external phy int\n"); bnx2x_link_int_enable()
6051 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); bnx2x_link_int_enable()
6056 DP(NETIF_MSG_LINK, "enabled external phy int\n"); bnx2x_link_int_enable()
6063 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, bnx2x_link_int_enable()
6066 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", bnx2x_link_int_enable()
6070 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", bnx2x_link_int_enable()
6087 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); bnx2x_rearm_latch_signal()
6141 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", bnx2x_link_int_ack()
6244 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); bnx2x_set_xgxs_loopback()
6277 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); bnx2x_set_xgxs_loopback()
6300 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); bnx2x_set_led()
6301 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", bnx2x_set_led()
6427 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", bnx2x_set_led()
6578 DP(NETIF_MSG_LINK, bnx2x_link_initialize()
6621 DP(NETIF_MSG_LINK, "reset external PHY\n"); bnx2x_common_ext_link_reset()
6630 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); bnx2x_update_link_down()
6694 DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); bnx2x_update_link_up()
6706 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); bnx2x_update_link_up()
6719 DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); bnx2x_update_link_up()
6822 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", bnx2x_link_update()
6828 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", bnx2x_link_update()
6833 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", bnx2x_link_update()
6857 DP(NETIF_MSG_LINK, "phy in index %d link is up\n", bnx2x_link_update()
6860 DP(NETIF_MSG_LINK, "phy in index %d link is down\n", bnx2x_link_update()
6893 DP(NETIF_MSG_LINK, "Invalid link indication" bnx2x_link_update()
6931 DP(NETIF_MSG_LINK, bnx2x_link_update()
6949 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", bnx2x_link_update()
6963 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," bnx2x_link_update()
6974 DP(NETIF_MSG_LINK, "Internal link speed %d is" bnx2x_link_update()
6999 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," bnx2x_link_update()
7063 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", bnx2x_save_spirom_version()
7133 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", bnx2x_8073_resolve_fc()
7181 DP(NETIF_MSG_LINK, bnx2x_8073_8727_external_rom_boot()
7207 DP(NETIF_MSG_LINK, bnx2x_8073_8727_external_rom_boot()
7272 DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); bnx2x_8073_xaui_wa()
7275 DP(NETIF_MSG_LINK, "bit 15 went off\n"); bnx2x_8073_xaui_wa()
7286 DP(NETIF_MSG_LINK, bnx2x_8073_xaui_wa()
7296 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); bnx2x_8073_xaui_wa()
7340 DP(NETIF_MSG_LINK, bnx2x_8073_set_pause_cl37()
7371 DP(NETIF_MSG_LINK, "Init 8073\n"); bnx2x_8073_config_init()
7393 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); bnx2x_8073_config_init()
7398 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); bnx2x_8073_config_init()
7422 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); bnx2x_8073_config_init()
7426 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); bnx2x_8073_config_init()
7453 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); bnx2x_8073_config_init()
7467 DP(NETIF_MSG_LINK, "Add 2.5G\n"); bnx2x_8073_config_init()
7473 DP(NETIF_MSG_LINK, "Disable 2.5G\n"); bnx2x_8073_config_init()
7507 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", bnx2x_8073_config_init()
7525 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); bnx2x_8073_read_status()
7532 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); bnx2x_8073_read_status()
7541 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); bnx2x_8073_read_status()
7546 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); bnx2x_8073_read_status()
7553 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); bnx2x_8073_read_status()
7570 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," bnx2x_8073_read_status()
7596 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", bnx2x_8073_read_status()
7601 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", bnx2x_8073_read_status()
7606 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", bnx2x_8073_read_status()
7610 DP(NETIF_MSG_LINK, "port %x: External link is down\n", bnx2x_8073_read_status()
7626 DP(NETIF_MSG_LINK, "Swapping 1G polarity for" bnx2x_8073_read_status()
7666 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", bnx2x_8073_link_reset()
7681 DP(NETIF_MSG_LINK, "init 8705\n"); bnx2x_8705_config_init()
7710 DP(NETIF_MSG_LINK, "read status 8705\n"); bnx2x_8705_read_status()
7713 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); bnx2x_8705_read_status()
7717 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); bnx2x_8705_read_status()
7727 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); bnx2x_8705_read_status()
7750 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); bnx2x_set_disable_pmd_transmit()
7752 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); bnx2x_set_disable_pmd_transmit()
7756 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); bnx2x_set_disable_pmd_transmit()
7790 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " bnx2x_sfp_e1e2_set_transmitter()
7828 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); bnx2x_sfp_e1e2_set_transmitter()
7838 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); bnx2x_sfp_set_transmitter()
7854 DP(NETIF_MSG_LINK, bnx2x_8726_read_sfp_module_eeprom()
7886 DP(NETIF_MSG_LINK, bnx2x_8726_read_sfp_module_eeprom()
7926 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", bnx2x_warpcore_power_module()
7946 DP(NETIF_MSG_LINK, bnx2x_warpcore_read_sfp_module_eeprom()
7983 DP(NETIF_MSG_LINK, bnx2x_8727_read_sfp_module_eeprom()
8043 DP(NETIF_MSG_LINK, bnx2x_8727_read_sfp_module_eeprom()
8080 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr); bnx2x_read_sfp_module_eeprom()
8127 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); bnx2x_get_edc_mode()
8146 DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); bnx2x_get_edc_mode()
8159 DP(NETIF_MSG_LINK, bnx2x_get_edc_mode()
8162 DP(NETIF_MSG_LINK, bnx2x_get_edc_mode()
8177 DP(NETIF_MSG_LINK, "1G SFP module detected\n"); bnx2x_get_edc_mode()
8198 DP(NETIF_MSG_LINK, "10G Optic module detected\n"); bnx2x_get_edc_mode()
8210 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", bnx2x_get_edc_mode()
8238 DP(NETIF_MSG_LINK, bnx2x_get_edc_mode()
8247 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); bnx2x_get_edc_mode()
8267 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); bnx2x_verify_sfp_module()
8279 DP(NETIF_MSG_LINK, bnx2x_verify_sfp_module()
8286 DP(NETIF_MSG_LINK, bnx2x_verify_sfp_module()
8294 DP(NETIF_MSG_LINK, "Approved module\n"); bnx2x_verify_sfp_module()
8349 DP(NETIF_MSG_LINK, bnx2x_wait_for_sfp_module_initialized()
8403 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", bnx2x_8726_set_limiting_mode()
8407 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); bnx2x_8726_set_limiting_mode()
8414 DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); bnx2x_8726_set_limiting_mode()
8516 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", bnx2x_8727_specific_func()
8542 DP(NETIF_MSG_LINK, "Set fault module-detected led " bnx2x_set_e1e2_module_fault_led()
8549 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", bnx2x_set_e1e2_module_fault_led()
8565 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", bnx2x_set_e3_module_fault_led()
8574 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); bnx2x_set_sfp_module_fault_led()
8603 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); bnx2x_power_sfp_module()
8687 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", bnx2x_sfp_module_detection()
8692 DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); bnx2x_sfp_module_detection()
8696 DP(NETIF_MSG_LINK, "Module verification failed!!\n"); bnx2x_sfp_module_detection()
8705 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); bnx2x_sfp_module_detection()
8746 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); bnx2x_handle_module_detect_int()
8786 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); bnx2x_handle_module_detect_int()
8832 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); bnx2x_8706_8726_read_status()
8845 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); bnx2x_8706_8726_read_status()
8856 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" bnx2x_8706_8726_read_status()
8910 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); bnx2x_8706_config_init()
8924 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" bnx2x_8706_config_init()
8931 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); bnx2x_8706_config_init()
8946 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); bnx2x_8706_config_init()
8982 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); bnx2x_8706_config_init()
9007 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); bnx2x_8726_config_loopback()
9061 DP(NETIF_MSG_LINK, "Tx is disabled\n"); bnx2x_8726_read_status()
9075 DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); bnx2x_8726_config_init()
9090 DP(NETIF_MSG_LINK, "Setting 1G force\n"); bnx2x_8726_config_init()
9106 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); bnx2x_8726_config_init()
9136 DP(NETIF_MSG_LINK, bnx2x_8726_config_init()
9159 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); bnx2x_8726_link_reset()
9239 DP(NETIF_MSG_LINK, "Setting 1G force\n"); bnx2x_8727_config_speed()
9246 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); bnx2x_8727_config_speed()
9266 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); bnx2x_8727_config_speed()
9299 DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); bnx2x_8727_config_init()
9334 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", bnx2x_8727_config_init()
9356 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); bnx2x_8727_config_init()
9389 DP(NETIF_MSG_LINK, bnx2x_8727_handle_mod_abs()
9415 DP(NETIF_MSG_LINK, bnx2x_8727_handle_mod_abs()
9448 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); bnx2x_8727_handle_mod_abs()
9454 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", bnx2x_8727_handle_mod_abs()
9481 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); bnx2x_8727_read_status()
9489 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); bnx2x_8727_read_status()
9507 DP(NETIF_MSG_LINK, bnx2x_8727_read_status()
9550 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); bnx2x_8727_read_status()
9553 DP(NETIF_MSG_LINK, "Tx is disabled\n"); bnx2x_8727_read_status()
9567 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", bnx2x_8727_read_status()
9572 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", bnx2x_8727_read_status()
9576 DP(NETIF_MSG_LINK, "port %x: External link is down\n", bnx2x_8727_read_status()
9596 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); bnx2x_8727_read_status()
9669 DP(NETIF_MSG_LINK, "Unable to read 848xx " bnx2x_save_848xx_spirom_version()
9688 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " bnx2x_save_848xx_spirom_version()
9805 DP(NETIF_MSG_LINK, "Advertising 1G\n"); bnx2x_848xx_cmn_config_init()
9821 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); bnx2x_848xx_cmn_config_init()
9830 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); bnx2x_848xx_cmn_config_init()
9838 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); bnx2x_848xx_cmn_config_init()
9846 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); bnx2x_848xx_cmn_config_init()
9862 DP(NETIF_MSG_LINK, "Setting 100M force\n"); bnx2x_848xx_cmn_config_init()
9872 DP(NETIF_MSG_LINK, "Setting 10M force\n"); bnx2x_848xx_cmn_config_init()
9896 DP(NETIF_MSG_LINK, "Advertising 10G\n"); bnx2x_848xx_cmn_config_init()
9954 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); bnx2x_84833_cmd_hdlr()
9976 DP(NETIF_MSG_LINK, "FW cmd failed.\n"); bnx2x_84833_cmd_hdlr()
10015 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); bnx2x_84833_pair_swap_cfg()
10085 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", bnx2x_84833_hw_reset_phy()
10099 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); bnx2x_8483x_disable_eee()
10105 DP(NETIF_MSG_LINK, "EEE disable failed.\n"); bnx2x_8483x_disable_eee()
10123 DP(NETIF_MSG_LINK, "EEE enable failed.\n"); bnx2x_8483x_enable_eee()
10218 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", bnx2x_848x3_config_init()
10234 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); bnx2x_848x3_config_init()
10266 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); bnx2x_848x3_config_init()
10279 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n"); bnx2x_848x3_config_init()
10313 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); bnx2x_848xx_read_status()
10335 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", bnx2x_848xx_read_status()
10356 DP(NETIF_MSG_LINK, bnx2x_848xx_read_status()
10378 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", bnx2x_848xx_read_status()
10496 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); bnx2x_848xx_set_link_led()
10531 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", bnx2x_848xx_set_link_led()
10589 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); bnx2x_848xx_set_link_led()
10658 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); bnx2x_848xx_set_link_led()
10672 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); bnx2x_848xx_set_link_led()
10795 DP(NETIF_MSG_LINK, "54618SE cfg init\n"); bnx2x_54618se_config_init()
10875 DP(NETIF_MSG_LINK, "Advertising 1G\n"); bnx2x_54618se_config_init()
10892 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); bnx2x_54618se_config_init()
10898 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); bnx2x_54618se_config_init()
10904 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); bnx2x_54618se_config_init()
10910 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); bnx2x_54618se_config_init()
10921 DP(NETIF_MSG_LINK, "Setting 100M force\n"); bnx2x_54618se_config_init()
10928 DP(NETIF_MSG_LINK, "Setting 10M force\n"); bnx2x_54618se_config_init()
10943 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); bnx2x_54618se_config_init()
10957 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); bnx2x_54618se_config_init()
10969 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); bnx2x_54618se_config_init()
10972 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n"); bnx2x_54618se_config_init()
11007 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); bnx2x_5461x_set_link_led()
11067 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); bnx2x_54618se_read_status()
11101 DP(NETIF_MSG_LINK, bnx2x_54618se_read_status()
11120 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", bnx2x_54618se_read_status()
11168 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); bnx2x_54618se_config_loopback()
11219 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); bnx2x_7101_config_init()
11230 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); bnx2x_7101_config_init()
11264 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", bnx2x_7101_read_status()
11270 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", bnx2x_7101_read_status()
11280 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", bnx2x_7101_read_status()
11916 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); bnx2x_get_ext_phy_config()
11934 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); bnx2x_populate_int_phy()
12011 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", bnx2x_populate_int_phy()
12039 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); bnx2x_populate_int_phy()
12052 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", bnx2x_populate_int_phy()
12179 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", bnx2x_populate_ext_phy()
12181 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", bnx2x_populate_ext_phy()
12222 DP(NETIF_MSG_LINK, bnx2x_phy_def_cfg()
12310 DP(NETIF_MSG_LINK, "Begin phy probe\n"); bnx2x_phy_probe()
12323 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," bnx2x_phy_probe()
12331 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", bnx2x_phy_probe()
12373 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); bnx2x_phy_probe()
12546 DP(NETIF_MSG_LINK, "Calling PHY specific func\n"); bnx2x_avoid_link_flap()
12666 DP(NETIF_MSG_LINK, "Phy Initialization started\n"); bnx2x_phy_init()
12667 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", bnx2x_phy_init()
12669 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", bnx2x_phy_init()
12671 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); bnx2x_phy_init()
12689 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n"); bnx2x_phy_init()
12693 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n", bnx2x_phy_init()
12710 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); bnx2x_phy_init()
12715 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); bnx2x_phy_init()
12756 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); bnx2x_link_reset()
12930 DP(NETIF_MSG_LINK, "populate_phy failed\n"); bnx2x_8073_common_init_phy()
12973 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", bnx2x_8073_common_init_phy()
13055 DP(NETIF_MSG_LINK, "populate phy failed\n"); bnx2x_8726_common_init_phy()
13171 DP(NETIF_MSG_LINK, "populate phy failed\n"); bnx2x_8727_common_init_phy()
13203 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", bnx2x_8727_common_init_phy()
13228 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", bnx2x_84833_common_init_phy()
13274 DP(NETIF_MSG_LINK, bnx2x_ext_phy_common_init()
13297 DP(NETIF_MSG_LINK, "Begin common phy init\n"); bnx2x_common_init_phy()
13308 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", bnx2x_common_init_phy()
13379 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); bnx2x_analyze_link_error()
13382 DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); bnx2x_analyze_link_error()
13385 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n"); bnx2x_analyze_link_error()
13387 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, bnx2x_analyze_link_error()
13513 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); bnx2x_sfp_tx_fault_detection()
13535 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", bnx2x_sfp_tx_fault_detection()
13546 DP(NETIF_MSG_LINK, "KR2 recovery\n"); bnx2x_kr2_recovery()
13573 DP(NETIF_MSG_LINK, "No sigdet\n"); bnx2x_check_kr2_wa()
13591 DP(NETIF_MSG_LINK, "No BP\n"); bnx2x_check_kr2_wa()
13607 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, bnx2x_check_kr2_wa()
13616 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page); bnx2x_check_kr2_wa()
13633 DP(NETIF_MSG_LINK, "Fault detection failed\n"); bnx2x_period_func()
13679 DP(NETIF_MSG_LINK, "populate phy failed\n"); bnx2x_fan_failure_det_req()
13731 DP(NETIF_MSG_LINK, "populate phy failed\n"); bnx2x_init_mod_abs_int()
13760 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", bnx2x_init_mod_abs_int()
|
| H A D | bnx2x_sriov.c | 98 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", bnx2x_vf_igu_ack_sb()
104 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", bnx2x_vf_igu_ack_sb()
119 DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n"); bnx2x_validate_vf_sp_objs()
131 DP(BNX2X_MSG_IOV, bnx2x_vfop_qctor_dump_tx()
149 DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n" bnx2x_vfop_qctor_dump_rx()
246 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); bnx2x_vf_queue_create()
255 DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n"); bnx2x_vf_queue_create()
288 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); bnx2x_vf_queue_destroy()
297 DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n"); bnx2x_vf_queue_destroy()
349 DP(BNX2X_MSG_SP, "Failed to take vlan mac read head; continuing anyway\n"); bnx2x_vf_vlan_credit()
366 DP(BNX2X_MSG_IOV, "vf[%d] - deleting all %s\n", vf->abs_vfid, bnx2x_vf_vlan_mac_clear()
413 DP(BNX2X_MSG_IOV, "vf[%d] - %s a %s filter\n", bnx2x_vf_mac_vlan_config()
472 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); bnx2x_vf_mac_vlan_config_list()
508 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); bnx2x_vf_queue_setup()
542 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); bnx2x_vf_queue_flr()
582 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); bnx2x_vf_mcast()
660 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); bnx2x_vf_rxmode()
672 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); bnx2x_vf_queue_teardown()
774 DP(BNX2X_MSG_IOV, bnx2x_vf_igu_reset()
809 DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid); bnx2x_vf_enable_access()
856 DP(BNX2X_MSG_IOV, "vf[%d] - %d vlan filter credits [previously %d]\n", bnx2x_iov_re_set_vlan_filters()
867 DP(BNX2X_MSG_IOV, "vf[%d] - Failed to configure vlan filter credits change\n", bnx2x_iov_re_set_vlan_filters()
933 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); bnx2x_vf_flr()
972 DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. Num of vfs: %d\n", bnx2x_vf_flr_clnup()
995 DP(BNX2X_MSG_MCP, "DRV_STATUS_VF_DISABLED ACK for vfs 0x%x 0x%x\n", bnx2x_vf_flr_clnup()
1018 DP(BNX2X_MSG_MCP, bnx2x_vf_handle_flr_event()
1037 DP(BNX2X_MSG_IOV, for_each_vf()
1147 DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n", bnx2x_get_vf_igu_cam_info()
1153 DP(BNX2X_MSG_IOV, "vf_sbs_pool is %d\n", BP_VFDB(bp)->vf_sbs_pool); bnx2x_get_vf_igu_cam_info()
1179 DP(BNX2X_MSG_IOV, "sriov ext pos %d\n", pos); bnx2x_sriov_pci_cfg_info()
1211 DP(BNX2X_MSG_IOV, bnx2x_sriov_info()
1297 DP(BNX2X_MSG_IOV, "num_vfs_param was %d, nr_virtfn was %d\n", bnx2x_iov_init_one()
1343 DP(BNX2X_MSG_IOV, "Failed err=%d\n", err);
1364 DP(BNX2X_MSG_IOV, "disabling internal access for vf %d\n", bnx2x_iov_remove_one()
1479 DP(BNX2X_MSG_IOV, bnx2x_vfq_init()
1541 DP(NETIF_MSG_LINK | BNX2X_MSG_IOV, bnx2x_iov_link_update_vf()
1591 DP(BNX2X_MSG_IOV, "vfdb was not allocated\n"); bnx2x_iov_nic_init()
1595 DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn); bnx2x_iov_nic_init()
1611 DP(BNX2X_MSG_IOV, for_each_vf()
1658 DP(BNX2X_MSG_IOV, for_each_vf()
1738 DP(BNX2X_MSG_IOV, "Scheduled next pending commands...\n"); bnx2x_vf_handle_classification_eqe()
1794 DP(BNX2X_MSG_IOV, "checking cfc-del comp cid=%d\n", cid); bnx2x_iov_eq_sp_event()
1802 DP(BNX2X_MSG_IOV, "checking filtering comp cid=%d\n", cid); bnx2x_iov_eq_sp_event()
1806 DP(BNX2X_MSG_IOV, "Got VF FLR notification abs_vfid=%d\n", bnx2x_iov_eq_sp_event()
1821 DP(BNX2X_MSG_IOV, "cid is outside vf range: %d\n", cid); bnx2x_iov_eq_sp_event()
1842 DP(BNX2X_MSG_IOV, "got VF [%d:%d] cfc delete ramrod\n", bnx2x_iov_eq_sp_event()
1850 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mac/vlan ramrod\n", bnx2x_iov_eq_sp_event()
1855 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mcast ramrod\n", bnx2x_iov_eq_sp_event()
1860 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set rx-mode ramrod\n", bnx2x_iov_eq_sp_event()
1865 DP(BNX2X_MSG_IOV, "got VF [%d:%d] RSS update ramrod\n", bnx2x_iov_eq_sp_event()
1952 DP(BNX2X_MSG_IOV, "add addresses for vf %d\n", vf->abs_vfid); for_each_vfq()
1973 DP(BNX2X_MSG_IOV, for_each_vfq()
2061 DP(BNX2X_MSG_IOV, "VF[%d] Trying to re-acquire resources (VF was not released or FLR'd)\n", bnx2x_vf_acquire()
2084 DP(BNX2X_MSG_IOV, bnx2x_vf_acquire()
2099 DP(BNX2X_MSG_IOV, bnx2x_vf_acquire()
2107 DP(BNX2X_MSG_IOV, "vf->vfqs was not allocated\n"); bnx2x_vf_acquire()
2123 DP(BNX2X_MSG_IOV, "VFQ[%d:%d]: index %d, cid 0x%x, cxt %p\n", for_each_vfq()
2148 DP(BNX2X_MSG_IOV, "VF[%d] is not in VF_ACQUIRED, but %d\n", for_each_vf_sb()
2215 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); bnx2x_vf_close()
2225 DP(BNX2X_MSG_IOV, "disabling igu\n"); bnx2x_vf_close()
2229 DP(BNX2X_MSG_IOV, "clearing qtbl\n"); bnx2x_vf_close()
2246 DP(BNX2X_MSG_IOV, "set state to acquired\n"); bnx2x_vf_close()
2262 DP(BNX2X_MSG_IOV, "VF[%d] STATE: %s\n", vf->abs_vfid, bnx2x_vf_free()
2276 DP(BNX2X_MSG_IOV, "about to free resources\n"); bnx2x_vf_free()
2294 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); bnx2x_vf_rss_update()
2307 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); bnx2x_vf_tpa_update()
2319 DP(BNX2X_MSG_IOV, "sge_addr[%d:%d] %08x:%08x\n", bnx2x_vf_tpa_update()
2342 DP(BNX2X_MSG_IOV, "PF releasing vf %d\n", vf->abs_vfid); bnx2x_vf_release()
2370 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel locked by %d\n", bnx2x_lock_vf_pf_channel()
2401 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n", bnx2x_unlock_vf_pf_channel()
2455 DP(BNX2X_MSG_IOV, "%s Tx Switching\n", enable ? "Enabled" : "Disabled");
2468 DP(BNX2X_MSG_IOV, "bnx2x_sriov_configure called with %d, BNX2X_NR_VIRTFN(bp) was %d\n", bnx2x_sriov_configure()
2529 DP(BNX2X_MSG_IOV, "assigning sb %d to vf %d\n", bnx2x_enable_sriov()
2540 DP(BNX2X_MSG_IOV, "vf_sbs_pool %d, num_vf_queues %d\n", bnx2x_enable_sriov()
2561 DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n",
2569 DP(BNX2X_MSG_IOV, "about to call enable sriov\n");
2581 DP(BNX2X_MSG_IOV, "sriov enabled (%d vfs)\n", req_vfs);
2590 DP(BNX2X_MSG_IOV, "configuring vlan for VFs from sp-task\n"); for_each_vf()
2601 DP(BNX2X_MSG_IOV, bnx2x_disable_sriov()
2831 DP(BNX2X_MSG_IOV, "configuring VF %d with VLAN %d qos %d\n", bnx2x_set_vf_vlan()
3017 DP(BNX2X_MSG_IOV, "link update speed %d flags %x\n", bnx2x_sample_bulletin()
3138 DP(BNX2X_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag); bnx2x_schedule_iov_task()
|
| H A D | bnx2x_sp.c | 73 DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n", bnx2x_exe_queue_init()
80 DP(BNX2X_MSG_SP, "Deleting an exe_queue element\n"); bnx2x_exe_queue_free_elem()
127 DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc); bnx2x_exe_queue_add()
188 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n"); bnx2x_exe_queue_step()
249 DP(BNX2X_MSG_SP, "Allocating a new exe_queue element\n"); bnx2x_exe_queue_alloc_elem()
290 DP(BNX2X_MSG_SP, "waiting for state to become %d\n", state); bnx2x_state_wait()
296 DP(BNX2X_MSG_SP, "exit (cnt %d)\n", 5000 - cnt); bnx2x_state_wait()
399 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - There are readers; Busy\n"); __bnx2x_vlan_mac_h_write_trylock()
403 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - Taken\n"); __bnx2x_vlan_mac_h_write_trylock()
422 DP(BNX2X_MSG_SP, "vlan_mac_lock execute pending command with ramrod flags %lu\n", __bnx2x_vlan_mac_h_exec_pending()
451 DP(BNX2X_MSG_SP, "Placing pending execution with ramrod flags %lu\n", __bnx2x_vlan_mac_h_pend()
472 DP(BNX2X_MSG_SP, "vlan_mac_lock - writer release encountered a pending request\n"); __bnx2x_vlan_mac_h_write_unlock()
492 DP(BNX2X_MSG_SP, "vlan_mac_lock - locked reader - number %d\n", __bnx2x_vlan_mac_h_read_lock()
538 DP(BNX2X_MSG_SP, "vlan_mac_lock - decreased readers to %d\n", __bnx2x_vlan_mac_h_read_unlock()
546 DP(BNX2X_MSG_SP, "vlan_mac_lock - reader release encountered a pending request\n"); __bnx2x_vlan_mac_h_read_unlock()
579 DP(BNX2X_MSG_SP, "get_n_elements - taking vlan_mac_lock (reader)\n"); bnx2x_get_n_elements()
589 DP(BNX2X_MSG_SP, "copied element number %d to address %p element was:\n", bnx2x_get_n_elements()
596 DP(BNX2X_MSG_SP, "get_n_elements - releasing vlan_mac_lock (reader)\n"); bnx2x_get_n_elements()
610 DP(BNX2X_MSG_SP, "Checking MAC %pM for ADD command\n", data->mac.mac); bnx2x_check_mac_add()
630 DP(BNX2X_MSG_SP, "Checking VLAN %d for ADD command\n", data->vlan.vlan); bnx2x_check_vlan_add()
647 DP(BNX2X_MSG_SP, "Checking MAC %pM for DEL command\n", data->mac.mac); bnx2x_check_mac_del()
664 DP(BNX2X_MSG_SP, "Checking VLAN %d for DEL command\n", data->vlan.vlan); bnx2x_check_vlan_del()
737 DP(BNX2X_MSG_SP, "Going to %s LLH configuration at entry %d\n", bnx2x_set_mac_in_nig()
853 DP(BNX2X_MSG_SP, "About to %s MAC %pM for Queue %d\n", bnx2x_set_one_mac_e2()
952 DP(BNX2X_MSG_SP, "%s MAC %pM CLID %d CAM offset %d\n", bnx2x_vlan_mac_set_rdata_e1x()
1011 DP(BNX2X_MSG_SP, "About to %s VLAN %d\n", (add ? "add" : "delete"), bnx2x_set_one_vlan_e2()
1162 DP(BNX2X_MSG_SP, "ADD command is not allowed considering current registry state.\n"); bnx2x_validate_vlan_mac_add()
1170 DP(BNX2X_MSG_SP, "There is a pending ADD command already\n"); bnx2x_validate_vlan_mac_add()
1213 DP(BNX2X_MSG_SP, "DEL command is not allowed considering current registry state\n"); bnx2x_validate_vlan_mac_del()
1231 DP(BNX2X_MSG_SP, "There is a pending DEL command already\n"); bnx2x_validate_vlan_mac_del()
1273 DP(BNX2X_MSG_SP, "MOVE command is not allowed considering current registry state\n"); bnx2x_validate_vlan_mac_move()
1292 DP(BNX2X_MSG_SP, "There is a pending MOVE command already\n"); bnx2x_validate_vlan_mac_move()
1403 DP(BNX2X_MSG_SP, "vlan_mac_execute_step - trying to take writer lock\n"); __bnx2x_vlan_mac_execute_step()
1516 DP(BNX2X_MSG_SP, "Optimizing %s command\n", bnx2x_optimize_vlan_mac()
1566 DP(BNX2X_MSG_SP, "Got cam offset %d\n", reg_elem->cam_offset); bnx2x_vlan_mac_get_registry_elem()
1776 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.\n"); bnx2x_config_vlan_mac()
1880 DP(BNX2X_MSG_SP, "vlan_mac_del_all -- taking vlan_mac_lock (reader)\n"); bnx2x_vlan_mac_del_all()
1900 DP(BNX2X_MSG_SP, "vlan_mac_del_all -- releasing vlan_mac_lock (reader)\n"); bnx2x_vlan_mac_del_all()
2123 DP(BNX2X_MSG_SP, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n" bnx2x_set_rx_mode_e1x()
2276 DP(BNX2X_MSG_SP, "About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\n", bnx2x_set_rx_mode_e2()
2408 DP(BNX2X_MSG_SP, "About to enqueue a new %d command. macs_list_len=%d\n", bnx2x_mcast_enqueue_cmd()
2558 DP(BNX2X_MSG_SP, "%s bin %d\n", bnx2x_mcast_set_one_rule_e2()
2594 DP(BNX2X_MSG_SP, "About to configure a bin %d\n", cur_bin); bnx2x_mcast_handle_restore_cmd_e2()
2624 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", bnx2x_mcast_hdl_pending_add_e2()
2656 DP(BNX2X_MSG_SP, "Deleting MAC. %d left,cnt is %d\n", bnx2x_mcast_hdl_pending_del_e2()
2746 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", bnx2x_mcast_hdl_add()
2764 DP(BNX2X_MSG_SP, "Deleting MAC. %d left\n", bnx2x_mcast_hdl_del()
2791 DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len); bnx2x_mcast_handle_current_cmd()
3040 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC, bin %d\n", bnx2x_mcast_hdl_add_e1h()
3059 DP(BNX2X_MSG_SP, "About to set bin %d\n", bit); bnx2x_mcast_hdl_restore_e1h()
3090 DP(BNX2X_MSG_SP, bnx2x_mcast_setup_e1h()
3137 DP(BNX2X_MSG_SP, "Command %d, p->mcast_list_len=%d\n", bnx2x_mcast_validate_e1()
3156 DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len); bnx2x_mcast_validate_e1()
3274 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", bnx2x_mcast_handle_restore_cmd_e1()
3308 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", bnx2x_mcast_handle_pending_cmds_e1()
3315 DP(BNX2X_MSG_SP, "About to delete %d multicast MACs\n", cnt); bnx2x_mcast_handle_pending_cmds_e1()
3394 DP(BNX2X_MSG_SP, "Adding registry entry for [%pM]\n", bnx2x_mcast_refresh_registry_e1()
3402 DP(BNX2X_MSG_SP, "Deleting a registry\n"); bnx2x_mcast_refresh_registry_e1()
3533 DP(BNX2X_MSG_SP, "o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d\n", bnx2x_config_mcast()
3991 DP(BNX2X_MSG_SP, "Setting indirection table to:\n"); bnx2x_debug_print_ind_table()
3992 DP(BNX2X_MSG_SP, "0x0000: "); bnx2x_debug_print_ind_table()
4000 DP(BNX2X_MSG_SP, "0x%04x: ", i + 1); bnx2x_debug_print_ind_table()
4028 DP(BNX2X_MSG_SP, "Configuring RSS\n"); bnx2x_setup_rss()
4042 DP(BNX2X_MSG_SP, "rss_mode=%d\n", rss_mode); bnx2x_setup_rss()
4081 DP(BNX2X_MSG_SP, "rss_engine_id=%d\n", data->rss_engine_id); bnx2x_setup_rss()
4128 DP(BNX2X_MSG_SP, "Not configuring RSS ramrod_flags=%lx\n", bnx2x_config_rss()
4190 DP(BNX2X_MSG_SP, "pending bit was=%lx\n", o->pending); bnx2x_queue_state_change()
4192 DP(BNX2X_MSG_SP, "pending bit now=%lx\n", o->pending); bnx2x_queue_state_change()
4273 DP(BNX2X_MSG_SP, bnx2x_queue_comp_cmd()
4278 DP(BNX2X_MSG_SP, "primary cid %d: num tx-only cons %d\n", bnx2x_queue_comp_cmd()
4341 DP(BNX2X_MSG_SP, "flags: active %d, cos %d, stats en %d\n", bnx2x_q_fill_init_general_data()
4504 DP(BNX2X_MSG_SP, "cid %d, tx bd page lo %x hi %x", bnx2x_q_fill_setup_tx_only()
4553 DP(BNX2X_MSG_SP, "setting context validation. cid %d, cos %d\n", bnx2x_q_init()
4555 DP(BNX2X_MSG_SP, "context pointer %p\n", init->cxts[cos]); bnx2x_q_init()
4639 DP(BNX2X_MSG_SP, "parameters received: cos: %d sp-id: %d\n", bnx2x_q_send_setup_tx_only()
4649 DP(BNX2X_MSG_SP, "sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d\n", bnx2x_q_send_setup_tx_only()
5167 DP(BNX2X_MSG_SP, "Good state transition: %d(%d)->%d\n", bnx2x_queue_chk_transition()
5174 DP(BNX2X_MSG_SP, "Bad state transition request: %d %d\n", state, cmd); bnx2x_queue_chk_transition()
5278 DP(BNX2X_MSG_SP, bnx2x_func_state_change_comp()
5415 DP(BNX2X_MSG_SP, "Good function state transition: %d(%d)->%d\n", bnx2x_func_chk_transition()
5421 DP(BNX2X_MSG_SP, "Bad function state transition request: %d %d\n", bnx2x_func_chk_transition()
5512 DP(BNX2X_MSG_SP, "function %d load_code %x\n", bnx2x_func_hw_init()
5631 DP(BNX2X_MSG_SP, "function %d reset_phase %x\n", BP_ABS_FUNC(bp), bnx2x_func_hw_reset()
5805 DP(BNX2X_MSG_SP, bnx2x_func_send_afex_update()
5844 DP(BNX2X_MSG_SP, "afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x\n", bnx2x_func_send_afex_viflists()
5924 DP(BNX2X_MSG_SP, "Set timesync command params: drift_cmd = %d, offset_cmd = %d, add_sub_drift = %d, drift_val = %d, drift_period = %d, offset_lo = %d, offset_hi = %d\n", bnx2x_func_send_set_timesync()
|
| H A D | bnx2x_main.c | 394 DP(msglvl, "DMAE: opcode 0x%08x\n" bnx2x_dp_dmae()
402 DP(msglvl, "DMAE: opcode 0x%08x\n" bnx2x_dp_dmae()
412 DP(msglvl, "DMAE: opcode 0x%08x\n" bnx2x_dp_dmae()
420 DP(msglvl, "DMAE: opcode 0x%08x\n" bnx2x_dp_dmae()
430 DP(msglvl, "DMAE: opcode 0x%08x\n" bnx2x_dp_dmae()
437 DP(msglvl, "DMAE: opcode 0x%08x\n" bnx2x_dp_dmae()
447 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", bnx2x_dp_dmae()
859 DP(NETIF_MSG_IFDOWN, bnx2x_hc_int_disable()
879 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); bnx2x_igu_int_disable()
912 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); bnx2x_panic_dump()
1214 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); bnx2x_pbf_pN_buf_flushed()
1215 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); bnx2x_pbf_pN_buf_flushed()
1216 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); bnx2x_pbf_pN_buf_flushed()
1225 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", bnx2x_pbf_pN_buf_flushed()
1227 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", bnx2x_pbf_pN_buf_flushed()
1229 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", bnx2x_pbf_pN_buf_flushed()
1234 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", bnx2x_pbf_pN_buf_flushed()
1248 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); bnx2x_pbf_pN_cmd_flushed()
1249 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); bnx2x_pbf_pN_cmd_flushed()
1257 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", bnx2x_pbf_pN_cmd_flushed()
1259 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", bnx2x_pbf_pN_cmd_flushed()
1261 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", bnx2x_pbf_pN_cmd_flushed()
1266 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", bnx2x_pbf_pN_cmd_flushed()
1396 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); bnx2x_send_final_clnup()
1401 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", bnx2x_send_final_clnup()
1472 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); bnx2x_hw_enable_status()
1475 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); bnx2x_hw_enable_status()
1478 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); bnx2x_hw_enable_status()
1481 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); bnx2x_hw_enable_status()
1484 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); bnx2x_hw_enable_status()
1487 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); bnx2x_hw_enable_status()
1490 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); bnx2x_hw_enable_status()
1493 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", bnx2x_hw_enable_status()
1501 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); bnx2x_pf_flr_clnup()
1507 DP(BNX2X_MSG_SP, "Polling usage counters\n"); bnx2x_pf_flr_clnup()
1569 DP(NETIF_MSG_IFUP, bnx2x_hc_int_enable()
1581 DP(NETIF_MSG_IFUP, bnx2x_hc_int_enable()
1647 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", bnx2x_igu_int_enable()
1721 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, bnx2x_trylock_hw_lock()
1726 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, bnx2x_trylock_hw_lock()
1744 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, bnx2x_trylock_hw_lock()
1806 DP(BNX2X_MSG_SP, bnx2x_sp_event()
1820 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); bnx2x_sp_event()
1825 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); bnx2x_sp_event()
1830 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); bnx2x_sp_event()
1835 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); bnx2x_sp_event()
1840 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid); bnx2x_sp_event()
1845 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); bnx2x_sp_event()
1850 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid); bnx2x_sp_event()
1880 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); bnx2x_sp_event()
1916 DP(NETIF_MSG_INTR, "not our interrupt!\n"); bnx2x_interrupt()
1919 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); bnx2x_interrupt()
1969 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
2112 DP(NETIF_MSG_LINK, bnx2x_set_gpio()
2121 DP(NETIF_MSG_LINK, bnx2x_set_gpio()
2130 DP(NETIF_MSG_LINK, bnx2x_set_gpio()
2163 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); bnx2x_set_mult_gpio()
2169 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); bnx2x_set_mult_gpio()
2175 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); bnx2x_set_mult_gpio()
2215 DP(NETIF_MSG_LINK, bnx2x_set_gpio_int()
2224 DP(NETIF_MSG_LINK, bnx2x_set_gpio_int()
2258 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); bnx2x_set_spio()
2265 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); bnx2x_set_spio()
2272 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); bnx2x_set_spio()
2338 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n", bnx2x_init_dropless_fc()
2473 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); bnx2x_calc_vn_min()
2477 DP(NETIF_MSG_IFUP, bnx2x_calc_vn_min()
2503 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); bnx2x_calc_vn_max()
2546 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); bnx2x_read_mf_cfg()
2549 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); bnx2x_read_mf_cfg()
2585 DP(NETIF_MSG_IFUP, bnx2x_cmng_fns_init()
2628 DP(NETIF_MSG_IFUP, bnx2x_set_local_cmng()
2802 DP(BNX2X_MSG_MCP, bnx2x_handle_afex_cmd()
2810 DP(BNX2X_MSG_MCP, bnx2x_handle_afex_cmd()
2823 DP(BNX2X_MSG_MCP, bnx2x_handle_afex_cmd()
2841 DP(BNX2X_MSG_MCP, bnx2x_handle_afex_cmd()
2948 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov); bnx2x_handle_update_svid_cmd()
2966 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); bnx2x_pmf_update()
3014 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", bnx2x_fw_command()
3026 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", bnx2x_fw_command()
3554 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); bnx2x_handle_eee_event()
3614 DP(BNX2X_MSG_MCP, "Management does not support indication\n"); bnx2x_handle_drv_info_req()
3633 DP(BNX2X_MSG_MCP, "Management did not release indication\n"); bnx2x_handle_drv_info_req()
3706 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n", bnx2x_update_mng_version()
3729 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event); bnx2x_oem_event()
3738 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); bnx2x_oem_event()
3743 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); bnx2x_oem_event()
3774 DP(BNX2X_MSG_SP, "end of spq\n"); bnx2x_sp_get_next()
3898 DP(BNX2X_MSG_SP, bnx2x_sp_post()
3985 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", bnx2x_attn_int_asserted()
3988 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); bnx2x_attn_int_asserted()
3993 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); bnx2x_attn_int_asserted()
3995 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); bnx2x_attn_int_asserted()
4017 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); bnx2x_attn_int_asserted()
4020 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); bnx2x_attn_int_asserted()
4023 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); bnx2x_attn_int_asserted()
4026 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); bnx2x_attn_int_asserted()
4030 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); bnx2x_attn_int_asserted()
4034 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); bnx2x_attn_int_asserted()
4038 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); bnx2x_attn_int_asserted()
4043 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); bnx2x_attn_int_asserted()
4047 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); bnx2x_attn_int_asserted()
4051 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); bnx2x_attn_int_asserted()
4064 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, bnx2x_attn_int_asserted()
4081 DP(NETIF_MSG_HW, bnx2x_attn_int_asserted()
4392 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); bnx2x_reset_is_global()
4465 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); bnx2x_set_pf_load()
4502 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); bnx2x_clear_pf_load()
4534 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); bnx2x_get_load_status()
4538 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", bnx2x_get_load_status()
4934 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" bnx2x_parity_attn()
5096 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", bnx2x_attn_int_deasserted()
5103 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", bnx2x_attn_int_deasserted()
5131 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, bnx2x_attn_int_deasserted()
5144 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", bnx2x_attn_int_deasserted()
5147 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); bnx2x_attn_int_deasserted()
5152 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); bnx2x_attn_int_deasserted()
5154 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); bnx2x_attn_int_deasserted()
5170 DP(NETIF_MSG_HW, bnx2x_attn_int()
5211 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); bnx2x_cnic_handle_cfc_del()
5262 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); bnx2x_handle_classification_eqe()
5270 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); bnx2x_handle_classification_eqe()
5287 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); bnx2x_handle_classification_eqe()
5315 DP(BNX2X_MSG_SP, bnx2x_after_afex_vif_lists()
5322 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); bnx2x_after_afex_vif_lists()
5395 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); bnx2x_cid_to_q_obj()
5432 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", bnx2x_eq_int()
5442 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", bnx2x_eq_int()
5472 DP(BNX2X_MSG_SP, bnx2x_eq_int()
5487 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); bnx2x_eq_int()
5495 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); bnx2x_eq_int()
5505 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, bnx2x_eq_int()
5514 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, bnx2x_eq_int()
5534 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, bnx2x_eq_int()
5542 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, bnx2x_eq_int()
5550 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP, bnx2x_eq_int()
5565 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", bnx2x_eq_int()
5580 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); bnx2x_eq_int()
5590 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); bnx2x_eq_int()
5600 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); bnx2x_eq_int()
5628 DP(BNX2X_MSG_SP, "sp task invoked\n"); bnx2x_sp_task()
5637 DP(BNX2X_MSG_SP, "status %x\n", status); bnx2x_sp_task()
5638 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); bnx2x_sp_task()
5671 DP(BNX2X_MSG_SP, bnx2x_sp_task()
5955 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); bnx2x_init_sb()
6346 DP(NETIF_MSG_IFUP,
6415 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); bnx2x_init_fcoe_fp()
6434 DP(NETIF_MSG_IFUP, bnx2x_init_fcoe_fp()
6693 DP(NETIF_MSG_HW, "part2\n"); bnx2x_int_mem_test()
6767 DP(NETIF_MSG_HW, "done\n"); bnx2x_int_mem_test()
6860 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); bnx2x_init_pxp()
6865 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); bnx2x_init_pxp()
6903 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); bnx2x_setup_fan_failure_detection()
6993 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); bnx2x_init_hw_common()
7453 DP(NETIF_MSG_HW, "starting port init port %d\n", port); bnx2x_init_hw_port()
7709 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", bnx2x_igu_clear_sb_gen()
7714 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", bnx2x_igu_clear_sb_gen()
7725 DP(NETIF_MSG_HW, bnx2x_igu_clear_sb_gen()
7845 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); bnx2x_reset_nic_mode()
7894 DP(NETIF_MSG_HW, "starting func init func %d\n", func); bnx2x_init_hw_func()
7939 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); bnx2x_init_hw_func()
7943 DP(NETIF_MSG_IFUP, "NIC MODE configured\n"); bnx2x_init_hw_func()
8167 DP(NETIF_MSG_HW, bnx2x_init_hw_func()
8392 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); bnx2x_set_mac_one()
8427 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); bnx2x_set_eth_mac()
8512 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); bnx2x_ilt_set_info()
8526 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", bnx2x_ilt_set_info()
8547 DP(NETIF_MSG_IFUP, bnx2x_ilt_set_info()
8566 DP(NETIF_MSG_IFUP, bnx2x_ilt_set_info()
8583 DP(NETIF_MSG_IFUP, bnx2x_ilt_set_info()
8644 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", bnx2x_pf_q_prep_init()
8679 DP(NETIF_MSG_IFUP, bnx2x_setup_tx_only()
8711 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); bnx2x_setup_queue()
8735 DP(NETIF_MSG_IFUP, "init complete\n"); bnx2x_setup_queue()
8791 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); bnx2x_stop_queue()
8805 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", bnx2x_stop_queue()
8954 DP(NETIF_MSG_IFDOWN, bnx2x_reset_port()
9060 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", bnx2x_send_unload_req()
9065 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", bnx2x_send_unload_req()
9141 DP(NETIF_MSG_IFDOWN, bnx2x_func_wait_started()
9200 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n"); bnx2x_stop_ptp()
9352 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); bnx2x_disable_close_the_gate()
9405 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", bnx2x_set_234_gates()
9447 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); bnx2x_reset_mcp_prep()
9848 DP(NETIF_MSG_HW, "Handling parity\n"); bnx2x_parity_recover()
9852 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); bnx2x_parity_recover()
9886 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); bnx2x_parity_recover()
10065 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); bnx2x_sp_rtnl_task()
10073 DP(BNX2X_MSG_SP, bnx2x_sp_rtnl_task()
10086 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n"); bnx2x_sp_rtnl_task()
10356 DP(NETIF_MSG_HW, "Path %d was marked by AER\n", bnx2x_prev_is_path_marked()
10402 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n", bnx2x_prev_mark_path()
10429 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", bnx2x_prev_mark_path()
12335 DP(BNX2X_MSG_SP, netdev_for_each_uc_addr()
12397 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); bnx2x_set_rx_mode()
12410 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); bnx2x_set_rx_mode_inner()
12473 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", bnx2x_mdio_read()
12482 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); bnx2x_mdio_read()
12496 DP(NETIF_MSG_LINK, bnx2x_mdio_write()
12522 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", bnx2x_ioctl()
13225 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb); bnx2x_ptp_adjfreq()
13228 DP(BNX2X_MSG_PTP, bnx2x_ptp_adjfreq()
13279 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val, bnx2x_ptp_adjfreq()
13289 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta); bnx2x_ptp_adjtime()
13303 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns); bnx2x_ptp_gettime()
13318 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns); bnx2x_ptp_settime()
13819 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n"); bnx2x_io_slot_reset()
14040 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", bnx2x_cnic_sp_post()
14083 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", bnx2x_cnic_sp_queue()
14392 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n", bnx2x_setup_cnic_info()
14407 DP(NETIF_MSG_IFUP, "Register_cnic called\n"); bnx2x_register_cnic()
14586 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n", bnx2x_ptp_task()
14589 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n"); bnx2x_ptp_task()
14614 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n", bnx2x_set_rx_ts()
14631 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles); bnx2x_cyclecounter_read()
14785 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n"); bnx2x_hwtstamp_ioctl()
14790 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n", bnx2x_hwtstamp_ioctl()
14883 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n"); bnx2x_init_ptp()
|
| H A D | bnx2x_vfpf.c | 43 DP(BNX2X_MSG_IOV, "preparing to send %d tlv over vf pf channel\n", bnx2x_vfpf_prep()
60 DP(BNX2X_MSG_IOV, "done sending [%d] tlv over vf pf channel\n", bnx2x_vfpf_finalize()
85 DP(BNX2X_MSG_IOV, "TLV list does not contain %d TLV\n", req_tlv); bnx2x_search_tlv_list()
98 DP(BNX2X_MSG_IOV, "TLV number %d: type %d, length %d\n", i, bnx2x_dp_tlv_list()
117 DP(BNX2X_MSG_IOV, "TLV number %d: type %d, length %d\n", i, bnx2x_dp_tlv_list()
156 DP(BNX2X_MSG_IOV, "detecting channel down. Aborting message\n"); bnx2x_send_msg2pf()
188 DP(BNX2X_MSG_SP, "Got a response from PF\n"); bnx2x_send_msg2pf()
214 DP(BNX2X_MSG_IOV, "valid ME register value: 0x%08x\n", me_reg); bnx2x_get_vf_id()
269 DP(BNX2X_MSG_SP, "attempting to acquire resources\n"); bnx2x_vfpf_acquire()
289 DP(BNX2X_MSG_SP, "resources acquired\n"); bnx2x_vfpf_acquire()
294 DP(BNX2X_MSG_SP, bnx2x_vfpf_acquire()
421 DP(BNX2X_MSG_SP, "vf released\n"); bnx2x_vfpf_release()
474 DP(BNX2X_MSG_SP, "INIT VF Succeeded\n"); bnx2x_vfpf_init()
750 DP(BNX2X_MSG_IOV, bnx2x_vfpf_config_mac()
823 DP(BNX2X_MSG_IOV, "rss flags %x\n", req->rss_flags); bnx2x_vfpf_config_rss()
840 DP(BNX2X_MSG_IOV, bnx2x_vfpf_config_rss()
859 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); bnx2x_vfpf_set_mcast()
868 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags); bnx2x_vfpf_set_mcast()
871 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n", netdev_for_each_mc_addr()
881 DP(NETIF_MSG_IFUP,
925 DP(NETIF_MSG_IFUP, "Rx mode is %d\n", mode); bnx2x_vfpf_storm_rx_mode()
1069 DP(BNX2X_MSG_IOV, "mailbox vf address hi 0x%x, lo 0x%x, offset 0x%x\n", bnx2x_vf_mbx_resp_send_msg()
1231 DP(BNX2X_MSG_IOV, "VF[%d] ACQUIRE_RESPONSE: pfdev_info- chip_num=0x%x, db_size=%d, idx_per_sb=%d, pf_cap=0x%x\n"
1323 DP(BNX2X_MSG_IOV, bnx2x_vf_mbx_acquire()
1337 DP(BNX2X_MSG_IOV, bnx2x_vf_mbx_acquire()
1352 DP(BNX2X_MSG_IOV, bnx2x_vf_mbx_acquire()
1366 DP(BNX2X_MSG_IOV, "VF[%d] supports long bulletin boards\n", bnx2x_vf_mbx_acquire()
1604 DP(msglvl, "MAC-VLAN[%d] -- flags=0x%x\n", idx, filter->flags); bnx2x_vf_mbx_dp_q_filter()
1623 DP(msglvl, "RX-MASK=0x%x\n", filters->rx_mask); bnx2x_vf_mbx_dp_q_filters()
1627 DP(msglvl, "MULTICAST=%pM\n", filters->multicast[i]); bnx2x_vf_mbx_dp_q_filters()
1801 DP(BNX2X_MSG_IOV, "VF[%d] Q_FILTERS: queue[%d]\n", bnx2x_vf_mbx_set_q_filters()
1819 DP(BNX2X_MSG_IOV, "VF[%d] Q_TEARDOWN: vf_qid=%d\n", bnx2x_vf_mbx_teardown_q()
1831 DP(BNX2X_MSG_IOV, "VF[%d] VF_CLOSE\n", vf->abs_vfid); bnx2x_vf_mbx_close_vf()
1842 DP(BNX2X_MSG_IOV, "VF[%d] VF_RELEASE\n", vf->abs_vfid); bnx2x_vf_mbx_release_vf()
2053 DP(BNX2X_MSG_IOV, bnx2x_vf_mbx_schedule()
2102 DP(BNX2X_MSG_IOV, for_each_vf()
|
| H A D | bnx2x_cmn.c | 210 DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d buff @(%p)->skb %p\n", bnx2x_free_tx_pkt()
294 DP(NETIF_MSG_TX_DONE, bnx2x_tx_int()
369 DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n", bnx2x_update_sge_prod()
400 DP(NETIF_MSG_RX_STATUS, bnx2x_update_sge_prod()
487 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n", bnx2x_tpa_start()
793 DP(NETIF_MSG_RX_STATUS, bnx2x_tpa_stop()
807 DP(NETIF_MSG_RX_STATUS, bnx2x_tpa_stop()
892 DP(NETIF_MSG_RX_STATUS, bnx2x_rx_int()
928 DP(NETIF_MSG_RX_STATUS, bnx2x_rx_int()
959 DP(NETIF_MSG_RX_STATUS, bnx2x_rx_int()
971 DP(NETIF_MSG_RX_STATUS, bnx2x_rx_int()
1006 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS, bnx2x_rx_int()
1020 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS, bnx2x_rx_int()
1043 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS, bnx2x_rx_int()
1126 DP(NETIF_MSG_INTR, bnx2x_msix_fp_int()
1355 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i); bnx2x_free_tpa_pool()
1396 DP(NETIF_MSG_IFUP, for_each_eth_queue()
1613 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n", bnx2x_free_msix_irqs()
1627 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq\n", for_each_eth_queue()
1678 DP(BNX2X_MSG_SP, "about to request enable msix with %d vectors\n",
1997 DP(NETIF_MSG_IFUP, "Setting real num queues to (tx, rx) (%d, %d)\n", bnx2x_set_real_num_queues()
2256 DP(BNX2X_MSG_SP, "stats fw_stats_num %d, vf headroom %d, num_groups %d\n", bnx2x_alloc_fw_stats_mem()
2288 DP(BNX2X_MSG_SP, "statistics request base address set to %x %x\n", bnx2x_alloc_fw_stats_mem()
2291 DP(BNX2X_MSG_SP, "statistics data base address set to %x %x\n", bnx2x_alloc_fw_stats_mem()
2361 DP(BNX2X_MSG_SP, "loaded fw %x, my fw %x\n", bnx2x_compare_fw_ver()
2383 DP(NETIF_MSG_IFUP, "NO MCP - load counts[%d] %d, %d, %d\n", bnx2x_nic_load_no_mcp()
2388 DP(NETIF_MSG_IFUP, "NO MCP - new load counts[%d] %d, %d, %d\n", bnx2x_nic_load_no_mcp()
2415 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); bnx2x_nic_load_pmf()
2499 DP(NETIF_MSG_IFUP, "Starting CNIC-related load\n"); bnx2x_load_cnic()
2526 DP(NETIF_MSG_IFUP, "cnic napi added\n"); bnx2x_load_cnic()
2560 DP(NETIF_MSG_IFUP, "Ending successfully CNIC-related load\n");
2588 DP(NETIF_MSG_IFUP, "Starting NIC load\n"); bnx2x_nic_load()
2589 DP(NETIF_MSG_IFUP, bnx2x_nic_load()
2615 DP(NETIF_MSG_IFUP, "num queues: %d", bp->num_queues); bnx2x_nic_load()
2673 DP(NETIF_MSG_IFUP, "napi added\n"); bnx2x_nic_load()
2874 DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n");
2939 DP(NETIF_MSG_IFUP, "Starting NIC unload\n"); bnx2x_nic_unload()
2964 DP(NETIF_MSG_IFDOWN, "Releasing a leadership...\n"); bnx2x_nic_unload()
3103 DP(NETIF_MSG_IFUP, "Ending NIC unload\n"); bnx2x_nic_unload()
3228 DP(NETIF_MSG_RX_STATUS,
3285 DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d (%x:%x)\n", bnx2x_tx_split()
3303 DP(NETIF_MSG_TX_QUEUED, bnx2x_tx_split()
3448 DP(NETIF_MSG_TX_QUEUED, bnx2x_pkt_req_lin()
3608 DP(NETIF_MSG_TX_QUEUED, bnx2x_set_pbd_csum()
3617 DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n", bnx2x_set_pbd_csum()
3753 DP(NETIF_MSG_TX_QUEUED, "indices: txq %d, fp %d, txdata %d\n", bnx2x_start_xmit()
3757 DP(NETIF_MSG_TX_QUEUED, bnx2x_start_xmit()
3780 DP(NETIF_MSG_TX_QUEUED, bnx2x_start_xmit()
3804 DP(NETIF_MSG_TX_QUEUED, bnx2x_start_xmit()
3815 DP(NETIF_MSG_TX_QUEUED, bnx2x_start_xmit()
3867 DP(NETIF_MSG_TX_QUEUED, bnx2x_start_xmit()
4001 DP(NETIF_MSG_TX_QUEUED, bnx2x_start_xmit()
4010 DP(NETIF_MSG_TX_QUEUED, bnx2x_start_xmit()
4049 DP(NETIF_MSG_TX_QUEUED, bnx2x_start_xmit()
4075 DP(NETIF_MSG_TX_QUEUED, bnx2x_start_xmit()
4081 DP(NETIF_MSG_TX_QUEUED, "last bd @%p\n", tx_data_bd); bnx2x_start_xmit()
4105 DP(NETIF_MSG_TX_QUEUED, bnx2x_start_xmit()
4112 DP(NETIF_MSG_TX_QUEUED, bnx2x_start_xmit()
4122 DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod); bnx2x_start_xmit()
4202 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, bnx2x_setup_tc()
4211 DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", 0, 0); bnx2x_setup_tc()
4214 DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", prio, 1); bnx2x_setup_tc()
4222 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, bnx2x_setup_tc()
4314 DP(NETIF_MSG_IFDOWN, for_each_cos_in_tx_queue()
4447 DP(BNX2X_MSG_SP, "calculated rx_ring_size %d\n", rx_ring_size); bnx2x_alloc_fp_mem_at()
4479 DP(NETIF_MSG_IFUP, for_each_cos_in_tx_queue()
4790 DP(BNX2X_MSG_IOV, "VFs are enabled, can not change MTU\n"); bnx2x_change_mtu()
4995 DP(NETIF_MSG_IFUP, storm_memset_hc_timeout()
5012 DP(NETIF_MSG_IFUP, storm_memset_hc_disable()
5035 DP((BNX2X_MSG_SP | verbose), "Scheduling sp_rtnl task [Flag: %d]\n", bnx2x_schedule_sp_rtnl()
|
| H A D | bnx2x_stats.c | 86 DP(BNX2X_MSG_STATS, "dumping stats:\n" bnx2x_dp_stats()
102 DP(BNX2X_MSG_STATS, bnx2x_dp_stats()
134 DP(BNX2X_MSG_STATS, "Sending statistics ramrod %d\n", bnx2x_storm_stats_post()
826 DP(BNX2X_MSG_STATS, bnx2x_hw_stats_update()
885 DP(BNX2X_MSG_STATS, bnx2x_storm_stats_validate_counters()
892 DP(BNX2X_MSG_STATS, bnx2x_storm_stats_validate_counters()
899 DP(BNX2X_MSG_STATS, bnx2x_storm_stats_validate_counters()
906 DP(BNX2X_MSG_STATS, bnx2x_storm_stats_validate_counters()
956 DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, bcast_sent 0x%x mcast_sent 0x%x\n", for_each_eth_queue()
960 DP(BNX2X_MSG_STATS, "---------------\n"); for_each_eth_queue()
1379 DP(BNX2X_MSG_STATS, bnx2x_stats_handle()
1394 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n", bnx2x_stats_handle()
1617 DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n", bnx2x_stats_init()
|
| H A D | bnx2x_cmn.h | 55 DP(NETIF_MSG_HW, \
65 DP(NETIF_MSG_HW, \
525 DP(NETIF_MSG_RX_STATUS, bnx2x_update_rx_prod()
643 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", bnx2x_igu_ack_sb_gen()
708 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", bnx2x_igu_ack_int()
1113 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", bnx2x_init_txdata()
1231 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, bnx2x_extract_max_cfg()
1302 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); bnx2x_update_drv_flags()
|
| H A D | bnx2x_init_ops.h | 479 DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n", bnx2x_init_pxp_arb()
484 DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n", bnx2x_init_pxp_arb()
489 DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n"); bnx2x_init_pxp_arb()
492 DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order); bnx2x_init_pxp_arb()
|
| H A D | bnx2x_init.h | 713 DP(NETIF_MSG_HW, "Setting parity mask " bnx2x_disable_blocks_parity()
746 DP(NETIF_MSG_HW, bnx2x_clear_blocks_parity()
756 DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n", bnx2x_clear_blocks_parity()
|
| H A D | bnx2x_reg.h | 2210 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2211 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2212 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2213 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2379 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2380 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2381 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2382 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2491 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2492 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2493 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2494 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2527 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2528 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2529 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2530 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
|
| H A D | bnx2x.h | 89 #define DP(__mask, fmt, ...) \ macro
|
| /linux-4.1.27/drivers/phy/ |
| H A D | phy-exynos-dp-video.c | 37 /* Disable power isolation on DP-PHY */ exynos_dp_video_phy_power_on()
46 /* Enable power isolation on DP-PHY */ exynos_dp_video_phy_power_off()
121 MODULE_DESCRIPTION("Samsung EXYNOS SoC DP PHY driver");
|
| /linux-4.1.27/drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_dp.c | 259 uint32_t DP; member in struct:cdv_intel_dp
308 * @intel_dp: DP struct
310 * If a CPU or PCH DP output is attached to an eDP panel, this function
602 /* Must try at least 3 times according to DP spec */ cdv_intel_dp_aux_ch()
1048 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; cdv_intel_dp_mode_set()
1049 intel_dp->DP |= intel_dp->color_range; cdv_intel_dp_mode_set()
1052 intel_dp->DP |= DP_SYNC_HS_HIGH; cdv_intel_dp_mode_set()
1054 intel_dp->DP |= DP_SYNC_VS_HIGH; cdv_intel_dp_mode_set()
1056 intel_dp->DP |= DP_LINK_TRAIN_OFF; cdv_intel_dp_mode_set()
1060 intel_dp->DP |= DP_PORT_WIDTH_1; cdv_intel_dp_mode_set()
1063 intel_dp->DP |= DP_PORT_WIDTH_2; cdv_intel_dp_mode_set()
1066 intel_dp->DP |= DP_PORT_WIDTH_4; cdv_intel_dp_mode_set()
1070 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; cdv_intel_dp_mode_set()
1082 intel_dp->DP |= DP_ENHANCED_FRAMING; cdv_intel_dp_mode_set()
1085 /* CPT DP's pipe select is decided in TRANS_DP_CTL */ cdv_intel_dp_mode_set()
1087 intel_dp->DP |= DP_PIPEB_SELECT; cdv_intel_dp_mode_set()
1089 REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN)); cdv_intel_dp_mode_set()
1090 DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP); cdv_intel_dp_mode_set()
1508 uint32_t DP = intel_dp->DP; cdv_intel_dp_start_link_train() local
1510 DP |= DP_PORT_EN; cdv_intel_dp_start_link_train()
1511 DP &= ~DP_LINK_TRAIN_MASK; cdv_intel_dp_start_link_train()
1513 reg = DP; cdv_intel_dp_start_link_train()
1532 reg = DP | DP_LINK_TRAIN_PAT_1; cdv_intel_dp_start_link_train()
1537 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n", cdv_intel_dp_start_link_train()
1554 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n", cdv_intel_dp_start_link_train()
1586 DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]); cdv_intel_dp_start_link_train()
1589 intel_dp->DP = DP; cdv_intel_dp_start_link_train()
1600 uint32_t DP = intel_dp->DP; cdv_intel_dp_complete_link_train() local
1608 reg = DP | DP_LINK_TRAIN_PAT_2; cdv_intel_dp_complete_link_train()
1612 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n", cdv_intel_dp_complete_link_train()
1625 DRM_ERROR("failed to train DP, aborting\n"); cdv_intel_dp_complete_link_train()
1638 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n", cdv_intel_dp_complete_link_train()
1670 reg = DP | DP_LINK_TRAIN_OFF; cdv_intel_dp_complete_link_train()
1683 uint32_t DP = intel_dp->DP; cdv_intel_dp_link_down() local
1692 DP &= ~DP_LINK_TRAIN_MASK; cdv_intel_dp_link_down()
1693 REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); cdv_intel_dp_link_down()
1699 REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); cdv_intel_dp_link_down()
1723 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1725 * \return true if DP port is connected.
1726 * \return false if DP port is disconnected.
1954 /* check the VBT to see whether the eDP is on DP-D port */ cdv_intel_dpc_is_edp()
1977 DP/eDP. TODO - investigate if we can turn it back to normality
|
| H A D | psb_intel_drv.h | 270 /* DP support */
|
| H A D | cdv_intel_display.c | 644 * unnecessary to consider it for DP/eDP. cdv_intel_crtc_mode_set()
646 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise cdv_intel_crtc_mode_set()
648 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz. cdv_intel_crtc_mode_set()
|
| H A D | psb_intel_reg.h | 1368 #define SB_P2_10 0 /* HDMI, DP, DAC */
1494 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
1521 * (the DP spec calls pixel_clock the 'strm_clk')
|
| H A D | intel_bios.h | 616 /* define the PORT for DP output type */
|
| /linux-4.1.27/drivers/gpu/drm/i915/ |
| H A D | intel_dp.c | 97 * @intel_dp: DP struct
99 * If a CPU or PCH DP output is attached to an eDP panel, this function
139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", intel_dp_max_link_bw()
332 uint32_t DP; vlv_power_sequencer_kick() local
345 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; vlv_power_sequencer_kick()
346 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; vlv_power_sequencer_kick()
347 DP |= DP_PORT_WIDTH(1); vlv_power_sequencer_kick()
348 DP |= DP_LINK_TRAIN_PAT_1; vlv_power_sequencer_kick()
351 DP |= DP_PIPE_SELECT_CHV(pipe); vlv_power_sequencer_kick()
353 DP |= DP_PIPEB_SELECT; vlv_power_sequencer_kick()
371 I915_WRITE(intel_dp->output_reg, DP); vlv_power_sequencer_kick()
374 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); vlv_power_sequencer_kick()
377 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); vlv_power_sequencer_kick()
396 /* We should never land here with regular DP ports */ vlv_power_sequencer_pipe()
859 /* Must try at least 3 times according to DP spec */ intel_dp_aux_ch()
1108 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which skl_edp_set_pll_config()
1376 DRM_DEBUG_KMS("DP link computation with max lane count %i " intel_dp_compute_config()
1455 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", intel_dp_compute_config()
1458 DRM_DEBUG_KMS("DP link bw required %i available %i\n", intel_dp_compute_config()
1504 intel_dp->DP |= DP_PLL_FREQ_160MHZ; ironlake_set_pll_cpu_edp()
1507 intel_dp->DP |= DP_PLL_FREQ_270MHZ; ironlake_set_pll_cpu_edp()
1526 * There are four kinds of DP registers: intel_dp_prepare()
1534 * except that the CPU DP PLL is configured in this intel_dp_prepare()
1545 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; intel_dp_prepare()
1547 /* Handle DP bits in common between all three register formats */ intel_dp_prepare()
1548 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; intel_dp_prepare()
1549 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); intel_dp_prepare()
1552 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; intel_dp_prepare()
1558 intel_dp->DP |= DP_SYNC_HS_HIGH; intel_dp_prepare()
1560 intel_dp->DP |= DP_SYNC_VS_HIGH; intel_dp_prepare()
1561 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; intel_dp_prepare()
1564 intel_dp->DP |= DP_ENHANCED_FRAMING; intel_dp_prepare()
1566 intel_dp->DP |= crtc->pipe << 29; intel_dp_prepare()
1569 intel_dp->DP |= intel_dp->color_range; intel_dp_prepare()
1572 intel_dp->DP |= DP_SYNC_HS_HIGH; intel_dp_prepare()
1574 intel_dp->DP |= DP_SYNC_VS_HIGH; intel_dp_prepare()
1575 intel_dp->DP |= DP_LINK_TRAIN_OFF; intel_dp_prepare()
1578 intel_dp->DP |= DP_ENHANCED_FRAMING; intel_dp_prepare()
1582 intel_dp->DP |= DP_PIPEB_SELECT; intel_dp_prepare()
1584 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); intel_dp_prepare()
1587 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; intel_dp_prepare()
2086 /* We don't adjust intel_dp->DP while tearing down the link, to ironlake_edp_pll_on()
2089 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); ironlake_edp_pll_on()
2090 intel_dp->DP |= DP_PLL_ENABLE; ironlake_edp_pll_on()
2091 I915_WRITE(DP_A, intel_dp->DP); ironlake_edp_pll_on()
2112 /* We can't rely on the value tracked for the DP register in ironlake_edp_pll_off()
2113 * intel_dp->DP because link_down must not change that (otherwise link ironlake_edp_pll_off()
2374 uint32_t *DP, _intel_dp_set_link_train()
2409 *DP &= ~DP_LINK_TRAIN_MASK_CPT; _intel_dp_set_link_train()
2413 *DP |= DP_LINK_TRAIN_OFF_CPT; _intel_dp_set_link_train()
2416 *DP |= DP_LINK_TRAIN_PAT_1_CPT; _intel_dp_set_link_train()
2419 *DP |= DP_LINK_TRAIN_PAT_2_CPT; _intel_dp_set_link_train()
2422 DRM_ERROR("DP training pattern 3 not supported\n"); _intel_dp_set_link_train()
2423 *DP |= DP_LINK_TRAIN_PAT_2_CPT; _intel_dp_set_link_train()
2429 *DP &= ~DP_LINK_TRAIN_MASK_CHV; _intel_dp_set_link_train()
2431 *DP &= ~DP_LINK_TRAIN_MASK; _intel_dp_set_link_train()
2435 *DP |= DP_LINK_TRAIN_OFF; _intel_dp_set_link_train()
2438 *DP |= DP_LINK_TRAIN_PAT_1; _intel_dp_set_link_train()
2441 *DP |= DP_LINK_TRAIN_PAT_2; _intel_dp_set_link_train()
2445 *DP |= DP_LINK_TRAIN_PAT_3_CHV; _intel_dp_set_link_train()
2447 DRM_ERROR("DP training pattern 3 not supported\n"); _intel_dp_set_link_train()
2448 *DP |= DP_LINK_TRAIN_PAT_2; _intel_dp_set_link_train()
2461 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, intel_dp_enable_port()
2464 I915_WRITE(intel_dp->output_reg, intel_dp->DP); intel_dp_enable_port()
2473 intel_dp->DP |= DP_PORT_EN; intel_dp_enable_port()
2475 I915_WRITE(intel_dp->output_reg, intel_dp->DP); intel_dp_enable_port()
2512 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", intel_enable_dp()
3312 /* Gen6's DP voltage swing and pre-emphasis control */
3340 /* Gen7's DP voltage swing and pre-emphasis control */
3371 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3408 /* Properly updates "DP" with the correct signal levels. */
3410 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) intel_dp_set_signal_levels() argument
3440 *DP = (*DP & ~mask) | signal_levels; intel_dp_set_signal_levels()
3445 uint32_t *DP, intel_dp_set_link_train()
3454 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat); intel_dp_set_link_train()
3456 I915_WRITE(intel_dp->output_reg, *DP); intel_dp_set_link_train()
3477 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, intel_dp_reset_link_train() argument
3481 intel_dp_set_signal_levels(intel_dp, DP); intel_dp_reset_link_train()
3482 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); intel_dp_reset_link_train()
3486 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, intel_dp_update_link_train() argument
3495 intel_dp_set_signal_levels(intel_dp, DP); intel_dp_update_link_train()
3497 I915_WRITE(intel_dp->output_reg, *DP); intel_dp_update_link_train()
3534 DRM_ERROR("Timed out waiting for DP idle patterns\n"); intel_dp_set_idle_link_train()
3546 uint32_t DP = intel_dp->DP; intel_dp_start_link_train() local
3566 DP |= DP_PORT_EN; intel_dp_start_link_train()
3569 if (!intel_dp_reset_link_train(intel_dp, &DP, intel_dp_start_link_train()
3603 intel_dp_reset_link_train(intel_dp, &DP, intel_dp_start_link_train()
3622 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { intel_dp_start_link_train()
3628 intel_dp->DP = DP; intel_dp_start_link_train()
3636 uint32_t DP = intel_dp->DP; intel_dp_complete_link_train() local
3644 if (!intel_dp_set_link_train(intel_dp, &DP, intel_dp_complete_link_train()
3658 DRM_ERROR("failed to train DP, aborting\n"); intel_dp_complete_link_train()
3671 intel_dp_set_link_train(intel_dp, &DP, intel_dp_complete_link_train()
3686 intel_dp_set_link_train(intel_dp, &DP, intel_dp_complete_link_train()
3695 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { intel_dp_complete_link_train()
3704 intel_dp->DP = DP; intel_dp_complete_link_train()
3707 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); intel_dp_complete_link_train()
3713 intel_dp_set_link_train(intel_dp, &intel_dp->DP, intel_dp_stop_link_train()
3724 uint32_t DP = intel_dp->DP; intel_dp_link_down() local
3735 DP &= ~DP_LINK_TRAIN_MASK_CPT; intel_dp_link_down()
3736 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); intel_dp_link_down()
3739 DP &= ~DP_LINK_TRAIN_MASK_CHV; intel_dp_link_down()
3741 DP &= ~DP_LINK_TRAIN_MASK; intel_dp_link_down()
3742 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); intel_dp_link_down()
3756 DP &= ~DP_PIPEB_SELECT; intel_dp_link_down()
3757 I915_WRITE(intel_dp->output_reg, DP); intel_dp_link_down()
3761 DP &= ~DP_AUDIO_OUTPUT_ENABLE; intel_dp_link_down()
3762 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); intel_dp_link_down()
3839 return true; /* native DP sink */ intel_dp_get_dpcd()
4032 * According to DP spec
4137 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); intel_dp_detect_dpcd()
4729 /* Return which DP Port should be selected for Transcoder DP control */
4748 /* check the VBT to see whether the eDP is on DP-D port */ intel_dp_is_edp()
5078 * @intel_dp: DP struct
5111 * @intel_dp: DP struct
5429 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); intel_edp_init_connector()
5431 pipe = PORT_TO_PIPE(intel_dp->DP); intel_edp_init_connector()
5482 intel_dp->DP = I915_READ(intel_dp->output_reg); intel_dp_init_connector()
5492 * for DP the encoder type can be set by the caller to intel_dp_init_connector()
5504 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", intel_dp_init_connector()
2373 _intel_dp_set_link_train(struct intel_dp *intel_dp, uint32_t *DP, uint8_t dp_train_pat) _intel_dp_set_link_train() argument
3444 intel_dp_set_link_train(struct intel_dp *intel_dp, uint32_t *DP, uint8_t dp_train_pat) intel_dp_set_link_train() argument
|
| H A D | intel_ddi.c | 37 * them for both DP and FDI transports, allowing those ports to
187 * values in advance. The buffer values are different for FDI and DP modes,
189 * in either FDI or DP modes only, as HDMI connections will work with both
305 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
467 intel_dp->DP = intel_dig_port->saved_port_bits | intel_ddi_init_dp_buf_reg()
469 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); intel_ddi_init_dp_buf_reg()
2036 intel_dp->DP |= DDI_BUF_CTL_ENABLE; intel_ddi_prepare_link_retrain()
2037 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); intel_ddi_prepare_link_retrain()
2239 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n", intel_ddi_init()
|
| H A D | intel_bios.c | 998 DRM_DEBUG_KMS("Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d\n", parse_ddi_port()
1002 DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n", parse_ddi_port()
1007 DRM_DEBUG_KMS("Analog port %c is also DP or TMDS compatible\n", parse_ddi_port()
1012 DRM_DEBUG_KMS("Port %c is not DP/TMDS/CRT compatible\n", parse_ddi_port()
1015 DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port)); parse_ddi_port()
|
| H A D | intel_psr.c | 43 * required DP aux message and could even retrain the link (that part isn't
326 * @intel_dp: Intel DP
446 * @intel_dp: Intel DP
|
| H A D | intel_drv.h | 163 * encoder are flushed (for example for DP AUX transactions) and
302 /* DP has a bunch of special case unfortunately, so mark the pipe
358 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
617 uint32_t DP; member in struct:intel_dp
|
| H A D | i915_drv.h | 304 /* HDMI only, 0 when used for DP */
1511 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1808 * if we get a HPD irq from DP and a HPD irq from non-DP
1809 * the non-DP HPD could block the workqueue on a mode config
1811 * userspace is waiting on the DP workqueue to run which is
1812 * blocked behind the non-DP one.
|
| H A D | i915_reg.h | 720 * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
742 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
746 * for each channel. This is used for DP AUX communication, but
786 * | DDI0 | DDI1 | DP/HDMI ports
798 * | DDI2 | DP/HDMI port
2547 /* embedded DP port on the north display block, reserved on ivb */
2554 /* with DP port the pipe source is invalid */
2562 /* with DP/TV port the pipe source is invalid */
2840 * HDMI/DP bits are gen4+
2849 /* VLV DP/HDMI bits again match Bspec */
3873 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
3901 * (the DP spec calls pixel_clock the 'strm_clk')
|
| H A D | intel_bios.h | 750 /* define the PORT for DP output type */
|
| H A D | i915_debugfs.c | 2903 seq_puts(m, "DP:\n"); drrs_status_per_crtc()
3192 "DP-B",
3193 "DP-C",
3194 "DP-D",
3282 WARN(1, "nonexisting DP port %c\n", for_each_intel_encoder()
|
| H A D | intel_display.c | 1515 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", assert_pch_dp_disabled()
1571 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), intel_init_dpio()
1572 * CHV x1 PHY (DP/HDMI D) intel_init_dpio()
1573 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) intel_init_dpio()
3982 * - DP transcoding bits
4036 /* For PCH DP, enable TRANS_DP_CTL */ ironlake_pch_enable()
10395 /* Fall back to 18 bpp when DP sink capability is unknown. */ connected_sink_compute_bpp()
11410 * type. For DP ports it behaves like most other platforms, but on HDMI update_scanline_offset()
13110 * (no way to plug in a DP->HDMI dongle) the DDC pins for intel_setup_outputs()
|
| H A D | intel_hdmi.c | 388 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
|
| H A D | intel_runtime_pm.c | 1463 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
|
| H A D | i915_irq.c | 3161 * Enable digital hotplug on the PCH, and configure the DP short pulse ibx_hpd_irq_setup()
4032 /* Note HDMI and DP share hotplug bits */ i915_hpd_irq_setup()
|
| /linux-4.1.27/net/sched/ |
| H A D | sch_gred.c | 37 u32 DP; /* the drop parameters */ member in struct:gred_sched_data
164 /* Pass through packets not assigned to a DP gred_enqueue()
165 * if no default DP has been configured. This gred_enqueue()
166 * allows for DP flows to be left untouched. gred_enqueue()
356 * and the DP is checked against DPs, i.e. shadowed VQs can no gred_change_table_def()
398 q->DP = dp; gred_change_vq()
449 if (ctl->DP >= table->DPs) gred_change()
459 printk(KERN_DEBUG "GRED: DP %u does not have a prio " gred_change()
460 "setting default to %d\n", ctl->DP, def_prio); gred_change()
470 err = gred_change_vq(sch, ctl->DP, ctl, prio, stab, max_P, &prealloc); gred_change()
548 at this DP */ gred_dump()
550 opt.DP = MAX_DPs + i; gred_dump()
555 opt.DP = q->DP; gred_dump()
|
| /linux-4.1.27/drivers/gpu/drm/imx/ |
| H A D | ipuv3-plane.h | 39 /* Init IDMAC, DMFC, DP */
|
| H A D | ipuv3-plane.c | 2 * i.MX IPUv3 DP Overlay Planes
|
| H A D | ipuv3-crtc.c | 380 /* If this crtc is using the DP, add an overlay plane */ ipu_crtc_init()
|
| /linux-4.1.27/drivers/net/wan/ |
| H A D | sbni.h | 10 #define DP( A ) A macro
12 #define DP( A ) macro
|
| /linux-4.1.27/drivers/gpu/drm/radeon/ |
| H A D | atombios_crtc.c | 986 /* DP/eDP */ atombios_crtc_prepare_pll()
1010 /* disable spread spectrum on DCE3 DP */ atombios_crtc_prepare_pll()
1731 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1736 * also in DP mode. For DP, a single PPLL can be used for all DP
1751 /* for DP use the same PLL for all */ radeon_get_shared_dp_ppll()
1760 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1765 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1793 /* for non-DP check the clock */ radeon_get_shared_nondp_ppll()
1810 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1811 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1813 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1822 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1824 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1827 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1828 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1831 * - PPLL0 is available to all UNIPHY (DP only)
1832 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1835 * - DCPLL is available to all UNIPHY (DP only)
1836 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1839 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1858 /* use the same PPLL for all DP monitors */ radeon_atom_pick_pll()
1906 /* use the same PPLL for all DP monitors */ radeon_atom_pick_pll()
1940 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, radeon_atom_pick_pll()
1947 * PPLL/DCPLL programming and only program the DP DTO for the radeon_atom_pick_pll()
1955 /* use PPLL0 for all DP */ radeon_atom_pick_pll()
1958 /* use DCPLL for all DP */ radeon_atom_pick_pll()
1961 /* use the same PPLL for all DP monitors */ radeon_atom_pick_pll()
2097 /* if we can't get a PPLL for a non-DP encoder, fail */ atombios_crtc_mode_fixup()
|
| H A D | dce6_afmt.c | 173 /* set DP mode */ dce6_afmt_dp_write_speaker_allocation()
271 /* Two dtos; generally use dto1 for DP */ dce6_dp_audio_set_dto()
|
| H A D | radeon_connectors.c | 78 /* just deal with DP (not eDP) here. */ radeon_connector_hotplug()
83 /* if existing sink type was not DP no need to retrain */ radeon_connector_hotplug()
1676 /* eDP is always DP */ radeon_dp_detect()
1688 /* DP bridges are always DP */ radeon_dp_detect()
1724 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ radeon_dp_detect()
1929 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); radeon_add_atom_connector()
2192 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); radeon_add_atom_connector()
2226 /* in theory with a DP to VGA converter... */ radeon_add_atom_connector()
2242 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); radeon_add_atom_connector()
|
| H A D | atombios.h | 704 // =0: DP encoder
773 // =0: DP encoder
849 // =0: DP encoder
854 // =5: DP audio
856 // =0: external DP
858 // =0x11: internal DP1 for NutMeg/Travis DP translator
861 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
908 // =0: DP encoder
913 // =5: DP audio
915 // =0: external DP
917 // =0x11: internal DP1 for NutMeg/Travis DP translator
920 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
954 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1029 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1042 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1082 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1121 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1216 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version
1273 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio
1367 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
1371 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
1761 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1775 #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS
2685 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2724 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
3652 #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
3653 #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
3729 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
4091 //for DP connector, eDP, DP to VGA/LVDS
4092 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4093 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4094 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4095 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
5103 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
5104 =1: DP mode use single PLL mode
5498 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
5529 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
7154 UCHAR ucConfig; // for DP training command
7299 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
7300 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
7301 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
7308 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
7309 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
7310 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
|
| H A D | atombios_dp.c | 252 /***** general DP utility functions *****/
304 /***** radeon specific DP functions *****/
431 /* DP bridge chips */ radeon_dp_get_panel_mode()
|
| H A D | evergreen_hdmi.c | 146 /* set DP mode */ dce4_afmt_dp_write_speaker_allocation()
279 /* Two dtos; generally use dto1 for DP */ dce4_dp_audio_set_dto()
|
| H A D | dce3_1_afmt.c | 57 /* set DP mode */ dce3_2_afmt_dp_write_speaker_allocation()
|
| H A D | atombios_encoders.c | 688 /* dp bridges are always DP */ atombios_get_encoder_mode()
826 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
1213 * DP PHY should be clocked from external src if there is atombios_dig_transmitter_setup2()
1216 /* On DCE4, if there is an external clock, it generates the DP ref clock */ atombios_dig_transmitter_setup2()
1235 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ atombios_dig_transmitter_setup2()
1272 * DP PHY should be clocked from external src if there is atombios_dig_transmitter_setup2()
1275 /* On DCE5 DCPLL usually generates the DP ref clock */ atombios_dig_transmitter_setup2()
1297 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ atombios_dig_transmitter_setup2()
1350 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ atombios_dig_transmitter_setup2()
|
| H A D | radeon_atombios.c | 1265 /* set a reasonable default for DP */ radeon_atom_get_clock_info()
|
| /linux-4.1.27/arch/m68k/68360/ |
| H A D | commproc.c | 18 * communication processor, and uses some of the DP ram for this
22 * applications that require more DP ram, we can expand the boundaries
51 static uint dp_alloc_base; /* Starting offset in DP ram */
100 /* Claim the DP memory for our use. m360_cpm_reset()
|
| /linux-4.1.27/drivers/power/ |
| H A D | isp1704_charger.c | 125 /* Enable strong pull-up on DP (1.5K) and reset */ isp1704_charger_type()
160 /* Clear the DP and DM pull-down bits */ isp1704_charger_verify()
164 /* Enable strong pull-up on DP (1.5K) and reset */ isp1704_charger_verify()
171 /* Disable strong pull-up on DP (1.5K) */ isp1704_charger_verify()
179 /* Enable weak pull-up resistor on DP */ isp1704_charger_verify()
183 /* Disable strong pull-up on DP (1.5K) */ isp1704_charger_verify()
195 /* Disable weak pull-up resistor on DP */ isp1704_charger_verify()
|
| /linux-4.1.27/include/drm/ |
| H A D | drm_dp_helper.h | 31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
32 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
40 * MST: Multistream Transport - part of DP 1.2a
202 * DP interop v1.1a only VGA defines additional detail.
529 /* DP 1.2 Sideband message defines */
530 /* peer device type - DP 1.2a Table 2-92 */
537 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
554 /* DP 1.2 MST sideband nak reasons - table 2.84 */
|
| H A D | drm_dp_mst_helper.h | 49 * @mcs: message capability status - DP 1.2 spec.
50 * @ddps: DisplayPort Device Plug Status - DP 1.2
90 struct edid *cached_edid; /* for DP logical ports - make tiling work */
106 * @guid: guid for DP 1.2 branch device. port under this branch can be
401 * @aux: aux channel for the DP connector.
413 * There should be one instance of this for every MST capable DP connector
|
| H A D | drm_crtc.h | 633 * @path_blob_ptr: DRM blob property data for the DP MST path property
|
| /linux-4.1.27/sound/pci/hda/ |
| H A D | patch_hdmi.c | 1100 * the user switches between HDMI/DP monitors. hdmi_pin_setup_infoframe()
2078 char hdmi_str[32] = "HDMI/DP"; generic_hdmi_build_jack()
2272 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
3312 { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
3313 { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
3315 { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
3316 { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
3317 { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
3318 { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
3319 { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
3320 { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
3321 { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
3322 { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
3324 { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
3325 { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
3326 { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
3327 { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
3328 { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
3330 { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
3331 { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
3332 { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
3333 { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
3334 { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
3335 { .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
3336 { .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
3338 { .id = 0x10de0070, .name = "GPU 70 HDMI/DP", .patch = patch_nvhdmi },
3339 { .id = 0x10de0071, .name = "GPU 71 HDMI/DP", .patch = patch_nvhdmi },
3340 { .id = 0x10de0072, .name = "GPU 72 HDMI/DP", .patch = patch_nvhdmi },
3341 { .id = 0x10de007d, .name = "GPU 7d HDMI/DP", .patch = patch_nvhdmi },
3342 { .id = 0x10de0082, .name = "GPU 82 HDMI/DP", .patch = patch_nvhdmi },
3343 { .id = 0x10de0083, .name = "GPU 83 HDMI/DP", .patch = patch_nvhdmi },
3345 { .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3346 { .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3347 { .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3348 { .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
|
| H A D | hda_bind.c | 177 /* if all audio out widgets are digital, let's assume the codec as a HDMI/DP */ is_likely_hdmi_codec()
|
| H A D | hda_proc.c | 304 snd_iprintf(buffer, " DP"); print_pin_caps()
|
| H A D | hda_intel.c | 1902 /* if the controller is bound only with HDMI/DP azx_probe_continue()
|
| /linux-4.1.27/drivers/gpu/drm/ |
| H A D | drm_dp_helper.c | 37 * levels to deal with Display Port sink devices and related things like DP aux
38 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
42 /* Helpers for DP link training */ dp_link_status()
346 * According to the DP 1.1 specification, a "Sink Device must exit the drm_dp_link_power_up()
439 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device drm_dp_i2c_do_msg()
473 * more careful with DP-to-legacy adapters where a drm_dp_i2c_do_msg()
545 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
552 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
|
| H A D | drm_edid.c | 3102 * @connector: connector corresponding to the HDMI/DP sink
3304 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3305 * @connector: connector associated with the HDMI/DP sink
3308 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3326 * HDMI/DP sink doesn't support audio or video? drm_av_sync_delay()
3345 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3349 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3350 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
3352 * Return: The connector associated with the first HDMI/DP sink that has ELD
|
| H A D | drm_dp_mst_topology.c | 2005 * into a DP MST capable port, or when a DP MST capable device is unplugged.
2883 * @aux: DP helper aux channel to talk to this device
|
| H A D | drm_crtc.c | 164 { DRM_MODE_CONNECTOR_DisplayPort, "DP" },
181 { DRM_MODE_ENCODER_DPMST, "DP MST" },
1852 /* mode_config.mutex protects the connector list against e.g. DP MST drm_mode_getresources()
|
| /linux-4.1.27/arch/cris/arch-v10/kernel/ |
| H A D | fasttimer.c | 43 #define DP(x) macro
672 DP(
721 DP(proc_fasttimer_read(buf0, NULL, 0, 0, 0)); fast_timer_test()
724 DP(proc_fasttimer_read(buf1, NULL, 0, 0, 0)); fast_timer_test()
727 DP(proc_fasttimer_read(buf2, NULL, 0, 0, 0)); fast_timer_test()
730 DP(proc_fasttimer_read(buf3, NULL, 0, 0, 0)); fast_timer_test()
733 DP(proc_fasttimer_read(buf4, NULL, 0, 0, 0)); fast_timer_test()
754 DP(printk("buf0:\n"); fast_timer_test()
|
| /linux-4.1.27/arch/cris/arch-v32/kernel/ |
| H A D | fasttimer.c | 50 #define DP(x) macro
645 DP(
694 DP(proc_fasttimer_read(buf0, NULL, 0, 0, 0)); fast_timer_test()
697 DP(proc_fasttimer_read(buf1, NULL, 0, 0, 0)); fast_timer_test()
700 DP(proc_fasttimer_read(buf2, NULL, 0, 0, 0)); fast_timer_test()
703 DP(proc_fasttimer_read(buf3, NULL, 0, 0, 0)); fast_timer_test()
706 DP(proc_fasttimer_read(buf4, NULL, 0, 0, 0)); fast_timer_test()
725 DP(printk("buf0:\n"); fast_timer_test()
|
| /linux-4.1.27/arch/c6x/include/asm/ |
| H A D | elf.h | 59 /* Nothing for now. Need to setup DP... */
|
| H A D | processor.h | 104 * saved kernel SP and DP of a blocked thread.
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/ |
| H A D | nv50.c | 84 * we need to avoid killing off the TMDS function on DP connectors mxm_match_dcb()
148 * common example is DP->eDP. mxm_dcb_sanitise_entry()
166 case 0x07: /* DP internal, wtf is this?? HP8670w */ mxm_dcb_sanitise_entry()
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| /linux-4.1.27/drivers/block/ |
| H A D | floppy.c | 303 #define DP (&drive_params[current_drive]) macro
627 if (DP->flags & DEBUGT) debugt()
823 if (DP->select_delay) twaddle()
942 if (DP->select_delay) scandrives()
1001 debug_dcl(DP->flags, "calling disk change from watchdog\n"); fd_watchdog()
1302 srt = 16 - DIV_ROUND_UP(DP->srt * scale_dtr / 1000, NOMINAL_DTR); fdc_specify()
1309 hlt = DIV_ROUND_UP(DP->hlt * scale_dtr / 2, NOMINAL_DTR); fdc_specify()
1315 hut = DIV_ROUND_UP(DP->hut * scale_dtr / 16, NOMINAL_DTR); fdc_specify()
1422 if (DP->flags & FTD_MSG) interpret_errors()
1425 } else if (*errors >= DP->max_errors.reporting) { interpret_errors()
1464 ready_date = DRS->spinup_date + DP->spinup; setup_rw_floppy()
1469 if (time_after(ready_date, jiffies + DP->select_delay)) { setup_rw_floppy()
1470 ready_date -= DP->select_delay; setup_rw_floppy()
1523 debug_dcl(DP->flags, seek_interrupt()
1525 debug_dcl(DP->flags, "jiffies=%lu\n", jiffies); seek_interrupt()
1546 debug_dcl(DP->flags, check_wp()
1548 debug_dcl(DP->flags, "wp=%x\n", ST3 & 0x40); check_wp()
1562 debug_dcl(DP->flags, "calling disk change from %s\n", __func__); seek_floppy()
1586 if (DP->flags & FD_SILENT_DCL_CLEAR) { seek_floppy()
1638 debug_dcl(DP->flags, recal_interrupt()
1879 return fd_wait_for_completion(DRS->select_date + DP->select_delay, start_motor()
1894 debug_dcl(DP->flags, "calling disk change from floppy_ready\n"); floppy_ready()
1896 disk_change(current_drive) && !DP->select_delay) floppy_ready()
1925 debug_dcl(DP->flags, "setting NEWCHANGE in floppy_start\n"); floppy_start()
2027 if (probed_format >= 8 || !DP->autodetect[probed_format]) { next_valid_format()
2031 if (floppy_type[DP->autodetect[probed_format]].sect) { next_valid_format()
2050 if (err_count > DP->max_errors.abort) bad_flp_intr()
2052 if (err_count > DP->max_errors.reset) bad_flp_intr()
2054 else if (err_count > DP->max_errors.recal) bad_flp_intr()
2181 _floppy->track > DP->tracks || do_format()
2345 if (DP->flags & FTD_MSG) rw_interrupt()
2675 *errors < DP->max_errors.read_track && make_raw_rw_request()
2677 (DP->read_track & (1 << DRS->probed_format)))))) { make_raw_rw_request()
2866 _floppy = floppy_type + DP->autodetect[DRS->probed_format]; redo_fd_request()
2936 debug_dcl(DP->flags, "setting NEWCHANGE in poll_drive\n"); poll_drive()
3207 debug_dcl(DP->flags, "calling disk change from raw_cmd ioctl\n"); raw_cmd_ioctl()
4021 DP->cmos = ints[2]; set_cmos()
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| /linux-4.1.27/drivers/gpu/drm/tegra/ |
| H A D | sor.c | 975 dev_err(sor->dev, "failed to enable DP: %d\n", err); tegra_sor_encoder_mode_set()
1094 /* switch to DP clock */ tegra_sor_encoder_mode_set()
1097 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err); tegra_sor_encoder_mode_set()
1099 /* power DP lanes */ tegra_sor_encoder_mode_set()
1250 dev_err(sor->dev, "DP fast link training failed: %d\n", tegra_sor_encoder_mode_set()
1265 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete tegra_sor_encoder_mode_set()
1413 dev_err(sor->dev, "failed to disable DP: %d\n", err); tegra_sor_encoder_disable()
1510 dev_err(sor->dev, "failed to attach DP: %d\n", err); tegra_sor_init()
1560 dev_err(sor->dev, "failed to detach DP: %d\n", err); tegra_sor_exit()
|
| H A D | dpaux.c | 113 /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */ tegra_dpaux_transfer()
|
| /linux-4.1.27/drivers/tty/serial/cpm_uart/ |
| H A D | cpm_uart_cpm1.c | 70 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
|
| H A D | cpm_uart_cpm2.c | 105 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
|
| /linux-4.1.27/drivers/sbus/char/ |
| H A D | display7seg.c | 64 * | DP | ALARM | FLIP | 4 | 3 | 2 | 1 | 0 |
67 * DP - Toggles decimal point on/off
|
| /linux-4.1.27/drivers/gpu/drm/exynos/ |
| H A D | exynos_dp_core.c | 2 * Samsung SoC DP (Display Port) interface driver.
646 * For DP rev.1.1, Maximum link rate of Main Link lanes exynos_dp_get_max_rx_bandwidth()
659 * For DP rev.1.1, Maximum number of Main Link lanes exynos_dp_get_max_rx_lane_count()
672 * the DP inter pair skew issue for at least 10 us exynos_dp_init_training()
699 /* All DP analog module power up */ exynos_dp_init_training()
1028 /* Pre-empt DP connector creation if there's a bridge */ exynos_dp_create_connector()
1232 dev_err(dp->dev, "no DP phy configured\n"); exynos_dp_bind()
1424 MODULE_DESCRIPTION("Samsung SoC DP Driver");
|
| H A D | exynos_dp_core.h | 2 * Header file for Samsung DP (Display Port) interface driver.
|
| H A D | exynos_dp_reg.h | 2 * Register definition file for Samsung DP driver
|
| H A D | exynos_dp_reg.c | 2 * Samsung DP (Display port) register interface driver.
|
| H A D | exynos_drm_fimd.c | 955 * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE fimd_dp_clock_enable()
|
| /linux-4.1.27/arch/c6x/kernel/ |
| H A D | entry.S | 21 #define DP B14 define
62 [B0] STDW .D2T2 SP:DP,*--B1[1] ; user: save user sp/dp kstack
64 ||[!B0] STDW .D2T2 SP:DP,*--SP[1] ; kernel: save on current stack
184 LDDW .D2T2 *+SP[1],SP:DP
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| /linux-4.1.27/arch/cris/arch-v10/drivers/ |
| H A D | gpio.c | 36 #define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0)
38 #define DP(x) macro
180 DP(printk("gpio_poll ready: mask 0x%08X\n", mask)); gpio_poll()
202 DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor)); etrax_gpio_wake_up_check()
|
| /linux-4.1.27/arch/cris/arch-v32/drivers/mach-fs/ |
| H A D | gpio.c | 56 #define DP(x) \
63 #define DP(x) macro
251 DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask)); gpio_poll()
277 DP(printk(KERN_DEBUG etrax_gpio_wake_up_check()
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| /linux-4.1.27/drivers/input/joystick/ |
| H A D | sidewinder.c | 539 * sw_3dp_id() translates the 3DP id into a human legible string.
567 * behavior for 3DP ID packet, and for example the FSP does this in
635 m |= sw_guess_mode(idbuf, j); /* ID packet should carry mode info [3DP] */ sw_connect()
|
| /linux-4.1.27/drivers/thunderbolt/ |
| H A D | switch.c | 33 return "DP/HDMI"; tb_port_type()
205 /* TODO: Read dual link port, DP port and more from EEPROM. */ tb_init_port()
|
| /linux-4.1.27/drivers/gpu/drm/bridge/ |
| H A D | ptn3460.c | 2 * NXP PTN3460 DP/LVDS bridge driver
|
| /linux-4.1.27/include/uapi/linux/ |
| H A D | mtio.h | 109 and SCSI emulated (DI, DP, USB) */
|
| H A D | pkt_sched.h | 280 __u32 DP; /* up to 2^32 DPs */ member in struct:tc_gred_qopt
|
| /linux-4.1.27/arch/powerpc/sysdev/ |
| H A D | cpm2.c | 69 /* Reclaim the DP memory for our use. cpm2_reset()
|
| H A D | cpm1.c | 16 * communication processor, and uses some of the DP ram for this
20 * applications that require more DP ram, we can expand the boundaries
|
| /linux-4.1.27/arch/arc/include/asm/ |
| H A D | arcregs.h | 263 /* ARCompact: Both SP and DP FPU BCRs have same format */
|
| /linux-4.1.27/lib/mpi/ |
| H A D | mpih-div.c | 40 /* Divide num (NP/NSIZE) by den (DP/DSIZE) and write
|
| /linux-4.1.27/arch/powerpc/include/asm/ |
| H A D | cpm1.h | 13 * bytes of the DP RAM and relocates the I2C parameter area to the
14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
|
| /linux-4.1.27/drivers/scsi/sym53c8xx_2/ |
| H A D | sym_fw2.h | 741 * Keep track we received a SAVE DP, so
743 * on the next PM since the DP may point
1628 * If we received a SAVE DP, switch to the
1669 * we received a SAVE DP.
|
| H A D | sym_fw1.h | 767 * Keep track we received a SAVE DP, so
769 * on the next PM since the DP may point
|
| H A D | sym_hipd.c | 4586 * WIDE RESIDUE messages are aliased as MODIFY DP (-1). sym_int_sir()
|
| /linux-4.1.27/arch/cris/arch-v32/drivers/mach-a3/ |
| H A D | gpio.c | 58 #define DP(x) \
65 #define DP(x) macro
252 DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask)); gpio_poll()
|
| /linux-4.1.27/arch/m68k/include/asm/ |
| H A D | commproc.h | 13 * bytes of the DP RAM and relocates the I2C parameter area to the
14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
57 * DP RAM aboard the 360 board - see the MC68360UM p.3-3 */
|
| /linux-4.1.27/drivers/target/ |
| H A D | target_core_spc.c | 603 * The PAGE LENGTH field is defined in SPC-4. If the DP bit is set to spc_emulate_evpd_b2()
604 * zero, then the page length shall be set to 0004h. If the DP bit spc_emulate_evpd_b2()
611 * Set Hardcoded length mentioned above for DP=0 spc_emulate_evpd_b2()
|
| /linux-4.1.27/arch/blackfin/mach-bf548/include/mach/ |
| H A D | anomaly.h | 212 /* USB DP/DM Data Pins May Lose State When Entering Hibernate */
|
| /linux-4.1.27/arch/arc/kernel/ |
| H A D | setup.c | 227 IS_AVAIL1(cpu->extn.fpu_dp, "DP ")); arc_extn_mumbojumbo()
|
| /linux-4.1.27/drivers/net/ethernet/sun/ |
| H A D | sunbmac.c | 58 #define DP(x) printk x macro
60 #define DP(x) macro
|
| /linux-4.1.27/drivers/usb/serial/ |
| H A D | cp210x.c | 53 { USB_DEVICE(0x0489, 0xE000) }, /* Pirelli Broadband S.p.A, DP-L10 SIP/GSM Mobile */
54 { USB_DEVICE(0x0489, 0xE003) }, /* Pirelli Broadband S.p.A, DP-L10 SIP/GSM Mobile */
|
| /linux-4.1.27/drivers/pinctrl/ |
| H A D | pinctrl-tegra210.c | 1461 PINGROUP(hdmi_int_dp_hpd_pcc1, DP, RSVD1, RSVD2, RSVD3, 0x319c, N, N, Y, 0xa28, 12, 5, 20, 5, -1, -1, -1, -1),
1466 PINGROUP(dp_hpd0_pcc6, DP, RSVD1, RSVD2, RSVD3, 0x31b0, N, N, N, 0x99c, 12, 5, 20, 5, -1, -1, -1, -1),
|
| H A D | pinctrl-tegra124.c | 2000 PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, 0x3430, N, N, N),
|
| /linux-4.1.27/drivers/i2c/busses/ |
| H A D | i2c-cpm.c | 519 * descriptors in the DP ram. cpm_i2c_setup()
|
| /linux-4.1.27/arch/parisc/mm/ |
| H A D | init.c | 737 into not treating it as DP-relative data. */ gateway_init()
|
| /linux-4.1.27/arch/ia64/kernel/ |
| H A D | palinfo.c | 500 "DP system processor",
|
| /linux-4.1.27/drivers/usb/phy/ |
| H A D | phy-msm-usb.c | 865 * Configure DM as current source, DP as current sink msm_chg_enable_secondary_det()
912 * Configure DP as current source, DM as current sink msm_chg_enable_primary_det()
|
| /linux-4.1.27/drivers/net/wan/lmc/ |
| H A D | lmc_main.c | 522 * DP: 0 (active) lmc_ioctl()
542 * DP: Input lmc_ioctl()
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| H A D | nv50.c | 1607 * seen, switching from DP to TMDS on a DP connector may result nv50_disp_intr_unk20_0()
|
| /linux-4.1.27/drivers/net/ethernet/3com/ |
| H A D | 3c574_cs.c | 65 http://www.national.com/opf/DP/DP83840A.html
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/ |
| H A D | nouveau_connector.c | 773 * DP requires this before mode_valid() is called. nouveau_connector_get_modes()
|
| /linux-4.1.27/arch/powerpc/xmon/ |
| H A D | spu-insns.h | 111 FPD DP floating pipeline
|
| /linux-4.1.27/drivers/net/ethernet/smsc/ |
| H A D | epic100.c | 137 http://www.national.com/pf/DP/DP83840A.html
|
| /linux-4.1.27/drivers/usb/class/ |
| H A D | usblp.c | 103 MFG:HEWLETT-PACKARD;MDL:DESKJET 970C;CMD:MLC,PCL,PML;CLASS:PRINTER;DESCRIPTION:Hewlett-Packard DeskJet 970C;SERN:US970CSEPROF;VSTATUS:$HB0$NC0,ff,DN,IDLE,CUT,K1,C0,DP,NR,KP000,CP027;VP:0800,FL,B0;VJ: ;
|
| /linux-4.1.27/drivers/usb/host/ |
| H A D | max3421-hcd.c | 1344 * enable pull-down registers on DM/DP: max3421_reset_hcd()
|
| /linux-4.1.27/sound/soc/sh/ |
| H A D | fsi.c | 1459 * ex) if 256 words of DP-RAM is connected fsi_fifo_init()
|
| /linux-4.1.27/drivers/usb/gadget/udc/ |
| H A D | atmel_usba_udc.c | 1799 /* This will also disable the DP pullup */ usba_stop()
|
| /linux-4.1.27/drivers/net/ethernet/hp/ |
| H A D | hp100.c | 50 ** - added KTI DP-200 EISA ID
|
| /linux-4.1.27/drivers/net/ethernet/natsemi/ |
| H A D | natsemi.c | 214 http://www.national.com/pf/DP/DP83815.html
|
| /linux-4.1.27/drivers/net/ethernet/realtek/ |
| H A D | r8169.c | 2324 /* 8168DP family. */ rtl8169_get_mac_version()
|