Searched refs:regval (Results 1 - 170 of 170) sorted by relevance

/linux-4.1.27/arch/arm/mach-w90x900/
H A Dgpio.c58 unsigned int regval; nuc900_gpio_get() local
60 regval = __raw_readl(pio); nuc900_gpio_get()
61 regval &= GPIO_GPIO(offset); nuc900_gpio_get()
63 return (regval != 0); nuc900_gpio_get()
70 unsigned int regval; nuc900_gpio_set() local
75 regval = __raw_readl(pio); nuc900_gpio_set()
78 regval |= GPIO_GPIO(offset); nuc900_gpio_set()
80 regval &= ~GPIO_GPIO(offset); nuc900_gpio_set()
82 __raw_writel(regval, pio); nuc900_gpio_set()
91 unsigned int regval; nuc900_dir_input() local
96 regval = __raw_readl(pio); nuc900_dir_input()
97 regval &= ~GPIO_GPIO(offset); nuc900_dir_input()
98 __raw_writel(regval, pio); nuc900_dir_input()
110 unsigned int regval; nuc900_dir_output() local
115 regval = __raw_readl(pio); nuc900_dir_output()
116 regval |= GPIO_GPIO(offset); nuc900_dir_output()
117 __raw_writel(regval, pio); nuc900_dir_output()
119 regval = __raw_readl(outreg); nuc900_dir_output()
122 regval |= GPIO_GPIO(offset); nuc900_dir_output()
124 regval &= ~GPIO_GPIO(offset); nuc900_dir_output()
126 __raw_writel(regval, outreg); nuc900_dir_output()
H A Dirq.c85 unsigned long regval; nuc900_group_enable() local
87 regval = __raw_readl(REG_AIC_GEN); nuc900_group_enable()
90 regval |= groupen; nuc900_group_enable()
92 regval &= ~groupen; nuc900_group_enable()
94 __raw_writel(regval, REG_AIC_GEN); nuc900_group_enable()
/linux-4.1.27/drivers/media/pci/cx23885/
H A Dcx23885-417.c284 u32 regval; cx23885_mc417_init() local
289 regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) | cx23885_mc417_init()
292 cx_write(MC417_CTL, regval); cx23885_mc417_init()
295 regval = MC417_MIRDY; cx23885_mc417_init()
296 cx_write(MC417_OEN, regval); cx23885_mc417_init()
299 regval = MC417_MIWR | MC417_MIRD | MC417_MICS; cx23885_mc417_init()
300 cx_write(MC417_RWD, regval); cx23885_mc417_init()
320 u32 regval; mc417_register_write() local
328 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 | mc417_register_write()
330 cx_write(MC417_RWD, regval); mc417_register_write()
333 regval |= MC417_MICS | MC417_MIWR; mc417_register_write()
334 cx_write(MC417_RWD, regval); mc417_register_write()
337 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 | mc417_register_write()
339 cx_write(MC417_RWD, regval); mc417_register_write()
340 regval |= MC417_MICS | MC417_MIWR; mc417_register_write()
341 cx_write(MC417_RWD, regval); mc417_register_write()
344 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 | mc417_register_write()
346 cx_write(MC417_RWD, regval); mc417_register_write()
347 regval |= MC417_MICS | MC417_MIWR; mc417_register_write()
348 cx_write(MC417_RWD, regval); mc417_register_write()
351 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 | mc417_register_write()
353 cx_write(MC417_RWD, regval); mc417_register_write()
354 regval |= MC417_MICS | MC417_MIWR; mc417_register_write()
355 cx_write(MC417_RWD, regval); mc417_register_write()
358 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 | mc417_register_write()
360 cx_write(MC417_RWD, regval); mc417_register_write()
361 regval |= MC417_MICS | MC417_MIWR; mc417_register_write()
362 cx_write(MC417_RWD, regval); mc417_register_write()
365 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 | mc417_register_write()
367 cx_write(MC417_RWD, regval); mc417_register_write()
368 regval |= MC417_MICS | MC417_MIWR; mc417_register_write()
369 cx_write(MC417_RWD, regval); mc417_register_write()
372 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE | mc417_register_write()
374 cx_write(MC417_RWD, regval); mc417_register_write()
375 regval |= MC417_MICS | MC417_MIWR; mc417_register_write()
376 cx_write(MC417_RWD, regval); mc417_register_write()
385 u32 regval; mc417_register_read() local
395 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 | mc417_register_read()
397 cx_write(MC417_RWD, regval); mc417_register_read()
398 regval |= MC417_MICS | MC417_MIWR; mc417_register_read()
399 cx_write(MC417_RWD, regval); mc417_register_read()
402 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 | mc417_register_read()
404 cx_write(MC417_RWD, regval); mc417_register_read()
405 regval |= MC417_MICS | MC417_MIWR; mc417_register_read()
406 cx_write(MC417_RWD, regval); mc417_register_read()
409 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE | mc417_register_read()
411 cx_write(MC417_RWD, regval); mc417_register_read()
412 regval |= MC417_MICS | MC417_MIWR; mc417_register_read()
413 cx_write(MC417_RWD, regval); mc417_register_read()
422 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0; mc417_register_read()
423 cx_write(MC417_RWD, regval); mc417_register_read()
430 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0; mc417_register_read()
431 cx_write(MC417_RWD, regval); mc417_register_read()
438 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; mc417_register_read()
439 cx_write(MC417_RWD, regval); mc417_register_read()
442 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1; mc417_register_read()
443 cx_write(MC417_RWD, regval); mc417_register_read()
444 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1; mc417_register_read()
445 cx_write(MC417_RWD, regval); mc417_register_read()
448 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; mc417_register_read()
449 cx_write(MC417_RWD, regval); mc417_register_read()
452 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2; mc417_register_read()
453 cx_write(MC417_RWD, regval); mc417_register_read()
454 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2; mc417_register_read()
455 cx_write(MC417_RWD, regval); mc417_register_read()
458 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; mc417_register_read()
459 cx_write(MC417_RWD, regval); mc417_register_read()
462 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3; mc417_register_read()
463 cx_write(MC417_RWD, regval); mc417_register_read()
464 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3; mc417_register_read()
465 cx_write(MC417_RWD, regval); mc417_register_read()
468 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; mc417_register_read()
469 cx_write(MC417_RWD, regval); mc417_register_read()
478 u32 regval; mc417_memory_write() local
486 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 | mc417_memory_write()
488 cx_write(MC417_RWD, regval); mc417_memory_write()
491 regval |= MC417_MICS | MC417_MIWR; mc417_memory_write()
492 cx_write(MC417_RWD, regval); mc417_memory_write()
495 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 | mc417_memory_write()
497 cx_write(MC417_RWD, regval); mc417_memory_write()
498 regval |= MC417_MICS | MC417_MIWR; mc417_memory_write()
499 cx_write(MC417_RWD, regval); mc417_memory_write()
502 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 | mc417_memory_write()
504 cx_write(MC417_RWD, regval); mc417_memory_write()
505 regval |= MC417_MICS | MC417_MIWR; mc417_memory_write()
506 cx_write(MC417_RWD, regval); mc417_memory_write()
509 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 | mc417_memory_write()
511 cx_write(MC417_RWD, regval); mc417_memory_write()
512 regval |= MC417_MICS | MC417_MIWR; mc417_memory_write()
513 cx_write(MC417_RWD, regval); mc417_memory_write()
516 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 | mc417_memory_write()
518 cx_write(MC417_RWD, regval); mc417_memory_write()
519 regval |= MC417_MICS | MC417_MIWR; mc417_memory_write()
520 cx_write(MC417_RWD, regval); mc417_memory_write()
523 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 | mc417_memory_write()
525 cx_write(MC417_RWD, regval); mc417_memory_write()
526 regval |= MC417_MICS | MC417_MIWR; mc417_memory_write()
527 cx_write(MC417_RWD, regval); mc417_memory_write()
530 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 | mc417_memory_write()
532 cx_write(MC417_RWD, regval); mc417_memory_write()
533 regval |= MC417_MICS | MC417_MIWR; mc417_memory_write()
534 cx_write(MC417_RWD, regval); mc417_memory_write()
543 u32 regval; mc417_memory_read() local
553 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 | mc417_memory_read()
555 cx_write(MC417_RWD, regval); mc417_memory_read()
556 regval |= MC417_MICS | MC417_MIWR; mc417_memory_read()
557 cx_write(MC417_RWD, regval); mc417_memory_read()
560 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 | mc417_memory_read()
562 cx_write(MC417_RWD, regval); mc417_memory_read()
563 regval |= MC417_MICS | MC417_MIWR; mc417_memory_read()
564 cx_write(MC417_RWD, regval); mc417_memory_read()
567 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 | mc417_memory_read()
569 cx_write(MC417_RWD, regval); mc417_memory_read()
570 regval |= MC417_MICS | MC417_MIWR; mc417_memory_read()
571 cx_write(MC417_RWD, regval); mc417_memory_read()
580 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3; mc417_memory_read()
581 cx_write(MC417_RWD, regval); mc417_memory_read()
584 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3; mc417_memory_read()
585 cx_write(MC417_RWD, regval); mc417_memory_read()
592 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; mc417_memory_read()
593 cx_write(MC417_RWD, regval); mc417_memory_read()
596 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2; mc417_memory_read()
597 cx_write(MC417_RWD, regval); mc417_memory_read()
598 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2; mc417_memory_read()
599 cx_write(MC417_RWD, regval); mc417_memory_read()
602 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; mc417_memory_read()
603 cx_write(MC417_RWD, regval); mc417_memory_read()
606 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1; mc417_memory_read()
607 cx_write(MC417_RWD, regval); mc417_memory_read()
608 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1; mc417_memory_read()
609 cx_write(MC417_RWD, regval); mc417_memory_read()
612 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; mc417_memory_read()
613 cx_write(MC417_RWD, regval); mc417_memory_read()
616 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0; mc417_memory_read()
617 cx_write(MC417_RWD, regval); mc417_memory_read()
618 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0; mc417_memory_read()
619 cx_write(MC417_RWD, regval); mc417_memory_read()
622 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; mc417_memory_read()
623 cx_write(MC417_RWD, regval); mc417_memory_read()
/linux-4.1.27/drivers/rapidio/switches/
H A Dtsi57x.c124 u32 regval; tsi57x_set_domain() local
132 TSI578_SP_MODE_GLBL, &regval); tsi57x_set_domain()
134 regval & ~TSI578_SP_MODE_LUT_512); tsi57x_set_domain()
146 u32 regval; tsi57x_get_domain() local
152 TSI578_GLBL_ROUTE_BASE, &regval); tsi57x_get_domain()
154 *sw_domain = (u8)(regval >> 24); tsi57x_get_domain()
162 u32 regval; tsi57x_em_init() local
171 TSI578_SP_MODE(portnum), &regval); tsi57x_em_init()
174 regval & ~TSI578_SP_MODE_PW_DIS); tsi57x_em_init()
180 &regval); tsi57x_em_init()
184 regval & 0x07120214); tsi57x_em_init()
187 TSI578_SP_INT_STATUS(portnum), &regval); tsi57x_em_init()
190 regval & 0x000700bd); tsi57x_em_init()
194 TSI578_SP_CTL_INDEP(portnum), &regval); tsi57x_em_init()
197 regval | 0x000b0000); tsi57x_em_init()
202 &regval); tsi57x_em_init()
203 if ((regval & RIO_PORT_N_CTL_PWIDTH) == RIO_PORT_N_CTL_PWIDTH_4) tsi57x_em_init()
221 u32 regval; tsi57x_em_handler() local
233 &regval); tsi57x_em_handler()
234 if (!(regval & RIO_PORT_N_CTL_LOCKOUT)) { tsi57x_em_handler()
237 regval | RIO_PORT_N_CTL_LOCKOUT); tsi57x_em_handler()
241 regval); tsi57x_em_handler()
249 &regval); tsi57x_em_handler()
264 &regval); tsi57x_em_handler()
265 if (regval & RIO_PORT_N_MNT_RSP_RVAL) tsi57x_em_handler()
281 TSI578_SP_LUT_PEINF(portnum), &regval); tsi57x_em_handler()
282 regval = (mport->sys_size) ? (regval >> 16) : (regval >> 24); tsi57x_em_handler()
283 route_port = rdev->rswitch->route_table[regval]; tsi57x_em_handler()
285 rio_name(rdev), portnum, regval); tsi57x_em_handler()
287 RIO_GLOBAL_TABLE, regval, route_port); tsi57x_em_handler()
H A Didt_gen2.c203 u32 regval; idtg2_get_domain() local
209 IDT_RIO_DOMAIN, &regval); idtg2_get_domain()
211 *sw_domain = (u8)(regval & 0xff); idtg2_get_domain()
219 u32 regval; idtg2_em_init() local
244 rio_read_config_32(rdev, IDT_DEV_CTRL_1, &regval); idtg2_em_init()
246 regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH); idtg2_em_init()
262 rio_read_config_32(rdev, IDT_PORT_OPS(i), &regval); idtg2_em_init()
264 IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW | idtg2_em_init()
284 rio_read_config_32(rdev, IDT_LANE_CTRL(i), &regval); idtg2_em_init()
286 regval | IDT_LANE_CTRL_GENPW); idtg2_em_init()
303 rio_read_config_32(rdev, IDT_I2C_MCTRL, &regval); idtg2_em_init()
304 rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW); idtg2_em_init()
314 rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, &regval); idtg2_em_init()
316 regval & ~IDT_CFGBLK_ERR_REPORT_GENPW); idtg2_em_init()
328 u32 regval, em_perrdet, em_ltlerrdet; idtg2_em_handler() local
337 IDT_ISLTL_ADDRESS_CAP, &regval); idtg2_em_handler()
341 rio_name(rdev), em_ltlerrdet, regval); idtg2_em_handler()
358 IDT_PORT_ISERR_DET(portnum), &regval); idtg2_em_handler()
361 " errors 0x%x\n", rio_name(rdev), regval); idtg2_em_handler()
377 u32 regval; idtg2_show_errlog() local
379 while (!rio_read_config_32(rdev, IDT_ERR_RD, &regval)) { idtg2_show_errlog()
380 if (!regval) /* 0 = end of log */ idtg2_show_errlog()
383 "%08x\n", regval); idtg2_show_errlog()
H A Didtcps.c109 u32 regval; idtcps_get_domain() local
115 IDTCPS_RIO_DOMAIN, &regval); idtcps_get_domain()
117 *sw_domain = (u8)(regval & 0xff); idtcps_get_domain()
H A Dtsi568.c117 u32 regval; tsi568_em_init() local
125 rio_read_config_32(rdev, TSI568_SP_MODE(portnum), &regval); tsi568_em_init()
127 regval | TSI568_SP_MODE_PW_DIS); tsi568_em_init()
/linux-4.1.27/arch/arm/mach-omap2/
H A Domap_phy_internal.c72 u32 regval; am35x_musb_reset() local
75 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); am35x_musb_reset()
77 regval |= AM35XX_USBOTGSS_SW_RST; am35x_musb_reset()
78 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); am35x_musb_reset()
80 regval &= ~AM35XX_USBOTGSS_SW_RST; am35x_musb_reset()
81 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); am35x_musb_reset()
83 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); am35x_musb_reset()
126 u32 regval; am35x_musb_clear_irq() local
128 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); am35x_musb_clear_irq()
129 regval |= AM35XX_USBOTGSS_INT_CLR; am35x_musb_clear_irq()
130 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); am35x_musb_clear_irq()
131 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); am35x_musb_clear_irq()
H A Dsdram-nokia.c158 static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, set_sdrc_timing_regval() argument
161 static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, set_sdrc_timing_regval()
171 *regval &= ~(mask << st_bit); set_sdrc_timing_regval()
172 *regval |= ticks << st_bit; set_sdrc_timing_regval()
195 static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit, set_sdrc_timing_regval_ps() argument
198 static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit, set_sdrc_timing_regval_ps()
211 ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks, set_sdrc_timing_regval_ps()
214 ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks); set_sdrc_timing_regval_ps()
H A Dclkt_clksel.c340 WARN(!found, "clock: %s: init parent: could not find regval %0x\n", omap2_clksel_find_parent_index()
/linux-4.1.27/drivers/regulator/
H A Dtps6105x-regulator.c63 u8 regval; tps6105x_regulator_is_enabled() local
66 ret = tps6105x_get(tps6105x, TPS6105X_REG_0, &regval); tps6105x_regulator_is_enabled()
69 regval &= TPS6105X_REG0_MODE_MASK; tps6105x_regulator_is_enabled()
70 regval >>= TPS6105X_REG0_MODE_SHIFT; tps6105x_regulator_is_enabled()
72 if (regval == TPS6105X_REG0_MODE_VOLTAGE) tps6105x_regulator_is_enabled()
81 u8 regval; tps6105x_regulator_get_voltage_sel() local
84 ret = tps6105x_get(tps6105x, TPS6105X_REG_0, &regval); tps6105x_regulator_get_voltage_sel()
88 regval &= TPS6105X_REG0_VOLTAGE_MASK; tps6105x_regulator_get_voltage_sel()
89 regval >>= TPS6105X_REG0_VOLTAGE_SHIFT; tps6105x_regulator_get_voltage_sel()
90 return (int) regval; tps6105x_regulator_get_voltage_sel()
H A Dab8500-ext.c63 u8 regval; ab8500_ext_regulator_enable() local
75 regval = info->update_val_hp; ab8500_ext_regulator_enable()
77 regval = info->update_val; ab8500_ext_regulator_enable()
81 info->update_mask, regval); ab8500_ext_regulator_enable()
91 info->update_mask, regval); ab8500_ext_regulator_enable() local
100 u8 regval; ab8500_ext_regulator_disable() local
111 regval = info->update_val_hw; ab8500_ext_regulator_disable()
113 regval = 0; ab8500_ext_regulator_disable()
117 info->update_mask, regval); ab8500_ext_regulator_disable()
127 info->update_mask, regval); ab8500_ext_regulator_disable() local
136 u8 regval; ab8500_ext_regulator_is_enabled() local
144 info->update_bank, info->update_reg, &regval); ab8500_ext_regulator_is_enabled()
154 info->update_mask, regval); ab8500_ext_regulator_is_enabled() local
156 if (((regval & info->update_mask) == info->update_val_lp) || ab8500_ext_regulator_is_enabled()
157 ((regval & info->update_mask) == info->update_val_hp)) ab8500_ext_regulator_is_enabled()
168 u8 regval; ab8500_ext_regulator_set_mode() local
177 regval = info->update_val_hp; ab8500_ext_regulator_set_mode()
180 regval = info->update_val_lp; ab8500_ext_regulator_set_mode()
195 info->update_mask, regval); ab8500_ext_regulator_set_mode()
206 info->update_mask, regval); ab8500_ext_regulator_set_mode() local
209 info->update_val = regval; ab8500_ext_regulator_set_mode()
H A Dab3100.c163 u8 regval; ab3100_enable_regulator() local
166 &regval); ab3100_enable_regulator()
174 if (regval & AB3100_REG_ON_MASK) ab3100_enable_regulator()
177 regval |= AB3100_REG_ON_MASK; ab3100_enable_regulator()
180 regval); ab3100_enable_regulator()
194 u8 regval; ab3100_disable_regulator() local
212 &regval); ab3100_disable_regulator()
218 regval &= ~AB3100_REG_ON_MASK; ab3100_disable_regulator()
220 regval); ab3100_disable_regulator()
226 u8 regval; ab3100_is_enabled_regulator() local
230 &regval); ab3100_is_enabled_regulator()
237 return regval & AB3100_REG_ON_MASK; ab3100_is_enabled_regulator()
243 u8 regval; ab3100_get_voltage_regulator() local
251 abreg->regreg, &regval); ab3100_get_voltage_regulator()
260 regval &= 0xE0; ab3100_get_voltage_regulator()
261 regval >>= 5; ab3100_get_voltage_regulator()
263 if (regval >= reg->desc->n_voltages) { ab3100_get_voltage_regulator()
270 return reg->desc->volt_table[regval]; ab3100_get_voltage_regulator()
277 u8 regval; ab3100_set_voltage_regulator_sel() local
281 abreg->regreg, &regval); ab3100_set_voltage_regulator_sel()
290 regval &= ~0xE0; ab3100_set_voltage_regulator_sel()
291 regval |= (selector << 5); ab3100_set_voltage_regulator_sel()
294 abreg->regreg, regval); ab3100_set_voltage_regulator_sel()
306 u8 regval; ab3100_set_suspend_voltage_regulator() local
322 targetreg, &regval); ab3100_set_suspend_voltage_regulator()
331 regval &= ~0xE0; ab3100_set_suspend_voltage_regulator()
332 regval |= (bestindex << 5); ab3100_set_suspend_voltage_regulator()
335 targetreg, regval); ab3100_set_suspend_voltage_regulator()
H A Dlp8755.c96 unsigned int regval; lp8755_buck_enable_time() local
100 ret = lp8755_read(pchip, 0x12 + id, &regval); lp8755_buck_enable_time()
105 return (regval & 0xff) * 100; lp8755_buck_enable_time()
154 unsigned int regval; lp8755_buck_get_mode() local
158 ret = lp8755_read(pchip, 0x06, &regval); lp8755_buck_get_mode()
163 if (regval & (0x01 << id)) lp8755_buck_get_mode()
166 ret = lp8755_read(pchip, 0x08 + id, &regval); lp8755_buck_get_mode()
171 if (regval & 0x20) lp8755_buck_get_mode()
185 unsigned int regval = 0x00; lp8755_buck_set_ramp() local
192 regval = 0x07; lp8755_buck_set_ramp()
195 regval = 0x06; lp8755_buck_set_ramp()
198 regval = 0x05; lp8755_buck_set_ramp()
201 regval = 0x04; lp8755_buck_set_ramp()
204 regval = 0x03; lp8755_buck_set_ramp()
207 regval = 0x02; lp8755_buck_set_ramp()
210 regval = 0x01; lp8755_buck_set_ramp()
213 regval = 0x00; lp8755_buck_set_ramp()
221 ret = lp8755_update_bits(pchip, 0x07 + id, 0x07, regval); lp8755_buck_set_ramp()
280 unsigned int regval; lp8755_init_data() local
285 ret = lp8755_read(pchip, 0x3D, &regval); lp8755_init_data()
288 pchip->mphase = regval & 0x0F; lp8755_init_data()
414 unsigned int regval; lp8755_int_config() local
421 ret = lp8755_read(pchip, 0x0F, &regval); lp8755_int_config()
424 pchip->irqmask = regval; lp8755_int_config()
H A Dmt6397-regulator.c151 u32 regval; mt6397_get_status() local
154 ret = regmap_read(rdev->regmap, info->desc.enable_reg, &regval); mt6397_get_status()
160 return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; mt6397_get_status()
253 u32 regval; mt6397_set_buck_vosel_reg() local
259 &regval) < 0) { mt6397_set_buck_vosel_reg()
265 if (regval & mt6397_regulators[i].vselctrl_mask) { mt6397_set_buck_vosel_reg()
H A Dfan53555.c164 int regval = -1, i; fan53555_set_ramp() local
168 regval = i; fan53555_set_ramp()
173 if (regval < 0) { fan53555_set_ramp()
179 CTL_SLEW_MASK, regval << CTL_SLEW_SHIFT); fan53555_set_ramp()
H A Dab8500.c296 u8 regval; ab8500_regulator_is_enabled() local
304 info->update_bank, info->update_reg, &regval); ab8500_regulator_is_enabled()
315 info->update_mask, regval); ab8500_regulator_is_enabled() local
317 if (regval & info->update_mask) ab8500_regulator_is_enabled()
483 u8 regval; ab8500_regulator_get_voltage_sel() local
493 info->voltage_bank, info->voltage_reg, &regval); ab8500_regulator_get_voltage_sel()
505 voltage_shift, regval); ab8500_regulator_get_voltage_sel() local
507 return (regval & info->voltage_mask) >> voltage_shift; ab8500_regulator_get_voltage_sel()
514 u8 regval, regval_expand; ab8540_aux3_regulator_get_voltage_sel() local
540 info->voltage_bank, info->voltage_reg, &regval); ab8540_aux3_regulator_get_voltage_sel()
550 info->voltage_mask, regval); ab8540_aux3_regulator_get_voltage_sel() local
554 return (regval & info->voltage_mask) >> voltage_shift; ab8540_aux3_regulator_get_voltage_sel()
562 u8 regval; ab8500_regulator_set_voltage_sel() local
572 regval = (u8)selector << voltage_shift; ab8500_regulator_set_voltage_sel()
575 info->voltage_mask, regval); ab8500_regulator_set_voltage_sel()
584 info->voltage_mask, regval); ab8500_regulator_set_voltage_sel() local
594 u8 regval, regval_expand; ab8540_aux3_regulator_set_voltage_sel() local
604 regval = (u8)selector << voltage_shift; ab8540_aux3_regulator_set_voltage_sel()
607 info->voltage_mask, regval); ab8540_aux3_regulator_set_voltage_sel()
617 info->voltage_mask, regval); ab8540_aux3_regulator_set_voltage_sel() local
/linux-4.1.27/drivers/phy/
H A Dphy-berlin-sata.c71 u32 regval; phy_berlin_sata_reg_setbits() local
77 regval = readl(ctrl_reg + PORT_VSR_DATA); phy_berlin_sata_reg_setbits()
78 regval &= ~mask; phy_berlin_sata_reg_setbits()
79 regval |= val; phy_berlin_sata_reg_setbits()
80 writel(regval, ctrl_reg + PORT_VSR_DATA); phy_berlin_sata_reg_setbits()
89 u32 regval; phy_berlin_sata_power_on() local
97 regval = readl(priv->base + HOST_VSA_DATA); phy_berlin_sata_power_on()
98 regval &= ~desc->power_bit; phy_berlin_sata_power_on()
99 writel(regval, priv->base + HOST_VSA_DATA); phy_berlin_sata_power_on()
103 regval = readl(priv->base + HOST_VSA_DATA); phy_berlin_sata_power_on()
104 regval |= MBUS_WRITE_REQUEST_SIZE_128 | MBUS_READ_REQUEST_SIZE_128; phy_berlin_sata_power_on()
105 writel(regval, priv->base + HOST_VSA_DATA); phy_berlin_sata_power_on()
124 regval = readl(ctrl_reg + PORT_SCR_CTL); phy_berlin_sata_power_on()
125 regval &= ~GENMASK(7, 4); phy_berlin_sata_power_on()
126 regval |= 0x30; phy_berlin_sata_power_on()
127 writel(regval, ctrl_reg + PORT_SCR_CTL); phy_berlin_sata_power_on()
140 u32 regval; phy_berlin_sata_power_off() local
148 regval = readl(priv->base + HOST_VSA_DATA); phy_berlin_sata_power_off()
149 regval |= desc->power_bit; phy_berlin_sata_power_off()
150 writel(regval, priv->base + HOST_VSA_DATA); phy_berlin_sata_power_off()
H A Dphy-miphy365x.c208 u8 regval; miphy365x_hfc_not_rdy() local
211 regval = readb_relaxed(miphy_phy->base + STATUS_REG); miphy365x_hfc_not_rdy()
212 if (!(regval & mask)) miphy365x_hfc_not_rdy()
227 u8 regval; miphy365x_rdy() local
230 regval = readb_relaxed(miphy_phy->base + STATUS_REG); miphy365x_rdy()
231 if ((regval & mask) == mask) miphy365x_rdy()
/linux-4.1.27/drivers/watchdog/
H A Dts72xx_wdt.c44 * @regval: watchdog timeout value suitable for control register
52 int regval; member in struct:ts72xx_wdt
88 int regval; member in struct:__anon10700
113 return ts72xx_wdt_map[i].regval; timeout_to_regval()
121 * @regval: control register value to be converted
123 * Function converts given @regval to timeout in seconds (1, 2, 4 or 8).
124 * If @regval cannot be converted, function returns %-EINVAL.
126 static int regval_to_timeout(int regval) regval_to_timeout() argument
131 if (ts72xx_wdt_map[i].regval == regval) regval_to_timeout()
166 __raw_writeb((u8)wdt->regval, wdt->control_reg); ts72xx_wdt_start()
184 int regval; ts72xx_wdt_open() local
190 regval = timeout_to_regval(timeout); ts72xx_wdt_open()
191 if (regval < 0) { ts72xx_wdt_open()
195 return regval; ts72xx_wdt_open()
207 wdt->regval = regval; ts72xx_wdt_open()
344 int regval; ts72xx_wdt_ioctl() local
350 regval = timeout_to_regval(new_timeout); ts72xx_wdt_ioctl()
351 if (regval < 0) { ts72xx_wdt_ioctl()
352 error = regval; ts72xx_wdt_ioctl()
356 wdt->regval = regval; ts72xx_wdt_ioctl()
363 error = put_user(regval_to_timeout(wdt->regval), p); ts72xx_wdt_ioctl()
H A Dda9063_wdt.c57 static int _da9063_wdt_set_timeout(struct da9063 *da9063, unsigned int regval) _da9063_wdt_set_timeout() argument
60 DA9063_TWDSCALE_MASK, regval); _da9063_wdt_set_timeout()
/linux-4.1.27/arch/mips/loongson/lemote-2f/
H A Dclock.c97 int regval; clk_set_rate() local
118 regval = LOONGSON_CHIPCFG(0); clk_set_rate()
119 regval = (regval & ~0x7) | (pos->driver_data - 1); clk_set_rate()
120 LOONGSON_CHIPCFG(0) = regval; clk_set_rate()
/linux-4.1.27/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.c525 u32 regval; ar9002_hw_antdiv_comb_conf_get() local
527 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); ar9002_hw_antdiv_comb_conf_get()
528 antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >> ar9002_hw_antdiv_comb_conf_get()
530 antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >> ar9002_hw_antdiv_comb_conf_get()
532 antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >> ar9002_hw_antdiv_comb_conf_get()
542 u32 regval; ar9002_hw_antdiv_comb_conf_set() local
544 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); ar9002_hw_antdiv_comb_conf_set()
545 regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF | ar9002_hw_antdiv_comb_conf_set()
548 regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S) ar9002_hw_antdiv_comb_conf_set()
550 regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S) ar9002_hw_antdiv_comb_conf_set()
552 regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S) ar9002_hw_antdiv_comb_conf_set()
555 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); ar9002_hw_antdiv_comb_conf_set()
564 u32 regval; ar9002_hw_set_bt_ant_diversity() local
599 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); ar9002_hw_set_bt_ant_diversity()
600 regval &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); ar9002_hw_set_bt_ant_diversity()
605 regval &= (~(AR_PHY_9285_FAST_DIV_BIAS)); ar9002_hw_set_bt_ant_diversity()
606 regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL); ar9002_hw_set_bt_ant_diversity()
607 regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); ar9002_hw_set_bt_ant_diversity()
608 regval |= SM((antdiv_ctrl2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); ar9002_hw_set_bt_ant_diversity()
609 regval |= SM((antdiv_ctrl1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); ar9002_hw_set_bt_ant_diversity()
610 regval |= SM((antdiv_ctrl1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB); ar9002_hw_set_bt_ant_diversity()
611 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); ar9002_hw_set_bt_ant_diversity()
613 regval = REG_READ(ah, AR_PHY_CCK_DETECT); ar9002_hw_set_bt_ant_diversity()
614 regval &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); ar9002_hw_set_bt_ant_diversity()
615 regval |= SM((antdiv_ctrl1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); ar9002_hw_set_bt_ant_diversity()
616 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); ar9002_hw_set_bt_ant_diversity()
H A Dar9003_phy.c1523 u32 regval; ar9003_hw_antdiv_comb_conf_get() local
1525 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_antdiv_comb_conf_get()
1526 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >> ar9003_hw_antdiv_comb_conf_get()
1528 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >> ar9003_hw_antdiv_comb_conf_get()
1530 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >> ar9003_hw_antdiv_comb_conf_get()
1555 u32 regval; ar9003_hw_antdiv_comb_conf_set() local
1557 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_antdiv_comb_conf_set()
1558 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | ar9003_hw_antdiv_comb_conf_set()
1563 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S) ar9003_hw_antdiv_comb_conf_set()
1565 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S) ar9003_hw_antdiv_comb_conf_set()
1567 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S) ar9003_hw_antdiv_comb_conf_set()
1569 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S) ar9003_hw_antdiv_comb_conf_set()
1571 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S) ar9003_hw_antdiv_comb_conf_set()
1574 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_antdiv_comb_conf_set()
1583 u32 regval; ar9003_hw_set_bt_ant_diversity() local
1589 regval = ar9003_hw_ant_ctrl_common_2_get(ah, ar9003_hw_set_bt_ant_diversity()
1592 regval &= ~AR_SWITCH_TABLE_COM2_ALL; ar9003_hw_set_bt_ant_diversity()
1593 regval |= ah->config.ant_ctrl_comm2g_switch_enable; ar9003_hw_set_bt_ant_diversity()
1596 AR_SWITCH_TABLE_COM2_ALL, regval); ar9003_hw_set_bt_ant_diversity()
1605 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_set_bt_ant_diversity()
1606 regval &= (~AR_ANT_DIV_CTRL_ALL); ar9003_hw_set_bt_ant_diversity()
1607 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S; ar9003_hw_set_bt_ant_diversity()
1608 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_set_bt_ant_diversity()
1614 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_set_bt_ant_diversity()
1615 regval &= ~AR_PHY_ANT_DIV_LNADIV; ar9003_hw_set_bt_ant_diversity()
1616 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S; ar9003_hw_set_bt_ant_diversity()
1618 regval |= AR_ANT_DIV_ENABLE; ar9003_hw_set_bt_ant_diversity()
1620 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_set_bt_ant_diversity()
1625 regval = REG_READ(ah, AR_PHY_CCK_DETECT); ar9003_hw_set_bt_ant_diversity()
1626 regval &= ~AR_FAST_DIV_ENABLE; ar9003_hw_set_bt_ant_diversity()
1627 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S; ar9003_hw_set_bt_ant_diversity()
1629 regval |= AR_FAST_DIV_ENABLE; ar9003_hw_set_bt_ant_diversity()
1631 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); ar9003_hw_set_bt_ant_diversity()
1634 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_set_bt_ant_diversity()
1635 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF | ar9003_hw_set_bt_ant_diversity()
1643 regval |= (ATH_ANT_DIV_COMB_LNA1 << ar9003_hw_set_bt_ant_diversity()
1645 regval |= (ATH_ANT_DIV_COMB_LNA2 << ar9003_hw_set_bt_ant_diversity()
1647 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_set_bt_ant_diversity()
1673 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_set_bt_ant_diversity()
1674 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | ar9003_hw_set_bt_ant_diversity()
1678 regval |= (ATH_ANT_DIV_COMB_LNA1 << ar9003_hw_set_bt_ant_diversity()
1680 regval |= (ATH_ANT_DIV_COMB_LNA2 << ar9003_hw_set_bt_ant_diversity()
1682 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_set_bt_ant_diversity()
H A Dar9003_mci.c853 u32 regval; ar9003_mci_set_btcoex_ctrl_9565_1ANT() local
855 regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) | ar9003_mci_set_btcoex_ctrl_9565_1ANT()
867 REG_WRITE(ah, AR_BTCOEX_CTRL, regval); ar9003_mci_set_btcoex_ctrl_9565_1ANT()
872 u32 regval; ar9003_mci_set_btcoex_ctrl_9565_2ANT() local
874 regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) | ar9003_mci_set_btcoex_ctrl_9565_2ANT()
886 REG_WRITE(ah, AR_BTCOEX_CTRL, regval); ar9003_mci_set_btcoex_ctrl_9565_2ANT()
891 u32 regval; ar9003_mci_set_btcoex_ctrl_9462() local
893 regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) | ar9003_mci_set_btcoex_ctrl_9462()
903 REG_WRITE(ah, AR_BTCOEX_CTRL, regval); ar9003_mci_set_btcoex_ctrl_9462()
911 u32 regval, i; ar9003_mci_reset() local
969 regval = MS(mci->config, ATH_MCI_CONFIG_CLK_DIV); ar9003_mci_reset()
970 REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval); ar9003_mci_reset()
974 regval = REG_READ(ah, AR_MCI_COMMAND2); ar9003_mci_reset()
975 regval |= SM(1, AR_MCI_COMMAND2_RESET_TX); ar9003_mci_reset()
976 REG_WRITE(ah, AR_MCI_COMMAND2, regval); ar9003_mci_reset()
980 regval &= ~SM(1, AR_MCI_COMMAND2_RESET_TX); ar9003_mci_reset()
981 REG_WRITE(ah, AR_MCI_COMMAND2, regval); ar9003_mci_reset()
991 regval |= SM(1, AR_MCI_COMMAND2_RESET_RX); ar9003_mci_reset()
992 REG_WRITE(ah, AR_MCI_COMMAND2, regval); ar9003_mci_reset()
994 regval &= ~SM(1, AR_MCI_COMMAND2_RESET_RX); ar9003_mci_reset()
995 REG_WRITE(ah, AR_MCI_COMMAND2, regval); ar9003_mci_reset()
1162 u32 regval; ar9003_mci_send_message() local
1167 regval = REG_READ(ah, AR_BTCOEX_CTRL); ar9003_mci_send_message()
1169 if ((regval == 0xdeadbeef) || !(regval & AR_BTCOEX_CTRL_MCI_MODE_EN)) { ar9003_mci_send_message()
H A Deeprom_9287.c420 u32 reg32, regOffset, regChainOffset, regval; ath9k_hw_set_ar9287_power_cal_table() local
499 regval = SM(pdGainOverlap_t2, ath9k_hw_set_ar9287_power_cal_table()
512 regval); ath9k_hw_set_ar9287_power_cal_table()
912 u32 regChainOffset, regval; ath9k_hw_ar9287_set_board_values() local
976 regval = REG_READ(ah, AR9287_AN_RF2G3_CH0); ath9k_hw_ar9287_set_board_values()
977 regval &= ~(AR9287_AN_RF2G3_DB1 | ath9k_hw_ar9287_set_board_values()
983 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) | ath9k_hw_ar9287_set_board_values()
990 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval); ath9k_hw_ar9287_set_board_values()
992 regval = REG_READ(ah, AR9287_AN_RF2G3_CH1); ath9k_hw_ar9287_set_board_values()
993 regval &= ~(AR9287_AN_RF2G3_DB1 | ath9k_hw_ar9287_set_board_values()
999 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) | ath9k_hw_ar9287_set_board_values()
1006 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval); ath9k_hw_ar9287_set_board_values()
H A Dar9002_calib.c401 int delta, currPDADC, regval; ar9280_hw_olc_temp_compensation() local
417 regval = ah->originalGain[i] - delta; ar9280_hw_olc_temp_compensation()
418 if (regval < 0) ar9280_hw_olc_temp_compensation()
419 regval = 0; ar9280_hw_olc_temp_compensation()
423 AR_PHY_TX_GAIN, regval); ar9280_hw_olc_temp_compensation()
H A Ddebug.c870 u32 regval; read_file_regval() local
873 regval = REG_READ_D(ah, sc->debug.regidx); read_file_regval()
875 len = sprintf(buf, "0x%08x\n", regval); read_file_regval()
884 unsigned long regval; write_file_regval() local
893 if (kstrtoul(buf, 0, &regval)) write_file_regval()
897 REG_WRITE_D(ah, sc->debug.regidx, regval); write_file_regval()
1355 debugfs_create_file("regval", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy, ath9k_init_debug()
H A Dhw.c821 u32 regval, pll2_divint, pll2_divfrac, refdiv; ath9k_hw_init_pll() local
854 regval = REG_READ(ah, AR_PHY_PLL_MODE); ath9k_hw_init_pll()
856 regval |= (0x1 << 22); ath9k_hw_init_pll()
858 regval |= (0x1 << 16); ath9k_hw_init_pll()
859 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); ath9k_hw_init_pll()
866 regval = REG_READ(ah, AR_PHY_PLL_MODE); ath9k_hw_init_pll()
868 regval = (regval & 0x80071fff) | ath9k_hw_init_pll()
874 regval = (regval & 0x01c00fff) | ath9k_hw_init_pll()
881 regval |= (0x6 << 12); ath9k_hw_init_pll()
883 regval = (regval & 0x80071fff) | ath9k_hw_init_pll()
888 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); ath9k_hw_init_pll()
H A Dar9003_eeprom.c3580 u32 regval, value, gpio; ar9003_hw_ant_ctrl_apply() local
3660 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_ant_ctrl_apply()
3661 regval &= (~AR_ANT_DIV_CTRL_ALL); ar9003_hw_ant_ctrl_apply()
3662 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S; ar9003_hw_ant_ctrl_apply()
3664 regval &= (~AR_PHY_ANT_DIV_LNADIV); ar9003_hw_ant_ctrl_apply()
3665 regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S; ar9003_hw_ant_ctrl_apply()
3668 regval |= AR_ANT_DIV_ENABLE; ar9003_hw_ant_ctrl_apply()
3672 regval |= (1 << AR_PHY_ANT_SW_RX_PROT_S); ar9003_hw_ant_ctrl_apply()
3681 regval &= ~(1 << AR_PHY_ANT_DIV_LNADIV_S); ar9003_hw_ant_ctrl_apply()
3682 regval &= ~(1 << AR_PHY_ANT_SW_RX_PROT_S); ar9003_hw_ant_ctrl_apply()
3693 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_ant_ctrl_apply()
3696 regval = REG_READ(ah, AR_PHY_CCK_DETECT); ar9003_hw_ant_ctrl_apply()
3697 regval &= (~AR_FAST_DIV_ENABLE); ar9003_hw_ant_ctrl_apply()
3698 regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S; ar9003_hw_ant_ctrl_apply()
3702 regval |= AR_FAST_DIV_ENABLE; ar9003_hw_ant_ctrl_apply()
3704 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); ar9003_hw_ant_ctrl_apply()
3707 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_ant_ctrl_apply()
3712 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF | ar9003_hw_ant_ctrl_apply()
3717 regval |= (ATH_ANT_DIV_COMB_LNA1 << ar9003_hw_ant_ctrl_apply()
3719 regval |= (ATH_ANT_DIV_COMB_LNA2 << ar9003_hw_ant_ctrl_apply()
3721 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_ant_ctrl_apply()
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-sirf.c105 u32 regval; i2c_sirfsoc_queue_cmd() local
111 regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0); i2c_sirfsoc_queue_cmd()
114 regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK; i2c_sirfsoc_queue_cmd()
115 writel(regval, i2c_sirfsoc_queue_cmd()
124 regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0); i2c_sirfsoc_queue_cmd()
127 regval |= SIRFSOC_I2C_STOP; i2c_sirfsoc_queue_cmd()
128 writel(regval, i2c_sirfsoc_queue_cmd()
185 u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE; i2c_sirfsoc_set_address() local
189 regval |= SIRFSOC_I2C_STOP; i2c_sirfsoc_set_address()
191 writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); i2c_sirfsoc_set_address()
206 u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL); i2c_sirfsoc_xfer_msg() local
212 writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN, i2c_sirfsoc_xfer_msg()
221 writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN), i2c_sirfsoc_xfer_msg()
285 u32 regval; i2c_sirfsoc_probe() local
362 regval = i2c_sirfsoc_probe()
365 regval = ctrl_speed / (bitrate * 5); i2c_sirfsoc_probe()
367 writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL); i2c_sirfsoc_probe()
368 if (regval > 0xFF) i2c_sirfsoc_probe()
371 writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY); i2c_sirfsoc_probe()
H A Di2c-jz4780.c193 unsigned short regval; jz4780_i2c_disable() local
199 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA); jz4780_i2c_disable()
200 if (!(regval & JZ4780_I2C_ENB_I2C)) jz4780_i2c_disable()
206 dev_err(&i2c->adap.dev, "disable failed: ENSTA=0x%04x\n", regval); jz4780_i2c_disable()
212 unsigned short regval; jz4780_i2c_enable() local
218 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA); jz4780_i2c_enable()
219 if (regval & JZ4780_I2C_ENB_I2C) jz4780_i2c_enable()
225 dev_err(&i2c->adap.dev, "enable failed: ENSTA=0x%04x\n", regval); jz4780_i2c_enable()
231 unsigned short regval; jz4780_i2c_set_target() local
235 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_STA); jz4780_i2c_set_target()
236 if ((regval & JZ4780_I2C_STA_TFE) && jz4780_i2c_set_target()
237 !(regval & JZ4780_I2C_STA_MSTACT)) jz4780_i2c_set_target()
250 address, regval); jz4780_i2c_set_target()
H A Di2c-cadence.c456 u32 regval; cdns_i2c_master_reset() local
461 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); cdns_i2c_master_reset()
462 regval &= ~CDNS_I2C_CR_HOLD; cdns_i2c_master_reset()
463 regval |= CDNS_I2C_CR_CLR_FIFO; cdns_i2c_master_reset()
464 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET); cdns_i2c_master_reset()
468 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); cdns_i2c_master_reset()
469 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET); cdns_i2c_master_reset()
471 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); cdns_i2c_master_reset()
472 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET); cdns_i2c_master_reset()
/linux-4.1.27/drivers/mfd/
H A Dtps6105x.c69 u8 regval; tps6105x_mask_and_set() local
77 regval = ret; tps6105x_mask_and_set()
78 regval = (~bitmask & regval) | (bitmask & bitvalues); tps6105x_mask_and_set()
79 ret = i2c_smbus_write_byte_data(tps6105x->client, reg, regval); tps6105x_mask_and_set()
92 u8 regval; tps6105x_startup() local
94 ret = tps6105x_get(tps6105x, TPS6105X_REG_0, &regval); tps6105x_startup()
97 switch (regval >> TPS6105X_REG0_MODE_SHIFT) { tps6105x_startup()
H A Dasic3.c244 int regval; asic3_mask_irq() local
248 regval = asic3_read_register(asic, asic3_mask_irq()
252 regval &= ~(ASIC3_INTMASK_MASK0 << asic3_mask_irq()
258 regval); asic3_mask_irq()
281 int regval; asic3_unmask_irq() local
285 regval = asic3_read_register(asic, asic3_unmask_irq()
289 regval |= (ASIC3_INTMASK_MASK0 << asic3_unmask_irq()
295 regval); asic3_unmask_irq()
H A Dab3100-core.c73 u8 reg, u8 regval) ab3100_set_register_interruptible()
75 u8 regandval[2] = {reg, regval}; ab3100_set_register_interruptible()
122 u8 reg, u8 regval) ab3100_set_test_register_interruptible()
124 u8 regandval[2] = {reg, regval}; ab3100_set_test_register_interruptible()
152 u8 reg, u8 *regval) ab3100_get_register_interruptible()
184 err = i2c_master_recv(ab3100->i2c_client, regval, 1); ab3100_get_register_interruptible()
72 ab3100_set_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval) ab3100_set_register_interruptible() argument
121 ab3100_set_test_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval) ab3100_set_test_register_interruptible() argument
151 ab3100_get_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 *regval) ab3100_get_register_interruptible() argument
/linux-4.1.27/sound/soc/qcom/
H A Dlpass-cpu.c88 unsigned int regval; lpass_cpu_daiops_hw_params() local
98 regval = LPAIF_I2SCTL_LOOPBACK_DISABLE | lpass_cpu_daiops_hw_params()
103 regval |= LPAIF_I2SCTL_BITWIDTH_16; lpass_cpu_daiops_hw_params()
106 regval |= LPAIF_I2SCTL_BITWIDTH_24; lpass_cpu_daiops_hw_params()
109 regval |= LPAIF_I2SCTL_BITWIDTH_32; lpass_cpu_daiops_hw_params()
119 regval |= LPAIF_I2SCTL_SPKMODE_SD0; lpass_cpu_daiops_hw_params()
120 regval |= LPAIF_I2SCTL_SPKMONO_MONO; lpass_cpu_daiops_hw_params()
123 regval |= LPAIF_I2SCTL_SPKMODE_SD0; lpass_cpu_daiops_hw_params()
124 regval |= LPAIF_I2SCTL_SPKMONO_STEREO; lpass_cpu_daiops_hw_params()
127 regval |= LPAIF_I2SCTL_SPKMODE_QUAD01; lpass_cpu_daiops_hw_params()
128 regval |= LPAIF_I2SCTL_SPKMONO_STEREO; lpass_cpu_daiops_hw_params()
131 regval |= LPAIF_I2SCTL_SPKMODE_6CH; lpass_cpu_daiops_hw_params()
132 regval |= LPAIF_I2SCTL_SPKMONO_STEREO; lpass_cpu_daiops_hw_params()
135 regval |= LPAIF_I2SCTL_SPKMODE_8CH; lpass_cpu_daiops_hw_params()
136 regval |= LPAIF_I2SCTL_SPKMONO_STEREO; lpass_cpu_daiops_hw_params()
145 LPAIF_I2SCTL_REG(LPAIF_I2S_PORT_MI2S), regval); lpass_cpu_daiops_hw_params()
H A Dlpass-platform.c91 unsigned int regval; lpass_platform_pcmops_hw_params() local
102 regval = LPAIF_RDMACTL_BURSTEN_INCR4 | lpass_platform_pcmops_hw_params()
111 regval |= LPAIF_RDMACTL_WPSCNT_ONE; lpass_platform_pcmops_hw_params()
114 regval |= LPAIF_RDMACTL_WPSCNT_TWO; lpass_platform_pcmops_hw_params()
117 regval |= LPAIF_RDMACTL_WPSCNT_THREE; lpass_platform_pcmops_hw_params()
120 regval |= LPAIF_RDMACTL_WPSCNT_FOUR; lpass_platform_pcmops_hw_params()
132 regval |= LPAIF_RDMACTL_WPSCNT_ONE; lpass_platform_pcmops_hw_params()
135 regval |= LPAIF_RDMACTL_WPSCNT_TWO; lpass_platform_pcmops_hw_params()
138 regval |= LPAIF_RDMACTL_WPSCNT_FOUR; lpass_platform_pcmops_hw_params()
141 regval |= LPAIF_RDMACTL_WPSCNT_SIX; lpass_platform_pcmops_hw_params()
144 regval |= LPAIF_RDMACTL_WPSCNT_EIGHT; lpass_platform_pcmops_hw_params()
159 LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S), regval); lpass_platform_pcmops_hw_params()
/linux-4.1.27/arch/sparc/include/asm/
H A Dturbosparc.h105 static inline void turbosparc_set_ccreg(unsigned long regval) turbosparc_set_ccreg() argument
109 : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS) turbosparc_set_ccreg()
115 unsigned long regval; turbosparc_get_ccreg() local
118 : "=r" (regval) turbosparc_get_ccreg()
120 return regval; turbosparc_get_ccreg()
H A Dviking.h145 static inline void viking_set_bpreg(unsigned long regval) viking_set_bpreg() argument
149 : "r" (regval), "i" (ASI_M_ACTION) viking_set_bpreg()
155 unsigned long regval; viking_get_bpreg() local
158 : "=r" (regval) viking_get_bpreg()
160 return regval; viking_get_bpreg()
H A Dpgtsrmmu.h149 void srmmu_set_mmureg(unsigned long regval);
/linux-4.1.27/drivers/edac/
H A Dsynopsys_edac.c156 u32 regval, clearval = 0; synps_edac_geterror_info() local
158 regval = readl(base + STAT_OFST); synps_edac_geterror_info()
159 if (!regval) synps_edac_geterror_info()
162 p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; synps_edac_geterror_info()
163 p->ue_cnt = regval & STAT_UECNT_MASK; synps_edac_geterror_info()
165 regval = readl(base + CE_LOG_OFST); synps_edac_geterror_info()
166 if (!(p->ce_cnt && (regval & LOG_VALID))) synps_edac_geterror_info()
169 p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; synps_edac_geterror_info()
170 regval = readl(base + CE_ADDR_OFST); synps_edac_geterror_info()
171 p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; synps_edac_geterror_info()
172 p->ceinfo.col = regval & ADDR_COL_MASK; synps_edac_geterror_info()
173 p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; synps_edac_geterror_info()
180 regval = readl(base + UE_LOG_OFST); synps_edac_geterror_info()
181 if (!(p->ue_cnt && (regval & LOG_VALID))) synps_edac_geterror_info()
184 regval = readl(base + UE_ADDR_OFST); synps_edac_geterror_info()
185 p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; synps_edac_geterror_info()
186 p->ueinfo.col = regval & ADDR_COL_MASK; synps_edac_geterror_info()
187 p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; synps_edac_geterror_info()
/linux-4.1.27/drivers/video/fbdev/core/
H A Dsvgalib.c25 u8 regval, bitval, bitnum; svga_wcrt_multi() local
28 regval = vga_rcrt(regbase, regset->regnum); svga_wcrt_multi()
32 regval = regval & ~bitval; svga_wcrt_multi()
33 if (value & 1) regval = regval | bitval; svga_wcrt_multi()
37 vga_wcrt(regbase, regset->regnum, regval); svga_wcrt_multi()
45 u8 regval, bitval, bitnum; svga_wseq_multi() local
48 regval = vga_rseq(regbase, regset->regnum); svga_wseq_multi()
52 regval = regval & ~bitval; svga_wseq_multi()
53 if (value & 1) regval = regval | bitval; svga_wseq_multi()
57 vga_wseq(regbase, regset->regnum, regval); svga_wseq_multi()
514 u8 regval; svga_set_timings() local
579 regval = vga_r(regbase, VGA_MIS_R); svga_set_timings()
582 regval = regval & ~0x80; svga_set_timings()
585 regval = regval | 0x80; svga_set_timings()
589 regval = regval & ~0x40; svga_set_timings()
592 regval = regval | 0x40; svga_set_timings()
594 vga_w(regbase, VGA_MIS_W, regval); svga_set_timings()
/linux-4.1.27/drivers/staging/iio/cdc/
H A Dad7152.c98 u8 regval) ad7152_start_calib()
114 regval |= AD7152_CONF_CH1EN; ad7152_start_calib()
116 regval |= AD7152_CONF_CH2EN; ad7152_start_calib()
119 ret = i2c_smbus_write_byte_data(chip->client, AD7152_REG_CFG, regval); ad7152_start_calib()
132 } while ((ret == regval) && timeout--); ad7152_start_calib()
327 u8 regval = 0; ad7152_read_raw() local
335 regval = chip->setup[chan->channel]; ad7152_read_raw()
342 if (regval != chip->setup[chan->channel]) { ad7152_read_raw()
351 regval = AD7152_CONF_CH1EN; ad7152_read_raw()
353 regval = AD7152_CONF_CH2EN; ad7152_read_raw()
356 regval |= AD7152_CONF_MODE_SINGLE_CONV; ad7152_read_raw()
358 regval); ad7152_read_raw()
94 ad7152_start_calib(struct device *dev, struct device_attribute *attr, const char *buf, size_t len, u8 regval) ad7152_start_calib() argument
H A Dad7746.c288 u8 regval) ad7746_start_calib()
303 regval |= chip->config; ad7746_start_calib()
304 ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG, regval); ad7746_start_calib()
317 } while ((ret == regval) && timeout--); ad7746_start_calib()
572 u8 regval, reg; ad7746_read_raw() local
584 regval = chip->config | AD7746_CONF_MODE_SINGLE_CONV; ad7746_read_raw()
586 regval); ad7746_read_raw()
701 unsigned char regval = 0; ad7746_probe() local
728 regval |= AD7746_EXCSETUP_NEXCA; ad7746_probe()
730 regval |= AD7746_EXCSETUP_EXCA; ad7746_probe()
735 regval |= AD7746_EXCSETUP_NEXCB; ad7746_probe()
737 regval |= AD7746_EXCSETUP_EXCB; ad7746_probe()
740 regval |= AD7746_EXCSETUP_EXCLVL(pdata->exclvl); ad7746_probe()
743 regval = AD7746_EXCSETUP_EXCA | AD7746_EXCSETUP_EXCB | ad7746_probe()
748 AD7746_REG_EXC_SETUP, regval); ad7746_probe()
284 ad7746_start_calib(struct device *dev, struct device_attribute *attr, const char *buf, size_t len, u8 regval) ad7746_start_calib() argument
/linux-4.1.27/arch/sparc/kernel/
H A Dauxio_64.c34 u8 regval, newval; __auxio_rmw() local
38 regval = (ebus ? __auxio_rmw()
41 newval = regval | bits_on; __auxio_rmw()
H A Dauxio_32.c87 unsigned char regval; set_auxio() local
94 regval = sbus_readb(auxio_register); set_auxio()
95 sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN4M, set_auxio()
/linux-4.1.27/drivers/spi/
H A Dspi-sirf.c491 u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL); spi_sirfsoc_chipselect() local
495 regval |= SIRFSOC_SPI_CS_IO_OUT; spi_sirfsoc_chipselect()
497 regval &= ~SIRFSOC_SPI_CS_IO_OUT; spi_sirfsoc_chipselect()
501 regval &= ~SIRFSOC_SPI_CS_IO_OUT; spi_sirfsoc_chipselect()
503 regval |= SIRFSOC_SPI_CS_IO_OUT; spi_sirfsoc_chipselect()
506 writel(regval, sspi->base + SIRFSOC_SPI_CTRL); spi_sirfsoc_chipselect()
527 u32 regval; spi_sirfsoc_setup_transfer() local
536 regval = (sspi->ctrl_freq / (2 * hz)) - 1; spi_sirfsoc_setup_transfer()
537 if (regval > 0xFFFF || regval < 0) { spi_sirfsoc_setup_transfer()
544 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8; spi_sirfsoc_setup_transfer()
550 regval |= (bits_per_word == 12) ? spi_sirfsoc_setup_transfer()
557 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32; spi_sirfsoc_setup_transfer()
572 regval |= SIRFSOC_SPI_CS_IDLE_STAT; spi_sirfsoc_setup_transfer()
574 regval |= SIRFSOC_SPI_TRAN_MSB; spi_sirfsoc_setup_transfer()
576 regval |= SIRFSOC_SPI_CLK_IDLE_STAT; spi_sirfsoc_setup_transfer()
584 regval &= ~SIRFSOC_SPI_DRV_POS_EDGE; spi_sirfsoc_setup_transfer()
586 regval |= SIRFSOC_SPI_DRV_POS_EDGE; spi_sirfsoc_setup_transfer()
600 regval |= (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) | spi_sirfsoc_setup_transfer()
604 regval &= ~SIRFSOC_SPI_CMD_MODE; spi_sirfsoc_setup_transfer()
611 regval |= SIRFSOC_SPI_CS_IO_MODE; spi_sirfsoc_setup_transfer()
612 writel(regval, sspi->base + SIRFSOC_SPI_CTRL); spi_sirfsoc_setup_transfer()
H A Dspi-fsl-espi.c612 u32 regval; fsl_espi_suspend() local
617 regval = mpc8xxx_spi_read_reg(&reg_base->mode); fsl_espi_suspend()
618 regval &= ~SPMODE_ENABLE; fsl_espi_suspend()
619 mpc8xxx_spi_write_reg(&reg_base->mode, regval); fsl_espi_suspend()
628 u32 regval; fsl_espi_resume() local
633 regval = mpc8xxx_spi_read_reg(&reg_base->mode); fsl_espi_resume()
634 regval |= SPMODE_ENABLE; fsl_espi_resume()
635 mpc8xxx_spi_write_reg(&reg_base->mode, regval); fsl_espi_resume()
649 u32 regval, csmode; fsl_espi_probe() local
726 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; fsl_espi_probe()
728 mpc8xxx_spi_write_reg(&reg_base->mode, regval); fsl_espi_probe()
832 u32 regval; of_fsl_espi_resume() local
849 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; of_fsl_espi_resume()
851 mpc8xxx_spi_write_reg(&reg_base->mode, regval); of_fsl_espi_resume()
H A Dspi-ep93xx.c147 u8 regval; ep93xx_spi_enable() local
154 regval = ep93xx_spi_read_u8(espi, SSPCR1); ep93xx_spi_enable()
155 regval |= SSPCR1_SSE; ep93xx_spi_enable()
156 ep93xx_spi_write_u8(espi, SSPCR1, regval); ep93xx_spi_enable()
163 u8 regval; ep93xx_spi_disable() local
165 regval = ep93xx_spi_read_u8(espi, SSPCR1); ep93xx_spi_disable()
166 regval &= ~SSPCR1_SSE; ep93xx_spi_disable()
167 ep93xx_spi_write_u8(espi, SSPCR1, regval); ep93xx_spi_disable()
174 u8 regval; ep93xx_spi_enable_interrupts() local
176 regval = ep93xx_spi_read_u8(espi, SSPCR1); ep93xx_spi_enable_interrupts()
177 regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); ep93xx_spi_enable_interrupts()
178 ep93xx_spi_write_u8(espi, SSPCR1, regval); ep93xx_spi_enable_interrupts()
183 u8 regval; ep93xx_spi_disable_interrupts() local
185 regval = ep93xx_spi_read_u8(espi, SSPCR1); ep93xx_spi_disable_interrupts()
186 regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); ep93xx_spi_disable_interrupts()
187 ep93xx_spi_write_u8(espi, SSPCR1, regval); ep93xx_spi_disable_interrupts()
H A Dspi-fsl-spi.c616 u32 regval; fsl_spi_probe() local
679 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; fsl_spi_probe()
681 regval &= ~SPMODE_LEN(0xF); fsl_spi_probe()
682 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); fsl_spi_probe()
685 regval |= SPMODE_OP; fsl_spi_probe()
687 mpc8xxx_spi_write_reg(&reg_base->mode, regval); fsl_spi_probe()
/linux-4.1.27/drivers/iio/adc/
H A Dad7291.c280 u16 regval; ad7291_write_event_config() local
283 regval = chip->command; ad7291_write_event_config()
301 regval &= ~AD7291_AUTOCYCLE; ad7291_write_event_config()
302 regval |= chip->c_mask; ad7291_write_event_config()
304 regval |= AD7291_AUTOCYCLE; ad7291_write_event_config()
306 ret = ad7291_i2c_write(chip, AD7291_COMMAND, regval); ad7291_write_event_config()
310 chip->command = regval; ad7291_write_event_config()
329 u16 regval; ad7291_read_raw() local
342 regval = chip->command & (~AD7291_VOLTAGE_MASK); ad7291_read_raw()
343 regval |= BIT(15 - chan->channel); ad7291_read_raw()
344 ret = ad7291_i2c_write(chip, AD7291_COMMAND, regval); ad7291_read_raw()
H A Dtwl4030-madc.c679 u8 regval; twl4030_madc_set_current_generator() local
682 &regval, TWL4030_BCI_BCICTL1); twl4030_madc_set_current_generator()
691 regval |= regmask; twl4030_madc_set_current_generator()
693 regval &= ~regmask; twl4030_madc_set_current_generator()
696 regval, TWL4030_BCI_BCICTL1); twl4030_madc_set_current_generator()
714 u8 regval; twl4030_madc_set_power() local
718 &regval, TWL4030_MADC_CTRL1); twl4030_madc_set_power()
725 regval |= TWL4030_MADC_MADCON; twl4030_madc_set_power()
727 regval &= ~TWL4030_MADC_MADCON; twl4030_madc_set_power()
728 ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, regval, TWL4030_MADC_CTRL1); twl4030_madc_set_power()
747 u8 regval; twl4030_madc_probe() local
796 &regval, TWL4030_BCI_BCICTL1); twl4030_madc_probe()
802 regval |= TWL4030_BCI_MESBAT; twl4030_madc_probe()
804 regval, TWL4030_BCI_BCICTL1); twl4030_madc_probe()
812 ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, &regval, TWL4030_REG_GPBR1); twl4030_madc_probe()
820 if (!(regval & TWL4030_GPBR1_MADC_HFCLK_EN)) { twl4030_madc_probe()
822 regval |= TWL4030_GPBR1_MADC_HFCLK_EN; twl4030_madc_probe()
823 ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, regval, twl4030_madc_probe()
/linux-4.1.27/drivers/hwmon/
H A Dk10temp.c79 u32 regval; show_temp() local
85 &regval); show_temp()
87 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, &regval); show_temp()
89 return sprintf(buf, "%u\n", (regval >> 21) * 125); show_temp()
103 u32 regval; show_temp_crit() local
107 REG_HARDWARE_THERMAL_CONTROL, &regval); show_temp_crit() local
108 value = ((regval >> 16) & 0x7f) * 500 + 52000; show_temp_crit()
110 value -= ((regval >> 24) & 0xf) * 500; show_temp_crit()
H A Dads7828.c69 unsigned int regval; ads7828_show_in() local
72 err = regmap_read(data->regmap, cmd, &regval); ads7828_show_in()
77 DIV_ROUND_CLOSEST(regval * data->lsb_resol, 1000)); ads7828_show_in()
123 unsigned int regval; ads7828_probe() local
165 regmap_read(data->regmap, data->cmd_byte, &regval); ads7828_probe()
H A Dasc7621.c250 u16 regval; show_fan16() local
253 regval = (data->reg[param->msb[0]] << 8) | data->reg[param->lsb[0]]; show_fan16()
257 (regval == 0 ? -1 : (regval) == show_fan16()
258 0xffff ? 0 : 5400000 / regval)); show_fan16()
311 u16 regval; show_in10() local
315 regval = (data->reg[param->msb[0]] << 8) | (data->reg[param->lsb[0]]); show_in10()
319 regval = (regval >> 6) * asc7621_in_scaling[nr] / (0xc0 << 2); show_in10()
321 return sprintf(buf, "%u\n", regval); show_in10()
418 u8 regval = data->reg[param->msb[0]]; show_temp62() local
419 int temp = ((s8) (regval & 0xfc) * 1000) + ((regval & 0x03) * 250); show_temp62()
464 u8 regval; show_ap2_temp() local
469 regval = show_ap2_temp()
471 temp = auto_point1 + asc7621_range_map[clamp_val(regval, 0, 15)]; show_ap2_temp()
514 u8 config, altbit, regval; show_pwm_ac() local
523 regval = config | (altbit << 3); show_pwm_ac()
526 return sprintf(buf, "%u\n", map[clamp_val(regval, 0, 15)]); show_pwm_ac()
663 u8 regval = show_pwm_freq() local
666 regval = clamp_val(regval, 0, 15); show_pwm_freq()
668 return sprintf(buf, "%u\n", asc7621_pwm_freq_map[regval]); show_pwm_freq()
711 u8 regval = show_pwm_ast() local
714 regval = clamp_val(regval, 0, 7); show_pwm_ast()
716 return sprintf(buf, "%u\n", asc7621_pwm_auto_spinup_map[regval]); show_pwm_ast()
760 u8 regval = show_temp_st() local
762 regval = clamp_val(regval, 0, 7); show_temp_st()
764 return sprintf(buf, "%u\n", asc7621_temp_smoothing_time_map[regval]); show_temp_st()
H A Dltc2945.c251 int regval; ltc2945_set_value() local
259 regval = ltc2945_val_to_reg(dev, reg, val); ltc2945_set_value()
261 regval = clamp_val(regval, 0, 0xffffff); ltc2945_set_value()
262 regbuf[0] = regval >> 16; ltc2945_set_value()
263 regbuf[1] = (regval >> 8) & 0xff; ltc2945_set_value()
264 regbuf[2] = regval; ltc2945_set_value()
267 regval = clamp_val(regval, 0, 0xfff) << 4; ltc2945_set_value()
268 regbuf[0] = regval >> 8; ltc2945_set_value()
269 regbuf[1] = regval & 0xff; ltc2945_set_value()
H A Dltc4245.c177 const u8 regval = data->vregs[reg - 0x10]; ltc4245_get_voltage() local
183 voltage = regval * 55; ltc4245_get_voltage()
187 voltage = regval * 22; ltc4245_get_voltage()
191 voltage = regval * 15; ltc4245_get_voltage()
195 voltage = regval * -55; ltc4245_get_voltage()
198 voltage = regval * 10; ltc4245_get_voltage()
213 const u8 regval = data->vregs[reg - 0x10]; ltc4245_get_current() local
234 voltage = regval * 250; /* voltage in uV */ ltc4245_get_current()
238 voltage = regval * 125; /* voltage in uV */ ltc4245_get_current()
242 voltage = regval * 125; /* voltage in uV */ ltc4245_get_current()
246 voltage = regval * 250; /* voltage in uV */ ltc4245_get_current()
H A Dtmp103.c70 unsigned int regval; tmp103_show_temp() local
73 ret = regmap_read(regmap, sda->index, &regval); tmp103_show_temp()
77 return sprintf(buf, "%d\n", tmp103_reg_to_mc(regval)); tmp103_show_temp()
H A Dadc128d818.c164 u8 reg, regval; adc128_set_in() local
174 regval = clamp_val(DIV_ROUND_CLOSEST(val, 10), 0, 255); adc128_set_in()
175 data->in[index][nr] = regval << 4; adc128_set_in()
177 i2c_smbus_write_byte_data(data->client, reg, regval); adc128_set_in()
205 s8 regval; adc128_set_temp() local
212 regval = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127); adc128_set_temp()
213 data->temp[index] = regval << 1; adc128_set_temp()
217 regval); adc128_set_temp()
H A Dltc4215.c82 const u8 regval = data->regs[reg]; ltc4215_get_voltage() local
88 voltage = regval * 151 / 1000; ltc4215_get_voltage()
92 voltage = regval * 605 / 10; ltc4215_get_voltage()
99 voltage = regval * 482 * 125 / 1000; ltc4215_get_voltage()
H A Dina209.c239 u16 regval; ina209_set_interval() local
250 regval = ina209_reg_from_interval(data->regs[INA209_CONFIGURATION], ina209_set_interval()
253 regval); ina209_set_interval()
254 data->regs[INA209_CONFIGURATION] = regval; ina209_set_interval()
255 data->update_interval = ina209_interval_from_reg(regval); ina209_set_interval()
H A Dlm95234.c472 u8 regval; set_interval() local
481 for (regval = 0; regval < 3; regval++) { set_interval()
482 if (val <= update_intervals[regval]) set_interval()
487 data->interval = msecs_to_jiffies(update_intervals[regval]); set_interval()
488 i2c_smbus_write_byte_data(data->client, LM95234_REG_CONVRATE, regval); set_interval()
H A Dnct7802.c350 unsigned int regval; show_beep() local
353 err = regmap_read(data->regmap, sattr->nr, &regval); show_beep()
357 return sprintf(buf, "%u\n", !!(regval & (1 << sattr->index))); show_beep()
H A Dnct6775.c3186 int regval; nct6775_check_fan_inputs() local
3194 regval = superio_inb(sioreg, 0x2c); nct6775_check_fan_inputs()
3196 fan3pin = regval & (1 << 6); nct6775_check_fan_inputs()
3197 pwm3pin = regval & (1 << 7); nct6775_check_fan_inputs()
3252 regval = superio_inb(sioreg, 0x24); nct6775_check_fan_inputs()
3253 fan3pin = !(regval & 0x80); nct6775_check_fan_inputs()
3254 pwm3pin = regval & 0x08; nct6775_check_fan_inputs()
3264 regval = superio_inb(sioreg, 0x1c); nct6775_check_fan_inputs()
3266 fan3pin = !(regval & (1 << 5)); nct6775_check_fan_inputs()
3267 fan4pin = !(regval & (1 << 6)); nct6775_check_fan_inputs()
3268 fan5pin = !(regval & (1 << 7)); nct6775_check_fan_inputs()
3270 pwm3pin = !(regval & (1 << 0)); nct6775_check_fan_inputs()
3271 pwm4pin = !(regval & (1 << 1)); nct6775_check_fan_inputs()
3272 pwm5pin = !(regval & (1 << 2)); nct6775_check_fan_inputs()
3277 regval = superio_inb(sioreg, 0x2d); nct6775_check_fan_inputs()
3278 fan6pin = (regval & (1 << 1)); nct6775_check_fan_inputs()
3279 pwm6pin = (regval & (1 << 0)); nct6775_check_fan_inputs()
H A Dw83627ehf.c1980 int fan3pin, fan4pin, fan4min, fan5pin, regval; w83627ehf_check_fan_inputs() local
2002 regval = superio_inb(sio_data->sioreg, SIO_REG_ENABLE); w83627ehf_check_fan_inputs()
2004 if (regval & 0x80) w83627ehf_check_fan_inputs()
2009 if (regval & 0x40) w83627ehf_check_fan_inputs()
2014 if (regval & 0x20) w83627ehf_check_fan_inputs()
2053 regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1); w83627ehf_check_fan_inputs()
2054 if ((regval & (1 << 2)) && fan4pin) { w83627ehf_check_fan_inputs()
2058 if (!(regval & (1 << 1)) && fan5pin) { w83627ehf_check_fan_inputs()
H A Dit87.c690 u8 reg, regval; set_temp() local
706 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE); set_temp()
707 if (!(regval & 0x80)) { set_temp()
708 regval |= 0x80; set_temp()
709 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval); set_temp()
/linux-4.1.27/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_core.c26 u32 regval; sxgbe_core_init() local
29 regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); sxgbe_core_init()
33 regval |= SXGBE_TX_JABBER_DISABLE; sxgbe_core_init()
34 writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG); sxgbe_core_init()
37 regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); sxgbe_core_init()
42 regval |= SXGBE_RX_JUMBPKT_ENABLE | SXGBE_RX_ACS_ENABLE; sxgbe_core_init()
43 writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG); sxgbe_core_init()
/linux-4.1.27/drivers/rtc/
H A Drtc-ab3100.c204 u8 regval; ab3100_rtc_probe() local
209 AB3100_RTC, &regval); ab3100_rtc_probe()
215 if ((regval & 0xFE) != RTC_SETTING) { ab3100_rtc_probe()
217 regval); ab3100_rtc_probe()
220 if ((regval & 1) == 0) { ab3100_rtc_probe()
225 regval = 1 | RTC_SETTING; ab3100_rtc_probe()
227 AB3100_RTC, regval); ab3100_rtc_probe()
/linux-4.1.27/drivers/net/ethernet/intel/igb/
H A Digb_ptp.c691 u64 regval; igb_ptp_tx_hwtstamp() local
693 regval = rd32(E1000_TXSTMPL); igb_ptp_tx_hwtstamp()
694 regval |= (u64)rd32(E1000_TXSTMPH) << 32; igb_ptp_tx_hwtstamp()
696 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); igb_ptp_tx_hwtstamp()
717 __le64 *regval = (__le64 *)va; igb_ptp_rx_pktstamp() local
724 le64_to_cpu(regval[1])); igb_ptp_rx_pktstamp()
740 u64 regval; igb_ptp_rx_rgtstamp() local
755 regval = rd32(E1000_RXSTMPL); igb_ptp_rx_rgtstamp()
756 regval |= (u64)rd32(E1000_RXSTMPH) << 32; igb_ptp_rx_rgtstamp()
758 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); igb_ptp_rx_rgtstamp()
810 u32 regval; igb_ptp_set_timestamp_mode() local
888 regval = rd32(E1000_RXPBS); igb_ptp_set_timestamp_mode()
889 regval |= E1000_RXPBS_CFG_TS_EN; igb_ptp_set_timestamp_mode()
890 wr32(E1000_RXPBS, regval); igb_ptp_set_timestamp_mode()
895 regval = rd32(E1000_TSYNCTXCTL); igb_ptp_set_timestamp_mode()
896 regval &= ~E1000_TSYNCTXCTL_ENABLED; igb_ptp_set_timestamp_mode()
897 regval |= tsync_tx_ctl; igb_ptp_set_timestamp_mode()
898 wr32(E1000_TSYNCTXCTL, regval); igb_ptp_set_timestamp_mode()
901 regval = rd32(E1000_TSYNCRXCTL); igb_ptp_set_timestamp_mode()
902 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); igb_ptp_set_timestamp_mode()
903 regval |= tsync_rx_ctl; igb_ptp_set_timestamp_mode()
904 wr32(E1000_TSYNCRXCTL, regval); igb_ptp_set_timestamp_mode()
941 regval = rd32(E1000_TXSTMPL); igb_ptp_set_timestamp_mode()
942 regval = rd32(E1000_TXSTMPH); igb_ptp_set_timestamp_mode()
943 regval = rd32(E1000_RXSTMPL); igb_ptp_set_timestamp_mode()
944 regval = rd32(E1000_RXSTMPH); igb_ptp_set_timestamp_mode()
H A Digb_main.c1483 u32 regval = rd32(E1000_EIAM); igb_irq_disable() local
1485 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); igb_irq_disable()
1487 regval = rd32(E1000_EIAC); igb_irq_disable()
1488 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); igb_irq_disable()
1514 u32 regval = rd32(E1000_EIAC); igb_irq_enable() local
1516 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); igb_irq_enable()
1517 regval = rd32(E1000_EIAM); igb_irq_enable()
1518 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); igb_irq_enable()
/linux-4.1.27/sound/sh/
H A Daica.c149 u32 regval; spu_disable() local
151 regval = readl(ARM_RESET_REGISTER); spu_disable()
152 regval |= 1; spu_disable()
155 writel(regval, ARM_RESET_REGISTER); spu_disable()
159 regval = readl(SPU_REGISTER_BASE + (i * 0x80)); spu_disable()
160 regval = (regval & ~0x4000) | 0x8000; spu_disable()
163 writel(regval, SPU_REGISTER_BASE + (i * 0x80)); spu_disable()
172 u32 regval = readl(ARM_RESET_REGISTER); spu_enable() local
173 regval &= ~1; spu_enable()
176 writel(regval, ARM_RESET_REGISTER); spu_enable()
/linux-4.1.27/drivers/i2c/muxes/
H A Di2c-mux-pca954x.c154 u8 regval; pca954x_select_chan() local
159 regval = chan | chip->enable; pca954x_select_chan()
161 regval = 1 << chan; pca954x_select_chan()
164 if (data->last_chan != regval) { pca954x_select_chan()
165 ret = pca954x_reg_write(adap, client, regval); pca954x_select_chan()
166 data->last_chan = regval; pca954x_select_chan()
/linux-4.1.27/drivers/staging/iio/frequency/
H A Dad9832.c36 unsigned long regval; ad9832_write_frequency() local
41 regval = ad9832_calc_freqreg(st->mclk, fout); ad9832_write_frequency()
45 ((regval >> 24) & 0xFF)); ad9832_write_frequency()
48 ((regval >> 16) & 0xFF)); ad9832_write_frequency()
51 ((regval >> 8) & 0xFF)); ad9832_write_frequency()
54 ((regval >> 0) & 0xFF)); ad9832_write_frequency()
H A Dad9834.c39 unsigned long regval; ad9834_write_frequency() local
44 regval = ad9834_calc_freqreg(st->mclk, fout); ad9834_write_frequency()
46 st->freq_data[0] = cpu_to_be16(addr | (regval & ad9834_write_frequency()
48 st->freq_data[1] = cpu_to_be16(addr | ((regval >> ad9834_write_frequency()
/linux-4.1.27/arch/ia64/sn/kernel/
H A Dirq.c422 u64 regval; sn_check_intr() local
441 regval = pcireg_intr_status_get(pcibus_info); sn_check_intr()
445 regval &= 0xff; sn_check_intr()
446 if (sn_irq_info->irq_int_bit & regval & sn_check_intr()
448 regval &= ~(sn_irq_info->irq_int_bit & regval); sn_check_intr()
453 sn_irq_info->irq_last_intr = regval; sn_check_intr()
/linux-4.1.27/drivers/iio/proximity/
H A Dsx9500.c199 __be16 regval; sx9500_read_proximity() local
205 ret = regmap_bulk_read(data->regmap, SX9500_REG_USE_MSB, &regval, 2); sx9500_read_proximity()
209 *val = be16_to_cpu(regval); sx9500_read_proximity()
218 unsigned int regval; sx9500_read_samp_freq() local
221 ret = regmap_read(data->regmap, SX9500_REG_PROX_CTRL0, &regval); sx9500_read_samp_freq()
227 regval = (regval & SX9500_SCAN_PERIOD_MASK) >> SX9500_SCAN_PERIOD_SHIFT; sx9500_read_samp_freq()
228 *val = sx9500_samp_freq_table[regval].val; sx9500_read_samp_freq()
229 *val2 = sx9500_samp_freq_table[regval].val2; sx9500_read_samp_freq()
/linux-4.1.27/drivers/iio/gyro/
H A Ditg3200_core.c93 u8 regval; itg3200_read_raw() local
112 ret = itg3200_read_reg_8(indio_dev, ITG3200_REG_DLPF, &regval); itg3200_read_raw()
116 *val = (regval & ITG3200_DLPF_CFG_MASK) ? 1000 : 8000; itg3200_read_raw()
120 &regval); itg3200_read_raw()
124 *val /= regval + 1; itg3200_read_raw()
/linux-4.1.27/drivers/net/ethernet/intel/i40e/
H A Di40e_ptp.c462 u32 tsyntype, regval; i40e_ptp_set_timestamp_mode() local
527 regval = rd32(hw, I40E_PRTTSYN_CTL0); i40e_ptp_set_timestamp_mode()
529 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; i40e_ptp_set_timestamp_mode()
531 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; i40e_ptp_set_timestamp_mode()
532 wr32(hw, I40E_PRTTSYN_CTL0, regval); i40e_ptp_set_timestamp_mode()
534 regval = rd32(hw, I40E_PFINT_ICR0_ENA); i40e_ptp_set_timestamp_mode()
536 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; i40e_ptp_set_timestamp_mode()
538 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; i40e_ptp_set_timestamp_mode()
539 wr32(hw, I40E_PFINT_ICR0_ENA, regval); i40e_ptp_set_timestamp_mode()
547 regval = rd32(hw, I40E_PRTTSYN_CTL1); i40e_ptp_set_timestamp_mode()
549 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; i40e_ptp_set_timestamp_mode()
551 regval |= tsyntype; i40e_ptp_set_timestamp_mode()
552 wr32(hw, I40E_PRTTSYN_CTL1, regval); i40e_ptp_set_timestamp_mode()
677 u32 regval; i40e_ptp_init() local
684 regval = rd32(hw, I40E_PRTTSYN_CTL0); i40e_ptp_init()
685 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; i40e_ptp_init()
686 wr32(hw, I40E_PRTTSYN_CTL0, regval); i40e_ptp_init()
687 regval = rd32(hw, I40E_PRTTSYN_CTL1); i40e_ptp_init()
688 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; i40e_ptp_init()
689 wr32(hw, I40E_PRTTSYN_CTL1, regval); i40e_ptp_init()
/linux-4.1.27/drivers/sbus/char/
H A Ddisplay7seg.c90 u8 regval = 0; d7s_release() local
92 regval = readb(p->regs); d7s_release()
94 regval |= D7S_FLIP; d7s_release()
96 regval &= ~D7S_FLIP; d7s_release()
97 writeb(regval, p->regs); d7s_release()
/linux-4.1.27/drivers/media/dvb-frontends/
H A Dstv0900_core.c624 if (INRANGE(lookup->table[imin].regval, agc_gain, stv0900_get_rf_level()
625 lookup->table[imax].regval)) { stv0900_get_rf_level()
629 if (INRANGE(lookup->table[imin].regval, stv0900_get_rf_level()
631 lookup->table[i].regval)) stv0900_get_rf_level()
637 rf_lvl = (s32)agc_gain - lookup->table[imin].regval; stv0900_get_rf_level()
640 rf_lvl /= (lookup->table[imax].regval - stv0900_get_rf_level()
641 lookup->table[imin].regval); stv0900_get_rf_level()
643 } else if (agc_gain > lookup->table[0].regval) stv0900_get_rf_level()
645 else if (agc_gain < lookup->table[lookup->size-1].regval) stv0900_get_rf_level()
680 regval, stv0900_carr_get_quality() local
699 regval = 0; stv0900_carr_get_quality()
702 regval += MAKEWORD(stv0900_get_bits(intp, stv0900_carr_get_quality()
709 regval /= 16; stv0900_carr_get_quality()
712 if (INRANGE(lookup->table[imin].regval, stv0900_carr_get_quality()
713 regval, stv0900_carr_get_quality()
714 lookup->table[imax].regval)) { stv0900_carr_get_quality()
717 if (INRANGE(lookup->table[imin].regval, stv0900_carr_get_quality()
718 regval, stv0900_carr_get_quality()
719 lookup->table[i].regval)) stv0900_carr_get_quality()
725 c_n = ((regval - lookup->table[imin].regval) stv0900_carr_get_quality()
728 / (lookup->table[imax].regval stv0900_carr_get_quality()
729 - lookup->table[imin].regval)) stv0900_carr_get_quality()
731 } else if (regval < lookup->table[imin].regval) stv0900_carr_get_quality()
H A Dstv0900_priv.h63 s32 regval;/* binary value */ member in struct:stv000_lookpoint
H A Dstv0367.c3279 u32 regval = 0, temp = 0; stv0367cab_read_snr() local
3314 regval += (stv0367_readbits(state, F367CAB_SNR_LO) stv0367cab_read_snr()
3318 regval /= 10; /*for average over 10 times in for loop above*/ stv0367cab_read_snr()
3319 if (regval != 0) { stv0367cab_read_snr()
3322 temp /= regval; stv0367cab_read_snr()
/linux-4.1.27/sound/soc/codecs/
H A Dmax98095.c1218 u8 regval; max98095_dai1_hw_params() local
1237 if (rate_value(rate, &regval)) max98095_dai1_hw_params()
1241 M98095_CLKMODE_MASK, regval); max98095_dai1_hw_params()
1279 u8 regval; max98095_dai2_hw_params() local
1298 if (rate_value(rate, &regval)) max98095_dai2_hw_params()
1302 M98095_CLKMODE_MASK, regval); max98095_dai2_hw_params()
1340 u8 regval; max98095_dai3_hw_params() local
1359 if (rate_value(rate, &regval)) max98095_dai3_hw_params()
1363 M98095_CLKMODE_MASK, regval); max98095_dai3_hw_params()
1435 u8 regval = 0; max98095_dai1_set_fmt() local
1452 regval |= M98095_DAI_MAS; max98095_dai1_set_fmt()
1463 regval |= M98095_DAI_DLY; max98095_dai1_set_fmt()
1475 regval |= M98095_DAI_WCI; max98095_dai1_set_fmt()
1478 regval |= M98095_DAI_BCI; max98095_dai1_set_fmt()
1481 regval |= M98095_DAI_BCI|M98095_DAI_WCI; max98095_dai1_set_fmt()
1489 M98095_DAI_WCI, regval); max98095_dai1_set_fmt()
1503 u8 regval = 0; max98095_dai2_set_fmt() local
1520 regval |= M98095_DAI_MAS; max98095_dai2_set_fmt()
1531 regval |= M98095_DAI_DLY; max98095_dai2_set_fmt()
1543 regval |= M98095_DAI_WCI; max98095_dai2_set_fmt()
1546 regval |= M98095_DAI_BCI; max98095_dai2_set_fmt()
1549 regval |= M98095_DAI_BCI|M98095_DAI_WCI; max98095_dai2_set_fmt()
1557 M98095_DAI_WCI, regval); max98095_dai2_set_fmt()
1572 u8 regval = 0; max98095_dai3_set_fmt() local
1589 regval |= M98095_DAI_MAS; max98095_dai3_set_fmt()
1600 regval |= M98095_DAI_DLY; max98095_dai3_set_fmt()
1612 regval |= M98095_DAI_WCI; max98095_dai3_set_fmt()
1615 regval |= M98095_DAI_BCI; max98095_dai3_set_fmt()
1618 regval |= M98095_DAI_BCI|M98095_DAI_WCI; max98095_dai3_set_fmt()
1626 M98095_DAI_WCI, regval); max98095_dai3_set_fmt()
2056 u8 regval = 0; max98095_handle_pdata() local
2065 regval |= M98095_DIGMIC_L; max98095_handle_pdata()
2068 regval |= M98095_DIGMIC_R; max98095_handle_pdata()
2070 snd_soc_write(codec, M98095_087_CFG_MIC, regval); max98095_handle_pdata()
H A Dmax98090.c1652 u8 regval; max98090_dai_set_fmt() local
1660 regval = 0; max98090_dai_set_fmt()
1676 regval |= M98090_MAS_MASK | max98090_dai_set_fmt()
1680 regval |= M98090_MAS_MASK | max98090_dai_set_fmt()
1684 regval |= M98090_MAS_MASK | max98090_dai_set_fmt()
1695 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval); max98090_dai_set_fmt()
1697 regval = 0; max98090_dai_set_fmt()
1700 regval |= M98090_DLY_MASK; max98090_dai_set_fmt()
1705 regval |= M98090_RJ_MASK; max98090_dai_set_fmt()
1718 regval |= M98090_WCI_MASK; max98090_dai_set_fmt()
1721 regval |= M98090_BCI_MASK; max98090_dai_set_fmt()
1724 regval |= M98090_BCI_MASK|M98090_WCI_MASK; max98090_dai_set_fmt()
1738 regval ^= M98090_BCI_MASK; max98090_dai_set_fmt()
1741 M98090_REG_INTERFACE_FORMAT, regval); max98090_dai_set_fmt()
2079 int regval; max98090_dai_digital_mute() local
2081 regval = mute ? M98090_DVM_MASK : 0; max98090_dai_digital_mute()
2083 M98090_DVM_MASK, regval); max98090_dai_digital_mute()
H A Dmax98088.c1229 u8 regval; max98088_dai1_hw_params() local
1250 if (rate_value(rate, &regval)) max98088_dai1_hw_params()
1254 M98088_CLKMODE_MASK, regval); max98088_dai1_hw_params()
1296 u8 regval; max98088_dai2_hw_params() local
1317 if (rate_value(rate, &regval)) max98088_dai2_hw_params()
1321 M98088_CLKMODE_MASK, regval); max98088_dai2_hw_params()
1862 u8 regval = 0; max98088_handle_pdata() local
1871 regval |= M98088_DIGMIC_L; max98088_handle_pdata()
1874 regval |= M98088_DIGMIC_R; max98088_handle_pdata()
1876 max98088->digmic = (regval ? 1 : 0); max98088_handle_pdata()
1878 snd_soc_write(codec, M98088_REG_48_CFG_MIC, regval); max98088_handle_pdata()
1881 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0); max98088_handle_pdata()
1883 M98088_REC_LINEMODE_MASK, regval); max98088_handle_pdata()
/linux-4.1.27/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_ptp.c464 u64 regval = 0, ns; ixgbe_ptp_tx_hwtstamp() local
467 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); ixgbe_ptp_tx_hwtstamp()
468 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32; ixgbe_ptp_tx_hwtstamp()
471 ns = timecounter_cyc2time(&adapter->tc, regval); ixgbe_ptp_tx_hwtstamp()
529 u64 regval = 0, ns; ixgbe_ptp_rx_hwtstamp() local
537 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); ixgbe_ptp_rx_hwtstamp()
538 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32; ixgbe_ptp_rx_hwtstamp()
541 ns = timecounter_cyc2time(&adapter->tc, regval); ixgbe_ptp_rx_hwtstamp()
594 u32 regval; ixgbe_ptp_set_timestamp_mode() local
664 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); ixgbe_ptp_set_timestamp_mode()
665 regval &= ~IXGBE_TSYNCTXCTL_ENABLED; ixgbe_ptp_set_timestamp_mode()
666 regval |= tsync_tx_ctl; ixgbe_ptp_set_timestamp_mode()
667 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval); ixgbe_ptp_set_timestamp_mode()
670 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); ixgbe_ptp_set_timestamp_mode()
671 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK); ixgbe_ptp_set_timestamp_mode()
672 regval |= tsync_rx_ctl; ixgbe_ptp_set_timestamp_mode()
673 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval); ixgbe_ptp_set_timestamp_mode()
681 regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH); ixgbe_ptp_set_timestamp_mode()
682 regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH); ixgbe_ptp_set_timestamp_mode()
H A Dixgbe_82598.c181 u32 regval; ixgbe_start_hw_82598() local
192 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); ixgbe_start_hw_82598()
193 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; ixgbe_start_hw_82598()
194 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); ixgbe_start_hw_82598()
199 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); ixgbe_start_hw_82598()
200 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | ixgbe_start_hw_82598()
202 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); ixgbe_start_hw_82598()
H A Dixgbe_sriov.c1376 u32 regval; ixgbe_ndo_set_vf_spoofchk() local
1383 regval = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); ixgbe_ndo_set_vf_spoofchk()
1384 regval &= ~(1 << vf_target_shift); ixgbe_ndo_set_vf_spoofchk()
1385 regval |= (setting << vf_target_shift); ixgbe_ndo_set_vf_spoofchk()
1386 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), regval); ixgbe_ndo_set_vf_spoofchk()
1390 regval = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); ixgbe_ndo_set_vf_spoofchk()
1391 regval &= ~(1 << vf_target_shift); ixgbe_ndo_set_vf_spoofchk()
1392 regval |= (setting << vf_target_shift); ixgbe_ndo_set_vf_spoofchk()
1393 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), regval); ixgbe_ndo_set_vf_spoofchk()
H A Dixgbe_common.h82 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
H A Dixgbe_common.c326 u32 regval; ixgbe_start_hw_gen2() local
328 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); ixgbe_start_hw_gen2()
329 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; ixgbe_start_hw_gen2()
330 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); ixgbe_start_hw_gen2()
334 u32 regval; ixgbe_start_hw_gen2() local
336 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); ixgbe_start_hw_gen2()
337 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | ixgbe_start_hw_gen2()
339 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); ixgbe_start_hw_gen2()
2640 * @regval: register value to write to RXCTRL
2644 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) ixgbe_enable_rx_dma_generic() argument
2646 if (regval & IXGBE_RXCTRL_RXEN) ixgbe_enable_rx_dma_generic()
H A Dixgbe_82599.c1966 * @regval: register value to write to RXCTRL
1970 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) ixgbe_enable_rx_dma_82599() argument
1980 if (regval & IXGBE_RXCTRL_RXEN) ixgbe_enable_rx_dma_82599()
/linux-4.1.27/arch/arm/mach-omap1/
H A Dclock.c232 u16 regval; omap1_clk_set_rate_dsp_domain() local
240 regval = __raw_readw(DSP_CKCTL); omap1_clk_set_rate_dsp_domain()
241 regval &= ~(3 << clk->rate_offset); omap1_clk_set_rate_dsp_domain()
242 regval |= dsor_exp << clk->rate_offset; omap1_clk_set_rate_dsp_domain()
243 __raw_writew(regval, DSP_CKCTL); omap1_clk_set_rate_dsp_domain()
262 u16 regval; omap1_clk_set_rate_ckctl_arm() local
270 regval = omap_readw(ARM_CKCTL); omap1_clk_set_rate_ckctl_arm()
271 regval &= ~(3 << clk->rate_offset); omap1_clk_set_rate_ckctl_arm()
272 regval |= dsor_exp << clk->rate_offset; omap1_clk_set_rate_ckctl_arm()
273 regval = verify_ckctl_value(regval); omap1_clk_set_rate_ckctl_arm()
274 omap_writew(regval, ARM_CKCTL); omap1_clk_set_rate_ckctl_arm()
/linux-4.1.27/drivers/video/fbdev/
H A Darkfb.c477 u8 regval; ark_dac_read_regs() local
480 regval = vga_rseq(par->state.vgabase, 0x1C); ark_dac_read_regs()
483 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); ark_dac_read_regs()
489 vga_wseq(par->state.vgabase, 0x1C, regval); ark_dac_read_regs()
496 u8 regval; ark_dac_write_regs() local
499 regval = vga_rseq(par->state.vgabase, 0x1C); ark_dac_write_regs()
502 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); ark_dac_write_regs()
508 vga_wseq(par->state.vgabase, 0x1C, regval); ark_dac_write_regs()
515 u8 regval; ark_set_pixclock() local
524 regval = vga_r(par->state.vgabase, VGA_MIS_R); ark_set_pixclock()
525 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); ark_set_pixclock()
632 u8 regval; arkfb_set_par() local
692 regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1; arkfb_set_par()
693 vga_wseq(par->state.vgabase, 0x18, regval); arkfb_set_par()
960 u8 regval; ark_pci_probe() local
1022 regval = vga_rseq(par->state.vgabase, 0x10); ark_pci_probe()
1023 info->screen_size = (1 << (regval >> 6)) << 20; ark_pci_probe()
H A Ds3fb.c473 u8 regval; s3_set_pixclock() local
484 regval = vga_r(par->state.vgabase, VGA_MIS_R); s3_set_pixclock()
485 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); s3_set_pixclock()
503 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ s3_set_pixclock()
504 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); s3_set_pixclock()
505 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); s3_set_pixclock()
506 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); s3_set_pixclock()
1131 u8 regval, cr38, cr39; s3_pci_probe() local
1202 regval = vga_rcrt(par->state.vgabase, 0x36); s3_pci_probe()
1207 switch ((regval & 0xE0) >> 5) { s3_pci_probe()
1221 switch ((regval & 0xC0) >> 6) { s3_pci_probe()
1230 switch ((regval & 0x60) >> 5) { s3_pci_probe()
1245 regval = vga_rcrt(par->state.vgabase, 0x37); s3_pci_probe()
1246 switch ((regval & 0x60) >> 5) { s3_pci_probe()
1255 info->screen_size = s3_memsizes[regval >> 5] << 10; s3_pci_probe()
1259 regval = vga_rseq(par->state.vgabase, 0x10); s3_pci_probe()
1260 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); s3_pci_probe()
1261 par->mclk_freq = par->mclk_freq >> (regval >> 5); s3_pci_probe()
H A Dvt8623fb.c264 u8 regval; vt8623_set_pixclock() local
274 regval = vga_r(par->state.vgabase, VGA_MIS_R); vt8623_set_pixclock()
275 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); vt8623_set_pixclock()
/linux-4.1.27/drivers/rapidio/
H A Drio.c576 u32 regval; rio_set_port_lockout() local
580 &regval); rio_set_port_lockout()
582 regval |= RIO_PORT_N_CTL_LOCKOUT; rio_set_port_lockout()
584 regval &= ~RIO_PORT_N_CTL_LOCKOUT; rio_set_port_lockout()
588 regval); rio_set_port_lockout()
610 u32 regval; rio_enable_rx_tx_port() local
624 &regval); rio_enable_rx_tx_port()
627 ext_ftr_ptr + RIO_PORT_N_CTL_CSR(port_num), &regval) < 0) rio_enable_rx_tx_port()
631 if (regval & RIO_PORT_N_CTL_P_TYP_SER) { rio_enable_rx_tx_port()
633 regval = regval | RIO_PORT_N_CTL_EN_RX_SER rio_enable_rx_tx_port()
637 regval = regval | RIO_PORT_N_CTL_EN_RX_PAR rio_enable_rx_tx_port()
643 RIO_PORT_N_CTL_CSR(0), regval); rio_enable_rx_tx_port()
646 ext_ftr_ptr + RIO_PORT_N_CTL_CSR(port_num), regval) < 0) rio_enable_rx_tx_port()
741 u32 regval; rio_get_input_status() local
749 &regval); rio_get_input_status()
767 &regval); rio_get_input_status()
768 if (regval & RIO_PORT_N_MNT_RSP_RVAL) { rio_get_input_status()
769 *lnkresp = regval; rio_get_input_status()
786 u32 regval; rio_clr_err_stopped() local
799 if (rio_get_input_status(rdev, pnum, &regval)) { rio_clr_err_stopped()
805 pnum, regval); rio_clr_err_stopped()
806 far_ackid = (regval & RIO_PORT_N_MNT_RSP_ASTAT) >> 5; rio_clr_err_stopped()
807 far_linkstat = regval & RIO_PORT_N_MNT_RSP_LSTAT; rio_clr_err_stopped()
810 &regval); rio_clr_err_stopped()
811 pr_debug("RIO_EM: SP%d_ACK_STS_CSR=0x%08x\n", pnum, regval); rio_clr_err_stopped()
812 near_ackid = (regval & RIO_PORT_N_ACK_INBOUND) >> 24; rio_clr_err_stopped()
821 if ((far_ackid != ((regval & RIO_PORT_N_ACK_OUTSTAND) >> 8)) || rio_clr_err_stopped()
822 (far_ackid != (regval & RIO_PORT_N_ACK_OUTBOUND))) { rio_clr_err_stopped()
H A Drio-scan.c568 u32 regval; rio_enum_peer() local
584 hopcount, RIO_COMPONENT_TAG_CSR, &regval); rio_enum_peer()
586 if (regval) { rio_enum_peer()
587 rdev = rio_get_comptag((regval & 0xffff), NULL); rio_enum_peer()
752 u32 regval; rio_enum_complete() local
755 &regval); rio_enum_complete()
756 return (regval & RIO_PORT_GEN_DISCOVERED) ? 1 : 0; rio_enum_complete()
/linux-4.1.27/arch/arm/mach-lpc32xx/
H A Dcommon.h51 extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval);
H A Dclock.c208 u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval) clk_get_pllrate_from_reg() argument
215 if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0) clk_get_pllrate_from_reg()
217 if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0) clk_get_pllrate_from_reg()
219 if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0) clk_get_pllrate_from_reg()
221 pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF); clk_get_pllrate_from_reg()
222 pllcfg.pll_n = 1 + ((regval >> 9) & 0x3); clk_get_pllrate_from_reg()
223 pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)]; clk_get_pllrate_from_reg()
/linux-4.1.27/drivers/pinctrl/sunxi/
H A Dpinctrl-sunxi.c492 u32 regval; sunxi_pinctrl_gpio_set() local
496 regval = readl(pctl->membase + reg); sunxi_pinctrl_gpio_set()
499 regval |= BIT(index); sunxi_pinctrl_gpio_set()
501 regval &= ~(BIT(index)); sunxi_pinctrl_gpio_set()
503 writel(regval, pctl->membase + reg); sunxi_pinctrl_gpio_set()
595 u32 regval; sunxi_pinctrl_irq_set_type() local
628 regval = readl(pctl->membase + reg); sunxi_pinctrl_irq_set_type()
629 regval &= ~(IRQ_CFG_IRQ_MASK << index); sunxi_pinctrl_irq_set_type()
630 writel(regval | (mode << index), pctl->membase + reg); sunxi_pinctrl_irq_set_type()
/linux-4.1.27/drivers/hwmon/pmbus/
H A Dpmbus_core.c666 u16 regval; pmbus_data2reg() local
670 regval = pmbus_data2reg_direct(data, sensor, val); pmbus_data2reg()
673 regval = pmbus_data2reg_vid(data, sensor, val); pmbus_data2reg()
677 regval = pmbus_data2reg_linear(data, sensor, val); pmbus_data2reg()
680 return regval; pmbus_data2reg()
714 u8 regval; pmbus_get_boolean() local
720 regval = status & mask; pmbus_get_boolean()
722 ret = !!regval; pmbus_get_boolean()
736 ret = !!(regval && v1 >= v2); pmbus_get_boolean()
777 u16 regval; pmbus_set_sensor() local
783 regval = pmbus_data2reg(data, sensor, val); pmbus_set_sensor()
784 ret = _pmbus_write_word_data(client, sensor->page, sensor->reg, regval); pmbus_set_sensor()
788 sensor->data = regval; pmbus_set_sensor()
1586 int regval; pmbus_add_fan_attributes() local
1600 regval = _pmbus_read_byte_data(client, page, pmbus_add_fan_attributes()
1602 if (regval < 0 || pmbus_add_fan_attributes()
1603 (!(regval & (PB_FAN_1_INSTALLED >> ((f & 1) * 4))))) pmbus_add_fan_attributes()
/linux-4.1.27/drivers/media/usb/stkwebcam/
H A Dstk-sensor.c282 struct regval *rv) stk_sensor_write_regvals()
310 static struct regval ov_initvals[] = {
400 static struct regval ov_fmt_uyvy[] = {
413 static struct regval ov_fmt_yuyv[] = {
427 static struct regval ov_fmt_rgbr[] = {
444 static struct regval ov_fmt_rgbp[] = {
461 static struct regval ov_fmt_bayer[] = {
509 struct regval *rv; stk_sensor_configure()
H A Dstk-webcam.h89 struct regval { struct
H A Dstk-webcam.c239 static struct regval stk1125_initvals[] = {
271 struct regval *rv; stk_initialise()
/linux-4.1.27/include/linux/fsl/bestcomm/
H A Dbestcomm_priv.h254 u16 regval; bcom_disable_prefetch() local
256 regval = in_be16(&bcom_eng->regs->PtdCntrl); bcom_disable_prefetch()
257 out_be16(&bcom_eng->regs->PtdCntrl, regval | 1); bcom_disable_prefetch()
/linux-4.1.27/drivers/pwm/
H A Dpwm-tiehrpwm.c154 unsigned short regval; ehrpwm_modify() local
156 regval = readw(base + offset); ehrpwm_modify()
157 regval &= ~mask; ehrpwm_modify()
158 regval |= val & mask; ehrpwm_modify()
159 writew(regval, base + offset); ehrpwm_modify()
/linux-4.1.27/drivers/media/usb/em28xx/
H A Dem28xx-input.c495 int regval; em28xx_query_buttons() local
502 regval = em28xx_read_reg(dev, dev->button_polling_addresses[i]); em28xx_query_buttons()
503 if (regval < 0) em28xx_query_buttons()
516 is_pressed = regval & button->mask; em28xx_query_buttons()
526 (~regval & button->mask) em28xx_query_buttons()
527 | (regval & ~button->mask)); em28xx_query_buttons()
558 dev->button_polling_last_values[i] = regval; em28xx_query_buttons()
/linux-4.1.27/drivers/memory/
H A Domap-gpmc.c1035 u32 regval; gpmc_configure() local
1047 regval = gpmc_read_reg(GPMC_CONFIG); gpmc_configure()
1049 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ gpmc_configure()
1051 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ gpmc_configure()
1052 gpmc_write_reg(GPMC_CONFIG, regval); gpmc_configure()
1119 u32 regval; gpmc_irq_endis() local
1123 regval = gpmc_read_reg(GPMC_IRQENABLE); gpmc_irq_endis()
1125 regval |= gpmc_client_irq[i].bitmask; gpmc_irq_endis()
1127 regval &= ~gpmc_client_irq[i].bitmask; gpmc_irq_endis()
1128 gpmc_write_reg(GPMC_IRQENABLE, regval); gpmc_irq_endis()
1152 u32 regval; gpmc_setup_irq() local
1187 regval = gpmc_read_reg(GPMC_IRQSTATUS); gpmc_setup_irq()
1188 gpmc_write_reg(GPMC_IRQSTATUS, regval); gpmc_setup_irq()
2232 u32 regval; gpmc_handle_irq() local
2234 regval = gpmc_read_reg(GPMC_IRQSTATUS); gpmc_handle_irq()
2236 if (!regval) gpmc_handle_irq()
2240 if (regval & gpmc_client_irq[i].bitmask) gpmc_handle_irq()
2243 gpmc_write_reg(GPMC_IRQSTATUS, regval); gpmc_handle_irq()
/linux-4.1.27/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet_main.c1204 u32 regval; axienet_ethtools_get_pauseparam() local
1207 regval = axienet_ior(lp, XAE_FCC_OFFSET); axienet_ethtools_get_pauseparam()
1208 epauseparm->tx_pause = regval & XAE_FCC_FCTX_MASK; axienet_ethtools_get_pauseparam()
1209 epauseparm->rx_pause = regval & XAE_FCC_FCRX_MASK; axienet_ethtools_get_pauseparam()
1226 u32 regval = 0; axienet_ethtools_set_pauseparam() local
1235 regval = axienet_ior(lp, XAE_FCC_OFFSET); axienet_ethtools_set_pauseparam()
1237 regval |= XAE_FCC_FCTX_MASK; axienet_ethtools_set_pauseparam()
1239 regval &= ~XAE_FCC_FCTX_MASK; axienet_ethtools_set_pauseparam()
1241 regval |= XAE_FCC_FCRX_MASK; axienet_ethtools_set_pauseparam()
1243 regval &= ~XAE_FCC_FCRX_MASK; axienet_ethtools_set_pauseparam()
1244 axienet_iow(lp, XAE_FCC_OFFSET, regval); axienet_ethtools_set_pauseparam()
1261 u32 regval = 0; axienet_ethtools_get_coalesce() local
1263 regval = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); axienet_ethtools_get_coalesce()
1264 ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK) axienet_ethtools_get_coalesce()
1266 regval = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); axienet_ethtools_get_coalesce()
1267 ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK) axienet_ethtools_get_coalesce()
/linux-4.1.27/drivers/pci/host/
H A Dpci-keystone-dw.c378 u32 regval; ks_pcie_cfg_setup() local
383 regval = (bus << 16) | (device << 8) | function; ks_pcie_cfg_setup()
391 regval |= BIT(24); ks_pcie_cfg_setup()
393 writel(regval, ks_pcie->va_app_base + CFG_SETUP); ks_pcie_cfg_setup()
/linux-4.1.27/drivers/ata/
H A Dsata_nv.c1895 u8 regval; nv_swncq_host_init() local
1898 pci_read_config_byte(pdev, 0x7f, &regval); nv_swncq_host_init()
1899 regval &= ~(1 << 7); nv_swncq_host_init()
1900 pci_write_config_byte(pdev, 0x7f, regval); nv_swncq_host_init()
2410 u8 regval; nv_init_one() local
2412 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval); nv_init_one()
2413 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; nv_init_one()
2414 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); nv_init_one()
2447 u8 regval; nv_pci_device_resume() local
2449 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval); nv_pci_device_resume()
2450 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; nv_pci_device_resume()
2451 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); nv_pci_device_resume()
2487 u8 regval; nv_ck804_host_stop() local
2490 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval); nv_ck804_host_stop()
2491 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN; nv_ck804_host_stop()
2492 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); nv_ck804_host_stop()
/linux-4.1.27/drivers/net/ethernet/intel/e1000e/
H A Dich8lan.c75 u16 regval; member in union:ich8_hws_flash_status
88 u16 regval; member in union:ich8_hws_flash_ctrl
99 u16 regval; member in union:ich8_hws_flash_regacc
112 u32 regval; member in union:ich8_flash_protected_range
3259 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); e1000_flash_cycle_init_ich8lan()
3271 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); e1000_flash_cycle_init_ich8lan()
3273 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); e1000_flash_cycle_init_ich8lan()
3290 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); e1000_flash_cycle_init_ich8lan()
3292 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); e1000_flash_cycle_init_ich8lan()
3301 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); e1000_flash_cycle_init_ich8lan()
3315 hsfsts.regval & 0xFFFF); e1000_flash_cycle_init_ich8lan()
3317 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); e1000_flash_cycle_init_ich8lan()
3341 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; e1000_flash_cycle_ich8lan()
3343 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); e1000_flash_cycle_ich8lan()
3347 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); e1000_flash_cycle_ich8lan()
3349 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); e1000_flash_cycle_ich8lan()
3353 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); e1000_flash_cycle_ich8lan()
3462 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); e1000_read_flash_data_ich8lan()
3466 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); e1000_read_flash_data_ich8lan()
3492 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); e1000_read_flash_data_ich8lan()
3539 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; e1000_read_flash_data32_ich8lan()
3547 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); e1000_read_flash_data32_ich8lan()
3568 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); e1000_read_flash_data32_ich8lan()
4006 pr0.regval = er32flash(ICH_FLASH_PR0); e1000e_write_protect_nvm_ich8lan()
4010 ew32flash(ICH_FLASH_PR0, pr0.regval); e1000e_write_protect_nvm_ich8lan()
4017 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); e1000e_write_protect_nvm_ich8lan()
4019 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); e1000e_write_protect_nvm_ich8lan()
4064 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; e1000_write_flash_data_ich8lan()
4066 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); e1000_write_flash_data_ich8lan()
4076 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); e1000_write_flash_data_ich8lan()
4078 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); e1000_write_flash_data_ich8lan()
4103 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); e1000_write_flash_data_ich8lan()
4150 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) e1000_write_flash_data32_ich8lan()
4153 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); e1000_write_flash_data32_ich8lan()
4163 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); e1000_write_flash_data32_ich8lan()
4165 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); e1000_write_flash_data32_ich8lan()
4186 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); e1000_write_flash_data32_ich8lan()
4302 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); e1000_erase_flash_bank_ich8lan()
4355 hsflctl.regval = e1000_erase_flash_bank_ich8lan()
4358 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); e1000_erase_flash_bank_ich8lan()
4363 hsflctl.regval << 16); e1000_erase_flash_bank_ich8lan()
4365 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); e1000_erase_flash_bank_ich8lan()
4382 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); e1000_erase_flash_bank_ich8lan()
H A Dnetdev.c3587 u32 regval; e1000e_config_hwtstamp() local
3684 regval = er32(TSYNCTXCTL); e1000e_config_hwtstamp()
3685 regval &= ~E1000_TSYNCTXCTL_ENABLED; e1000e_config_hwtstamp()
3686 regval |= tsync_tx_ctl; e1000e_config_hwtstamp()
3687 ew32(TSYNCTXCTL, regval); e1000e_config_hwtstamp()
3689 (regval & E1000_TSYNCTXCTL_ENABLED)) { e1000e_config_hwtstamp()
3695 regval = er32(TSYNCRXCTL); e1000e_config_hwtstamp()
3696 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); e1000e_config_hwtstamp()
3697 regval |= tsync_rx_ctl; e1000e_config_hwtstamp()
3698 ew32(TSYNCRXCTL, regval); e1000e_config_hwtstamp()
3701 (regval & (E1000_TSYNCRXCTL_ENABLED | e1000e_config_hwtstamp()
3728 ret_val = e1000e_get_base_timinca(adapter, &regval); e1000e_config_hwtstamp()
3731 ew32(TIMINCA, regval); e1000e_config_hwtstamp()
/linux-4.1.27/drivers/irqchip/
H A Dirq-mips-gic.c58 unsigned int regval; gic_update_bits() local
60 regval = gic_read(reg); gic_update_bits()
61 regval &= ~mask; gic_update_bits()
62 regval |= val; gic_update_bits()
63 gic_write(reg, regval); gic_update_bits()
/linux-4.1.27/drivers/net/phy/
H A Dmicrel.c471 int regval; ksz8873mll_read_status() local
474 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); ksz8873mll_read_status()
476 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); ksz8873mll_read_status()
478 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) ksz8873mll_read_status()
483 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) ksz8873mll_read_status()
/linux-4.1.27/drivers/net/wireless/brcm80211/brcmsmac/
H A Dmain.h52 * regval = R_REG(osh, &regs->regfoo);
53 * field = GFIELD(regval, <NAME>);
54 * regval = SFIELD(regval, <NAME>, 1);
55 * W_REG(osh, &regs->regfoo, regval);
/linux-4.1.27/drivers/pinctrl/
H A Dpinctrl-tegra-xusb.c369 u32 regval; tegra_xusb_padctl_pinconf_group_set() local
383 regval = padctl_readl(padctl, lane->offset); tegra_xusb_padctl_pinconf_group_set()
386 regval &= ~BIT(lane->iddq); tegra_xusb_padctl_pinconf_group_set()
388 regval |= BIT(lane->iddq); tegra_xusb_padctl_pinconf_group_set()
390 padctl_writel(padctl, regval, lane->offset); tegra_xusb_padctl_pinconf_group_set()
H A Dpinctrl-u300.c936 u16 regval, val, mask; u300_pmx_endisable() local
949 regval = readw(upmx->virtbase + u300_pmx_registers[i]); u300_pmx_endisable()
950 regval &= ~mask; u300_pmx_endisable()
951 regval |= val; u300_pmx_endisable()
952 writew(regval, upmx->virtbase + u300_pmx_registers[i]); u300_pmx_endisable()
/linux-4.1.27/drivers/rapidio/devices/
H A Dtsi721.c376 u32 regval; tsi721_dbell_handler() local
379 regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); tsi721_dbell_handler()
380 regval &= ~TSI721_SR_CHINT_IDBQRCV; tsi721_dbell_handler()
381 iowrite32(regval, tsi721_dbell_handler()
398 u32 regval; tsi721_db_dpc() local
447 regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); tsi721_db_dpc()
448 regval |= TSI721_SR_CHINT_IDBQRCV; tsi721_db_dpc()
449 iowrite32(regval, tsi721_db_dpc()
889 u32 regval; tsi721_rio_map_inb_mem() local
897 regval = ioread32(priv->regs + TSI721_IBWIN_LB(i)); tsi721_rio_map_inb_mem()
898 if (!(regval & TSI721_IBWIN_LB_WEN)) tsi721_rio_map_inb_mem()
936 u32 regval; tsi721_rio_unmap_inb_mem() local
940 regval = ioread32(priv->regs + TSI721_IBWIN_LB(i)); tsi721_rio_unmap_inb_mem()
941 if (regval & TSI721_IBWIN_LB_WEN) { tsi721_rio_unmap_inb_mem()
942 regval = ioread32(priv->regs + TSI721_IBWIN_TUA(i)); tsi721_rio_unmap_inb_mem()
943 addr = (u64)regval << 32; tsi721_rio_unmap_inb_mem()
944 regval = ioread32(priv->regs + TSI721_IBWIN_TLA(i)); tsi721_rio_unmap_inb_mem()
945 addr |= regval & TSI721_IBWIN_TLA_ADD; tsi721_rio_unmap_inb_mem()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192ce/
H A Dphy.c98 u16 regval; rtl92c_phy_bb_config() local
103 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); rtl92c_phy_bb_config()
105 regval | BIT(13) | BIT(0) | BIT(1)); rtl92c_phy_bb_config()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192cu/
H A Dphy.c126 u16 regval; rtl92cu_phy_bb_config() local
131 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); rtl92cu_phy_bb_config()
132 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) | rtl92cu_phy_bb_config()
/linux-4.1.27/drivers/staging/rtl8188eu/hal/
H A Dbb_cfg.c709 u32 regval; rtl88eu_phy_bb_config() local
715 regval = usb_read16(adapt, REG_SYS_FUNC_EN); rtl88eu_phy_bb_config()
716 usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval|BIT13|BIT0|BIT1)); rtl88eu_phy_bb_config()
/linux-4.1.27/sound/oss/
H A Dsb_mixer.c235 static void oss_change_bits(sb_devc *devc, unsigned char *regval, int dev, int chn, int newval) oss_change_bits() argument
245 *regval &= ~(mask << shift); /* Mask out previous value */ oss_change_bits()
246 *regval |= (newval & mask) << shift; /* Set the new value */ oss_change_bits()
H A Dad1848.c459 static void oss_change_bits(ad1848_info *devc, unsigned char *regval, oss_change_bits() argument
488 *regval &= ~(mask << shift); /* Clear bits */ oss_change_bits()
489 *regval |= (newval & mask) << shift; /* Set new value */ oss_change_bits()
/linux-4.1.27/drivers/iio/magnetometer/
H A Dak8975.c426 u8 regval; ak8975_set_mode() local
429 regval = (data->cntl_cache & ~data->def->ctrl_masks[CNTL_MODE]) | ak8975_set_mode()
432 data->def->ctrl_regs[CNTL], regval); ak8975_set_mode()
436 data->cntl_cache = regval; ak8975_set_mode()
/linux-4.1.27/drivers/media/usb/stk1160/
H A Dstk1160.h171 struct regval { struct
H A Dstk1160-v4l.c58 static struct regval std525[] = { stk1160_set_std()
77 static struct regval std625[] = { stk1160_set_std()
H A Dstk1160-core.c133 static const struct regval ctl[] = { stk1160_reg_reset()
/linux-4.1.27/drivers/spmi/
H A Dspmi-pmic-arb.c818 u32 regval; spmi_pmic_arb_probe() local
849 regval = readl_relaxed(core + PMIC_ARB_REG_CHNL(chan)); spmi_pmic_arb_probe()
850 if (!regval) spmi_pmic_arb_probe()
853 ppid = (regval >> 8) & 0xFFF; spmi_pmic_arb_probe()
/linux-4.1.27/drivers/mmc/host/
H A Domap_hsmmc.c529 unsigned long regval; omap_hsmmc_set_clock() local
537 regval = OMAP_HSMMC_READ(host->base, SYSCTL); omap_hsmmc_set_clock()
538 regval = regval & ~(CLKD_MASK | DTO_MASK); omap_hsmmc_set_clock()
540 regval = regval | (clkdiv << 6) | (DTO << 16); omap_hsmmc_set_clock()
541 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); omap_hsmmc_set_clock()
564 regval = OMAP_HSMMC_READ(host->base, HCTL); omap_hsmmc_set_clock()
566 regval |= HSPE; omap_hsmmc_set_clock()
568 regval &= ~HSPE; omap_hsmmc_set_clock()
570 OMAP_HSMMC_WRITE(host->base, HCTL, regval); omap_hsmmc_set_clock()
/linux-4.1.27/drivers/net/ethernet/adi/
H A Dbfin_mac.c857 u64 regval; bfin_tx_hwtstamp() local
859 regval = bfin_read_EMAC_PTP_TXSNAPLO(); bfin_tx_hwtstamp()
860 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32; bfin_tx_hwtstamp()
862 ns = regval << lp->shift; bfin_tx_hwtstamp()
873 u64 regval, ns; bfin_rx_hwtstamp() local
885 regval = bfin_read_EMAC_PTP_RXSNAPLO(); bfin_rx_hwtstamp()
886 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32; bfin_rx_hwtstamp()
887 ns = regval << lp->shift; bfin_rx_hwtstamp()
/linux-4.1.27/drivers/net/ethernet/amd/
H A Dsunlance.c468 u16 regval = 0; init_restart_lance() local
479 regval = sbus_readw(lp->lregs + RDP); init_restart_lance()
481 if (regval & (LE_C0_ERR | LE_C0_IDON)) init_restart_lance()
485 if (i == 100 || (regval & LE_C0_ERR)) { init_restart_lance()
487 i, regval); init_restart_lance()
928 u32 regval = lp->init_block_dvma & 0xff000000; lance_open() local
930 sbus_writel(regval, lp->dregs + DMA_TEST); lance_open()
1383 lp->busmaster_regval = of_getintprop_default(dp, "busmaster-regval", sparc_lance_probe_one()
/linux-4.1.27/drivers/tty/serial/
H A Dxilinx_uartps.c558 unsigned int regval; cdns_uart_stop_tx() local
560 regval = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_stop_tx()
561 regval |= CDNS_UART_CR_TX_DIS; cdns_uart_stop_tx()
563 writel(regval, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_stop_tx()
572 unsigned int regval; cdns_uart_stop_rx() local
574 regval = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_stop_rx()
575 regval |= CDNS_UART_CR_RX_DIS; cdns_uart_stop_rx()
577 writel(regval, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_stop_rx()
H A Dip22zilog.c139 unsigned char regval; ip22zilog_clear_fifo() local
141 regval = readb(&channel->control); ip22zilog_clear_fifo()
143 if (regval & Rx_CH_AV) ip22zilog_clear_fifo()
146 regval = read_zsreg(channel, R1); ip22zilog_clear_fifo()
150 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) { ip22zilog_clear_fifo()
H A Dsunzilog.c156 unsigned char regval; sunzilog_clear_fifo() local
158 regval = readb(&channel->control); sunzilog_clear_fifo()
160 if (regval & Rx_CH_AV) sunzilog_clear_fifo()
163 regval = read_zsreg(channel, R1); sunzilog_clear_fifo()
167 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) { sunzilog_clear_fifo()
/linux-4.1.27/drivers/net/wireless/ath/ath5k/
H A Dreset.c450 u32 regval; ath5k_hw_wisoc_reset() local
478 regval = ioread32(reg); ath5k_hw_wisoc_reset()
479 iowrite32(regval | val, reg); ath5k_hw_wisoc_reset()
480 regval = ioread32(reg); ath5k_hw_wisoc_reset()
484 iowrite32(regval & ~val, reg); ath5k_hw_wisoc_reset()
485 regval = ioread32(reg); ath5k_hw_wisoc_reset()
/linux-4.1.27/arch/m68k/ifpsp060/src/
H A Dilsp.S798 mov.l 0x8(%a6), %d2 # get regval
817 mov.l 0x8(%a6), %d2 # get regval
836 mov.l 0x8(%a6), %d2 # get regval
852 mov.l 0x8(%a6), %d2 # get regval
875 mov.l 0x8(%a6), %d2 # get regval
898 mov.l 0x8(%a6), %d2 # get regval
H A Disp.S1901 mov.l (EXC_DREGS,%a6,%d0.w*4), %d2 # get regval
/linux-4.1.27/sound/soc/
H A Dsoc-ops.c846 unsigned int regval; snd_soc_get_xr_sx() local
851 ret = snd_soc_component_read(component, regbase+i, &regval); snd_soc_get_xr_sx()
854 val |= (regval & regwmask) << (regwshift*(regcount-i-1)); snd_soc_get_xr_sx()
894 unsigned int i, regval, regmask; snd_soc_put_xr_sx() local
901 regval = (val >> (regwshift*(regcount-i-1))) & regwmask; snd_soc_put_xr_sx()
904 regmask, regval); snd_soc_put_xr_sx()
/linux-4.1.27/virt/kvm/arm/
H A Dvgic.c399 u32 regval; vgic_reg_access() local
407 regval = *reg; vgic_reg_access()
410 regval = 0; vgic_reg_access()
420 regval |= data; vgic_reg_access()
424 regval &= ~data; vgic_reg_access()
428 regval = (regval & ~(mask << word_offset)) | data; vgic_reg_access()
431 *reg = regval; vgic_reg_access()
435 regval = 0; vgic_reg_access()
439 mmio_data_write(mmio, mask, regval >> word_offset); vgic_reg_access()
/linux-4.1.27/drivers/thermal/ti-soc-thermal/
H A Dti-bandgap.c957 bgp->regval[id].data = data; ti_bandgap_set_sensor_data()
976 return bgp->regval[id].data; ti_bandgap_get_sensor_data()
1230 bgp->regval = devm_kzalloc(&pdev->dev, sizeof(*bgp->regval) * ti_bandgap_build()
1232 if (!bgp->regval) { ti_bandgap_build()
1488 rval = &bgp->regval[i]; ti_bandgap_save_ctxt()
1521 rval = &bgp->regval[i]; ti_bandgap_restore_ctxt()
H A Dti-bandgap.h227 * @regval: temperature sensor register values
243 struct temp_sensor_regval *regval; member in struct:ti_bandgap
/linux-4.1.27/drivers/net/ethernet/broadcom/
H A Dsb1250-mac.c441 int regval; sbmac_mii_read() local
489 regval = 0; sbmac_mii_read()
492 regval <<= 1; sbmac_mii_read()
496 regval |= 1; sbmac_mii_read()
508 return regval; sbmac_mii_read()
514 * SBMAC_MII_WRITE(bus, phyaddr, regidx, regval)
522 * regval - data to write to register
529 u16 regval) sbmac_mii_write()
542 sbmac_mii_senddata(sbm_mdio, regval, 16); sbmac_mii_write()
528 sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, u16 regval) sbmac_mii_write() argument
/linux-4.1.27/drivers/staging/netlogic/
H A Dxlr_net.c341 u32 regval; xlr_set_rx_mode() local
343 regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG); xlr_set_rx_mode()
346 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) | xlr_set_rx_mode()
351 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) | xlr_set_rx_mode()
355 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval); xlr_set_rx_mode()
/linux-4.1.27/drivers/gpu/ipu-v3/
H A Dipu-common.c357 u32 bursts, regval; ipu_idmac_lock_enable() local
387 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); ipu_idmac_lock_enable()
388 regval &= ~(0x03 << idmac_lock_en_info[i].shift); ipu_idmac_lock_enable()
389 regval |= (bursts << idmac_lock_en_info[i].shift); ipu_idmac_lock_enable()
390 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); ipu_idmac_lock_enable()
/linux-4.1.27/drivers/net/usb/
H A Dsmsc95xx.c224 int idx, int regval, int in_pm) __smsc95xx_mdio_write()
239 val = regval; __smsc95xx_mdio_write()
273 int idx, int regval) smsc95xx_mdio_write_nopm()
275 __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 1); smsc95xx_mdio_write_nopm()
284 int regval) smsc95xx_mdio_write()
286 __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 0); smsc95xx_mdio_write()
223 __smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx, int regval, int in_pm) __smsc95xx_mdio_write() argument
272 smsc95xx_mdio_write_nopm(struct net_device *netdev, int phy_id, int idx, int regval) smsc95xx_mdio_write_nopm() argument
283 smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx, int regval) smsc95xx_mdio_write() argument
H A Dsmsc75xx.c233 int idx, int regval, int in_pm) __smsc75xx_mdio_write()
248 val = regval; __smsc75xx_mdio_write()
284 int idx, int regval) smsc75xx_mdio_write_nopm()
286 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1); smsc75xx_mdio_write_nopm()
295 int regval) smsc75xx_mdio_write()
297 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0); smsc75xx_mdio_write()
232 __smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx, int regval, int in_pm) __smsc75xx_mdio_write() argument
283 smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id, int idx, int regval) smsc75xx_mdio_write_nopm() argument
294 smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx, int regval) smsc75xx_mdio_write() argument
/linux-4.1.27/drivers/net/ethernet/sun/
H A Dsunbmac.c102 u32 regval; qec_init() local
108 regval = GLOB_CTRL_B32; qec_init()
110 regval = GLOB_CTRL_B16; qec_init()
111 sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL); qec_init()
/linux-4.1.27/drivers/net/wireless/brcm80211/brcmsmac/phy/
H A Dphy_n.c15098 u16 regval[4]; wlc_phy_adjust_lnagaintbl_nphy() local
15131 regval[0] = nphy_def_lnagains[2] + gain_delta[core]; wlc_phy_adjust_lnagaintbl_nphy()
15132 regval[1] = nphy_def_lnagains[3] + gain_delta[core]; wlc_phy_adjust_lnagaintbl_nphy()
15133 regval[2] = nphy_def_lnagains[3] + gain_delta[core]; wlc_phy_adjust_lnagaintbl_nphy()
15134 regval[3] = nphy_def_lnagains[3] + gain_delta[core]; wlc_phy_adjust_lnagaintbl_nphy()
15137 regval[ctr] = wlc_phy_adjust_lnagaintbl_nphy()
15141 wlc_phy_table_write_nphy(pi, core, 4, 8, 16, regval); wlc_phy_adjust_lnagaintbl_nphy()
15596 u16 regval[21]; wlc_phy_workarounds_nphy_gainctrl() local
16022 regval[ctr] = (hpf_code << 8) | 0x7c; wlc_phy_workarounds_nphy_gainctrl()
16023 wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval); wlc_phy_workarounds_nphy_gainctrl()
16028 regval[0] = 0; wlc_phy_workarounds_nphy_gainctrl()
16029 regval[1] = 1; wlc_phy_workarounds_nphy_gainctrl()
16030 regval[2] = 1; wlc_phy_workarounds_nphy_gainctrl()
16031 regval[3] = 1; wlc_phy_workarounds_nphy_gainctrl()
16032 wlc_phy_table_write_nphy(pi, 2, 4, 8, 16, regval); wlc_phy_workarounds_nphy_gainctrl()
16033 wlc_phy_table_write_nphy(pi, 3, 4, 8, 16, regval); wlc_phy_workarounds_nphy_gainctrl()
16036 regval[ctr] = (hpf_code << 8) | 0x74; wlc_phy_workarounds_nphy_gainctrl()
16037 wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval); wlc_phy_workarounds_nphy_gainctrl()
16042 regval[ctr] = 3 * ctr; wlc_phy_workarounds_nphy_gainctrl()
16043 wlc_phy_table_write_nphy(pi, 0, 21, 32, 16, regval); wlc_phy_workarounds_nphy_gainctrl()
16044 wlc_phy_table_write_nphy(pi, 1, 21, 32, 16, regval); wlc_phy_workarounds_nphy_gainctrl()
16047 regval[ctr] = (u16) ctr; wlc_phy_workarounds_nphy_gainctrl()
16048 wlc_phy_table_write_nphy(pi, 2, 21, 32, 16, regval); wlc_phy_workarounds_nphy_gainctrl()
16049 wlc_phy_table_write_nphy(pi, 3, 21, 32, 16, regval); wlc_phy_workarounds_nphy_gainctrl()
16148 u16 regval; wlc_phy_workarounds_nphy() local
17054 regval = 0x000a; wlc_phy_workarounds_nphy()
17055 wlc_phy_table_write_nphy(pi, 8, 1, 0, 16, &regval); wlc_phy_workarounds_nphy()
17056 wlc_phy_table_write_nphy(pi, 8, 1, 0x10, 16, &regval); wlc_phy_workarounds_nphy()
17059 regval = 0xcdaa; wlc_phy_workarounds_nphy()
17060 wlc_phy_table_write_nphy(pi, 8, 1, 0x02, 16, &regval); wlc_phy_workarounds_nphy()
17061 wlc_phy_table_write_nphy(pi, 8, 1, 0x12, 16, &regval); wlc_phy_workarounds_nphy()
17065 regval = 0x0000; wlc_phy_workarounds_nphy()
17066 wlc_phy_table_write_nphy(pi, 8, 1, 0x08, 16, &regval); wlc_phy_workarounds_nphy()
17067 wlc_phy_table_write_nphy(pi, 8, 1, 0x18, 16, &regval); wlc_phy_workarounds_nphy()
17069 regval = 0x7aab; wlc_phy_workarounds_nphy()
17070 wlc_phy_table_write_nphy(pi, 8, 1, 0x07, 16, &regval); wlc_phy_workarounds_nphy()
17071 wlc_phy_table_write_nphy(pi, 8, 1, 0x17, 16, &regval); wlc_phy_workarounds_nphy()
17073 regval = 0x0800; wlc_phy_workarounds_nphy()
17074 wlc_phy_table_write_nphy(pi, 8, 1, 0x06, 16, &regval); wlc_phy_workarounds_nphy()
17075 wlc_phy_table_write_nphy(pi, 8, 1, 0x16, 16, &regval); wlc_phy_workarounds_nphy()
17673 u32 regval[64]; wlc_phy_txpwrctrl_pwr_setup_nphy() local
17858 regval[idx] = (u32) pwr_est; wlc_phy_txpwrctrl_pwr_setup_nphy()
17861 regval); wlc_phy_txpwrctrl_pwr_setup_nphy()
18899 u32 regval[128]; wlc_phy_txpwrctrl_coeff_setup_nphy() local
18918 regval[idx] = iqcomp; wlc_phy_txpwrctrl_coeff_setup_nphy()
18920 regval); wlc_phy_txpwrctrl_coeff_setup_nphy()
18946 regval[idx] = curr_locomp; wlc_phy_txpwrctrl_coeff_setup_nphy()
18949 regval); wlc_phy_txpwrctrl_coeff_setup_nphy()
19078 u16 regval; wlc_phy_adjust_crsminpwr_nphy() local
19084 regval = read_phy_reg(pi, 0x27d); wlc_phy_adjust_crsminpwr_nphy()
19085 pi->nphy_crsminpwr[0] = regval & 0xff; wlc_phy_adjust_crsminpwr_nphy()
19086 regval &= 0xff00; wlc_phy_adjust_crsminpwr_nphy()
19087 regval |= (u16) minpwr; wlc_phy_adjust_crsminpwr_nphy()
19088 write_phy_reg(pi, 0x27d, regval); wlc_phy_adjust_crsminpwr_nphy()
19090 regval = read_phy_reg(pi, 0x280); wlc_phy_adjust_crsminpwr_nphy()
19091 pi->nphy_crsminpwr[1] = regval & 0xff; wlc_phy_adjust_crsminpwr_nphy()
19092 regval &= 0xff00; wlc_phy_adjust_crsminpwr_nphy()
19093 regval |= (u16) minpwr; wlc_phy_adjust_crsminpwr_nphy()
19094 write_phy_reg(pi, 0x280, regval); wlc_phy_adjust_crsminpwr_nphy()
19096 regval = read_phy_reg(pi, 0x283); wlc_phy_adjust_crsminpwr_nphy()
19097 pi->nphy_crsminpwr[2] = regval & 0xff; wlc_phy_adjust_crsminpwr_nphy()
19098 regval &= 0xff00; wlc_phy_adjust_crsminpwr_nphy()
19099 regval |= (u16) minpwr; wlc_phy_adjust_crsminpwr_nphy()
19100 write_phy_reg(pi, 0x283, regval); wlc_phy_adjust_crsminpwr_nphy()
19106 regval = read_phy_reg(pi, 0x27d); wlc_phy_adjust_crsminpwr_nphy()
19107 regval &= 0xff00; wlc_phy_adjust_crsminpwr_nphy()
19108 regval |= pi->nphy_crsminpwr[0]; wlc_phy_adjust_crsminpwr_nphy()
19109 write_phy_reg(pi, 0x27d, regval); wlc_phy_adjust_crsminpwr_nphy()
19111 regval = read_phy_reg(pi, 0x280); wlc_phy_adjust_crsminpwr_nphy()
19112 regval &= 0xff00; wlc_phy_adjust_crsminpwr_nphy()
19113 regval |= pi->nphy_crsminpwr[1]; wlc_phy_adjust_crsminpwr_nphy()
19114 write_phy_reg(pi, 0x280, regval); wlc_phy_adjust_crsminpwr_nphy()
19116 regval = read_phy_reg(pi, 0x283); wlc_phy_adjust_crsminpwr_nphy()
19117 regval &= 0xff00; wlc_phy_adjust_crsminpwr_nphy()
19118 regval |= pi->nphy_crsminpwr[2]; wlc_phy_adjust_crsminpwr_nphy()
19119 write_phy_reg(pi, 0x283, regval); wlc_phy_adjust_crsminpwr_nphy()
19734 u16 regval; wlc_phy_rxcore_setstate_nphy() local
19754 regval = read_phy_reg(pi, 0xa2); wlc_phy_rxcore_setstate_nphy()
19755 regval &= ~(0xf << 4); wlc_phy_rxcore_setstate_nphy()
19756 regval |= ((u16) (rxcore_bitmask & 0x3)) << 4; wlc_phy_rxcore_setstate_nphy()
19757 write_phy_reg(pi, 0xa2, regval); wlc_phy_rxcore_setstate_nphy()
19814 u16 regval, rxen_bits; wlc_phy_rxcore_getstate_nphy() local
19817 regval = read_phy_reg(pi, 0xa2); wlc_phy_rxcore_getstate_nphy()
19818 rxen_bits = (regval >> 4) & 0xf; wlc_phy_rxcore_getstate_nphy()
28294 u16 regval[84]; wlc_phy_txpwrctrl_enable_nphy() local
28325 regval[ctr] = 0; wlc_phy_txpwrctrl_enable_nphy()
28327 regval); wlc_phy_txpwrctrl_enable_nphy()
28329 regval); wlc_phy_txpwrctrl_enable_nphy()
28446 u16 regval[2]; wlc_phy_txpwr_index_nphy() local
28609 regval[0] = (u16) iqcomp_a; wlc_phy_txpwr_index_nphy()
28610 regval[1] = (u16) iqcomp_b; wlc_phy_txpwr_index_nphy()
28613 regval); wlc_phy_txpwr_index_nphy()
/linux-4.1.27/drivers/staging/iio/
H A Diio_simple_dummy.c45 * @regval: register value - magic device specific numbers.
50 int regval; /* what would be written to hardware */ member in struct:iio_dummy_accel_calibscale
/linux-4.1.27/drivers/clk/st/
H A Dclkgen-mux.c85 u32 regval = readl(mux->feedback_reg[mux->muxsel]); clkgena_divmux_is_running() local
86 u32 running = regval & BIT(mux->feedback_bit_idx); clkgena_divmux_is_running()
/linux-4.1.27/drivers/media/tuners/
H A Dxc5000.c672 u16 regval; xc_debug_dump() local
714 xc5000_readreg(priv, priv->pll_register_no, &regval); xc_debug_dump()
715 dprintk(1, "*** PLL lock status = 0x%04x\n", regval); xc_debug_dump()
/linux-4.1.27/drivers/net/wireless/b43/
H A Dphy_ht.c730 u32 regval[64]; b43_phy_ht_tx_power_ctl_setup() local
736 regval[i] = pwr; b43_phy_ht_tx_power_ctl_setup()
738 b43_httab_write_bulk(dev, B43_HTTAB16(26 + c, 0), 64, regval); b43_phy_ht_tx_power_ctl_setup()
H A Dphy_n.c4066 u32 regval[64]; b43_nphy_tx_power_ctl_setup() local
4216 regval[i] = pwr; b43_nphy_tx_power_ctl_setup()
4218 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval); b43_nphy_tx_power_ctl_setup()
/linux-4.1.27/drivers/net/wireless/brcm80211/brcmfmac/
H A Dsdio.c181 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
182 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
183 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
184 #define SBSDIO_CLKAV(regval, alponly) \
185 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
755 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset) w_sdreg32() argument
761 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret); w_sdreg32()
/linux-4.1.27/sound/isa/opti9xx/
H A Dmiro.c1206 unsigned char regval; snd_card_miro_aci_detect() local
1216 regval=inb(miro->mc_base + 4); snd_card_miro_aci_detect()
1217 aci->aci_port = (regval & 0x10) ? 0x344 : 0x354; snd_card_miro_aci_detect()
/linux-4.1.27/drivers/usb/gadget/udc/
H A Datmel_usba_udc.c1104 u32 regval; set_address() local
1107 regval = usba_readl(udc, CTRL); set_address()
1108 regval = USBA_BFINS(DEV_ADDR, addr, regval); set_address()
1109 usba_writel(udc, CTRL, regval); set_address()
/linux-4.1.27/drivers/usb/serial/
H A Dmos7840.c453 __u8 regval = 0x0; mos7840_control_callback() local
477 regval = (__u8) data[0]; mos7840_control_callback()
478 dev_dbg(dev, "%s data is %x\n", __func__, regval); mos7840_control_callback()
480 mos7840_handle_new_msr(mos7840_port, regval); mos7840_control_callback()
482 mos7840_handle_new_lsr(mos7840_port, regval); mos7840_control_callback()
/linux-4.1.27/drivers/scsi/pm8001/
H A Dpm80xx_hwi.c1190 u32 regval; pm80xx_chip_soft_rst() local
1202 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); pm80xx_chip_soft_rst()
1204 pm8001_printk("reset register before write : 0x%x\n", regval)); pm80xx_chip_soft_rst()
1209 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); pm80xx_chip_soft_rst()
1211 pm8001_printk("reset register after write 0x%x\n", regval)); pm80xx_chip_soft_rst()
1213 if ((regval & SPCv_SOFT_RESET_READ_MASK) == pm80xx_chip_soft_rst()
1216 pm8001_printk(" soft reset successful [regval: 0x%x]\n", pm80xx_chip_soft_rst()
1217 regval)); pm80xx_chip_soft_rst()
1220 pm8001_printk(" soft reset failed [regval: 0x%x]\n", pm80xx_chip_soft_rst()
1221 regval)); pm80xx_chip_soft_rst()
/linux-4.1.27/drivers/net/ethernet/natsemi/
H A Dnatsemi.c2725 u32 regval = readl(ioaddr + WOLCmd); netdev_get_wol() local
2737 if (regval & WakePhy) netdev_get_wol()
2739 if (regval & WakeUnicast) netdev_get_wol()
2741 if (regval & WakeMulticast) netdev_get_wol()
2743 if (regval & WakeBroadcast) netdev_get_wol()
2745 if (regval & WakeArp) netdev_get_wol()
2747 if (regval & WakeMagic) netdev_get_wol()
2749 if (regval & WakeMagicSecure) { netdev_get_wol()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8188ee/
H A Dphy.c259 u16 regval; rtl88e_phy_bb_config() local
263 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); rtl88e_phy_bb_config()
265 regval | BIT(13) | BIT(0) | BIT(1)); rtl88e_phy_bb_config()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723be/
H A Dphy.c122 u16 regval; rtl8723be_phy_bb_config() local
127 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); rtl8723be_phy_bb_config()
129 regval | BIT(13) | BIT(0) | BIT(1)); rtl8723be_phy_bb_config()
/linux-4.1.27/drivers/net/wan/
H A Dfarsync.c682 unsigned int regval; fst_cpureset() local
714 regval = inl(card->pci_conf + CNTRL_9052); fst_cpureset()
716 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052); fst_cpureset()
717 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052); fst_cpureset()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8821ae/
H A Dphy.c327 u8 regval; rtl8821ae_phy_bb_config() local
332 regval = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); rtl8821ae_phy_bb_config()
333 regval |= FEN_PCIEA; rtl8821ae_phy_bb_config()
334 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, regval); rtl8821ae_phy_bb_config()
336 regval | FEN_BB_GLB_RSTN | FEN_BBRSTB); rtl8821ae_phy_bb_config()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192de/
H A Dphy.c756 u16 regval; rtl92d_phy_bb_config() local
761 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); rtl92d_phy_bb_config()
763 regval | BIT(13) | BIT(0) | BIT(1)); rtl92d_phy_bb_config()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192ee/
H A Dphy.c249 u16 regval; rtl92ee_phy_bb_config() local
254 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); rtl92ee_phy_bb_config()
256 regval | BIT(13) | BIT(0) | BIT(1)); rtl92ee_phy_bb_config()
/linux-4.1.27/drivers/net/ethernet/dec/tulip/
H A Dde4x5.c1997 u_char irq, regval; de4x5_eisa_probe() local
2028 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT); de4x5_eisa_probe()
2047 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0); de4x5_eisa_probe()
2049 irq = de4x5_irq[(regval >> 1) & 0x03]; de4x5_eisa_probe()
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4fw_api.h2922 __be32 regval; member in struct:fw_error_cmd::fw_error::fw_error_hwmodule
/linux-4.1.27/drivers/atm/
H A Diphase.c1028 // regval = readl((u32)ia_cmds->maddr); desc_dbg()

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