Searched refs:membase (Results 1 - 200 of 226) sorted by relevance

12

/linux-4.1.27/drivers/tty/serial/
H A Dbfin_sport_uart.h34 #define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
35 #define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
36 #define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
37 #define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
38 #define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
39 #define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
51 __ret = bfin_read32((sport)->port.membase + OFFSET_RX); \
56 #define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
57 #define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
58 #define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
59 #define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))
60 #define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT))
62 #define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
63 #define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
64 #define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
65 #define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
66 #define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)
67 #define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)
68 #define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
69 #define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
70 #define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
71 #define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
72 #define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v)
H A Dnetx-serial.c121 val = readl(port->membase + UART_CR); netx_stop_tx()
122 writel(val & ~CR_TIE, port->membase + UART_CR); netx_stop_tx()
128 val = readl(port->membase + UART_CR); netx_stop_rx()
129 writel(val & ~CR_RIE, port->membase + UART_CR); netx_stop_rx()
135 val = readl(port->membase + UART_CR); netx_enable_ms()
136 writel(val | CR_MSIE, port->membase + UART_CR); netx_enable_ms()
144 writel(port->x_char, port->membase + UART_DR); netx_transmit_buffer()
158 writel(xmit->buf[xmit->tail], port->membase + UART_DR); netx_transmit_buffer()
164 } while (!(readl(port->membase + UART_FR) & FR_TXFF)); netx_transmit_buffer()
173 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR); netx_start_tx()
175 if (!(readl(port->membase + UART_FR) & FR_TXFF)) netx_start_tx()
181 return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT; netx_tx_empty()
203 while (!(readl(port->membase + UART_FR) & FR_RXFE)) { netx_rxint()
204 rx = readl(port->membase + UART_DR); netx_rxint()
207 status = readl(port->membase + UART_SR); netx_rxint()
209 writel(0, port->membase + UART_SR); netx_rxint()
252 status = readl(port->membase + UART_IIR) & IIR_MASK; netx_int()
259 if (readl(port->membase + UART_FR) & FR_CTS) netx_int()
264 writel(0, port->membase + UART_IIR); netx_int()
265 status = readl(port->membase + UART_IIR) & IIR_MASK; netx_int()
276 if (readl(port->membase + UART_FR) & FR_CTS) netx_get_mctrl()
288 val = readl(port->membase + UART_RTS_CR); netx_set_mctrl()
289 writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR); netx_set_mctrl()
298 line_cr = readl(port->membase + UART_LINE_CR); netx_break_ctl()
303 writel(line_cr, port->membase + UART_LINE_CR); netx_break_ctl()
319 writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN, netx_startup()
320 port->membase + UART_LINE_CR); netx_startup()
323 port->membase + UART_CR); netx_startup()
331 writel(0, port->membase + UART_CR) ; netx_shutdown()
382 old_cr = readl(port->membase + UART_CR); netx_set_termios()
386 port->membase + UART_CR); netx_set_termios()
389 while (readl(port->membase + UART_FR) & FR_BUSY); netx_set_termios()
392 writel(old_cr & ~CR_UART_EN, port->membase + UART_CR); netx_set_termios()
399 writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB); netx_set_termios()
400 writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB); netx_set_termios()
401 writel(line_cr, port->membase + UART_LINE_CR); netx_set_termios()
403 writel(rts_cr, port->membase + UART_RTS_CR); netx_set_termios()
427 writel(old_cr, port->membase + UART_CR); netx_set_termios()
489 .membase = (char __iomem *)io_p2v(NETX_PA_UART0),
502 .membase = (char __iomem *)io_p2v(NETX_PA_UART1),
515 .membase = (char __iomem *)io_p2v(NETX_PA_UART2),
531 while (readl(port->membase + UART_FR) & FR_BUSY); netx_console_putchar()
532 writel(ch, port->membase + UART_DR); netx_console_putchar()
541 cr_save = readl(port->membase + UART_CR); netx_console_write()
542 writel(cr_save | CR_UART_EN, port->membase + UART_CR); netx_console_write()
546 while (readl(port->membase + UART_FR) & FR_BUSY); netx_console_write()
547 writel(cr_save, port->membase + UART_CR); netx_console_write()
556 *baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) | netx_console_get_options()
557 readl(port->membase + UART_BAUDDIV_LSB); netx_console_get_options()
564 line_cr = readl(port->membase + UART_LINE_CR); netx_console_get_options()
588 if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO) netx_console_get_options()
616 if (readl(sport->port.membase + UART_CR) & CR_UART_EN) { netx_console_setup()
687 writel(1, port->membase + UART_RXFIFO_IRQLEVEL); serial_netx_probe()
H A Dmcf.c66 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ? mcf_tx_empty()
77 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ? mcf_get_mctrl()
95 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); mcf_set_mctrl()
97 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0); mcf_set_mctrl()
108 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR); mcf_start_tx()
110 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); mcf_start_tx()
113 writeb(pp->imr, port->membase + MCFUART_UIMR); mcf_start_tx()
123 writeb(pp->imr, port->membase + MCFUART_UIMR); mcf_stop_tx()
133 writeb(pp->imr, port->membase + MCFUART_UIMR); mcf_stop_rx()
144 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR); mcf_break_ctl()
146 writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR); mcf_break_ctl()
160 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); mcf_startup()
161 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR); mcf_startup()
165 port->membase + MCFUART_UCR); mcf_startup()
169 writeb(pp->imr, port->membase + MCFUART_UIMR); mcf_startup()
187 writeb(pp->imr, port->membase + MCFUART_UIMR); mcf_shutdown()
190 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); mcf_shutdown()
191 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR); mcf_shutdown()
266 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); mcf_set_termios()
267 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR); mcf_set_termios()
268 writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR); mcf_set_termios()
269 writeb(mr1, port->membase + MCFUART_UMR); mcf_set_termios()
270 writeb(mr2, port->membase + MCFUART_UMR); mcf_set_termios()
271 writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1); mcf_set_termios()
272 writeb((baudclk & 0xff), port->membase + MCFUART_UBG2); mcf_set_termios()
274 writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD); mcf_set_termios()
277 port->membase + MCFUART_UCSR); mcf_set_termios()
279 port->membase + MCFUART_UCR); mcf_set_termios()
290 while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) { mcf_rx_chars()
291 ch = readb(port->membase + MCFUART_URB); mcf_rx_chars()
297 port->membase + MCFUART_UCR); mcf_rx_chars()
340 writeb(port->x_char, port->membase + MCFUART_UTB); mcf_tx_chars()
346 while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) { mcf_tx_chars()
349 writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB); mcf_tx_chars()
359 writeb(pp->imr, port->membase + MCFUART_UIMR); mcf_tx_chars()
363 port->membase + MCFUART_UCR); mcf_tx_chars()
376 isr = readb(port->membase + MCFUART_UISR) & pp->imr; mcf_interrupt()
400 writeb(0, port->membase + MCFUART_UIMR); mcf_config_port()
446 mr1 = readb(port->membase + MCFUART_UMR); mcf_config_rs485()
447 mr2 = readb(port->membase + MCFUART_UMR); mcf_config_rs485()
456 writeb(mr1, port->membase + MCFUART_UMR); mcf_config_rs485()
457 writeb(mr2, port->membase + MCFUART_UMR); mcf_config_rs485()
505 port->membase = (platp[i].membase) ? platp[i].membase : early_mcf_setup()
526 if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) mcf_console_putc()
529 writeb(c, port->membase + MCFUART_UTB); mcf_console_putc()
531 if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) mcf_console_putc()
560 if (port->membase == 0) mcf_console_setup()
630 port->membase = (platp[i].membase) ? platp[i].membase : mcf_probe()
H A Dfsl_lpuart.c289 temp = readb(port->membase + UARTCR2); lpuart_stop_tx()
291 writeb(temp, port->membase + UARTCR2); lpuart_stop_tx()
298 temp = lpuart32_read(port->membase + UARTCTRL); lpuart32_stop_tx()
300 lpuart32_write(temp, port->membase + UARTCTRL); lpuart32_stop_tx()
307 temp = readb(port->membase + UARTCR2); lpuart_stop_rx()
308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); lpuart_stop_rx()
315 temp = lpuart32_read(port->membase + UARTCTRL); lpuart32_stop_rx()
316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL); lpuart32_stop_rx()
353 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) { lpuart_pio_tx()
354 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); lpuart_pio_tx()
363 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS, lpuart_pio_tx()
364 sport->port.membase + UARTCR5); lpuart_pio_tx()
406 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS, lpuart_prepare_tx()
407 sport->port.membase + UARTCR5); lpuart_prepare_tx()
409 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS, lpuart_prepare_tx()
410 sport->port.membase + UARTCR5); lpuart_prepare_tx()
507 temp = readb(sport->port.membase + UARTCR5); lpuart_timer_func()
508 writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); lpuart_timer_func()
524 temp = readb(sport->port.membase + UARTCR5); lpuart_prepare_rx()
525 writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5); lpuart_prepare_rx()
535 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { lpuart_transmit_buffer()
536 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); lpuart_transmit_buffer()
553 txcnt = lpuart32_read(sport->port.membase + UARTWATER); lpuart32_transmit_buffer()
557 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA); lpuart32_transmit_buffer()
560 txcnt = lpuart32_read(sport->port.membase + UARTWATER); lpuart32_transmit_buffer()
579 temp = readb(port->membase + UARTCR2); lpuart_start_tx()
580 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); lpuart_start_tx()
586 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) lpuart_start_tx()
596 temp = lpuart32_read(port->membase + UARTCTRL); lpuart32_start_tx()
597 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL); lpuart32_start_tx()
599 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE) lpuart32_start_tx()
612 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA); lpuart_txint()
614 writeb(sport->port.x_char, sport->port.membase + UARTDR); lpuart_txint()
649 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { lpuart_rxint()
656 sr = readb(sport->port.membase + UARTSR1); lpuart_rxint()
657 rx = readb(sport->port.membase + UARTDR); lpuart_rxint()
712 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) { lpuart32_rxint()
719 sr = lpuart32_read(sport->port.membase + UARTSTAT); lpuart32_rxint()
720 rx = lpuart32_read(sport->port.membase + UARTDATA); lpuart32_rxint()
771 sts = readb(sport->port.membase + UARTSR1); lpuart_int()
772 crdma = readb(sport->port.membase + UARTCR5); lpuart_int()
795 sts = lpuart32_read(sport->port.membase + UARTSTAT); lpuart32_int()
796 rxcount = lpuart32_read(sport->port.membase + UARTWATER); lpuart32_int()
803 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE)) lpuart32_int()
806 lpuart32_write(sts, sport->port.membase + UARTSTAT); lpuart32_int()
813 return (readb(port->membase + UARTSR1) & UARTSR1_TC) ? lpuart_tx_empty()
819 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ? lpuart32_tx_empty()
828 reg = readb(port->membase + UARTMODEM); lpuart_get_mctrl()
843 reg = lpuart32_read(port->membase + UARTMODIR); lpuart32_get_mctrl()
857 temp = readb(port->membase + UARTMODEM) & lpuart_set_mctrl()
866 writeb(temp, port->membase + UARTMODEM); lpuart_set_mctrl()
873 temp = lpuart32_read(port->membase + UARTMODIR) & lpuart32_set_mctrl()
882 lpuart32_write(temp, port->membase + UARTMODIR); lpuart32_set_mctrl()
889 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; lpuart_break_ctl()
894 writeb(temp, port->membase + UARTCR2); lpuart_break_ctl()
901 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK; lpuart32_break_ctl()
906 lpuart32_write(temp, port->membase + UARTCTRL); lpuart32_break_ctl()
914 cr2 = readb(sport->port.membase + UARTCR2); lpuart_setup_watermark()
918 writeb(cr2, sport->port.membase + UARTCR2); lpuart_setup_watermark()
920 val = readb(sport->port.membase + UARTPFIFO); lpuart_setup_watermark()
922 sport->port.membase + UARTPFIFO); lpuart_setup_watermark()
925 readb(sport->port.membase + UARTSR1); lpuart_setup_watermark()
929 sport->port.membase + UARTCFIFO); lpuart_setup_watermark()
931 writeb(0, sport->port.membase + UARTTWFIFO); lpuart_setup_watermark()
932 writeb(1, sport->port.membase + UARTRWFIFO); lpuart_setup_watermark()
935 writeb(cr2_saved, sport->port.membase + UARTCR2); lpuart_setup_watermark()
943 ctrl = lpuart32_read(sport->port.membase + UARTCTRL); lpuart32_setup_watermark()
947 lpuart32_write(ctrl, sport->port.membase + UARTCTRL); lpuart32_setup_watermark()
950 val = lpuart32_read(sport->port.membase + UARTFIFO); lpuart32_setup_watermark()
953 lpuart32_write(val, sport->port.membase + UARTFIFO); lpuart32_setup_watermark()
957 lpuart32_write(val, sport->port.membase + UARTWATER); lpuart32_setup_watermark()
960 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL); lpuart32_setup_watermark()
1077 temp = readb(sport->port.membase + UARTPFIFO); lpuart_startup()
1097 temp = readb(port->membase + UARTCR5); lpuart_startup()
1099 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5); lpuart_startup()
1112 temp = readb(sport->port.membase + UARTCR2); lpuart_startup()
1114 writeb(temp, sport->port.membase + UARTCR2); lpuart_startup()
1128 temp = lpuart32_read(sport->port.membase + UARTFIFO); lpuart32_startup()
1145 temp = lpuart32_read(sport->port.membase + UARTCTRL); lpuart32_startup()
1148 lpuart32_write(temp, sport->port.membase + UARTCTRL); lpuart32_startup()
1163 temp = readb(port->membase + UARTCR2); lpuart_shutdown()
1166 writeb(temp, port->membase + UARTCR2); lpuart_shutdown()
1190 temp = lpuart32_read(port->membase + UARTCTRL); lpuart32_shutdown()
1193 lpuart32_write(temp, port->membase + UARTCTRL); lpuart32_shutdown()
1211 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); lpuart_set_termios()
1212 old_cr2 = readb(sport->port.membase + UARTCR2); lpuart_set_termios()
1213 cr4 = readb(sport->port.membase + UARTCR4); lpuart_set_termios()
1214 bdh = readb(sport->port.membase + UARTBDH); lpuart_set_termios()
1215 modem = readb(sport->port.membase + UARTMODEM); lpuart_set_termios()
1312 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) lpuart_set_termios()
1317 sport->port.membase + UARTCR2); lpuart_set_termios()
1325 writeb(cr4 | brfa, sport->port.membase + UARTCR4); lpuart_set_termios()
1326 writeb(bdh, sport->port.membase + UARTBDH); lpuart_set_termios()
1327 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); lpuart_set_termios()
1328 writeb(cr1, sport->port.membase + UARTCR1); lpuart_set_termios()
1329 writeb(modem, sport->port.membase + UARTMODEM); lpuart_set_termios()
1332 writeb(old_cr2, sport->port.membase + UARTCR2); lpuart_set_termios()
1348 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL); lpuart32_set_termios()
1349 bd = lpuart32_read(sport->port.membase + UARTBAUD); lpuart32_set_termios()
1350 modem = lpuart32_read(sport->port.membase + UARTMODIR); lpuart32_set_termios()
1436 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC)) lpuart32_set_termios()
1441 sport->port.membase + UARTCTRL); lpuart32_set_termios()
1448 lpuart32_write(bd, sport->port.membase + UARTBAUD); lpuart32_set_termios()
1449 lpuart32_write(modem, sport->port.membase + UARTMODIR); lpuart32_set_termios()
1450 lpuart32_write(ctrl, sport->port.membase + UARTCTRL); lpuart32_set_termios()
1540 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) lpuart_console_putchar()
1543 writeb(ch, port->membase + UARTDR); lpuart_console_putchar()
1548 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)) lpuart32_console_putchar()
1551 lpuart32_write(ch, port->membase + UARTDATA); lpuart32_console_putchar()
1561 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); lpuart_console_write()
1564 writeb(cr2, sport->port.membase + UARTCR2); lpuart_console_write()
1569 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) lpuart_console_write()
1572 writeb(old_cr2, sport->port.membase + UARTCR2); lpuart_console_write()
1582 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL); lpuart32_console_write()
1585 lpuart32_write(cr, sport->port.membase + UARTCTRL); lpuart32_console_write()
1590 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC)) lpuart32_console_write()
1593 lpuart32_write(old_cr, sport->port.membase + UARTCTRL); lpuart32_console_write()
1607 cr = readb(sport->port.membase + UARTCR2); lpuart_console_get_options()
1614 cr = readb(sport->port.membase + UARTCR1); lpuart_console_get_options()
1629 bdh = readb(sport->port.membase + UARTBDH); lpuart_console_get_options()
1631 bdl = readb(sport->port.membase + UARTBDL); lpuart_console_get_options()
1635 brfa = readb(sport->port.membase + UARTCR4); lpuart_console_get_options()
1656 cr = lpuart32_read(sport->port.membase + UARTCTRL); lpuart32_console_get_options()
1663 cr = lpuart32_read(sport->port.membase + UARTCTRL); lpuart32_console_get_options()
1678 bd = lpuart32_read(sport->port.membase + UARTBAUD); lpuart32_console_get_options()
1786 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); lpuart_probe()
1787 if (IS_ERR(sport->port.membase)) lpuart_probe()
1788 return PTR_ERR(sport->port.membase); lpuart_probe()
1869 temp = lpuart32_read(sport->port.membase + UARTCTRL); lpuart_suspend()
1871 lpuart32_write(temp, sport->port.membase + UARTCTRL); lpuart_suspend()
1874 temp = readb(sport->port.membase + UARTCR2); lpuart_suspend()
1876 writeb(temp, sport->port.membase + UARTCR2); lpuart_suspend()
1891 temp = lpuart32_read(sport->port.membase + UARTCTRL); lpuart_resume()
1894 lpuart32_write(temp, sport->port.membase + UARTCTRL); lpuart_resume()
1897 temp = readb(sport->port.membase + UARTCR2); lpuart_resume()
1899 writeb(temp, sport->port.membase + UARTCR2); lpuart_resume()
H A Dmeson_uart.c102 val = readl(port->membase + AML_UART_STATUS); meson_uart_tx_empty()
110 val = readl(port->membase + AML_UART_CONTROL); meson_uart_stop_tx()
112 writel(val, port->membase + AML_UART_CONTROL); meson_uart_stop_tx()
119 val = readl(port->membase + AML_UART_CONTROL); meson_uart_stop_rx()
121 writel(val, port->membase + AML_UART_CONTROL); meson_uart_stop_rx()
133 val = readl(port->membase + AML_UART_CONTROL); meson_uart_shutdown()
136 writel(val, port->membase + AML_UART_CONTROL); meson_uart_shutdown()
151 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { meson_uart_start_tx()
153 writel(port->x_char, port->membase + AML_UART_WFIFO); meson_uart_start_tx()
163 writel(ch, port->membase + AML_UART_WFIFO); meson_uart_start_tx()
181 status = readl(port->membase + AML_UART_STATUS); meson_receive_chars()
191 mode = readl(port->membase + AML_UART_CONTROL); meson_receive_chars()
193 writel(mode, port->membase + AML_UART_CONTROL); meson_receive_chars()
197 writel(mode, port->membase + AML_UART_CONTROL); meson_receive_chars()
206 ch = readl(port->membase + AML_UART_RFIFO); meson_receive_chars()
215 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)); meson_receive_chars()
228 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)) meson_uart_interrupt()
231 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) meson_uart_interrupt()
249 val = readl(port->membase + AML_UART_CONTROL); meson_uart_startup()
251 writel(val, port->membase + AML_UART_CONTROL); meson_uart_startup()
254 writel(val, port->membase + AML_UART_CONTROL); meson_uart_startup()
257 writel(val, port->membase + AML_UART_CONTROL); meson_uart_startup()
260 writel(val, port->membase + AML_UART_CONTROL); meson_uart_startup()
263 writel(val, port->membase + AML_UART_MISC); meson_uart_startup()
275 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_EMPTY)) meson_uart_change_speed()
278 val = readl(port->membase + AML_UART_REG5); meson_uart_change_speed()
282 writel(val, port->membase + AML_UART_REG5); meson_uart_change_speed()
298 val = readl(port->membase + AML_UART_CONTROL); meson_uart_set_termios()
337 writel(val, port->membase + AML_UART_CONTROL); meson_uart_set_termios()
373 iounmap(port->membase); meson_uart_release_port()
374 port->membase = NULL; meson_uart_release_port()
398 port->membase = devm_ioremap_nocache(port->dev, meson_uart_request_port()
401 if (port->membase == NULL) meson_uart_request_port()
437 if (!port->membase) meson_console_putchar()
440 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL) meson_console_putchar()
442 writel(ch, port->membase + AML_UART_WFIFO); meson_console_putchar()
485 if (!port || !port->membase) meson_serial_console_setup()
H A Dtimbuart.c54 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; timbuart_stop_rx()
55 iowrite32(ier, port->membase + TIMBUART_IER); timbuart_stop_rx()
61 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; timbuart_stop_tx()
62 iowrite32(ier, port->membase + TIMBUART_IER); timbuart_stop_tx()
76 u32 isr = ioread32(port->membase + TIMBUART_ISR); timbuart_tx_empty()
84 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | timbuart_flush_buffer()
87 iowrite8(ctl, port->membase + TIMBUART_CTRL); timbuart_flush_buffer()
88 iowrite32(TXBF, port->membase + TIMBUART_ISR); timbuart_flush_buffer()
96 while (ioread32(port->membase + TIMBUART_ISR) & RXDP) { timbuart_rx_chars()
97 u8 ch = ioread8(port->membase + TIMBUART_RXFIFO); timbuart_rx_chars()
114 while (!(ioread32(port->membase + TIMBUART_ISR) & TXBF) && timbuart_tx_chars()
117 port->membase + TIMBUART_TXFIFO); timbuart_tx_chars()
126 ioread8(port->membase + TIMBUART_CTRL), timbuart_tx_chars()
128 ioread8(port->membase + TIMBUART_BAUDRATE)); timbuart_tx_chars()
146 iowrite32(TXFLAGS, port->membase + TIMBUART_ISR); timbuart_handle_tx_port()
170 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | timbuart_handle_rx_port()
172 iowrite8(ctl, port->membase + TIMBUART_CTRL); timbuart_handle_rx_port()
178 iowrite32(RXFLAGS, port->membase + TIMBUART_ISR); timbuart_handle_rx_port()
194 isr = ioread32(uart->port.membase + TIMBUART_ISR); timbuart_tasklet()
205 iowrite32(ier, uart->port.membase + TIMBUART_IER); timbuart_tasklet()
213 u8 cts = ioread8(port->membase + TIMBUART_CTRL); timbuart_get_mctrl()
227 iowrite8(TIMBUART_CTRL_RTS, port->membase + TIMBUART_CTRL); timbuart_set_mctrl()
229 iowrite8(0, port->membase + TIMBUART_CTRL); timbuart_set_mctrl()
238 iowrite32(CTS_DELTA, port->membase + TIMBUART_ISR); timbuart_mctrl_check()
259 iowrite8(TIMBUART_CTRL_FLSHRX, port->membase + TIMBUART_CTRL); timbuart_startup()
260 iowrite32(0x1ff, port->membase + TIMBUART_ISR); timbuart_startup()
263 port->membase + TIMBUART_IER); timbuart_startup()
275 iowrite32(0, port->membase + TIMBUART_IER); timbuart_shutdown()
314 iowrite8((u8)bindex, port->membase + TIMBUART_BAUDRATE); timbuart_set_termios()
334 iounmap(port->membase); timbuart_release_port()
335 port->membase = NULL; timbuart_release_port()
351 port->membase = ioremap(port->mapbase, size); timbuart_request_port()
352 if (port->membase == NULL) { timbuart_request_port()
365 if (ioread8(uart->port.membase + TIMBUART_IPR)) { timbuart_handleinterrupt()
366 uart->last_ier = ioread32(uart->port.membase + TIMBUART_IER); timbuart_handleinterrupt()
369 iowrite32(0, uart->port.membase + TIMBUART_IER); timbuart_handleinterrupt()
457 uart->port.membase = NULL; timbuart_probe()
H A Dimx.c293 ucr->ucr1 = readl(port->membase + UCR1); imx_port_ucrs_save()
294 ucr->ucr2 = readl(port->membase + UCR2); imx_port_ucrs_save()
295 ucr->ucr3 = readl(port->membase + UCR3); imx_port_ucrs_save()
302 writel(ucr->ucr1, port->membase + UCR1); imx_port_ucrs_restore()
303 writel(ucr->ucr2, port->membase + UCR2); imx_port_ucrs_restore()
304 writel(ucr->ucr3, port->membase + UCR3); imx_port_ucrs_restore()
368 temp = readl(port->membase + UCR1); imx_stop_tx()
369 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); imx_stop_tx()
373 readl(port->membase + USR2) & USR2_TXDC) { imx_stop_tx()
374 temp = readl(port->membase + UCR2); imx_stop_tx()
379 writel(temp, port->membase + UCR2); imx_stop_tx()
381 temp = readl(port->membase + UCR4); imx_stop_tx()
383 writel(temp, port->membase + UCR4); imx_stop_tx()
404 temp = readl(sport->port.membase + UCR2); imx_stop_rx()
405 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); imx_stop_rx()
408 temp = readl(sport->port.membase + UCR1); imx_stop_rx()
409 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); imx_stop_rx()
430 writel(sport->port.x_char, sport->port.membase + URTX0); imx_transmit_buffer()
446 temp = readl(sport->port.membase + UCR1); imx_transmit_buffer()
450 writel(temp, sport->port.membase + UCR1); imx_transmit_buffer()
452 writel(temp, sport->port.membase + UCR1); imx_transmit_buffer()
458 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { imx_transmit_buffer()
461 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); imx_transmit_buffer()
485 temp = readl(sport->port.membase + UCR1); dma_tx_callback()
487 writel(temp, sport->port.membase + UCR1); dma_tx_callback()
559 temp = readl(sport->port.membase + UCR1); imx_dma_tx()
561 writel(temp, sport->port.membase + UCR1); imx_dma_tx()
580 temp = readl(port->membase + UCR2); imx_start_tx()
585 writel(temp, port->membase + UCR2); imx_start_tx()
587 temp = readl(port->membase + UCR4); imx_start_tx()
589 writel(temp, port->membase + UCR4); imx_start_tx()
593 temp = readl(sport->port.membase + UCR1); imx_start_tx()
594 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); imx_start_tx()
601 temp = readl(sport->port.membase + UCR1); imx_start_tx()
604 writel(temp, sport->port.membase + UCR1); imx_start_tx()
623 writel(USR1_RTSD, sport->port.membase + USR1); imx_rtsint()
624 val = readl(sport->port.membase + USR1) & USR1_RTSS; imx_rtsint()
652 while (readl(sport->port.membase + USR2) & USR2_RDR) { imx_rxint()
656 rx = readl(sport->port.membase + URXD0); imx_rxint()
658 temp = readl(sport->port.membase + USR2); imx_rxint()
660 writel(USR2_BRCD, sport->port.membase + USR2); imx_rxint()
724 temp = readl(sport->port.membase + USR2); imx_dma_rxint()
729 temp = readl(sport->port.membase + UCR1); imx_dma_rxint()
731 writel(temp, sport->port.membase + UCR1); imx_dma_rxint()
746 sts = readl(sport->port.membase + USR1); imx_int()
747 sts2 = readl(sport->port.membase + USR2); imx_int()
757 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) || imx_int()
759 readl(sport->port.membase + UCR4) & UCR4_TCEN)) imx_int()
766 writel(USR1_AWAKE, sport->port.membase + USR1); imx_int()
771 writel(USR2_ORE, sport->port.membase + USR2); imx_int()
785 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; imx_tx_empty()
802 if (readl(sport->port.membase + USR1) & USR1_RTSS) imx_get_mctrl()
805 if (readl(sport->port.membase + UCR2) & UCR2_CTS) imx_get_mctrl()
808 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) imx_get_mctrl()
820 temp = readl(sport->port.membase + UCR2); imx_set_mctrl()
824 writel(temp, sport->port.membase + UCR2); imx_set_mctrl()
827 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; imx_set_mctrl()
830 writel(temp, sport->port.membase + uts_reg(sport)); imx_set_mctrl()
843 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; imx_break_ctl()
848 writel(temp, sport->port.membase + UCR1); imx_break_ctl()
861 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); imx_setup_ufcr()
863 writel(val, sport->port.membase + UFCR); imx_setup_ufcr()
876 temp = readl(sport->port.membase + UCR1); imx_rx_dma_done()
878 writel(temp, sport->port.membase + UCR1); imx_rx_dma_done()
915 if (readl(sport->port.membase + USR2) & USR2_IDLE) { dma_rx_callback()
919 writel(USR2_IDLE, sport->port.membase + USR2); dma_rx_callback()
930 } else if (readl(sport->port.membase + USR2) & USR2_RDR) { dma_rx_callback()
1058 temp = readl(sport->port.membase + UCR1); imx_enable_dma()
1062 writel(temp, sport->port.membase + UCR1); imx_enable_dma()
1065 temp = readl(sport->port.membase + UCR4); imx_enable_dma()
1067 writel(temp, sport->port.membase + UCR4); imx_enable_dma()
1077 temp = readl(sport->port.membase + UCR1); imx_disable_dma()
1079 writel(temp, sport->port.membase + UCR1); imx_disable_dma()
1082 temp = readl(sport->port.membase + UCR2); imx_disable_dma()
1084 writel(temp, sport->port.membase + UCR2); imx_disable_dma()
1087 temp = readl(sport->port.membase + UCR4); imx_disable_dma()
1089 writel(temp, sport->port.membase + UCR4); imx_disable_dma()
1117 temp = readl(sport->port.membase + UCR4); imx_startup()
1123 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); imx_startup()
1128 temp = readl(sport->port.membase + UCR2); imx_startup()
1130 writel(temp, sport->port.membase + UCR2); imx_startup()
1132 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) imx_startup()
1140 writel(USR1_RTSD, sport->port.membase + USR1); imx_startup()
1141 writel(USR2_ORE, sport->port.membase + USR2); imx_startup()
1143 temp = readl(sport->port.membase + UCR1); imx_startup()
1146 writel(temp, sport->port.membase + UCR1); imx_startup()
1148 temp = readl(sport->port.membase + UCR4); imx_startup()
1150 writel(temp, sport->port.membase + UCR4); imx_startup()
1152 temp = readl(sport->port.membase + UCR2); imx_startup()
1156 writel(temp, sport->port.membase + UCR2); imx_startup()
1159 temp = readl(sport->port.membase + UCR3); imx_startup()
1161 writel(temp, sport->port.membase + UCR3); imx_startup()
1200 temp = readl(sport->port.membase + UCR2); imx_shutdown()
1202 writel(temp, sport->port.membase + UCR2); imx_shutdown()
1215 temp = readl(sport->port.membase + UCR1); imx_shutdown()
1218 writel(temp, sport->port.membase + UCR1); imx_shutdown()
1240 temp = readl(sport->port.membase + UCR1); imx_flush_buffer()
1242 writel(temp, sport->port.membase + UCR1); imx_flush_buffer()
1253 ubir = readl(sport->port.membase + UBIR); imx_flush_buffer()
1254 ubmr = readl(sport->port.membase + UBMR); imx_flush_buffer()
1255 uts = readl(sport->port.membase + IMX21_UTS); imx_flush_buffer()
1257 temp = readl(sport->port.membase + UCR2); imx_flush_buffer()
1259 writel(temp, sport->port.membase + UCR2); imx_flush_buffer()
1261 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) imx_flush_buffer()
1265 writel(ubir, sport->port.membase + UBIR); imx_flush_buffer()
1266 writel(ubmr, sport->port.membase + UBMR); imx_flush_buffer()
1267 writel(uts, sport->port.membase + IMX21_UTS); imx_flush_buffer()
1377 old_ucr1 = readl(sport->port.membase + UCR1); imx_set_termios()
1379 sport->port.membase + UCR1); imx_set_termios()
1381 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) imx_set_termios()
1385 old_txrxen = readl(sport->port.membase + UCR2); imx_set_termios()
1387 sport->port.membase + UCR2); imx_set_termios()
1413 ufcr = readl(sport->port.membase + UFCR); imx_set_termios()
1417 writel(ufcr, sport->port.membase + UFCR); imx_set_termios()
1419 writel(num, sport->port.membase + UBIR); imx_set_termios()
1420 writel(denom, sport->port.membase + UBMR); imx_set_termios()
1424 sport->port.membase + IMX21_ONEMS); imx_set_termios()
1426 writel(old_ucr1, sport->port.membase + UCR1); imx_set_termios()
1429 writel(ucr2 | old_txrxen, sport->port.membase + UCR2); imx_set_termios()
1505 temp = readl(sport->port.membase + UCR1); imx_poll_init()
1510 writel(temp, sport->port.membase + UCR1); imx_poll_init()
1512 temp = readl(sport->port.membase + UCR2); imx_poll_init()
1514 writel(temp, sport->port.membase + UCR2); imx_poll_init()
1523 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) imx_poll_get_char()
1526 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; imx_poll_get_char()
1535 status = readl_relaxed(port->membase + USR1); imx_poll_put_char()
1539 writel_relaxed(c, port->membase + URTX0); imx_poll_put_char()
1543 status = readl_relaxed(port->membase + USR2); imx_poll_put_char()
1566 temp = readl(sport->port.membase + UCR2); imx_rs485_config()
1572 writel(temp, sport->port.membase + UCR2); imx_rs485_config()
1610 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) imx_console_putchar()
1613 writel(ch, sport->port.membase + URTX0); imx_console_putchar()
1656 writel(ucr1, sport->port.membase + UCR1); imx_console_write()
1658 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); imx_console_write()
1666 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); imx_console_write()
1686 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { imx_console_get_options()
1692 ucr2 = readl(sport->port.membase + UCR2); imx_console_get_options()
1707 ubir = readl(sport->port.membase + UBIR) & 0xffff; imx_console_get_options()
1708 ubmr = readl(sport->port.membase + UBMR) & 0xffff; imx_console_get_options()
1710 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; imx_console_get_options()
1821 val = readl(sport->port.membase + UCR3); serial_imx_suspend()
1823 writel(val, sport->port.membase + UCR3); serial_imx_suspend()
1836 val = readl(sport->port.membase + UCR3); serial_imx_resume()
1838 writel(val, sport->port.membase + UCR3); serial_imx_resume()
1931 sport->port.membase = base; serial_imx_probe()
H A Dxilinx_uartps.c195 isrstatus = readl(port->membase + CDNS_UART_ISR_OFFSET); cdns_uart_isr()
203 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & cdns_uart_isr()
205 if (!readl(port->membase + CDNS_UART_FIFO_OFFSET)) { cdns_uart_isr()
211 port->membase + CDNS_UART_ISR_OFFSET); cdns_uart_isr()
224 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & cdns_uart_isr()
226 data = readl(port->membase + CDNS_UART_FIFO_OFFSET); cdns_uart_isr()
277 port->membase + CDNS_UART_IDR_OFFSET); cdns_uart_isr()
290 port->membase + CDNS_UART_FIFO_OFFSET); cdns_uart_isr()
308 writel(isrstatus, port->membase + CDNS_UART_ISR_OFFSET); cdns_uart_isr()
398 mreg = readl(port->membase + CDNS_UART_MR_OFFSET); cdns_uart_set_baud_rate()
403 writel(mreg, port->membase + CDNS_UART_MR_OFFSET); cdns_uart_set_baud_rate()
404 writel(cd, port->membase + CDNS_UART_BAUDGEN_OFFSET); cdns_uart_set_baud_rate()
405 writel(bdiv, port->membase + CDNS_UART_BAUDDIV_OFFSET); cdns_uart_set_baud_rate()
452 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_clk_notifier_cb()
454 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_clk_notifier_cb()
479 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_clk_notifier_cb()
481 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_clk_notifier_cb()
483 while (readl(port->membase + CDNS_UART_CR_OFFSET) & cdns_uart_clk_notifier_cb()
492 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); cdns_uart_clk_notifier_cb()
493 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_clk_notifier_cb()
496 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_clk_notifier_cb()
518 status = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_start_tx()
523 port->membase + CDNS_UART_CR_OFFSET); cdns_uart_start_tx()
525 while (numbytes-- && ((readl(port->membase + CDNS_UART_SR_OFFSET) & cdns_uart_start_tx()
535 port->membase + CDNS_UART_FIFO_OFFSET); cdns_uart_start_tx()
544 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR_OFFSET); cdns_uart_start_tx()
546 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER_OFFSET); cdns_uart_start_tx()
560 regval = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_stop_tx()
563 writel(regval, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_stop_tx()
574 regval = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_stop_rx()
577 writel(regval, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_stop_rx()
590 status = readl(port->membase + CDNS_UART_SR_OFFSET) & cdns_uart_tx_empty()
608 status = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_break_ctl()
612 port->membase + CDNS_UART_CR_OFFSET); cdns_uart_break_ctl()
616 port->membase + CDNS_UART_CR_OFFSET); cdns_uart_break_ctl()
639 if (!(readl(port->membase + CDNS_UART_CR_OFFSET) & cdns_uart_set_termios()
641 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & cdns_uart_set_termios()
648 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_set_termios()
650 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_set_termios()
669 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_set_termios()
671 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_set_termios()
677 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_set_termios()
680 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_set_termios()
682 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); cdns_uart_set_termios()
702 mode_reg = readl(port->membase + CDNS_UART_MR_OFFSET); cdns_uart_set_termios()
743 writel(cval, port->membase + CDNS_UART_MR_OFFSET); cdns_uart_set_termios()
765 port->membase + CDNS_UART_CR_OFFSET); cdns_uart_startup()
771 port->membase + CDNS_UART_CR_OFFSET); cdns_uart_startup()
773 status = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_startup()
781 port->membase + CDNS_UART_CR_OFFSET); cdns_uart_startup()
788 port->membase + CDNS_UART_MR_OFFSET); cdns_uart_startup()
794 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM_OFFSET); cdns_uart_startup()
800 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); cdns_uart_startup()
803 writel(readl(port->membase + CDNS_UART_ISR_OFFSET), cdns_uart_startup()
804 port->membase + CDNS_UART_ISR_OFFSET); cdns_uart_startup()
810 port->membase + CDNS_UART_IER_OFFSET); cdns_uart_startup()
824 status = readl(port->membase + CDNS_UART_IMR_OFFSET); cdns_uart_shutdown()
825 writel(status, port->membase + CDNS_UART_IDR_OFFSET); cdns_uart_shutdown()
829 port->membase + CDNS_UART_CR_OFFSET); cdns_uart_shutdown()
882 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); cdns_uart_request_port()
883 if (!port->membase) { cdns_uart_request_port()
901 iounmap(port->membase); cdns_uart_release_port()
902 port->membase = NULL; cdns_uart_release_port()
931 val = readl(port->membase + CDNS_UART_MODEMCR_OFFSET); cdns_uart_set_mctrl()
940 writel(val, port->membase + CDNS_UART_MODEMCR_OFFSET); cdns_uart_set_mctrl()
950 imr = readl(port->membase + CDNS_UART_IMR_OFFSET); cdns_uart_poll_get_char()
951 writel(imr, port->membase + CDNS_UART_IDR_OFFSET); cdns_uart_poll_get_char()
954 if (readl(port->membase + CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY) cdns_uart_poll_get_char()
958 port->membase + CDNS_UART_FIFO_OFFSET); cdns_uart_poll_get_char()
961 writel(imr, port->membase + CDNS_UART_IER_OFFSET); cdns_uart_poll_get_char()
971 imr = readl(port->membase + CDNS_UART_IMR_OFFSET); cdns_uart_poll_put_char()
972 writel(imr, port->membase + CDNS_UART_IDR_OFFSET); cdns_uart_poll_put_char()
975 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & cdns_uart_poll_put_char()
980 writel(c, port->membase + CDNS_UART_FIFO_OFFSET); cdns_uart_poll_put_char()
983 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & cdns_uart_poll_put_char()
988 writel(imr, port->membase + CDNS_UART_IER_OFFSET); cdns_uart_poll_put_char()
1043 port->membase = NULL; cdns_uart_get_port()
1062 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & cdns_uart_console_wait_tx()
1075 writel(ch, port->membase + CDNS_UART_FIFO_OFFSET); cdns_uart_console_putchar()
1088 if (!device->port.membase) cdns_early_console_setup()
1117 imr = readl(port->membase + CDNS_UART_IMR_OFFSET); cdns_uart_console_write()
1118 writel(imr, port->membase + CDNS_UART_IDR_OFFSET); cdns_uart_console_write()
1124 ctrl = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_console_write()
1126 port->membase + CDNS_UART_CR_OFFSET); cdns_uart_console_write()
1131 writel(ctrl, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_console_write()
1134 writel(imr, port->membase + CDNS_UART_IER_OFFSET); cdns_uart_console_write()
1158 if (!port->membase) { cdns_uart_console_setup()
1246 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & cdns_uart_suspend()
1248 readl(port->membase + CDNS_UART_FIFO_OFFSET); cdns_uart_suspend()
1250 writel(1, port->membase + CDNS_UART_RXWM_OFFSET); cdns_uart_suspend()
1253 port->membase + CDNS_UART_IDR_OFFSET); cdns_uart_suspend()
1292 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_resume()
1294 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_resume()
1295 while (readl(port->membase + CDNS_UART_CR_OFFSET) & cdns_uart_resume()
1300 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); cdns_uart_resume()
1302 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); cdns_uart_resume()
1305 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_resume()
1312 port->membase + CDNS_UART_RXWM_OFFSET); cdns_uart_resume()
1315 port->membase + CDNS_UART_IER_OFFSET); cdns_uart_resume()
H A Damba-pl010.c82 cr = readb(uap->port.membase + UART010_CR); pl010_stop_tx()
84 writel(cr, uap->port.membase + UART010_CR); pl010_stop_tx()
93 cr = readb(uap->port.membase + UART010_CR); pl010_start_tx()
95 writel(cr, uap->port.membase + UART010_CR); pl010_start_tx()
104 cr = readb(uap->port.membase + UART010_CR); pl010_stop_rx()
106 writel(cr, uap->port.membase + UART010_CR); pl010_stop_rx()
114 cr = readb(uap->port.membase + UART010_CR); pl010_disable_ms()
116 writel(cr, uap->port.membase + UART010_CR); pl010_disable_ms()
125 cr = readb(uap->port.membase + UART010_CR); pl010_enable_ms()
127 writel(cr, uap->port.membase + UART010_CR); pl010_enable_ms()
134 status = readb(uap->port.membase + UART01x_FR); pl010_rx_chars()
136 ch = readb(uap->port.membase + UART01x_DR); pl010_rx_chars()
145 rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; pl010_rx_chars()
147 writel(0, uap->port.membase + UART01x_ECR); pl010_rx_chars()
177 status = readb(uap->port.membase + UART01x_FR); pl010_rx_chars()
190 writel(uap->port.x_char, uap->port.membase + UART01x_DR); pl010_tx_chars()
202 writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); pl010_tx_chars()
220 writel(0, uap->port.membase + UART010_ICR); pl010_modem_status()
222 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; pl010_modem_status()
250 status = readb(uap->port.membase + UART010_IIR); pl010_int()
263 status = readb(uap->port.membase + UART010_IIR); pl010_int()
278 unsigned int status = readb(uap->port.membase + UART01x_FR); pl010_tx_empty()
289 status = readb(uap->port.membase + UART01x_FR); pl010_get_mctrl()
306 uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl); pl010_set_mctrl()
317 lcr_h = readb(uap->port.membase + UART010_LCRH); pl010_break_ctl()
322 writel(lcr_h, uap->port.membase + UART010_LCRH); pl010_break_ctl()
351 uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; pl010_startup()
357 uap->port.membase + UART010_CR); pl010_startup()
380 writel(0, uap->port.membase + UART010_CR); pl010_shutdown()
383 writel(readb(uap->port.membase + UART010_LCRH) & pl010_shutdown()
385 uap->port.membase + UART010_LCRH); pl010_shutdown()
469 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; pl010_set_termios()
474 writel(0, uap->port.membase + UART010_CR); pl010_set_termios()
478 writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); pl010_set_termios()
479 writel(quot & 0xff, uap->port.membase + UART010_LCRL); pl010_set_termios()
486 writel(lcr_h, uap->port.membase + UART010_LCRH); pl010_set_termios()
487 writel(old_cr, uap->port.membase + UART010_CR); pl010_set_termios()
588 status = readb(uap->port.membase + UART01x_FR); pl010_console_putchar()
591 writel(ch, uap->port.membase + UART01x_DR); pl010_console_putchar()
605 old_cr = readb(uap->port.membase + UART010_CR); pl010_console_write()
606 writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); pl010_console_write()
615 status = readb(uap->port.membase + UART01x_FR); pl010_console_write()
618 writel(old_cr, uap->port.membase + UART010_CR); pl010_console_write()
627 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { pl010_console_get_options()
629 lcr_h = readb(uap->port.membase + UART010_LCRH); pl010_console_get_options()
644 quot = readb(uap->port.membase + UART010_LCRL) | pl010_console_get_options()
645 readb(uap->port.membase + UART010_LCRM) << 8; pl010_console_get_options()
739 uap->port.membase = base; pl010_probe()
H A Ddigicolor-usart.c89 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & digicolor_uart_tx_full()
95 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & digicolor_uart_rx_empty()
101 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); digicolor_uart_stop_tx()
104 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); digicolor_uart_stop_tx()
109 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); digicolor_uart_start_tx()
112 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); digicolor_uart_start_tx()
117 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); digicolor_uart_stop_rx()
120 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); digicolor_uart_stop_rx()
131 writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET); digicolor_rx_poll()
149 ch = readb_relaxed(port->membase + UA_EMI_REC); digicolor_uart_rx()
150 status = readb_relaxed(port->membase + UA_STATUS); digicolor_uart_rx()
196 writeb_relaxed(port->x_char, port->membase + UA_EMI_REC); digicolor_uart_tx()
208 writeb(xmit->buf[xmit->tail], port->membase + UA_EMI_REC); digicolor_uart_tx()
226 u8 int_status = readb_relaxed(port->membase + UA_INT_STATUS); digicolor_uart_int()
229 port->membase + UA_INTFLAG_CLEAR); digicolor_uart_int()
241 u8 status = readb_relaxed(port->membase + UA_STATUS); digicolor_uart_tx_empty()
264 writeb_relaxed(UA_ENABLE_ENABLE, port->membase + UA_ENABLE); digicolor_uart_startup()
265 writeb_relaxed(UA_CONTROL_SOFT_RESET, port->membase + UA_CONTROL); digicolor_uart_startup()
266 writeb_relaxed(0, port->membase + UA_CONTROL); digicolor_uart_startup()
270 port->membase + UA_CONFIG_FIFO); digicolor_uart_startup()
272 port->membase + UA_STATUS_FIFO); digicolor_uart_startup()
274 port->membase + UA_CONTROL); digicolor_uart_startup()
276 port->membase + UA_INT_ENABLE); digicolor_uart_startup()
288 writeb_relaxed(0, port->membase + UA_ENABLE); digicolor_uart_shutdown()
344 writeb_relaxed(config, port->membase + UA_CONFIG); digicolor_uart_set_termios()
345 writeb_relaxed(divisor & 0xff, port->membase + UA_HBAUD_LO); digicolor_uart_set_termios()
346 writeb_relaxed(divisor >> 8, port->membase + UA_HBAUD_HI); digicolor_uart_set_termios()
393 writeb_relaxed(ch, port->membase + UA_EMI_REC); digicolor_uart_console_putchar()
416 status = readb_relaxed(port->membase + UA_STATUS); digicolor_uart_console_write()
480 dp->port.membase = devm_ioremap_resource(&pdev->dev, res); digicolor_uart_probe()
481 if (IS_ERR(dp->port.membase)) digicolor_uart_probe()
482 return PTR_ERR(dp->port.membase); digicolor_uart_probe()
H A Dlpc32xx_hs.c111 port->membase))) == 0) wait_for_xmit_empty()
125 port->membase))) < 32) wait_for_xmit_ready()
136 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); lpc32xx_hsuart_console_putchar()
176 if (!port->membase) lpc32xx_hsuart_console_setup()
253 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && __serial_uart_flush()
255 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); __serial_uart_flush()
264 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); __serial_lpc32xx_rx()
272 LPC32XX_HSUART_IIR(port->membase)); __serial_lpc32xx_rx()
280 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); __serial_lpc32xx_rx()
294 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); __serial_lpc32xx_tx()
305 LPC32XX_HSUART_LEVEL(port->membase))) < 64) { __serial_lpc32xx_tx()
307 LPC32XX_HSUART_FIFO(port->membase)); __serial_lpc32xx_tx()
319 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); __serial_lpc32xx_tx()
321 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); __serial_lpc32xx_tx()
334 status = readl(LPC32XX_HSUART_IIR(port->membase)); serial_lpc32xx_interrupt()
338 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase)); serial_lpc32xx_interrupt()
345 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase)); serial_lpc32xx_interrupt()
350 LPC32XX_HSUART_IIR(port->membase)); serial_lpc32xx_interrupt()
362 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase)); serial_lpc32xx_interrupt()
376 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0) serial_lpc32xx_tx_empty()
401 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_stop_tx()
403 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_stop_tx()
412 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_start_tx()
414 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_start_tx()
422 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_stop_rx()
424 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_stop_rx()
427 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase)); serial_lpc32xx_stop_rx()
438 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_break_ctl()
443 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_break_ctl()
489 LPC32XX_HSUART_IIR(port->membase)); serial_lpc32xx_startup()
491 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); serial_lpc32xx_startup()
499 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_startup()
509 LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_startup()
524 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_shutdown()
556 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_set_termios()
561 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_set_termios()
563 writel(quot, LPC32XX_HSUART_RATE(port->membase)); serial_lpc32xx_set_termios()
583 iounmap(port->membase); serial_lpc32xx_release_port()
584 port->membase = NULL; serial_lpc32xx_release_port()
601 port->membase = ioremap(port->mapbase, SZ_4K); serial_lpc32xx_request_port()
602 if (!port->membase) { serial_lpc32xx_request_port()
626 LPC32XX_HSUART_IIR(port->membase)); serial_lpc32xx_config_port()
628 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); serial_lpc32xx_config_port()
634 LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_config_port()
692 p->port.membase = NULL; serial_hs_lpc32xx_probe()
H A Daltera_jtaguart.c68 return (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) & altera_jtaguart_tx_empty()
87 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); altera_jtaguart_start_tx()
96 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); altera_jtaguart_stop_tx()
105 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); altera_jtaguart_stop_rx()
127 while ((status = readl(port->membase + ALTERA_JTAGUART_DATA_REG)) & altera_jtaguart_rx_chars()
151 writel(port->x_char, port->membase + ALTERA_JTAGUART_DATA_REG); altera_jtaguart_tx_chars()
159 count = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) & altera_jtaguart_tx_chars()
168 port->membase + ALTERA_JTAGUART_DATA_REG); altera_jtaguart_tx_chars()
179 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); altera_jtaguart_tx_chars()
190 isr = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) >> altera_jtaguart_interrupt()
210 writel(0, port->membase + ALTERA_JTAGUART_CONTROL_REG); altera_jtaguart_config_port()
232 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); altera_jtaguart_startup()
249 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); altera_jtaguart_shutdown()
313 while (((status = readl(port->membase + ALTERA_JTAGUART_CONTROL_REG)) & altera_jtaguart_console_putc()
323 writel(c, port->membase + ALTERA_JTAGUART_DATA_REG); altera_jtaguart_console_putc()
332 while ((readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) & altera_jtaguart_console_putc()
338 writel(c, port->membase + ALTERA_JTAGUART_DATA_REG); altera_jtaguart_console_putc()
359 if (port->membase == NULL) altera_jtaguart_console_setup()
435 port->membase = ioremap(port->mapbase, ALTERA_JTAGUART_SIZE); altera_jtaguart_probe()
436 if (!port->membase) altera_jtaguart_probe()
H A Dlantiq.c154 ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); lqasc_stop_rx()
163 fifocnt = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; lqasc_rx_chars()
166 ch = ltq_r8(port->membase + LTQ_ASC_RBUF); lqasc_rx_chars()
167 rsr = (ltq_r32(port->membase + LTQ_ASC_STATE) lqasc_rx_chars()
180 port->membase + LTQ_ASC_WHBSTATE); lqasc_rx_chars()
184 port->membase + LTQ_ASC_WHBSTATE); lqasc_rx_chars()
189 port->membase + LTQ_ASC_WHBSTATE); lqasc_rx_chars()
227 while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) & lqasc_tx_chars()
230 ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF); lqasc_tx_chars()
240 port->membase + LTQ_ASC_TBUF); lqasc_tx_chars()
255 ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); lqasc_tx_int()
269 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); lqasc_err_int()
280 ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); lqasc_rx_int()
290 status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; lqasc_tx_empty()
321 port->membase + LTQ_ASC_CLC); lqasc_startup()
323 ltq_w32(0, port->membase + LTQ_ASC_PISEL); lqasc_startup()
327 port->membase + LTQ_ASC_TXFCON); lqasc_startup()
331 port->membase + LTQ_ASC_RXFCON); lqasc_startup()
337 ASCCON_ROEN, port->membase + LTQ_ASC_CON); lqasc_startup()
361 port->membase + LTQ_ASC_IRNREN); lqasc_startup()
379 ltq_w32(0, port->membase + LTQ_ASC_CON); lqasc_shutdown()
381 port->membase + LTQ_ASC_RXFCON); lqasc_shutdown()
383 port->membase + LTQ_ASC_TXFCON); lqasc_shutdown()
454 ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON); lqasc_set_termios()
462 ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON); lqasc_set_termios()
465 ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); lqasc_set_termios()
468 ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); lqasc_set_termios()
471 ltq_w32(divisor, port->membase + LTQ_ASC_BG); lqasc_set_termios()
474 ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON); lqasc_set_termios()
477 ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); lqasc_set_termios()
503 devm_iounmap(&pdev->dev, port->membase); lqasc_release_port()
504 port->membase = NULL; lqasc_release_port()
530 port->membase = devm_ioremap_nocache(&pdev->dev, lqasc_request_port()
532 if (port->membase == NULL) lqasc_request_port()
584 if (!port->membase) lqasc_console_putchar()
588 fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT) lqasc_console_putchar()
591 ltq_w8(ch, port->membase + LTQ_ASC_TBUF); lqasc_console_putchar()
H A Dmxs-auart.c296 while (!(readl(s->port.membase + AUART_STAT) & mxs_auart_tx_chars()
301 s->port.membase + AUART_DATA); mxs_auart_tx_chars()
308 s->port.membase + AUART_DATA); mxs_auart_tx_chars()
318 s->port.membase + AUART_INTR_CLR); mxs_auart_tx_chars()
321 s->port.membase + AUART_INTR_SET); mxs_auart_tx_chars()
333 c = readl(s->port.membase + AUART_DATA); mxs_auart_rx_char()
334 stat = readl(s->port.membase + AUART_STAT); mxs_auart_rx_char()
369 writel(stat, s->port.membase + AUART_STAT); mxs_auart_rx_char()
377 stat = readl(s->port.membase + AUART_STAT); mxs_auart_rx_chars()
383 writel(stat, s->port.membase + AUART_STAT); mxs_auart_rx_chars()
419 u32 ctrl = readl(u->membase + AUART_CTRL2); mxs_auart_set_mctrl()
429 writel(ctrl, u->membase + AUART_CTRL2); mxs_auart_set_mctrl()
460 u32 stat = readl(u->membase + AUART_STAT); mxs_auart_get_mctrl()
537 stat = readl(s->port.membase + AUART_STAT); dma_rx_callback()
544 writel(stat, s->port.membase + AUART_STAT); dma_rx_callback()
608 s->port.membase + AUART_CTRL2_CLR); mxs_auart_dma_exit()
667 ctrl2 = readl(u->membase + AUART_CTRL2); mxs_auart_settermios()
760 writel(ctrl, u->membase + AUART_LINECTRL); mxs_auart_settermios()
761 writel(ctrl2, u->membase + AUART_CTRL2); mxs_auart_settermios()
771 u->membase + AUART_INTR_CLR); mxs_auart_settermios()
801 u32 stat = readl(s->port.membase + AUART_STAT); mxs_auart_irq_handle()
803 istat = readl(s->port.membase + AUART_INTR); mxs_auart_irq_handle()
810 s->port.membase + AUART_INTR_CLR); mxs_auart_irq_handle()
827 s->port.membase + AUART_INTR_CLR); mxs_auart_irq_handle()
850 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR); mxs_auart_reset()
853 reg = readl(u->membase + AUART_CTRL0); mxs_auart_reset()
858 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); mxs_auart_reset()
870 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); mxs_auart_startup()
872 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET); mxs_auart_startup()
875 u->membase + AUART_INTR); mxs_auart_startup()
884 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET); mxs_auart_startup()
902 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR); mxs_auart_shutdown()
905 u->membase + AUART_INTR_CLR); mxs_auart_shutdown()
907 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET); mxs_auart_shutdown()
914 if ((readl(u->membase + AUART_STAT) & mxs_auart_tx_empty()
926 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET); mxs_auart_start_tx()
933 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR); mxs_auart_stop_tx()
938 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR); mxs_auart_stop_rx()
945 u->membase + AUART_LINECTRL_SET); mxs_auart_break_ctl()
948 u->membase + AUART_LINECTRL_CLR); mxs_auart_break_ctl()
978 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) { mxs_auart_console_putchar()
984 writel(ch, port->membase + AUART_DATA); mxs_auart_console_putchar()
1004 old_ctrl2 = readl(port->membase + AUART_CTRL2); auart_console_write()
1005 old_ctrl0 = readl(port->membase + AUART_CTRL0); auart_console_write()
1008 port->membase + AUART_CTRL0_CLR); auart_console_write()
1010 port->membase + AUART_CTRL2_SET); auart_console_write()
1015 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) { auart_console_write()
1027 if (!(readl(port->membase + AUART_STAT) & AUART_STAT_BUSY)) { auart_console_write()
1028 writel(old_ctrl0, port->membase + AUART_CTRL0); auart_console_write()
1029 writel(old_ctrl2, port->membase + AUART_CTRL2); auart_console_write()
1041 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN)) auart_console_get_options()
1044 lcr_h = readl(port->membase + AUART_LINECTRL); auart_console_get_options()
1059 quot = ((readl(port->membase + AUART_LINECTRL) auart_console_get_options()
1062 quot |= ((readl(port->membase + AUART_LINECTRL) auart_console_get_options()
1257 s->port.membase = ioremap(r->start, resource_size(r)); mxs_auart_probe()
1300 version = readl(s->port.membase + AUART_VERSION); mxs_auart_probe()
H A Damba-pl011.c186 status = readw(uap->port.membase + UART01x_FR); pl011_fifo_to_tty()
191 ch = readw(uap->port.membase + UART01x_DR) | pl011_fifo_to_tty()
428 writew(uap->dmacr, uap->port.membase + UART011_DMACR); pl011_dma_tx_callback()
542 writew(uap->dmacr, uap->port.membase + UART011_DMACR); pl011_dma_tx_refill()
578 writew(uap->dmacr, uap->port.membase + UART011_DMACR); pl011_dma_tx_irq()
580 writew(uap->im, uap->port.membase + UART011_IMSC); pl011_dma_tx_irq()
590 writew(uap->im, uap->port.membase + UART011_IMSC); pl011_dma_tx_irq()
604 writew(uap->dmacr, uap->port.membase + UART011_DMACR); pl011_dma_tx_stop()
630 writew(uap->im, uap->port.membase + pl011_dma_tx_start()
637 uap->port.membase + UART011_DMACR); pl011_dma_tx_start()
648 writew(uap->dmacr, uap->port.membase + UART011_DMACR); pl011_dma_tx_start()
650 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { pl011_dma_tx_start()
659 writew(uap->port.x_char, uap->port.membase + UART01x_DR); pl011_dma_tx_start()
665 writew(dmacr, uap->port.membase + UART011_DMACR); pl011_dma_tx_start()
693 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
733 writew(uap->dmacr, uap->port.membase + UART011_DMACR); pl011_dma_rx_trigger_dma()
737 writew(uap->im, uap->port.membase + UART011_IMSC); pl011_dma_rx_trigger_dma()
796 uap->port.membase + UART011_ICR); pl011_dma_rx_chars()
844 writew(uap->dmacr, uap->port.membase + UART011_DMACR); pl011_dma_rx_irq()
864 writew(uap->im, uap->port.membase + UART011_IMSC); pl011_dma_rx_irq()
912 writew(uap->im, uap->port.membase + UART011_IMSC); pl011_dma_rx_callback()
925 writew(uap->dmacr, uap->port.membase + UART011_DMACR); pl011_dma_rx_stop()
969 writew(uap->im, uap->port.membase + UART011_IMSC); pl011_dma_rx_poll()
1031 writew(uap->dmacr, uap->port.membase + UART011_DMACR); pl011_dma_startup()
1040 uap->port.membase + ST_UART011_DMAWM); pl011_dma_startup()
1065 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) pl011_dma_shutdown()
1070 writew(uap->dmacr, uap->port.membase + UART011_DMACR); pl011_dma_shutdown()
1171 writew(uap->im, uap->port.membase + UART011_IMSC); pl011_stop_tx()
1181 writew(uap->im, uap->port.membase + UART011_IMSC); pl011_start_tx_pio()
1202 writew(uap->im, uap->port.membase + UART011_IMSC); pl011_stop_rx()
1213 writew(uap->im, uap->port.membase + UART011_IMSC); pl011_enable_ms()
1233 writew(uap->im, uap->port.membase + UART011_IMSC);
1258 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) pl011_tx_char()
1261 writew(c, uap->port.membase + UART01x_DR); pl011_tx_char()
1294 readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)) pl011_tx_chars()
1337 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; pl011_modem_status()
1388 status = readw(uap->port.membase + UART011_MIS); pl011_int()
1393 writew(0x00, uap->port.membase + UART011_ICR); pl011_int()
1400 dummy_read = readw(uap->port.membase + UART011_ICR); pl011_int()
1401 dummy_read = readw(uap->port.membase + UART011_ICR); pl011_int()
1406 uap->port.membase + UART011_ICR); pl011_int()
1425 status = readw(uap->port.membase + UART011_MIS); pl011_int()
1439 unsigned int status = readw(uap->port.membase + UART01x_FR); pl011_tx_empty()
1448 unsigned int status = readw(uap->port.membase + UART01x_FR); pl011_get_mctrl()
1468 cr = readw(uap->port.membase + UART011_CR); pl011_set_mctrl()
1488 writew(cr, uap->port.membase + UART011_CR); pl011_set_mctrl()
1499 lcr_h = readw(uap->port.membase + uap->lcrh_tx); pl011_break_ctl()
1504 writew(lcr_h, uap->port.membase + uap->lcrh_tx); pl011_break_ctl()
1514 unsigned char __iomem *regs = uap->port.membase; pl011_quiesce_irqs()
1545 status = readw(uap->port.membase + UART01x_FR); pl011_get_poll_char()
1549 return readw(uap->port.membase + UART01x_DR); pl011_get_poll_char()
1558 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) pl011_put_poll_char()
1561 writew(ch, uap->port.membase + UART01x_DR); pl011_put_poll_char()
1586 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR); pl011_hwinit()
1592 uap->im = readw(uap->port.membase + UART011_IMSC); pl011_hwinit()
1593 writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC); pl011_hwinit()
1607 writew(lcr_h, uap->port.membase + uap->lcrh_rx); pl011_write_lcr_h()
1615 writew(0xff, uap->port.membase + UART011_MIS); pl011_write_lcr_h()
1616 writew(lcr_h, uap->port.membase + uap->lcrh_tx); pl011_write_lcr_h()
1631 writew(uap->im, uap->port.membase + UART011_IMSC); pl011_startup()
1640 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); pl011_startup()
1650 writew(cr, uap->port.membase + UART011_CR); pl011_startup()
1657 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; pl011_startup()
1670 uap->port.membase + UART011_ICR); pl011_startup()
1674 writew(uap->im, uap->port.membase + UART011_IMSC); pl011_startup()
1689 val = readw(uap->port.membase + lcrh); pl011_shutdown_channel()
1691 writew(val, uap->port.membase + lcrh); pl011_shutdown_channel()
1707 writew(uap->im, uap->port.membase + UART011_IMSC); pl011_shutdown()
1708 writew(0xffff, uap->port.membase + UART011_ICR); pl011_shutdown()
1726 cr = readw(uap->port.membase + UART011_CR); pl011_shutdown()
1730 writew(cr, uap->port.membase + UART011_CR); pl011_shutdown()
1855 old_cr = readw(port->membase + UART011_CR); pl011_set_termios()
1856 writew(0, port->membase + UART011_CR); pl011_set_termios()
1889 writew(quot & 0x3f, port->membase + UART011_FBRD); pl011_set_termios()
1890 writew(quot >> 6, port->membase + UART011_IBRD); pl011_set_termios()
1899 writew(old_cr, port->membase + UART011_CR); pl011_set_termios()
1988 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) pl011_console_putchar()
1990 writew(ch, uap->port.membase + UART01x_DR); pl011_console_putchar()
2014 old_cr = readw(uap->port.membase + UART011_CR); pl011_console_write()
2017 writew(new_cr, uap->port.membase + UART011_CR); pl011_console_write()
2026 status = readw(uap->port.membase + UART01x_FR); pl011_console_write()
2028 writew(old_cr, uap->port.membase + UART011_CR); pl011_console_write()
2041 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { pl011_console_get_options()
2044 lcr_h = readw(uap->port.membase + uap->lcrh_tx); pl011_console_get_options()
2059 ibrd = readw(uap->port.membase + UART011_IBRD); pl011_console_get_options()
2060 fbrd = readw(uap->port.membase + UART011_FBRD); pl011_console_get_options()
2065 if (readw(uap->port.membase + UART011_CR) pl011_console_get_options()
2132 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) pl011_putc()
2134 writeb(c, port->membase + UART01x_DR); pl011_putc()
2135 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) pl011_putc()
2149 if (!device->port.membase) pl011_early_console_setup()
2241 uap->port.membase = base; pl011_probe()
2251 writew(0, uap->port.membase + UART011_IMSC); pl011_probe()
2252 writew(0xffff, uap->port.membase + UART011_ICR); pl011_probe()
H A Dpch_uart.c230 void __iomem *membase; member in struct:eg20t_port
263 /* protect the eg20t_port private structure and io access to membase */
339 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); port_show_regs()
341 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); port_show_regs()
343 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); port_show_regs()
345 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); port_show_regs()
347 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); port_show_regs()
349 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); port_show_regs()
352 ioread8(priv->membase + PCH_UART_BRCSR)); port_show_regs()
354 lcr = ioread8(priv->membase + UART_LCR); port_show_regs()
355 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); port_show_regs()
357 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); port_show_regs()
359 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); port_show_regs()
360 iowrite8(lcr, priv->membase + UART_LCR); port_show_regs()
441 u8 ier = ioread8(priv->membase + UART_IER); pch_uart_hal_enable_interrupt()
443 iowrite8(ier, priv->membase + UART_IER); pch_uart_hal_enable_interrupt()
449 u8 ier = ioread8(priv->membase + UART_IER); pch_uart_hal_disable_interrupt()
451 iowrite8(ier, priv->membase + UART_IER); pch_uart_hal_disable_interrupt()
491 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); pch_uart_hal_set_line()
492 iowrite8(dll, priv->membase + PCH_UART_DLL); pch_uart_hal_set_line()
493 iowrite8(dlm, priv->membase + PCH_UART_DLM); pch_uart_hal_set_line()
494 iowrite8(lcr, priv->membase + UART_LCR); pch_uart_hal_set_line()
508 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); pch_uart_hal_fifo_reset()
510 priv->membase + UART_FCR); pch_uart_hal_fifo_reset()
511 iowrite8(priv->fcr, priv->membase + UART_FCR); pch_uart_hal_fifo_reset()
560 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); pch_uart_hal_set_fifo()
562 priv->membase + UART_FCR); pch_uart_hal_set_fifo()
563 iowrite8(fcr, priv->membase + UART_FCR); pch_uart_hal_set_fifo()
571 unsigned int msr = ioread8(priv->membase + UART_MSR); pch_uart_hal_get_modem()
584 iowrite8(thr, priv->membase + PCH_UART_THR); pch_uart_hal_write()
595 lsr = ioread8(priv->membase + UART_LSR); pch_uart_hal_read()
596 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); pch_uart_hal_read()
598 lsr = ioread8(priv->membase + UART_LSR)) { pch_uart_hal_read()
599 rbr = ioread8(priv->membase + PCH_UART_RBR); pch_uart_hal_read()
620 return ioread8(priv->membase + UART_IIR) &\ pch_uart_hal_get_iid()
626 return ioread8(priv->membase + UART_LSR); pch_uart_hal_get_line_status()
633 lcr = ioread8(priv->membase + UART_LCR); pch_uart_hal_set_break()
639 iowrite8(lcr, priv->membase + UART_LCR); pch_uart_hal_set_break()
1229 iowrite8(mcr, priv->membase + UART_MCR); pch_uart_set_mctrl()
1461 pci_iounmap(priv->pdev, priv->membase); pch_uart_release_port()
1469 void __iomem *membase; pch_uart_request_port() local
1476 membase = pci_iomap(priv->pdev, 1, 0); pch_uart_request_port()
1477 if (!membase) { pch_uart_request_port()
1481 priv->membase = port->membase = membase; pch_uart_request_port()
1537 status = ioread8(up->membase + UART_LSR); wait_for_xmitr()
1550 unsigned int msr = ioread8(up->membase + UART_MSR); wait_for_xmitr()
1569 u8 lsr = ioread8(priv->membase + UART_LSR); pch_uart_get_poll_char()
1574 return ioread8(priv->membase + PCH_UART_RBR); pch_uart_get_poll_char()
1588 ier = ioread8(priv->membase + UART_IER); pch_uart_put_poll_char()
1595 iowrite8(c, priv->membase + PCH_UART_THR); pch_uart_put_poll_char()
1602 iowrite8(ier, priv->membase + UART_IER); pch_uart_put_poll_char()
1638 iowrite8(ch, priv->membase + PCH_UART_THR); pch_console_putchar()
1677 ier = ioread8(priv->membase + UART_IER); pch_console_write()
1688 iowrite8(ier, priv->membase + UART_IER); pch_console_write()
1714 if (!port || (!port->iobase && !port->membase)) pch_console_setup()
1809 priv->port.membase = NULL; pch_uart_init_port()
H A Dmen_z135_uart.c149 reg = ioread32(port->membase + addr); men_z135_reg_set()
151 iowrite32(reg, port->membase + addr); men_z135_reg_set()
171 reg = ioread32(port->membase + addr); men_z135_reg_clr()
173 iowrite32(reg, port->membase + addr); men_z135_reg_clr()
232 stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG); get_rx_fifo_content()
275 memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room); men_z135_handle_rx()
278 iowrite32(room, port->membase + MEN_Z135_RX_CTRL); men_z135_handle_rx()
324 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); men_z135_handle_tx()
358 memcpy_toio(port->membase + MEN_Z135_TX_RAM, &xmit->buf[xmit->tail], n); men_z135_handle_tx()
362 iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL); men_z135_handle_tx()
397 uart->stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG); men_z135_intr()
405 iowrite8(irq_id, port->membase + MEN_Z135_STAT_REG); men_z135_intr()
467 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); men_z135_tx_empty()
489 conf_reg = old = ioread32(port->membase + MEN_Z135_CONF_REG); men_z135_set_mctrl()
516 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); men_z135_set_mctrl()
530 msr = ioread8(port->membase + MEN_Z135_STAT_REG + 1); men_z135_get_mctrl()
625 conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG); men_z135_startup()
633 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); men_z135_startup()
636 iowrite32(rx_timeout, port->membase + MEN_Z135_TIMEOUT); men_z135_startup()
664 conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG); men_z135_set_termios()
711 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); men_z135_set_termios()
713 uart_freq = ioread32(port->membase + MEN_Z135_UART_FREQ); men_z135_set_termios()
724 iowrite32(bd_reg, port->membase + MEN_Z135_BAUD_REG); men_z135_set_termios()
737 iounmap(port->membase); men_z135_release_port()
738 port->membase = NULL; men_z135_release_port()
750 port->membase = ioremap(port->mapbase, MEN_Z135_MEM_SIZE); men_z135_request_port()
751 if (port->membase == NULL) { men_z135_request_port()
839 uart->port.membase = NULL; men_z135_probe()
H A Dclps711x.c113 ch = readw(port->membase + UARTDR_OFFSET); uart_clps711x_int_rx()
159 writew(port->x_char, port->membase + UARTDR_OFFSET); uart_clps711x_int_tx()
176 writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET); uart_clps711x_int_tx()
220 ubrlcr = readl(port->membase + UBRLCR_OFFSET); uart_clps711x_break_ctl()
225 writel(ubrlcr, port->membase + UBRLCR_OFFSET); uart_clps711x_break_ctl()
244 writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK, uart_clps711x_startup()
245 port->membase + UBRLCR_OFFSET); uart_clps711x_startup()
317 writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET); uart_clps711x_set_termios()
369 writew(ch, port->membase + UARTDR_OFFSET); uart_clps711x_console_putchar()
410 ubrlcr = readl(port->membase + UBRLCR_OFFSET); uart_clps711x_console_setup()
466 s->port.membase = devm_ioremap_resource(&pdev->dev, res); uart_clps711x_probe()
467 if (IS_ERR(s->port.membase)) uart_clps711x_probe()
468 return PTR_ERR(s->port.membase); uart_clps711x_probe()
H A Dserial_ks8695.c47 #define UART_GET_CHAR(p) (__raw_readl((p)->membase + KS8695_URRB) & 0xFF)
48 #define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + KS8695_URTH)
49 #define UART_GET_FCR(p) __raw_readl((p)->membase + KS8695_URFC)
50 #define UART_PUT_FCR(p, c) __raw_writel((c), (p)->membase + KS8695_URFC)
51 #define UART_GET_MSR(p) __raw_readl((p)->membase + KS8695_URMS)
52 #define UART_GET_LSR(p) __raw_readl((p)->membase + KS8695_URLS)
53 #define UART_GET_LCR(p) __raw_readl((p)->membase + KS8695_URLC)
54 #define UART_PUT_LCR(p, c) __raw_writel((c), (p)->membase + KS8695_URLC)
55 #define UART_GET_MCR(p) __raw_readl((p)->membase + KS8695_URMC)
56 #define UART_PUT_MCR(p, c) __raw_writel((c), (p)->membase + KS8695_URMC)
57 #define UART_GET_BRDR(p) __raw_readl((p)->membase + KS8695_URBD)
58 #define UART_PUT_BRDR(p, c) __raw_writel((c), (p)->membase + KS8695_URBD)
550 .membase = KS8695_UART_VA,
H A Dsa1100.c60 #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
61 #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
62 #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
63 #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
64 #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
65 #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
66 #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
68 #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
69 #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
70 #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
71 #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
72 #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
73 #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
74 #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
679 sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0; sa1100_register_uart()
686 sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0; sa1100_register_uart()
693 sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0; sa1100_register_uart()
H A Dsamsung.h116 #define portaddr(port, reg) ((port)->membase + (reg))
118 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
H A Daltera_uart.c90 return readl(port->membase + (reg << port->regshift)); altera_uart_readl()
95 writel(dat, port->membase + (reg << port->regshift)); altera_uart_writel()
334 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG); altera_uart_startup()
350 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG); altera_uart_shutdown()
439 writel(c, port->membase + ALTERA_UART_TXDATA_REG); altera_uart_console_putc()
461 if (!port->membase) altera_uart_console_setup()
578 port->membase = ioremap(port->mapbase, ALTERA_UART_SIZE); altera_uart_probe()
579 if (!port->membase) altera_uart_probe()
H A Datmel_serial.c92 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
93 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
94 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
95 #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
96 #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
97 #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
98 #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
99 #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
100 #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
101 #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
102 #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
103 #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
104 #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR)
105 #define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME)
106 #define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION)
109 #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
110 #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
112 #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
113 #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
114 #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
115 #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
116 #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
118 #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
119 #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
120 #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
2146 iounmap(port->membase); atmel_release_port()
2147 port->membase = NULL; atmel_release_port()
2163 port->membase = ioremap(port->mapbase, size); atmel_request_port()
2164 if (port->membase == NULL) { atmel_request_port()
2283 port->membase = pdata->regs; atmel_init_port()
2286 port->membase = NULL; atmel_init_port()
2416 if (port->membase == NULL) { atmel_console_setup()
H A Duartlite.c99 return reg_ops->in(port->membase + offset); uart_in32()
106 reg_ops->out(val, port->membase + offset); uart_out32()
321 iounmap(port->membase); ulite_release_port()
322 port->membase = NULL; ulite_release_port()
337 port->membase = ioremap(port->mapbase, ULITE_REGION); ulite_request_port()
338 if (!port->membase) { ulite_request_port()
491 if (!port->membase) { ulite_console_setup()
579 port->membase = NULL; ulite_assign()
H A Dapbuart.h45 #define APBBASE(port) ((struct grlib_apbuart_regs_map *)((port)->membase))
H A Dmux.c71 #define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + IO_DATA_REG_OFFSET)
72 #define UART_GET_FIFO_CNT(p) __raw_readl((p)->membase + IO_DCOUNT_REG_OFFSET)
240 data = __raw_readl(port->membase + IO_DATA_REG_OFFSET); mux_read()
366 if(port->membase == NULL) mux_verify_port()
486 port->membase = ioremap_nocache(port->mapbase, MUX_LINE_OFFSET); mux_probe()
528 if(port->membase) mux_remove()
529 iounmap(port->membase); mux_remove()
H A Dbcm63xx_uart.c83 return __raw_readl(port->membase + offset); bcm_uart_readl()
89 __raw_writel(value, port->membase + offset); bcm_uart_writel()
743 if (!port->membase) bcm_console_setup()
782 if (!device->port.membase) bcm_early_console_setup()
823 if (port->membase) bcm_uart_probe()
832 port->membase = devm_ioremap_resource(&pdev->dev, res_mem); bcm_uart_probe()
833 if (IS_ERR(port->membase)) bcm_uart_probe()
834 return PTR_ERR(port->membase); bcm_uart_probe()
857 ports[pdev->id].membase = NULL; bcm_uart_probe()
871 ports[pdev->id].membase = NULL; bcm_uart_remove()
H A Dsb1250-duart.c127 void __iomem *csr = sport->port.membase + reg; __read_sbdchn()
141 void __iomem *csr = sport->port.membase + reg; __write_sbdchn()
661 iounmap(uport->membase); sbd_release_port()
662 uport->membase = NULL; sbd_release_port()
676 if (!uport->membase) sbd_map_port()
677 uport->membase = ioremap_nocache(uport->mapbase, sbd_map_port()
679 if (!uport->membase) { sbd_map_port()
689 iounmap(uport->membase); sbd_map_port()
690 uport->membase = NULL; sbd_map_port()
H A Dvr41xx_siu.c72 #define siu_read(port, offset) readb((port)->membase + (offset))
73 #define siu_write(port, offset, value) writeb((value), (port)->membase + (offset))
451 if (port->membase == NULL) siu_startup()
633 iounmap(port->membase); siu_release_port()
634 port->membase = NULL; siu_release_port()
652 port->membase = ioremap(port->mapbase, size); siu_request_port()
653 if (port->membase == NULL) { siu_request_port()
797 if (port->membase == NULL) { siu_console_setup()
800 port->membase = ioremap(port->mapbase, siu_port_size(port)); siu_console_setup()
H A Dvt8500_serial.c127 writel(val, port->membase + off); vt8500_write()
132 return readl(port->membase + off); vt8500_read()
182 c = readw(port->membase + VT8500_RXFIFO) & 0x3ff; handle_rx()
210 writeb(port->x_char, port->membase + VT8500_TXFIFO); handle_tx()
223 writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO); handle_tx()
505 writeb(c, port->membase + VT8500_TXFIFO); vt8500_console_putchar()
685 vt8500_port->uart.membase = devm_ioremap_resource(&pdev->dev, mmres); vt8500_serial_probe()
686 if (IS_ERR(vt8500_port->uart.membase)) vt8500_serial_probe()
687 return PTR_ERR(vt8500_port->uart.membase); vt8500_serial_probe()
H A Dearlycon.c117 port->membase = earlycon_map(port->mapbase, 64); register_earlycon()
205 port->membase = earlycon_map(addr, SZ_4K); of_setup_earlycon()
H A Dmsm_serial.h131 writel_relaxed(val, port->membase + off); msm_write()
137 return readl_relaxed(port->membase + off); msm_read()
H A Dsccnxp.c217 return readb(port->membase + (reg << port->regshift)); sccnxp_read()
222 writeb(v, port->membase + (reg << port->regshift)); sccnxp_write()
856 void __iomem *membase; sccnxp_probe() local
859 membase = devm_ioremap_resource(&pdev->dev, res); sccnxp_probe()
860 if (IS_ERR(membase)) sccnxp_probe()
861 return PTR_ERR(membase); sccnxp_probe()
951 s->port[i].membase = membase; sccnxp_probe()
H A Dsprd_serial.c126 return readl_relaxed(port->membase + offset); serial_in()
131 writel_relaxed(value, port->membase + offset); serial_out()
603 !(readl(port->membase + SPRD_LSR) & SPRD_LSR_TX_OVER)) sprd_putc()
606 writeb(c, port->membase + SPRD_TXD); sprd_putc()
621 if (!device->port.membase) sprd_early_console_setup()
728 up->membase = devm_ioremap_resource(&pdev->dev, res); sprd_probe()
729 if (IS_ERR(up->membase)) sprd_probe()
730 return PTR_ERR(up->membase); sprd_probe()
H A Dst-asc.c155 return readl_relaxed(port->membase + offset); asc_in()
157 return readl(port->membase + offset); asc_in()
164 writel_relaxed(value, port->membase + offset); asc_out()
166 writel(value, port->membase + offset); asc_out()
679 port->membase = devm_ioremap_resource(&pdev->dev, res); asc_init_port()
680 if (IS_ERR(port->membase)) asc_init_port()
681 return PTR_ERR(port->membase); asc_init_port()
853 if (ascport->port.mapbase == 0 || ascport->port.membase == NULL) asc_console_setup()
H A Dmsm_serial.c138 ioread32_rep(port->membase + UARTDM_RF, buf, 1); handle_rx_dm()
243 tf = port->membase + UARTDM_TF; handle_tx()
245 tf = port->membase + UART_TF; handle_tx()
611 iounmap(port->membase); msm_release_port()
612 port->membase = NULL; msm_release_port()
631 port->membase = ioremap(port->mapbase, size); msm_request_port()
632 if (!port->membase) { msm_request_port()
857 tf = port->membase + UARTDM_TF; __msm_console_write()
859 tf = port->membase + UART_TF; __msm_console_write()
933 if (unlikely(!port->membase)) msm_console_setup()
957 if (!device->port.membase) msm_serial_early_console_setup()
979 if (!device->port.membase) msm_serial_early_console_setup_dm()
H A Dar933x_uart.c63 return readl(up->port.membase + offset); ar933x_uart_read()
69 writel(value, up->port.membase + offset); ar933x_uart_write()
675 port->membase = devm_ioremap_resource(&pdev->dev, mem_res); ar933x_uart_probe()
676 if (IS_ERR(port->membase)) ar933x_uart_probe()
677 return PTR_ERR(port->membase); ar933x_uart_probe()
H A Dserial_txx9.c177 return __raw_readl(up->port.membase + offset); sio_in()
188 __raw_writel(value, up->port.membase + offset); sio_out()
769 up->port.membase = ioremap(up->port.mapbase, size); serial_txx9_request_resource()
770 if (!up->port.membase) { serial_txx9_request_resource()
795 iounmap(up->port.membase); serial_txx9_release_resource()
796 up->port.membase = NULL; serial_txx9_release_resource()
1044 uart->port.membase = port->membase; serial_txx9_register_port()
1078 uart->port.membase = NULL; serial_txx9_unregister_port()
1095 port.membase = p->membase; serial_txx9_probe()
H A Ddz.c104 void __iomem *addr = dport->port.membase + offset; dz_in()
111 void __iomem *addr = dport->port.membase + offset; dz_out()
668 iounmap(uport->membase); dz_release_port()
669 uport->membase = NULL; dz_release_port()
678 if (!uport->membase) dz_map_port()
679 uport->membase = ioremap_nocache(uport->mapbase, dz_map_port()
681 if (!uport->membase) { dz_map_port()
H A Darc_uart.c12 * +Using platform_get_resource() for irq/membase (thx to bfin_uart.c)
75 #define RBASE(port, reg) (port->membase + reg)
507 if (!port->membase) arc_serial_console_setup()
566 if (!dev->port.membase) arc_early_console_setup()
615 port->membase = of_iomap(np, 0); arc_serial_probe()
616 if (!port->membase) arc_serial_probe()
H A Defm32-uart.c93 writel_relaxed(value, efm_port->port.membase + offset); efm32_uart_write32()
99 return readl_relaxed(efm_port->port.membase + offset); efm32_uart_read32()
438 iounmap(port->membase); efm32_uart_release_port()
446 port->membase = ioremap(port->mapbase, 60); efm32_uart_request_port()
447 if (!efm_port->port.membase) { efm32_uart_request_port()
465 iounmap(port->membase); efm32_uart_request_port()
H A Dzs.c143 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET; read_zsreg()
158 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET; write_zsreg()
172 void __iomem *data = zport->port.membase + read_zsdata()
183 void __iomem *data = zport->port.membase + write_zsdata()
986 iounmap(uport->membase); zs_release_port()
987 uport->membase = 0; zs_release_port()
993 if (!uport->membase) zs_map_port()
994 uport->membase = ioremap_nocache(uport->mapbase, zs_map_port()
996 if (!uport->membase) { zs_map_port()
H A Dmpc52xx_uart.c80 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
767 #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
1274 iounmap(port->membase); mpc52xx_uart_release_port()
1275 port->membase = NULL; mpc52xx_uart_release_port()
1287 port->membase = ioremap(port->mapbase, mpc52xx_uart_request_port()
1290 if (!port->membase) mpc52xx_uart_request_port()
1311 iounmap(port->membase); mpc52xx_uart_request_port()
1312 port->membase = NULL; mpc52xx_uart_request_port()
1651 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc)); mpc52xx_console_setup()
1654 if (port->membase == NULL) mpc52xx_console_setup()
1658 (void *)port->mapbase, port->membase, mpc52xx_console_setup()
H A Dbfin_uart.c1237 if (!(bfin_earlyprintk_port.port.membase bfin_serial_probe()
1271 uart->port.membase = ioremap(res->start, resource_size(res)); bfin_serial_probe()
1272 if (!uart->port.membase) { bfin_serial_probe()
1357 iounmap(uart->port.membase); bfin_serial_probe()
1376 iounmap(uart->port.membase); bfin_serial_remove()
1445 bfin_earlyprintk_port.port.membase = ioremap(res->start, bfin_earlyprintk_probe()
1447 if (!bfin_earlyprintk_port.port.membase) { bfin_earlyprintk_probe()
1498 if (!bfin_earlyprintk_port.port.membase) bfin_earlyserial_init()
H A Dm32r_sio.c19 * A note about mapbase / membase
25 * membase is an 'ioremapped' cookie. This is compatible with the old
850 iounmap(up->port.membase); m32r_sio_release_port()
851 up->port.membase = NULL; m32r_sio_release_port()
889 up->port.membase = ioremap(up->port.mapbase, size); m32r_sio_request_port()
890 if (!up->port.membase) m32r_sio_request_port()
960 up->port.membase = old_serial_port[i].iomem_base; m32r_sio_init_ports()
H A Dsunsab.c976 up->port.membase = of_ioremap(&op->resource[0], offset, sunsab_init_one()
979 if (!up->port.membase) sunsab_init_one()
981 up->regs = (union sab82532_async_regs __iomem *) up->port.membase; sunsab_init_one()
1066 up[1].port.membase, sab_probe()
1070 up[0].port.membase, sab_probe()
1083 up[1].port.membase, sab_remove()
1086 up[0].port.membase, sab_remove()
H A Dbfin_sport_uart.c794 sport->port.membase = ioremap(res->start, resource_size(res)); sport_uart_probe()
795 if (!sport->port.membase) { sport_uart_probe()
845 iounmap(sport->port.membase); sport_uart_probe()
865 iounmap(sport->port.membase); sport_uart_remove()
H A Dpxa.c63 return readl(up->port.membase + offset); serial_in()
69 writel(value, up->port.membase + offset); serial_out()
896 sport->port.membase = ioremap(mmres->start, resource_size(mmres)); serial_pxa_probe()
897 if (!sport->port.membase) { serial_pxa_probe()
H A Dsh-sci.c382 return ioread8(p->membase + (reg->offset << p->regshift)); sci_serial_in()
384 return ioread16(p->membase + (reg->offset << p->regshift)); sci_serial_in()
396 iowrite8(value, p->membase + (reg->offset << p->regshift)); sci_serial_out()
398 iowrite16(value, p->membase + (reg->offset << p->regshift)); sci_serial_out()
2095 * Nothing to do if there's already an established membase. sci_remap_port()
2097 if (port->membase) sci_remap_port()
2101 port->membase = ioremap_nocache(port->mapbase, size); sci_remap_port()
2102 if (unlikely(!port->membase)) { sci_remap_port()
2112 port->membase = (void __iomem *)(uintptr_t)port->mapbase; sci_remap_port()
2121 iounmap(port->membase); sci_release_port()
2122 port->membase = NULL; sci_release_port()
H A Dnwpserial.c379 up->port.membase = port->membase; nwpserial_register_port()
H A Dsunsu.c117 return readb(up->port.membase + offset); serial_in()
147 writeb(value, up->port.membase + offset); serial_out()
1443 up->port.membase = of_ioremap(rp, 0, up->reg_size, "su"); su_probe()
1444 if (!up->port.membase) { su_probe()
1462 up->port.membase, up->reg_size); su_probe()
1502 of_iounmap(&op->resource[0], up->port.membase, up->reg_size); su_probe()
1522 if (up->port.membase) su_remove()
1523 of_iounmap(&op->resource[0], up->port.membase, up->reg_size); su_remove()
H A Dsamsung.c1004 port, (unsigned long long)port->mapbase, port->membase); s3c24xx_serial_startup()
1052 port, (unsigned long long)port->mapbase, port->membase); s3c64xx_serial_startup()
1730 port->membase = devm_ioremap(port->dev, res->start, resource_size(res)); s3c24xx_serial_init_port()
1731 if (!port->membase) { s3c24xx_serial_init_port()
1784 &port->mapbase, port->membase, port->irq, s3c24xx_serial_init_port()
2427 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE)) samsung_early_busyuart()
2435 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask) samsung_early_busyuart_fifo()
2441 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) samsung_early_putc()
2446 writeb(c, port->membase + S3C2410_UTXH); samsung_early_putc()
2459 if (!device->port.membase) samsung_early_console_setup()
H A Dserial-tegra.c144 return readl(tup->uport.membase + (reg << tup->uport.regshift)); tegra_uart_read()
150 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); tegra_uart_write()
1307 u->membase = devm_ioremap_resource(&pdev->dev, resource); tegra_uart_probe()
1308 if (IS_ERR(u->membase)) tegra_uart_probe()
1309 return PTR_ERR(u->membase); tegra_uart_probe()
H A Dsirfsoc_uart.h445 #define portaddr(port, reg) ((port)->membase + (reg))
H A Dpnx8xxx_uart.c71 return (__raw_readl(sport->port.membase + offset)); serial_in()
76 __raw_writel(value, sport->port.membase + offset); serial_out()
H A Domap-serial.c185 return readw(up->port.membase + offset); serial_in()
191 writew(value, up->port.membase + offset); serial_out()
1510 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift)); omap_serial_fill_features_erratas()
1695 up->port.membase = base; serial_omap_probe()
H A Dsunhv.c554 port->membase = (unsigned char __iomem *) __pa(port); hv_probe()
H A Dip22zilog.c90 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
1102 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB; ip22zilog_prepare()
1103 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA; ip22zilog_prepare()
H A Dsunzilog.c108 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
1435 up[0].port.membase = (void __iomem *) &rp->channelA; zs_probe()
1452 up[1].port.membase = (void __iomem *) &rp->channelB; zs_probe()
H A Dapbuart.c623 port->membase = ioremap(addr, sizeof(struct grlib_apbuart_regs_map)); for_each_matching_node()
H A Dpmac_zilog.c1429 uap->port.membase = ioremap(uap->port.mapbase, 0x1000); pmz_init_port()
1431 uap->control_reg = uap->port.membase; pmz_init_port()
1727 uap->port.membase = (unsigned char __iomem *) r_ports->start; pmz_init_port()
1736 uap->control_reg = uap->port.membase; pmz_init_port()
/linux-4.1.27/drivers/net/ethernet/allwinner/
H A Dsun4i-emac.c71 void __iomem *membase; member in struct:emac_board_info
94 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); emac_update_speed()
98 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); emac_update_speed()
107 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); emac_update_duplex()
111 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); emac_update_duplex()
192 writel(0, db->membase + EMAC_CTL_REG); emac_reset()
194 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); emac_reset()
266 reg_val = readl(db->membase + EMAC_TX_MODE_REG); emac_setup()
269 db->membase + EMAC_TX_MODE_REG); emac_setup()
273 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); emac_setup()
276 db->membase + EMAC_MAC_CTL0_REG); emac_setup()
279 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); emac_setup()
283 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); emac_setup()
286 writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG); emac_setup()
290 db->membase + EMAC_MAC_IPGR_REG); emac_setup()
294 db->membase + EMAC_MAC_CLRT_REG); emac_setup()
298 db->membase + EMAC_MAC_MAXF_REG); emac_setup()
309 reg_val = readl(db->membase + EMAC_RX_CTL_REG); emac_set_rx_mode()
320 db->membase + EMAC_RX_CTL_REG); emac_set_rx_mode()
330 reg_val = readl(db->membase + EMAC_RX_CTL_REG); emac_powerup()
332 writel(reg_val, db->membase + EMAC_RX_CTL_REG); emac_powerup()
337 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); emac_powerup()
339 writel(reg_val, db->membase + EMAC_MAC_CTL0_REG); emac_powerup()
342 reg_val = readl(db->membase + EMAC_MAC_MCFG_REG); emac_powerup()
345 writel(reg_val, db->membase + EMAC_MAC_MCFG_REG); emac_powerup()
348 writel(0x0, db->membase + EMAC_RX_FBC_REG); emac_powerup()
351 writel(0, db->membase + EMAC_INT_CTL_REG); emac_powerup()
352 reg_val = readl(db->membase + EMAC_INT_STA_REG); emac_powerup()
353 writel(reg_val, db->membase + EMAC_INT_STA_REG); emac_powerup()
362 dev_addr[2], db->membase + EMAC_MAC_A1_REG); emac_powerup()
364 dev_addr[5], db->membase + EMAC_MAC_A0_REG); emac_powerup()
382 dev_addr[2], db->membase + EMAC_MAC_A1_REG); emac_set_mac_address()
384 dev_addr[5], db->membase + EMAC_MAC_A0_REG); emac_set_mac_address()
402 reg_val = readl(db->membase + EMAC_CTL_REG); emac_init_device()
404 db->membase + EMAC_CTL_REG); emac_init_device()
407 reg_val = readl(db->membase + EMAC_INT_CTL_REG); emac_init_device()
409 writel(reg_val, db->membase + EMAC_INT_CTL_REG); emac_init_device()
454 writel(channel, db->membase + EMAC_TX_INS_REG); emac_start_xmit()
456 emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG, emac_start_xmit()
464 writel(skb->len, db->membase + EMAC_TX_PL0_REG); emac_start_xmit()
466 writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1, emac_start_xmit()
467 db->membase + EMAC_TX_CTL0_REG); emac_start_xmit()
473 writel(skb->len, db->membase + EMAC_TX_PL1_REG); emac_start_xmit()
475 writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1, emac_start_xmit()
476 db->membase + EMAC_TX_CTL1_REG); emac_start_xmit()
532 rxcount = readl(db->membase + EMAC_RX_FBC_REG); emac_rx()
548 reg_val = readl(db->membase + EMAC_RX_CTL_REG); emac_rx()
550 writel(reg_val, db->membase + EMAC_RX_CTL_REG); emac_rx()
555 reg_val = readl(db->membase + EMAC_INT_CTL_REG); emac_rx()
557 writel(reg_val, db->membase + EMAC_INT_CTL_REG); emac_rx()
560 rxcount = readl(db->membase + EMAC_RX_FBC_REG); emac_rx()
565 reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG); emac_rx()
570 reg_val = readl(db->membase + EMAC_CTL_REG); emac_rx()
572 db->membase + EMAC_CTL_REG); emac_rx()
575 reg_val = readl(db->membase + EMAC_RX_CTL_REG); emac_rx()
577 db->membase + EMAC_RX_CTL_REG); emac_rx()
580 reg_val = readl(db->membase + EMAC_RX_CTL_REG); emac_rx()
584 reg_val = readl(db->membase + EMAC_CTL_REG); emac_rx()
586 db->membase + EMAC_CTL_REG); emac_rx()
587 reg_val = readl(db->membase + EMAC_INT_CTL_REG); emac_rx()
589 writel(reg_val, db->membase + EMAC_INT_CTL_REG); emac_rx()
599 emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG, emac_rx()
647 emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG, emac_rx()
673 writel(0, db->membase + EMAC_INT_CTL_REG); emac_interrupt()
677 int_status = readl(db->membase + EMAC_INT_STA_REG); emac_interrupt()
679 writel(int_status, db->membase + EMAC_INT_STA_REG); emac_interrupt()
700 reg_val = readl(db->membase + EMAC_INT_CTL_REG); emac_interrupt()
702 writel(reg_val, db->membase + EMAC_INT_CTL_REG); emac_interrupt()
758 writel(0, db->membase + EMAC_INT_CTL_REG); emac_shutdown()
761 reg_val = readl(db->membase + EMAC_INT_STA_REG); emac_shutdown()
762 writel(reg_val, db->membase + EMAC_INT_STA_REG); emac_shutdown()
765 reg_val = readl(db->membase + EMAC_CTL_REG); emac_shutdown()
767 writel(reg_val, db->membase + EMAC_CTL_REG); emac_shutdown()
836 db->membase = of_iomap(np, 0); emac_probe()
837 if (!db->membase) { emac_probe()
844 ndev->base_addr = (unsigned long)db->membase; emac_probe()
900 ndev->name, db->membase, ndev->irq, ndev->dev_addr); emac_probe()
/linux-4.1.27/drivers/isdn/hisax/
H A Dtelespci.c183 return (readisac(cs->hw.teles0.membase, offset)); ReadISAC()
189 writeisac(cs->hw.teles0.membase, offset, value); WriteISAC()
195 read_fifo_isac(cs->hw.teles0.membase, data, size); ReadISACfifo()
201 write_fifo_isac(cs->hw.teles0.membase, data, size); WriteISACfifo()
207 return (readhscx(cs->hw.teles0.membase, hscx, offset)); ReadHSCX()
213 writehscx(cs->hw.teles0.membase, hscx, offset, value); WriteHSCX()
220 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
221 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
222 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
223 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
235 hval = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA); telespci_interrupt()
238 ival = readisac(cs->hw.teles0.membase, ISAC_ISTA); telespci_interrupt()
246 writel(0x70000000, cs->hw.teles0.membase + 0x3C); telespci_interrupt()
248 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF); telespci_interrupt()
249 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF); telespci_interrupt()
250 writeisac(cs->hw.teles0.membase, ISAC_MASK, 0xFF); telespci_interrupt()
251 writeisac(cs->hw.teles0.membase, ISAC_MASK, 0x0); telespci_interrupt()
252 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0); telespci_interrupt()
253 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0); telespci_interrupt()
261 iounmap(cs->hw.teles0.membase); release_io_telespci()
306 cs->hw.teles0.membase = ioremap(pci_resource_start(dev_tel, 0), setup_telespci()
317 writel(0x00000000, cs->hw.teles0.membase + 0x28); setup_telespci()
318 writel(0x01000000, cs->hw.teles0.membase + 0x28); setup_telespci()
319 writel(0x01000000, cs->hw.teles0.membase + 0x28); setup_telespci()
320 writel(0x7BFFFFFF, cs->hw.teles0.membase + 0x2C); setup_telespci()
321 writel(0x70000000, cs->hw.teles0.membase + 0x3C); setup_telespci()
322 writel(0x61000000, cs->hw.teles0.membase + 0x40); setup_telespci()
323 /* writel(0x00800000, cs->hw.teles0.membase + 0x200); */ setup_telespci()
328 cs->hw.teles0.membase); setup_telespci()
H A Dteles0.c100 return (readisac(cs->hw.teles0.membase, offset)); ReadISAC()
106 writeisac(cs->hw.teles0.membase, offset, value); WriteISAC()
112 read_fifo_isac(cs->hw.teles0.membase, data, size); ReadISACfifo()
118 write_fifo_isac(cs->hw.teles0.membase, data, size); WriteISACfifo()
124 return (readhscx(cs->hw.teles0.membase, hscx, offset)); ReadHSCX()
130 writehscx(cs->hw.teles0.membase, hscx, offset, value); WriteHSCX()
137 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
138 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
139 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
140 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
153 val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA); teles0_interrupt()
157 val = readisac(cs->hw.teles0.membase, ISAC_ISTA); teles0_interrupt()
162 val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA); teles0_interrupt()
168 val = readisac(cs->hw.teles0.membase, ISAC_ISTA); teles0_interrupt()
174 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF); teles0_interrupt()
175 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF); teles0_interrupt()
176 writeisac(cs->hw.teles0.membase, ISAC_MASK, 0xFF); teles0_interrupt()
177 writeisac(cs->hw.teles0.membase, ISAC_MASK, 0x0); teles0_interrupt()
178 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0); teles0_interrupt()
179 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0); teles0_interrupt()
189 iounmap(cs->hw.teles0.membase); release_io_teles0()
234 writeb(0, cs->hw.teles0.membase + 0x80); mb(); reset_teles0()
236 writeb(1, cs->hw.teles0.membase + 0x80); mb(); reset_teles0()
285 "Teles0: membase configured DOSish, assuming 0x%lx\n", setup_teles0()
336 cs->hw.teles0.membase = ioremap(cs->hw.teles0.phymem, TELES_IOMEM_SIZE); setup_teles0()
340 cs->hw.teles0.membase, cs->hw.teles0.cfg_reg); setup_teles0()
/linux-4.1.27/drivers/net/phy/
H A Dmdio-sun4i.c35 void __iomem *membase; member in struct:sun4i_mdio_data
46 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); sun4i_mdio_read()
48 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); sun4i_mdio_read()
52 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { sun4i_mdio_read()
59 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); sun4i_mdio_read()
61 value = readl(data->membase + EMAC_MAC_MRDD_REG); sun4i_mdio_read()
73 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); sun4i_mdio_write()
75 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); sun4i_mdio_write()
79 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { sun4i_mdio_write()
86 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); sun4i_mdio_write()
88 writel(value, data->membase + EMAC_MAC_MWTD_REG); sun4i_mdio_write()
123 data->membase = devm_ioremap_resource(&pdev->dev, res); sun4i_mdio_probe()
124 if (IS_ERR(data->membase)) { sun4i_mdio_probe()
125 ret = PTR_ERR(data->membase); sun4i_mdio_probe()
/linux-4.1.27/drivers/gpio/
H A Dgpio-timberdale.c46 void __iomem *membase; member in struct:timbgpio
60 reg = ioread32(tgpio->membase + offset); timbgpio_update_bit()
67 iowrite32(reg, tgpio->membase + offset); timbgpio_update_bit()
83 value = ioread32(tgpio->membase + TGPIOVAL); timbgpio_gpio_get()
120 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); timbgpio_irq_disable()
132 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); timbgpio_irq_enable()
148 ver = ioread32(tgpio->membase + TGPIO_VER); timbgpio_irq_type()
152 lvr = ioread32(tgpio->membase + TGPIO_LVR); timbgpio_irq_type()
153 flr = ioread32(tgpio->membase + TGPIO_FLR); timbgpio_irq_type()
155 bflr = ioread32(tgpio->membase + TGPIO_BFLR); timbgpio_irq_type()
183 iowrite32(lvr, tgpio->membase + TGPIO_LVR); timbgpio_irq_type()
184 iowrite32(flr, tgpio->membase + TGPIO_FLR); timbgpio_irq_type()
186 iowrite32(bflr, tgpio->membase + TGPIO_BFLR); timbgpio_irq_type()
188 iowrite32(1 << offset, tgpio->membase + TGPIO_ICR); timbgpio_irq_type()
202 ipr = ioread32(tgpio->membase + TGPIO_IPR); timbgpio_irq()
203 iowrite32(ipr, tgpio->membase + TGPIO_ICR); timbgpio_irq()
209 iowrite32(0, tgpio->membase + TGPIO_IER); timbgpio_irq()
214 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); timbgpio_irq()
260 tgpio->membase = devm_ioremap(dev, iomem->start, resource_size(iomem)); timbgpio_probe()
261 if (!tgpio->membase) { timbgpio_probe()
288 iowrite32(0x0, tgpio->membase + TGPIO_IER); timbgpio_probe()
H A Dgpio-mvebu.c81 void __iomem *membase; member in struct:mvebu_gpio_chip
102 return mvchip->membase + GPIO_OUT_OFF; mvebu_gpioreg_out()
107 return mvchip->membase + GPIO_BLINK_EN_OFF; mvebu_gpioreg_blink()
113 return mvchip->membase + GPIO_IO_CONF_OFF; mvebu_gpioreg_io_conf()
118 return mvchip->membase + GPIO_IN_POL_OFF; mvebu_gpioreg_in_pol()
124 return mvchip->membase + GPIO_DATA_IN_OFF; mvebu_gpioreg_data_in()
135 return mvchip->membase + GPIO_EDGE_CAUSE_OFF; mvebu_gpioreg_edge_cause()
152 return mvchip->membase + GPIO_EDGE_MASK_OFF; mvebu_gpioreg_edge_mask()
155 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); mvebu_gpioreg_edge_mask()
171 return mvchip->membase + GPIO_LEVEL_MASK_OFF; mvebu_gpioreg_level_mask()
174 return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); mvebu_gpioreg_level_mask()
592 readl(mvchip->membase + GPIO_EDGE_MASK_OFF); mvebu_gpio_suspend()
594 readl(mvchip->membase + GPIO_LEVEL_MASK_OFF); mvebu_gpio_suspend()
599 readl(mvchip->membase + mvebu_gpio_suspend()
602 readl(mvchip->membase + mvebu_gpio_suspend()
609 readl(mvchip->membase + mvebu_gpio_suspend()
612 readl(mvchip->membase + mvebu_gpio_suspend()
636 mvchip->membase + GPIO_EDGE_MASK_OFF); mvebu_gpio_resume()
638 mvchip->membase + GPIO_LEVEL_MASK_OFF); mvebu_gpio_resume()
643 mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i)); mvebu_gpio_resume()
645 mvchip->membase + mvebu_gpio_resume()
652 mvchip->membase + mvebu_gpio_resume()
655 mvchip->membase + mvebu_gpio_resume()
727 mvchip->membase = devm_ioremap_resource(&pdev->dev, res); mvebu_gpio_probe()
728 if (IS_ERR(mvchip->membase)) mvebu_gpio_probe()
729 return PTR_ERR(mvchip->membase); mvebu_gpio_probe()
746 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); mvebu_gpio_probe()
747 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); mvebu_gpio_probe()
748 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); mvebu_gpio_probe()
751 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); mvebu_gpio_probe()
753 writel_relaxed(0, mvchip->membase + mvebu_gpio_probe()
755 writel_relaxed(0, mvchip->membase + mvebu_gpio_probe()
760 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); mvebu_gpio_probe()
761 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); mvebu_gpio_probe()
762 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); mvebu_gpio_probe()
802 mvchip->membase, handle_level_irq); mvebu_gpio_probe()
/linux-4.1.27/drivers/reset/
H A Dreset-socfpga.c31 void __iomem *membase; member in struct:socfpga_reset_data
48 reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS)); socfpga_reset_assert()
49 writel(reg | BIT(offset), data->membase + OFFSET_MODRST + socfpga_reset_assert()
70 reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS)); socfpga_reset_deassert()
71 writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST + socfpga_reset_deassert()
88 reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS)); socfpga_reset_status()
119 data->membase = devm_ioremap_resource(&pdev->dev, res); socfpga_reset_probe()
120 if (IS_ERR(data->membase)) socfpga_reset_probe()
121 return PTR_ERR(data->membase); socfpga_reset_probe()
H A Dreset-sunxi.c27 void __iomem *membase; member in struct:sunxi_reset_data
44 reg = readl(data->membase + (bank * 4)); sunxi_reset_assert()
45 writel(reg & ~BIT(offset), data->membase + (bank * 4)); sunxi_reset_assert()
65 reg = readl(data->membase + (bank * 4)); sunxi_reset_deassert()
66 writel(reg | BIT(offset), data->membase + (bank * 4)); sunxi_reset_deassert()
99 data->membase = ioremap(res.start, size); sunxi_reset_init()
100 if (!data->membase) { sunxi_reset_init()
158 data->membase = devm_ioremap_resource(&pdev->dev, res); sunxi_reset_probe()
159 if (IS_ERR(data->membase)) sunxi_reset_probe()
160 return PTR_ERR(data->membase); sunxi_reset_probe()
/linux-4.1.27/drivers/atm/
H A Didt77252.h352 void __iomem *membase; /* SAR's memory base address */ member in struct:idt77252_dev
438 #define SAR_REG_DR0 (card->membase + 0x00)
439 #define SAR_REG_DR1 (card->membase + 0x04)
440 #define SAR_REG_DR2 (card->membase + 0x08)
441 #define SAR_REG_DR3 (card->membase + 0x0C)
442 #define SAR_REG_CMD (card->membase + 0x10)
443 #define SAR_REG_CFG (card->membase + 0x14)
444 #define SAR_REG_STAT (card->membase + 0x18)
445 #define SAR_REG_RSQB (card->membase + 0x1C)
446 #define SAR_REG_RSQT (card->membase + 0x20)
447 #define SAR_REG_RSQH (card->membase + 0x24)
448 #define SAR_REG_CDC (card->membase + 0x28)
449 #define SAR_REG_VPEC (card->membase + 0x2C)
450 #define SAR_REG_ICC (card->membase + 0x30)
451 #define SAR_REG_RAWCT (card->membase + 0x34)
452 #define SAR_REG_TMR (card->membase + 0x38)
453 #define SAR_REG_TSTB (card->membase + 0x3C)
454 #define SAR_REG_TSQB (card->membase + 0x40)
455 #define SAR_REG_TSQT (card->membase + 0x44)
456 #define SAR_REG_TSQH (card->membase + 0x48)
457 #define SAR_REG_GP (card->membase + 0x4C)
458 #define SAR_REG_VPM (card->membase + 0x50)
459 #define SAR_REG_RXFD (card->membase + 0x54)
460 #define SAR_REG_RXFT (card->membase + 0x58)
461 #define SAR_REG_RXFH (card->membase + 0x5C)
462 #define SAR_REG_RAWHND (card->membase + 0x60)
463 #define SAR_REG_RXSTAT (card->membase + 0x64)
464 #define SAR_REG_ABRSTD (card->membase + 0x68)
465 #define SAR_REG_ABRRQ (card->membase + 0x6C)
466 #define SAR_REG_VBRRQ (card->membase + 0x70)
467 #define SAR_REG_RTBL (card->membase + 0x74)
468 #define SAR_REG_MDFCT (card->membase + 0x78)
469 #define SAR_REG_TXSTAT (card->membase + 0x7C)
470 #define SAR_REG_TCMDQ (card->membase + 0x80)
471 #define SAR_REG_IRCP (card->membase + 0x84)
472 #define SAR_REG_FBQP0 (card->membase + 0x88)
473 #define SAR_REG_FBQP1 (card->membase + 0x8C)
474 #define SAR_REG_FBQP2 (card->membase + 0x90)
475 #define SAR_REG_FBQP3 (card->membase + 0x94)
476 #define SAR_REG_FBQS0 (card->membase + 0x98)
477 #define SAR_REG_FBQS1 (card->membase + 0x9C)
478 #define SAR_REG_FBQS2 (card->membase + 0xA0)
479 #define SAR_REG_FBQS3 (card->membase + 0xA4)
480 #define SAR_REG_FBQWP0 (card->membase + 0xA8)
481 #define SAR_REG_FBQWP1 (card->membase + 0xAC)
482 #define SAR_REG_FBQWP2 (card->membase + 0xB0)
483 #define SAR_REG_FBQWP3 (card->membase + 0xB4)
484 #define SAR_REG_NOW (card->membase + 0xB8)
H A Dnicstar.c104 #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
213 writel(0x00000000, card->membase + CFG); nicstar_remove_one()
252 iounmap(card->membase); nicstar_remove_one()
317 writel(sram_address, card->membase + CMD); ns_read_sram()
319 data = readl(card->membase + DR0); ns_read_sram()
335 writel(*(value++), card->membase + i); ns_write_sram()
337 so card->membase + DR0 == card->membase */ ns_write_sram()
341 writel(sram_address, card->membase + CMD); ns_write_sram()
355 unsigned long membase; ns_init_card() local
390 membase = pci_resource_start(pcidev, 1); ns_init_card()
391 card->membase = ioremap(membase, NS_IOREMAP_SIZE); ns_init_card()
392 if (!card->membase) { ns_init_card()
393 printk("nicstar%d: can't ioremap() membase.\n", i); ns_init_card()
398 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase); ns_init_card()
429 data = readl(card->membase + STAT); ns_init_card()
431 writel(NS_STAT_TMROF, card->membase + STAT); ns_init_card()
434 writel(NS_CFG_SWRST, card->membase + CFG); ns_init_card()
436 writel(0x00000000, card->membase + CFG); ns_init_card()
439 writel(0x00000008, card->membase + GP); ns_init_card()
441 writel(0x00000001, card->membase + GP); ns_init_card()
444 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */ ns_init_card()
449 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD); ns_init_card()
451 data = readl(card->membase + DR0); ns_init_card()
457 writel(0x00000008, card->membase + DR0); ns_init_card()
458 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD); ns_init_card()
460 writel(NS_STAT_SFBQF, card->membase + STAT); ns_init_card()
463 writel(0x00000022, card->membase + DR0); ns_init_card()
464 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD); ns_init_card()
473 writel(0x00000002, card->membase + DR0); ns_init_card()
474 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD); ns_init_card()
483 writel(0x00000000, card->membase + GP); ns_init_card()
523 nicstar_init_eprom(card->membase); ns_init_card()
526 writel(0x00000000, card->membase + VPM); ns_init_card()
543 writel(0x00000000, card->membase + TSQH); ns_init_card()
544 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB); ns_init_card()
562 writel(0x00000000, card->membase + RSQH); ns_init_card()
563 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB); ns_init_card()
600 writel(NS_TST0 << 2, card->membase + TSTB); ns_init_card()
688 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) { ns_init_card()
718 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) { ns_init_card()
774 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET, ns_init_card()
777 nicstar_read_eprom(card->membase, ns_init_card()
806 NS_CFG_PHYIE, card->membase + CFG); ns_init_card()
816 writel(0x00000000, card->membase + CFG); ns_init_card_error()
849 iounmap(card->membase); ns_init_card_error()
965 stat = readl(card->membase + STAT); push_rxbufs()
1029 writel(addr2, card->membase + DR3); push_rxbufs()
1030 writel(id2, card->membase + DR2); push_rxbufs()
1031 writel(addr1, card->membase + DR1); push_rxbufs()
1032 writel(id1, card->membase + DR0); push_rxbufs()
1034 card->membase + CMD); push_rxbufs()
1046 writel((readl(card->membase + CFG) | NS_CFG_EFBIE), push_rxbufs()
1047 card->membase + CFG); push_rxbufs()
1069 stat_r = readl(card->membase + STAT); ns_irq_handler()
1075 writel(NS_STAT_TSIF, card->membase + STAT); ns_irq_handler()
1080 writel(NS_STAT_TXICP, card->membase + STAT); ns_irq_handler()
1087 writel(NS_STAT_TSQF, card->membase + STAT); ns_irq_handler()
1094 writel(NS_STAT_TMROF, card->membase + STAT); ns_irq_handler()
1100 writel(NS_STAT_PHYI, card->membase + STAT); ns_irq_handler()
1109 writel(NS_STAT_SFBQF, card->membase + STAT); ns_irq_handler()
1116 writel(NS_STAT_LFBQF, card->membase + STAT); ns_irq_handler()
1123 writel(NS_STAT_RSQF, card->membase + STAT); ns_irq_handler()
1132 writel(NS_STAT_EOPDU, card->membase + STAT); ns_irq_handler()
1137 writel(NS_STAT_RAWCF, card->membase + STAT); ns_irq_handler()
1145 while (readl(card->membase + RAWCT) != card->rawch) { ns_irq_handler()
1169 writel(NS_STAT_SFBQE, card->membase + STAT); ns_irq_handler()
1175 writel(readl(card->membase + CFG) & ns_irq_handler()
1176 ~NS_CFG_EFBIE, card->membase + CFG); ns_irq_handler()
1194 writel(NS_STAT_LFBQE, card->membase + STAT); ns_irq_handler()
1200 writel(readl(card->membase + CFG) & ns_irq_handler()
1201 ~NS_CFG_EFBIE, card->membase + CFG); ns_irq_handler()
1216 writel(NS_STAT_RSQAF, card->membase + STAT); ns_irq_handler()
1432 card->membase + CMD); ns_close()
1440 stat = readl(card->membase + STAT); ns_close()
1549 stat = readl(card->membase + STAT); ns_close()
1550 cfg = readl(card->membase + CFG); ns_close()
1555 card->tsq.last, readl(card->membase + TSQT)); ns_close()
1559 card->rsq.last, readl(card->membase + RSQT)); ns_close()
1899 card->membase + TSQH); process_tsq()
1959 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH); process_rsq()
1975 stat = readl(card->membase + STAT); dequeue_rx()
2401 stat = readl(card->membase + STAT); ns_proc_read()
2438 card->membase + CMD); ns_proc_read()
2440 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF; ns_proc_read()
2478 ns_stat_sfbqc_get(readl(card->membase + STAT)); ns_ioctl()
2486 ns_stat_lfbqc_get(readl(card->membase + STAT)); ns_ioctl()
2698 stat_r = readl(card->membase + STAT); ns_poll()
2707 writel(stat_w, card->membase + STAT); ns_poll()
2723 writel((u32) value, card->membase + DR0); ns_phy_put()
2725 card->membase + CMD); ns_phy_put()
2739 card->membase + CMD); ns_phy_get()
2741 data = readl(card->membase + DR0) & 0x000000FF; ns_phy_get()
H A Dhe.c176 #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
177 #define he_readl(dev, reg) readl((dev)->membase + (reg))
976 unsigned long membase; he_start() local
989 membase = pci_resource_start(pci_dev, 0); he_start()
990 HPRINTK("membase = 0x%lx irq = %d.\n", membase, pci_dev->irq); he_start()
1050 if (!(he_dev->membase = ioremap(membase, HE_REGMAP_SIZE))) { he_start()
1537 if (he_dev->membase) { he_stop()
1606 if (he_dev->membase) he_stop()
1607 iounmap(he_dev->membase); he_stop()
2796 val = readl(he_dev->membase + HOST_CNTL); read_prom_byte()
H A Didt77252.c3102 if (card->membase) deinit_card()
3103 iounmap(card->membase); deinit_card()
3605 unsigned long membase, srambase; idt77252_init_one() local
3634 membase = pci_resource_start(pcidev, 1); idt77252_init_one()
3646 card->membase = ioremap(membase, 1024); idt77252_init_one()
3647 if (!card->membase) { idt77252_init_one()
3648 printk("%s: can't ioremap() membase\n", card->name); idt77252_init_one()
3691 'A' + card->revision - 1 : '?', membase, srambase, idt77252_init_one()
3727 iounmap(card->membase); idt77252_init_one()
H A Dambassador.h631 u32 * membase; member in struct:amb_dev
H A Dhorizon.h409 u32 * membase; member in struct:hrz_dev
H A Dambassador.c314 dev->membase[addr / sizeof(u32)] = data; wr_plain()
322 u32 data = dev->membase[addr / sizeof(u32)]; rd_plain()
334 dev->membase[addr / sizeof(u32)] = be; wr_mem()
342 __be32 be = dev->membase[addr / sizeof(u32)]; rd_mem()
2149 dev->membase = bus_to_virt(pci_resource_start(pci_dev, 0)); setup_dev()
/linux-4.1.27/arch/arm/mach-davinci/
H A Dserial.c39 WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset); serial_write_reg()
41 __raw_writel(value, p->membase + offset); serial_write_reg()
93 if (!p->membase && p->mapbase) { davinci_serial_init()
94 p->membase = ioremap(p->mapbase, SZ_4K); davinci_serial_init()
96 if (p->membase) davinci_serial_init()
102 if (p->membase && p->type != PORT_AR7) davinci_serial_init()
/linux-4.1.27/arch/mips/ralink/
H A Dcevt-rt3352.c33 void __iomem *membase; member in struct:systick_device
49 count = ioread32(sdev->membase + SYSTICK_COUNT); systick_next_event()
51 iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE); systick_next_event()
103 systick.membase + SYSTICK_CONFIG); systick_set_clock_mode()
110 iowrite32(0, systick.membase + SYSTICK_CONFIG); systick_set_clock_mode()
121 systick.membase = of_iomap(np, 0); ralink_systick_init()
122 if (!systick.membase) ralink_systick_init()
136 clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name, ralink_systick_init()
H A Dtimer.c32 void __iomem *membase; member in struct:rt_timer
40 __raw_writel(val, rt->membase + reg); rt_timer_w32()
45 return __raw_readl(rt->membase + reg); rt_timer_r32()
129 rt->membase = devm_ioremap_resource(&pdev->dev, res); rt_timer_probe()
130 if (IS_ERR(rt->membase)) rt_timer_probe()
131 return PTR_ERR(rt->membase); rt_timer_probe()
H A Dbootrom.c15 static void __iomem *membase = (void __iomem *) KSEG1ADDR(BOOTROM_OFFSET); variable
19 seq_write(s, membase, BOOTROM_SIZE); bootrom_show()
/linux-4.1.27/drivers/input/keyboard/
H A Dlocomokbd.c87 static inline void locomokbd_charge_all(unsigned long membase) locomokbd_charge_all() argument
89 locomo_writel(0x00FF, membase + LOCOMO_KSC); locomokbd_charge_all()
92 static inline void locomokbd_activate_all(unsigned long membase) locomokbd_activate_all() argument
96 locomo_writel(0, membase + LOCOMO_KSC); locomokbd_activate_all()
97 r = locomo_readl(membase + LOCOMO_KIC); locomokbd_activate_all()
99 locomo_writel(r, membase + LOCOMO_KIC); locomokbd_activate_all()
102 static inline void locomokbd_activate_col(unsigned long membase, int col) locomokbd_activate_col() argument
109 locomo_writel(nbset, membase + LOCOMO_KSC); locomokbd_activate_col()
112 static inline void locomokbd_reset_col(unsigned long membase, int col) locomokbd_reset_col() argument
117 locomo_writel(nbset, membase + LOCOMO_KSC); locomokbd_reset_col()
132 unsigned long membase = locomokbd->base; locomokbd_scankeyboard() local
136 locomokbd_charge_all(membase); locomokbd_scankeyboard()
141 locomokbd_activate_col(membase, col); locomokbd_scankeyboard()
144 rowd = ~locomo_readl(membase + LOCOMO_KIB); locomokbd_scankeyboard()
174 locomokbd_reset_col(membase, col); locomokbd_scankeyboard()
176 locomokbd_activate_all(membase); locomokbd_scankeyboard()
/linux-4.1.27/drivers/isdn/hardware/avm/
H A Dt1pci.c73 card->membase = p->membase; t1pci_add_card()
83 card->mbase = ioremap(card->membase, 64); t1pci_add_card()
86 card->membase); t1pci_add_card()
134 card->port, card->irq, card->membase); t1pci_add_card()
183 cinfo->card ? cinfo->card->membase : 0 t1pci_procinfo()
203 param.membase = pci_resource_start(dev, 0); t1pci_probe()
206 param.port, param.irq, param.membase); t1pci_probe()
211 param.port, param.irq, param.membase); t1pci_probe()
H A Db1pci.c175 cinfo->card ? cinfo->card->membase : 0, b1pciv4_procinfo()
207 card->membase = p->membase; b1pciv4_probe()
217 card->mbase = ioremap(card->membase, 64); b1pciv4_probe()
220 card->membase); b1pciv4_probe()
265 card->port, card->irq, card->membase, card->revision); b1pciv4_probe()
318 param.membase = pci_resource_start(pdev, 0); b1pci_pci_probe()
322 param.port, param.irq, param.membase); b1pci_pci_probe()
330 param.port, param.irq, param.membase); b1pci_pci_probe()
333 param.membase = 0; b1pci_pci_probe()
H A Dc4.c1063 cinfo->card ? cinfo->card->membase : 0 c4_procinfo()
1079 seq_printf(m, "%-16s 0x%lx\n", "membase", card->membase); c4_proc_show()
1169 card->membase = p->membase; c4_add_card()
1179 card->mbase = ioremap(card->membase, 128); c4_add_card()
1182 card->membase); c4_add_card()
1232 card->membase); c4_add_card()
1266 param.membase = pci_resource_start(dev, 0); c4_probe()
1269 nr, param.port, param.irq, param.membase); c4_probe()
1274 nr, param.port, param.irq, param.membase); c4_probe()
H A Db1dma.c874 seq_printf(m, "%-16s 0x%lx\n", "membase", card->membase); b1dmactl_proc_show()
H A Davmcard.h83 unsigned long membase; member in struct:avmcard
/linux-4.1.27/drivers/dma/
H A Dtimb_dma.c84 void __iomem *membase; member in struct:timb_dma_chan
101 void __iomem *membase; member in struct:timb_dma
130 ier = ioread32(td->membase + TIMBDMA_IER); __td_enable_chan_irq()
134 iowrite32(ier, td->membase + TIMBDMA_IER); __td_enable_chan_irq()
148 isr = ioread32(td->membase + TIMBDMA_ISR) & (1 << id); __td_dma_done_ack()
150 iowrite32(isr, td->membase + TIMBDMA_ISR); __td_dma_done_ack()
204 "td_chan: %p, chan: %d, membase: %p\n", __td_start_dma()
205 td_chan, td_chan->chan.chan_id, td_chan->membase); __td_start_dma()
210 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR); __td_start_dma()
211 iowrite32(td_desc->txd.phys, td_chan->membase + __td_start_dma()
214 iowrite32(td_chan->bytes_per_line, td_chan->membase + __td_start_dma()
217 iowrite32(TIMBDMA_RX_EN, td_chan->membase + TIMBDMA_OFFS_RX_ER); __td_start_dma()
220 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DHAR); __td_start_dma()
221 iowrite32(td_desc->txd.phys, td_chan->membase + __td_start_dma()
251 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_ER); __td_finish()
254 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DLAR); __td_finish()
593 isr = ioread32(td->membase + TIMBDMA_ISR); td_tasklet()
597 iowrite32(ipr, td->membase + TIMBDMA_ISR); td_tasklet()
610 iowrite32(ier, td->membase + TIMBDMA_IER); td_tasklet()
617 u32 ipr = ioread32(td->membase + TIMBDMA_IPR); td_irq()
621 iowrite32(0, td->membase + TIMBDMA_IER); td_irq()
666 td->membase = ioremap(iomem->start, resource_size(iomem)); td_probe()
667 if (!td->membase) { td_probe()
674 iowrite32(TIMBDMA_32BIT_ADDR, td->membase + TIMBDMA_ACR); td_probe()
677 iowrite32(0x0, td->membase + TIMBDMA_IER); td_probe()
678 iowrite32(0xFFFFFFFF, td->membase + TIMBDMA_ISR); td_probe()
727 td_chan->membase = td->membase + td_probe()
731 dev_dbg(&pdev->dev, "Chan: %d, membase: %p\n", td_probe()
732 i, td_chan->membase); td_probe()
752 iounmap(td->membase); td_probe()
771 iounmap(td->membase); td_remove()
H A Dpch_dma.c104 void __iomem *membase; member in struct:pch_dma_chan
123 readl((pdc)->membase + PDC_##name)
125 writel((val), (pdc)->membase + PDC_##name)
129 void __iomem *membase; member in struct:pch_dma
145 readl((pd)->membase + PCH_DMA_##name)
147 writel((val), (pd)->membase + PCH_DMA_##name)
876 regs = pd->membase = pci_iomap(pdev, 1, 0); pch_dma_probe()
877 if (!pd->membase) { pch_dma_probe()
909 pd_chan->membase = &regs->desc[i]; pch_dma_probe()
946 pci_iounmap(pdev, pd->membase); pch_dma_probe()
975 pci_iounmap(pdev, pd->membase); pch_dma_remove()
H A Dfsl-edma.c166 void __iomem *membase; member in struct:fsl_edma_engine
230 void __iomem *addr = fsl_chan->edma->membase; fsl_edma_enable_request()
239 void __iomem *addr = fsl_chan->edma->membase; fsl_edma_disable_request()
361 void __iomem *addr = fsl_chan->edma->membase; fsl_edma_desc_residue()
433 void __iomem *addr = fsl_chan->edma->membase; fsl_edma_set_tcd_regs()
660 base_addr = fsl_edma->membase; fsl_edma_tx_handler()
697 err = edma_readl(fsl_edma, fsl_edma->membase + EDMA_ERR); fsl_edma_err_handler()
705 fsl_edma->membase + EDMA_CERR); fsl_edma_err_handler()
857 fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res); fsl_edma_probe()
858 if (IS_ERR(fsl_edma->membase)) fsl_edma_probe()
859 return PTR_ERR(fsl_edma->membase); fsl_edma_probe()
899 edma_writew(fsl_edma, 0x0, fsl_edma->membase + EDMA_TCD_CSR(i)); fsl_edma_probe()
941 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, fsl_edma->membase + EDMA_CR); fsl_edma_probe()
/linux-4.1.27/arch/mips/loongson/common/
H A Dserial.c36 .membase = (void __iomem *)NULL, \
69 uart8250_data[mips_machtype][0].membase = serial_init()
90 uart8250_data[mips_machtype][i].membase = serial_init()
/linux-4.1.27/arch/arm/kernel/
H A Disa.c25 .procname = "membase",
64 register_isa_ports(unsigned int membase, unsigned int portbase, unsigned int portshift) register_isa_ports() argument
66 isa_membase = membase; register_isa_ports()
/linux-4.1.27/drivers/clk/sunxi/
H A Dclk-sun9i-mmc.c34 void __iomem *membase; member in struct:sun9i_mmc_clk_data
48 void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id; sun9i_mmc_reset_assert()
70 void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id; sun9i_mmc_reset_deassert()
109 data->membase = devm_ioremap_resource(&pdev->dev, r); sun9i_a80_mmc_config_clk_probe()
110 if (IS_ERR(data->membase)) sun9i_a80_mmc_config_clk_probe()
111 return PTR_ERR(data->membase); sun9i_a80_mmc_config_clk_probe()
145 data->membase + SUN9I_MMC_WIDTH * i, sun9i_a80_mmc_config_clk_probe()
/linux-4.1.27/drivers/tty/serial/8250/
H A D8250_early.c42 return readb(port->membase + offset); serial8250_early_in()
44 return readl(port->membase + (offset << 2)); serial8250_early_in()
46 return ioread32be(port->membase + (offset << 2)); serial8250_early_in()
58 writeb(value, port->membase + offset); serial8250_early_out()
61 writel(value, port->membase + (offset << 2)); serial8250_early_out()
64 iowrite32be(value, port->membase + (offset << 2)); serial8250_early_out()
137 if (!(device->port.membase || device->port.iobase)) early_serial8250_setup()
H A D8250_em.c43 writeb(value, p->membase); serial8250_em_serial_out()
49 writel(value, p->membase + ((offset + 1) << 2)); serial8250_em_serial_out()
56 writel(value, p->membase + (offset << 2)); serial8250_em_serial_out()
64 return readb(p->membase); serial8250_em_serial_in()
69 return readl(p->membase + ((offset + 1) << 2)); serial8250_em_serial_in()
74 return readl(p->membase + (offset << 2)); serial8250_em_serial_in()
H A D8250_dw.c109 writeb(value, p->membase + (offset << p->regshift)); dw8250_serial_out()
119 writeb(value, p->membase + (UART_LCR << p->regshift)); dw8250_serial_out()
130 unsigned int value = readb(p->membase + (offset << p->regshift)); dw8250_serial_in()
140 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); dw8250_serial_inq()
153 __raw_writeq(value, p->membase + (offset << p->regshift)); dw8250_serial_outq()
155 __raw_readq(p->membase + (UART_LCR << p->regshift)); dw8250_serial_outq()
166 p->membase + (UART_LCR << p->regshift)); dw8250_serial_outq()
183 writel(value, p->membase + (offset << p->regshift)); dw8250_serial_out32()
193 writel(value, p->membase + (UART_LCR << p->regshift)); dw8250_serial_out32()
204 unsigned int value = readl(p->membase + (offset << p->regshift)); dw8250_serial_in32()
272 u32 reg = readl(p->membase + DW_UART_UCV); dw8250_setup_port()
284 reg = readl(p->membase + DW_UART_CPR); dw8250_setup_port()
430 uart.port.membase = devm_ioremap(&pdev->dev, regs->start, dw8250_probe()
432 if (!uart.port.membase) dw8250_probe()
H A D8250_gsc.c62 uart.port.membase = ioremap_nocache(address, 16); serial_init_chip()
71 iounmap(uart.port.membase); serial_init_chip()
H A D8250_hp300.c118 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE); hp300_setup_serial_console()
135 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE); hp300_setup_serial_console()
177 uart.port.membase = (char *)(uart.port.mapbase + DIO_VIRADDRBASE); hpdca_init_one()
258 uart.port.membase = (char *)(base + DIO_VIRADDRBASE); hp300_8250_init()
H A D8250_acorn.c74 uart.port.membase = info->vaddr + type->offset[i]; serial_card_probe()
H A D8250_mtk.c166 uart.port.membase = devm_ioremap(&pdev->dev, regs->start, mtk8250_probe()
168 if (!uart.port.membase) mtk8250_probe()
195 writel(0x0, uart.port.membase + mtk8250_probe()
H A D8250_core.c13 * A note about mapbase / membase
16 * membase is an 'ioremapped' cookie.
397 return __raw_readl(p->membase + (offset << p->regshift)); au_serial_in()
407 __raw_writel(value, p->membase + (offset << p->regshift)); au_serial_out()
413 return __raw_readl(up->port.membase + 0x28); au_serial_dl_read()
418 __raw_writel(value, up->port.membase + 0x28); au_serial_dl_write()
440 return readb(p->membase + offset); mem_serial_in()
446 writeb(value, p->membase + offset); mem_serial_out()
452 writel(value, p->membase + offset); mem32_serial_out()
458 return readl(p->membase + offset); mem32_serial_in()
464 iowrite32be(value, p->membase + offset); mem32be_serial_out()
470 return ioread32be(p->membase + offset); mem32be_serial_in()
1153 if (!port->iobase && !port->mapbase && !port->membase) autoconfig()
1157 serial_index(port), port->iobase, port->membase); autoconfig()
2788 port->membase = ioremap_nocache(port->mapbase, size); serial8250_request_std_resource()
2789 if (!port->membase) { serial8250_request_std_resource()
2820 iounmap(port->membase); serial8250_release_std_resource()
2821 port->membase = NULL; serial8250_release_std_resource()
3314 port->membase = old_serial_port[i].iomem_base; serial8250_isa_init_ports()
3465 if (!port->iobase && !port->membase) serial8250_console_setup()
3595 p->membase = port->membase; early_serial_setup()
3686 uart.port.membase = p->membase; serial8250_probe()
3849 uart->port.membase = up->port.membase; serial8250_register_8250_port()
H A D8250_omap.c105 return readl(up->port.membase + (reg << up->port.regshift)); uart_read()
1048 void __iomem *membase; omap8250_probe() local
1059 membase = devm_ioremap_nocache(&pdev->dev, regs->start, omap8250_probe()
1061 if (!membase) omap8250_probe()
1067 up.port.membase = membase; omap8250_probe()
H A D8250_pci.c97 port->port.membase = priv->remapped_bar[bar] + offset; setup_port()
103 port->port.membase = NULL; setup_port()
1422 writel(reg, p->membase + BYT_PRV_CLK); byt_set_termios()
1424 writel(reg, p->membase + BYT_PRV_CLK); byt_set_termios()
1510 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT); byt_serial_setup()
1545 writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */ intel_mid_set_termios()
1546 writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */ intel_mid_set_termios()
1547 writel(div, p->membase + INTEL_MID_UART_DIV); intel_mid_set_termios()
/linux-4.1.27/arch/mips/pmcs-msp71xx/
H A Dmsp_serial.c54 writeb(value, p->membase + offset); msp_serial_out()
61 return readb(p->membase + offset); msp_serial_in()
67 unsigned int iir = readb(p->membase + (UART_IIR << p->regshift)); msp_serial_handle_irq()
82 (void)readb(p->membase + 0xc0); msp_serial_handle_irq()
83 writeb(d->last_lcr, p->membase + (UART_LCR << p->regshift)); msp_serial_handle_irq()
108 up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN); msp_serial_setup()
146 up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN); msp_serial_setup()
/linux-4.1.27/drivers/tty/serial/jsm/
H A Djsm_driver.c147 brd->membase = pci_resource_start(pdev, 4); jsm_probe_one()
150 if (brd->membase & 0x1) jsm_probe_one()
151 brd->membase &= ~0x3; jsm_probe_one()
153 brd->membase &= ~0xF; jsm_probe_one()
165 brd->re_map_membase = ioremap(brd->membase, jsm_probe_one()
199 brd->membase = pci_resource_start(pdev, 0); jsm_probe_one()
202 if (brd->membase & 1) jsm_probe_one()
203 brd->membase &= ~0x3; jsm_probe_one()
205 brd->membase &= ~0xF; jsm_probe_one()
213 brd->re_map_membase = ioremap(brd->membase, jsm_probe_one()
H A Djsm.h152 u64 membase; /* Start of base memory of the card */ member in struct:jsm_board
/linux-4.1.27/drivers/spi/
H A Dspi-sh-sci.c31 void __iomem *membase; member in struct:sh_sci_spi
37 #define SCSPTR(sp) (sp->membase + 0x1c)
154 sp->membase = ioremap(r->start, resource_size(r)); sh_sci_spi_probe()
155 if (!sp->membase) { sh_sci_spi_probe()
167 iounmap(sp->membase); sh_sci_spi_probe()
180 iounmap(sp->membase); sh_sci_spi_remove()
H A Dspi-txx9.c80 void __iomem *membase; member in struct:txx9spi
89 return __raw_readl(c->membase + reg); txx9spi_rd()
93 __raw_writel(val, c->membase + reg); txx9spi_wr()
360 c->membase = devm_ioremap_resource(&dev->dev, res); txx9spi_probe()
361 if (IS_ERR(c->membase)) txx9spi_probe()
/linux-4.1.27/arch/x86/platform/ce4100/
H A Dce4100.c50 return readl(p->membase + offset); mem_serial_in()
69 ret = readl(p->membase + offset); ce4100_mem_serial_in()
90 writel(value, p->membase + offset); ce4100_mem_serial_out()
107 up->membase = ce4100_serial_fixup()
109 up->membase += up->mapbase & ~PAGE_MASK; ce4100_serial_fixup()
111 up->membase += port * 0x100; ce4100_serial_fixup()
/linux-4.1.27/drivers/pinctrl/sunxi/
H A Dpinctrl-sunxi.c315 val = readl(pctl->membase + sunxi_dlevel_reg(pin)); sunxi_pconf_group_set()
319 pctl->membase + sunxi_dlevel_reg(pin)); sunxi_pconf_group_set()
322 val = readl(pctl->membase + sunxi_pull_reg(pin)); sunxi_pconf_group_set()
325 pctl->membase + sunxi_pull_reg(pin)); sunxi_pconf_group_set()
328 val = readl(pctl->membase + sunxi_pull_reg(pin)); sunxi_pconf_group_set()
331 pctl->membase + sunxi_pull_reg(pin)); sunxi_pconf_group_set()
389 val = readl(pctl->membase + sunxi_mux_reg(pin)); sunxi_pmx_set()
392 pctl->membase + sunxi_mux_reg(pin)); sunxi_pmx_set()
477 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; sunxi_pinctrl_gpio_get()
496 regval = readl(pctl->membase + reg); sunxi_pinctrl_gpio_set()
503 writel(regval, pctl->membase + reg); sunxi_pinctrl_gpio_set()
628 regval = readl(pctl->membase + reg); sunxi_pinctrl_irq_set_type()
630 writel(regval | (mode << index), pctl->membase + reg); sunxi_pinctrl_irq_set_type()
644 writel(1 << status_idx, pctl->membase + status_reg); sunxi_pinctrl_irq_ack()
658 val = readl(pctl->membase + reg); sunxi_pinctrl_irq_mask()
659 writel(val & ~(1 << idx), pctl->membase + reg); sunxi_pinctrl_irq_mask()
675 val = readl(pctl->membase + reg); sunxi_pinctrl_irq_unmask()
676 writel(val | (1 << idx), pctl->membase + reg); sunxi_pinctrl_irq_unmask()
726 val = readl(pctl->membase + reg); sunxi_pinctrl_irq_handler()
869 pctl->membase = devm_ioremap_resource(&pdev->dev, res); sunxi_pinctrl_init()
870 if (IS_ERR(pctl->membase)) sunxi_pinctrl_init()
871 return PTR_ERR(pctl->membase); sunxi_pinctrl_init()
1004 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i)); sunxi_pinctrl_init()
1006 pctl->membase + sunxi_irq_status_reg_from_bank(i)); sunxi_pinctrl_init()
H A Dpinctrl-sunxi.h116 void __iomem *membase; member in struct:sunxi_pinctrl
/linux-4.1.27/drivers/net/ethernet/sfc/
H A Dio.h85 __raw_writeq((__force u64)value, efx->membase + reg); _efx_writeq()
89 return (__force __le64)__raw_readq(efx->membase + reg); _efx_readq()
96 __raw_writel((__force u32)value, efx->membase + reg); _efx_writed()
100 return (__force __le32)__raw_readl(efx->membase + reg); _efx_readd()
128 static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase, efx_sram_writeq() argument
140 __raw_writeq((__force u64)value->u64[0], membase + addr); efx_sram_writeq()
142 __raw_writel((__force u32)value->u32[0], membase + addr); efx_sram_writeq()
143 __raw_writel((__force u32)value->u32[1], membase + addr + 4); efx_sram_writeq()
180 static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase, efx_sram_readq() argument
188 value->u64[0] = (__force __le64)__raw_readq(membase + addr); efx_sram_readq()
190 value->u32[0] = (__force __le32)__raw_readl(membase + addr); efx_sram_readq()
191 value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4); efx_sram_readq()
H A Def10.c533 void __iomem *membase; efx_ef10_dimension_resources() local
614 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size); efx_ef10_dimension_resources()
615 if (!membase) { efx_ef10_dimension_resources()
621 iounmap(efx->membase); efx_ef10_dimension_resources()
622 efx->membase = membase; efx_ef10_dimension_resources()
648 &efx->membase_phys, efx->membase, uc_mem_map_size, efx_ef10_dimension_resources()
H A Defx.c1245 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size); efx_init_io()
1246 if (!efx->membase) { efx_init_io()
1256 efx->membase); efx_init_io()
1274 if (efx->membase) { efx_fini_io()
1275 iounmap(efx->membase); efx_fini_io()
1276 efx->membase = NULL; efx_fini_io()
H A Dnic.c427 efx->membase + table->offset, efx_nic_get_regs()
/linux-4.1.27/include/uapi/linux/
H A Dkernelcapi.h27 unsigned int membase; member in struct:kcapi_carddef
/linux-4.1.27/drivers/net/irda/
H A Dbfin_sir.h40 unsigned char __iomem *membase; member in struct:bfin_sir_port
85 #define port_membase(port) (((struct bfin_sir_port *)(port))->membase)
H A Dsh_irda.c143 void __iomem *membase; member in struct:sh_irda_self
173 iowrite16(data, self->membase + offset); sh_irda_write()
183 ret = ioread16(self->membase + offset); sh_irda_read()
196 old = ioread16(self->membase + offset); sh_irda_update_bits()
199 iowrite16(data, self->membase + offset); sh_irda_update_bits()
610 self->tx_buff.head = self->membase + IRDARAM; sh_irda_init_iobuf()
776 self->membase = ioremap_nocache(res->start, resource_size(res)); sh_irda_probe()
777 if (!self->membase) { sh_irda_probe()
821 iounmap(self->membase); sh_irda_probe()
839 iounmap(self->membase); sh_irda_remove()
H A Dsh_sir.c107 void __iomem *membase; member in struct:sh_sir_self
129 iowrite16(data, self->membase + offset); sh_sir_write()
134 return ioread16(self->membase + offset); sh_sir_read()
725 self->membase = ioremap_nocache(res->start, resource_size(res)); sh_sir_probe()
726 if (!self->membase) { sh_sir_probe()
775 iounmap(self->membase); sh_sir_probe()
793 iounmap(self->membase); sh_sir_remove()
H A Dbfin_sir.c43 sp->membase = (void __iomem *)res->start; bfin_sir_init_ports()
/linux-4.1.27/arch/mips/bcm47xx/
H A Dserial.c40 p->membase = (void *)ssb_port->regs; uart8250_init_ssb()
66 p->membase = (void *)bcma_port->regs; uart8250_init_bcma()
/linux-4.1.27/arch/arm/mach-iop33x/
H A Duart.c34 .membase = (char *)IOP33X_UART0_VIRT,
84 .membase = (char *)IOP33X_UART1_VIRT,
/linux-4.1.27/arch/arm/mach-omap1/
H A Dserial.c37 return (unsigned int)__raw_readb(up->membase + offset); omap_serial_in()
44 __raw_writeb(value, p->membase + offset); omap_serial_outp()
128 serial_platform_data[i].membase = NULL; omap_serial_init()
134 serial_platform_data[i].membase = omap_serial_init()
136 if (!serial_platform_data[i].membase) { omap_serial_init()
H A Dboard-ams-delta.c528 .membase = IOMEM(MODEM_VIRT),
/linux-4.1.27/arch/mips/emma/markeins/
H A Dplatform.c109 .membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
117 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
125 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
/linux-4.1.27/arch/mips/jz4740/
H A Dserial.c32 writeb(value, p->membase + (offset << p->regshift)); jz4740_serial_out()
/linux-4.1.27/arch/mips/netlogic/xlr/
H A Dplatform.c32 uartbase = (uint64_t)(long)p->membase; nlm_xlr_uart_in()
49 uartbase = (uint64_t)(long)p->membase; nlm_xlr_uart_out()
92 xlr_uart_data[0].membase = (void __iomem *)uartbase; nlm_uart_init()
96 xlr_uart_data[1].membase = (void __iomem *)uartbase; nlm_uart_init()
/linux-4.1.27/drivers/pinctrl/
H A Dpinctrl-falcon.c253 void __iomem *mem = info->membase[PORT(pin)]; falcon_pinconf_get()
290 void __iomem *mem = info->membase[PORT(pin)]; falcon_pinconf_set()
338 pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset)))); falcon_pinconf_dbg_show()
390 if ((port >= PORTS) || (!info->membase[port])) falcon_mux_apply()
393 pad_w32(info->membase[port], mux, falcon_mux_apply()
420 if ((id >= PORTS) || (!falcon_info.membase[id])) pinctrl_falcon_get_range_size()
423 avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL); pinctrl_falcon_get_range_size()
463 falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev, pinctrl_falcon_probe()
465 if (IS_ERR(falcon_info.membase[*bank])) pinctrl_falcon_probe()
466 return PTR_ERR(falcon_info.membase[*bank]); pinctrl_falcon_probe()
468 avail = pad_r32(falcon_info.membase[*bank], pinctrl_falcon_probe()
H A Dpinctrl-xway.c465 !gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); xway_pinconf_get()
473 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) { xway_pinconf_get()
482 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) xway_pinconf_get()
491 gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); xway_pinconf_get()
523 gpio_setbit(info->membase[0], xway_pinconf_set()
527 gpio_clearbit(info->membase[0], xway_pinconf_set()
538 gpio_clearbit(info->membase[0], xway_pinconf_set()
543 gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); xway_pinconf_set()
550 gpio_clearbit(info->membase[0], xway_pinconf_set()
554 gpio_setbit(info->membase[0], xway_pinconf_set()
565 gpio_clearbit(info->membase[0], xway_pinconf_set()
569 gpio_setbit(info->membase[0], xway_pinconf_set()
623 gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); xway_mux_apply()
625 gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); xway_mux_apply()
628 gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin)); xway_mux_apply()
630 gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin)); xway_mux_apply()
654 gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); xway_gpio_set()
656 gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); xway_gpio_set()
663 return gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin)); xway_gpio_get()
670 gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); xway_gpio_dir_in()
679 gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); xway_gpio_dir_out()
764 xway_info.membase[0] = devm_ioremap_resource(&pdev->dev, res); pinmux_xway_probe()
765 if (IS_ERR(xway_info.membase[0])) pinmux_xway_probe()
766 return PTR_ERR(xway_info.membase[0]); pinmux_xway_probe()
H A Dpinctrl-lantiq.h70 void __iomem *membase[5]; member in struct:ltq_pinmux_info
/linux-4.1.27/arch/arm/plat-orion/
H A Dcommon.c90 void __iomem *membase, uart_complete()
96 data->membase = membase; uart_complete()
124 void __init orion_uart0_init(void __iomem *membase, orion_uart0_init() argument
130 membase, mapbase, irq, clk); orion_uart0_init()
152 void __init orion_uart1_init(void __iomem *membase, orion_uart1_init() argument
158 membase, mapbase, irq, clk); orion_uart1_init()
180 void __init orion_uart2_init(void __iomem *membase, orion_uart2_init() argument
186 membase, mapbase, irq, clk); orion_uart2_init()
208 void __init orion_uart3_init(void __iomem *membase, orion_uart3_init() argument
214 membase, mapbase, irq, clk); orion_uart3_init()
86 uart_complete( struct platform_device *orion_uart, struct plat_serial8250_port *data, struct resource *resources, void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) uart_complete() argument
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Dii_pci20kc.c421 unsigned int membase; ii20k_attach() local
426 membase = it->options[0]; ii20k_attach()
427 if (!membase || (membase & ~(0x100000 - II20K_SIZE))) { ii20k_attach()
434 if (!request_mem_region(membase, II20K_SIZE, dev->board_name)) { ii20k_attach()
436 dev->board_name, membase, II20K_SIZE); ii20k_attach()
439 dev->iobase = membase; /* actually, a memory address */ ii20k_attach()
441 dev->mmio = ioremap(membase, II20K_SIZE); ii20k_attach()
/linux-4.1.27/arch/arm/mach-ixp4xx/
H A Dcoyote-setup.c64 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
100 coyote_uart_data[0].membase = coyote_init()
H A Davila-setup.c81 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
90 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dvulcan-setup.c80 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
89 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dgateway7001-setup.c58 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dwg302v2-setup.c59 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dfsg-setup.c92 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
101 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dixdp425-setup.c154 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
163 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Domixp-setup.c128 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
136 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
H A Ddsmg600-setup.c130 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
139 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dnas100d-setup.c132 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
141 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dnslu2-setup.c144 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
153 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dgtwx5715-setup.c110 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
H A Dgoramo_mlr.c250 .membase = (char __iomem *)IXP4XX_UART1_BASE_VIRT +
260 .membase = (char __iomem *)IXP4XX_UART2_BASE_VIRT +
/linux-4.1.27/drivers/net/can/
H A Dbfin_can.c144 void __iomem *membase; member in struct:bfin_can_priv
174 struct bfin_can_regs __iomem *reg = priv->membase; bfin_can_set_bittiming()
200 struct bfin_can_regs __iomem *reg = priv->membase; bfin_can_set_reset_mode()
259 struct bfin_can_regs __iomem *reg = priv->membase; bfin_can_set_normal_mode()
331 struct bfin_can_regs __iomem *reg = priv->membase; bfin_can_get_berr_counter()
344 struct bfin_can_regs __iomem *reg = priv->membase; bfin_can_start_xmit()
389 struct bfin_can_regs __iomem *reg = priv->membase; bfin_can_rx()
436 struct bfin_can_regs __iomem *reg = priv->membase; bfin_can_err()
523 struct bfin_can_regs __iomem *reg = priv->membase; bfin_can_interrupt()
676 priv->membase = devm_ioremap_resource(&pdev->dev, res_mem); bfin_can_probe()
677 if (IS_ERR(priv->membase)) { bfin_can_probe()
678 err = PTR_ERR(priv->membase); bfin_can_probe()
705 DRV_NAME, priv->membase, priv->rx_irq, bfin_can_probe()
737 struct bfin_can_regs __iomem *reg = priv->membase; bfin_can_suspend()
759 struct bfin_can_regs __iomem *reg = priv->membase; bfin_can_resume()
/linux-4.1.27/drivers/staging/dgnc/
H A Ddgnc_driver.c448 brd->membase = pci_resource_start(pdev, 4); dgnc_found_board()
450 if (!brd->membase) { dgnc_found_board()
458 if (brd->membase & 1) dgnc_found_board()
459 brd->membase &= ~3; dgnc_found_board()
461 brd->membase &= ~15; dgnc_found_board()
512 brd->membase = pci_resource_start(pdev, 0); dgnc_found_board()
515 if (brd->membase & 1) dgnc_found_board()
516 brd->membase &= ~3; dgnc_found_board()
518 brd->membase &= ~15; dgnc_found_board()
637 brd->re_map_membase = ioremap(brd->membase, 0x1000); dgnc_do_remap()
H A Ddgnc_mgmt.c150 di.info_physaddr = (ulong) dgnc_Board[brd]->membase; dgnc_mgmt_ioctl()
151 di.info_physsize = (ulong) dgnc_Board[brd]->membase - dgnc_Board[brd]->membase_end; dgnc_mgmt_ioctl()
H A Ddgnc_driver.h190 ulong membase; /* Start of base memory of the card */ member in struct:dgnc_board
/linux-4.1.27/arch/mips/rb532/
H A Dserial.c44 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
H A Ddevices.c227 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
/linux-4.1.27/arch/arm/mach-w90x900/
H A Dcpu.h29 .membase = name##_BA, \
/linux-4.1.27/arch/arm/mach-gemini/
H A Ddevices.c23 .membase = (void *)IO_ADDRESS(GEMINI_UART_BASE),
/linux-4.1.27/arch/powerpc/boot/
H A Dwrapper338 membase=`${CROSS}objdump -p "$kernel" | grep -m 1 LOAD | awk '{print $7}'`
343 ${MKIMAGE} -A ppc -O linux -T kernel -C gzip -a $membase -e $membase \
360 ${MKIMAGE} -A ppc -O linux -T multi -C gzip -a $membase -e $membase \
/linux-4.1.27/drivers/net/ethernet/8390/
H A Dmac8390.c238 static enum mac8390_access __init mac8390_testio(volatile unsigned long membase) mac8390_testio() argument
243 memcpy_toio(membase, &outdata, 4); mac8390_testio()
245 if (memcmp_withio(&outdata, membase, 4) == 0) mac8390_testio()
248 word_memcpy_tocard(membase, &outdata, 4); mac8390_testio()
250 word_memcpy_fromcard(&indata, membase, 4); mac8390_testio()
256 static int __init mac8390_memsize(unsigned long membase) mac8390_memsize() argument
264 volatile unsigned short *m = (unsigned short *)(membase + (i * 0x1000)); mac8390_memsize()
279 volatile unsigned short *p = (unsigned short *)(membase + (j * 0x1000)); mac8390_memsize()
/linux-4.1.27/arch/mips/pnx833x/common/
H A Dplatform.c70 .membase = (void __iomem *)PNX833X_UART0_PORTS_START,
83 .membase = (void __iomem *)PNX833X_UART1_PORTS_START,
/linux-4.1.27/drivers/misc/ibmasm/
H A Duart.c55 uart.port.membase = iomem_base; ibmasm_register_uart()
/linux-4.1.27/drivers/firmware/efi/libstub/
H A Defi-stub-helper.c117 unsigned long membase = EFI_ERROR; get_dram_base() local
124 return membase; get_dram_base()
130 if (membase > md->phys_addr) get_dram_base()
131 membase = md->phys_addr; get_dram_base()
135 return membase; get_dram_base()
/linux-4.1.27/arch/xtensa/platforms/xt2000/
H A Dsetup.c119 .membase = (void*)(_base), \
/linux-4.1.27/drivers/video/
H A Dvgastate.c407 if (!state->membase) save_vga()
408 state->membase = 0xA0000; save_vga()
410 fbbase = ioremap(state->membase, state->memsize); save_vga()
467 void __iomem *fbbase = ioremap(state->membase, state->memsize); restore_vga()
/linux-4.1.27/arch/mips/jazz/
H A Dsetup.c100 .membase = (void *)(_base), \
/linux-4.1.27/arch/mips/vr41xx/common/
H A Dsiu.c152 port.membase = (unsigned char __iomem *)KSEG1ADDR(res[i].start); vr41xx_siu_setup()
/linux-4.1.27/arch/arm/mach-iop32x/
H A Dglantank.c140 .membase = (char *)GLANTANK_UART,
H A Diq80321.c146 .membase = (char *)IQ80321_UART,
H A Dem7210.c154 .membase = (char *)IQ31244_UART,
H A Diq31244.c220 .membase = (char *)IQ31244_UART,
H A Dn2100.c174 .membase = (char *)N2100_UART,
/linux-4.1.27/arch/arm/mach-ks8695/
H A Dboard-og.c103 .membase = (char *) S8250_VIRT,
/linux-4.1.27/include/linux/isdn/
H A Dcapilli.h36 unsigned int membase; member in struct:capicardparams
/linux-4.1.27/arch/mips/alchemy/common/
H A Dplatform.c37 alchemy_uart_enable(CPHYSADDR(port->membase)); alchemy_8250_pm()
42 alchemy_uart_disable(CPHYSADDR(port->membase)); alchemy_8250_pm()
/linux-4.1.27/arch/blackfin/mach-bf533/boards/
H A DH8606.c325 .membase = (void *)0x20200000,
334 .membase = (void *)0x20200010,
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-cadence.c116 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
117 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
121 * @membase: Base address of the I2C device
140 void __iomem *membase; member in struct:cdns_i2c
841 id->membase = devm_ioremap_resource(&pdev->dev, r_mem); cdns_i2c_probe()
842 if (IS_ERR(id->membase)) cdns_i2c_probe()
843 return PTR_ERR(id->membase); cdns_i2c_probe()
/linux-4.1.27/drivers/net/ethernet/
H A Dethoc.c181 * @membase: pointer to buffer memory region
201 void __iomem *membase; member in struct:ethoc
311 vma = dev->membase; ethoc_init_ring()
1087 priv->membase = devm_ioremap_nocache(&pdev->dev, ethoc_probe()
1089 if (!priv->membase) { ethoc_probe()
1096 priv->membase = dmam_alloc_coherent(&pdev->dev, ethoc_probe()
1099 if (!priv->membase) { ethoc_probe()
/linux-4.1.27/arch/arm/mach-pxa/
H A Dzeus.c275 .membase = (void *)&FFUART,
284 .membase = (void *)&BTUART,
293 .membase = (void *)&STUART,
H A Dviper.c522 .membase = (void *)&FFUART,
531 .membase = (void *)&BTUART,
540 .membase = (void *)&STUART,
/linux-4.1.27/drivers/isdn/hysdn/
H A Dhysdn_init.c81 card->membase = pci_resource_start(akt_pcidev, PCI_REG_MEMORY_BASE); hysdn_pci_init_one()
H A Dboardergo.c421 card->memend = card->membase + ERG_DPRAM_PAGE_SIZE - 1; ergo_inithardware()
422 if (!(card->dpram = ioremap(card->membase, ERG_DPRAM_PAGE_SIZE))) { ergo_inithardware()
H A Dhysdn_defs.h151 unsigned long membase; /* DPRAM memory base */ member in struct:HYSDN_CARD
H A Dhysdn_procconf.c281 card->membase, hysdn_conf_open()
/linux-4.1.27/include/linux/
H A Dserial_8250.h22 void __iomem *membase; /* ioremap cookie or NULL */ member in struct:plat_serial8250_port
H A Dserial_core.h120 unsigned char __iomem *membase; /* read/write[bwl] */ member in struct:uart_port
/linux-4.1.27/arch/powerpc/kernel/
H A Dlegacy_serial.c59 tmp = readl(p->membase + (UART_IIR & ~3)); tsi_serial_in()
62 return readb(p->membase + offset); tsi_serial_in()
69 writeb(value, p->membase + offset); tsi_serial_out()
513 port->membase = ioremap(port->mapbase, 0x100); fixup_port_mmio()
/linux-4.1.27/arch/arm/mach-cns3xxx/
H A Dcns3420vb.c96 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT, cns3420_early_serial_setup()
/linux-4.1.27/arch/arm/mach-imx/
H A Dmach-kzm_arm11_01.c72 .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
H A Dmach-mx31ads.c84 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
91 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
/linux-4.1.27/arch/arm/mach-iop13xx/
H A Dsetup.c76 .membase = IOP13XX_UART0_VIRT,
89 .membase = IOP13XX_UART1_VIRT,
/linux-4.1.27/drivers/pci/host/
H A Dpci-mvebu.c83 u16 membase; member in struct:mvebu_sw_pci_bridge
395 /* Are the new membase/memlimit values invalid? */ mvebu_pcie_handle_membase_change()
396 if (port->bridge.memlimit < port->bridge.membase || mvebu_pcie_handle_membase_change()
416 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16); mvebu_pcie_handle_membase_change()
497 *value = (bridge->memlimit << 16 | bridge->membase); mvebu_sw_pci_bridge_read()
585 bridge->membase = value & 0xffff; mvebu_sw_pci_bridge_write()
H A Dpcie-designware.c765 u32 membase; dw_pcie_setup_rc() local
817 membase = ((u32)pp->mem_base & 0xfff00000) >> 16; dw_pcie_setup_rc()
819 val = memlimit | membase; dw_pcie_setup_rc()
/linux-4.1.27/drivers/scsi/pm8001/
H A Dpm8001_init.c418 pm8001_ha->io_mem[logicalBar].membase = pm8001_ioremap()
420 pm8001_ha->io_mem[logicalBar].membase &= pm8001_ioremap()
425 ioremap(pm8001_ha->io_mem[logicalBar].membase, pm8001_ioremap()
432 (u64)pm8001_ha->io_mem[logicalBar].membase, pm8001_ioremap()
437 pm8001_ha->io_mem[logicalBar].membase = 0; pm8001_ioremap()
H A Dpm8001_sas.h466 u64 membase; member in struct:pm8001_hba_memspace
/linux-4.1.27/arch/mips/ar7/
H A Dplatform.c585 uart_port.membase = ioremap(uart_port.mapbase, 256); ar7_register_uarts()
596 uart_port.membase = ioremap(uart_port.mapbase, 256); ar7_register_uarts()
/linux-4.1.27/drivers/staging/wlan-ng/
H A Dp80211netdev.h176 unsigned int membase; member in struct:wlandevice
/linux-4.1.27/arch/m68k/include/asm/
H A Dmcfuart.h20 void __iomem *membase; /* Virtual address if mapped */ member in struct:mcf_platform_uart
/linux-4.1.27/drivers/isdn/icn/
H A Dicn.c19 static unsigned long membase = ICN_MEMADDR; variable
28 module_param(membase, ulong, 0);
29 MODULE_PARM_DESC(membase, "Shared memory address of all cards");
1610 membase = (unsigned long)ints[2]; icn_setup()
1631 dev.memaddr = (membase & 0x0ffc000); icn_init()
/linux-4.1.27/drivers/staging/dgap/
H A Ddgap.c1397 if (!request_mem_region(brd->membase, 0x200000, "dgap")) dgap_remap()
1400 if (!request_mem_region(brd->membase + PCI_IO_OFFSET, 0x200000, dgap_remap()
1404 brd->re_map_membase = ioremap(brd->membase, 0x200000); dgap_remap()
1408 brd->re_map_port = ioremap((brd->membase + PCI_IO_OFFSET), 0x200000); dgap_remap()
1417 release_mem_region(brd->membase + PCI_IO_OFFSET, 0x200000); dgap_remap()
1419 release_mem_region(brd->membase, 0x200000); dgap_remap()
1428 release_mem_region(brd->membase + PCI_IO_OFFSET, 0x200000); dgap_unmap()
1429 release_mem_region(brd->membase, 0x200000); dgap_unmap()
2171 brd->membase = pci_resource_start(pdev, 2); dgap_found_board()
2176 brd->membase = pci_resource_start(pdev, 0); dgap_found_board()
2180 if (!brd->membase) { dgap_found_board()
2185 if (brd->membase & 1) dgap_found_board()
2186 brd->membase &= ~3; dgap_found_board()
2188 brd->membase &= ~15; dgap_found_board()
2196 brd->port = brd->membase + PCI_IO_OFFSET; dgap_found_board()
6294 magic = brd->membase | 0x01; dgap_get_vpd()
/linux-4.1.27/arch/mn10300/kernel/
H A Dmn10300-serial.c158 .uart.membase = (void __iomem *) &SC0CTR,
220 .uart.membase = (void __iomem *) &SC1CTR,
282 .uart.membase = (void __iomem *) &SC2CTR,
/linux-4.1.27/include/video/
H A Dvga.h184 unsigned long membase; /* VGA window base, 0 for default - 0xA000 */ member in struct:vgastate
/linux-4.1.27/arch/blackfin/include/asm/
H A Dbfin_serial.h269 #define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
/linux-4.1.27/drivers/isdn/capi/
H A Dkcapi.c1235 cparams.membase = cdef.membase; capi20_manufacturer()
/linux-4.1.27/arch/frv/kernel/
H A Dsetup.c192 .membase = (char *) UART0_BASE,
201 .membase = (char *) UART1_BASE,
/linux-4.1.27/drivers/isdn/act2000/
H A Dmodule.c40 MODULE_PARM_DESC(membase, "Base port address of first card");

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