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/linux-4.1.27/arch/arm/boot/dts/
Dam33xx-clocks.dtsi2 * Device Tree Source for AM33xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
23 clock-mult = <1>;
24 clock-div = <1>;
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
31 clock-mult = <1>;
[all …]
Dam43xx-clocks.dtsi2 * Device Tree Source for AM43xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
20 #clock-cells = <0>;
21 compatible = "ti,mux-clock";
28 #clock-cells = <0>;
29 compatible = "ti,mux-clock";
36 #clock-cells = <0>;
37 compatible = "fixed-factor-clock";
39 clock-mult = <1>;
[all …]
Domap3xxx-clocks.dtsi2 * Device Tree Source for OMAP3 clock data
12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <16800000>;
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
25 #clock-cells = <0>;
26 compatible = "ti,divider-clock";
35 #clock-cells = <0>;
36 compatible = "ti,gate-clock";
[all …]
Domap24xx-clocks.dtsi2 * Device Tree Source for OMAP24xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,composite-mux-clock";
20 #clock-cells = <0>;
21 compatible = "ti,composite-clock";
26 #clock-cells = <0>;
27 compatible = "ti,composite-mux-clock";
34 #clock-cells = <0>;
35 compatible = "ti,composite-clock";
42 #clock-cells = <0>;
[all …]
Domap54xx-clocks.dtsi2 * Device Tree Source for OMAP5 clock data
12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <12000000>;
18 #clock-cells = <0>;
19 compatible = "ti,gate-clock";
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <32768>;
32 #clock-cells = <0>;
[all …]
Domap44xx-clocks.dtsi2 * Device Tree Source for OMAP4 clock data
12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <59000000>;
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <12000000>;
24 #clock-cells = <0>;
25 compatible = "ti,gate-clock";
32 #clock-cells = <0>;
[all …]
Ddra7xx-clocks.dtsi2 * Device Tree Source for DRA7xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,dra7-atl-clock";
18 #clock-cells = <0>;
19 compatible = "ti,dra7-atl-clock";
24 #clock-cells = <0>;
25 compatible = "ti,dra7-atl-clock";
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
36 #clock-cells = <0>;
[all …]
Dkeystone-clocks.dtsi2 * Device Tree Source for Keystone 2 clock tree
17 #clock-cells = <0>;
18 compatible = "ti,keystone,pll-mux-clock";
23 clock-output-names = "mainmuxclk";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
30 clock-div = <1>;
31 clock-mult = <1>;
32 clock-output-names = "chipclk1";
36 #clock-cells = <0>;
[all …]
Dste-nomadik-stn8815.dtsi33 clock-names = "timclk", "apb_pclk";
42 clock-names = "timclk", "apb_pclk";
175 #clock-cells = <0>;
176 compatible = "fixed-clock";
177 clock-frequency = <19200000>;
181 * The 2.4 MHz TIMCLK reference clock is active at
183 * divided by 8. This clock is used by the timers and
187 #clock-cells = <0>;
188 compatible = "fixed-factor-clock";
189 clock-div = <8>;
[all …]
Ddm816x-clocks.dtsi9 #clock-cells = <1>;
10 compatible = "ti,dm816-fapll-clock";
13 clock-indices = <1>, <2>, <3>, <4>, <5>,
15 clock-output-names = "main_pll_clk1",
25 #clock-cells = <1>;
26 compatible = "ti,dm816-fapll-clock";
29 clock-indices = <1>, <2>, <3>, <4>;
30 clock-output-names = "ddr_pll_clk1",
37 #clock-cells = <1>;
38 compatible = "ti,dm816-fapll-clock";
[all …]
Domap36xx-omap3430es2plus-clocks.dtsi2 * Device Tree Source for OMAP34xx/OMAP36xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,composite-no-wait-gate-clock";
20 #clock-cells = <0>;
21 compatible = "ti,composite-divider-clock";
29 #clock-cells = <0>;
30 compatible = "ti,composite-clock";
35 #clock-cells = <0>;
36 compatible = "fixed-factor-clock";
38 clock-mult = <1>;
[all …]
Dk2hk-clocks.dtsi4 * Keystone 2 Kepler/Hawking SoC clock nodes
13 #clock-cells = <0>;
14 compatible = "ti,keystone,pll-clock";
16 clock-output-names = "arm-pll-clk";
22 #clock-cells = <0>;
23 compatible = "ti,keystone,main-pll-clock";
30 #clock-cells = <0>;
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "papllclk";
39 #clock-cells = <0>;
[all …]
Dk2l-clocks.dtsi4 * Keystone 2 lamarr SoC clock nodes
13 #clock-cells = <0>;
14 compatible = "ti,keystone,pll-clock";
16 clock-output-names = "arm-pll-clk";
22 #clock-cells = <0>;
23 compatible = "ti,keystone,main-pll-clock";
30 #clock-cells = <0>;
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "papllclk";
39 #clock-cells = <0>;
[all …]
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi2 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
12 #clock-cells = <0>;
13 compatible = "fixed-factor-clock";
15 clock-mult = <1>;
16 clock-div = <3>;
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
23 clock-mult = <1>;
24 clock-div = <5>;
29 #clock-cells = <0>;
[all …]
Dr8a7794.dtsi12 #include <dt-bindings/clock/r8a7794-clock.h>
30 clock-frequency = <1000000000>;
37 clock-frequency = <1000000000>;
59 clock-names = "fck";
78 clock-names = "fck";
135 clock-names = "fck";
165 clock-names = "fck";
175 clock-names = "sci_ick";
184 clock-names = "sci_ick";
193 clock-names = "sci_ick";
[all …]
Domap34xx-omap36xx-clocks.dtsi2 * Device Tree Source for OMAP34XX/OMAP36XX clock data
12 #clock-cells = <0>;
13 compatible = "fixed-factor-clock";
15 clock-mult = <1>;
16 clock-div = <1>;
20 #clock-cells = <0>;
21 compatible = "ti,omap3-interface-clock";
28 #clock-cells = <0>;
29 compatible = "ti,omap3-interface-clock";
36 #clock-cells = <0>;
[all …]
Domap2430-clocks.dtsi2 * Device Tree Source for OMAP2430 clock data
13 #clock-cells = <0>;
14 compatible = "ti,composite-mux-clock";
20 #clock-cells = <0>;
21 compatible = "ti,composite-clock";
26 #clock-cells = <0>;
27 compatible = "ti,composite-mux-clock";
34 #clock-cells = <0>;
35 compatible = "ti,composite-clock";
40 #clock-cells = <0>;
[all …]
Domap2420-clocks.dtsi2 * Device Tree Source for OMAP2420 clock data
13 #clock-cells = <0>;
14 compatible = "ti,composite-no-wait-gate-clock";
21 #clock-cells = <0>;
22 compatible = "ti,composite-mux-clock";
29 #clock-cells = <0>;
30 compatible = "ti,composite-clock";
35 #clock-cells = <0>;
36 compatible = "ti,divider-clock";
45 #clock-cells = <0>;
[all …]
Dexynos5420.dtsi16 #include <dt-bindings/clock/exynos5420.h>
20 #include <dt-bindings/clock/exynos-audss-clk.h>
62 clock-frequency = <1800000000>;
70 clock-frequency = <1800000000>;
78 clock-frequency = <1800000000>;
86 clock-frequency = <1800000000>;
94 clock-frequency = <1000000000>;
102 clock-frequency = <1000000000>;
110 clock-frequency = <1000000000>;
118 clock-frequency = <1000000000>;
[all …]
Dexynos4.dtsi22 #include <dt-bindings/clock/exynos4.h>
23 #include <dt-bindings/clock/exynos-audss-clk.h>
54 clock_audss: clock-controller@03810000 {
55 compatible = "samsung,exynos4210-audss-clock";
57 #clock-cells = <1>;
64 clock-names = "iis";
65 #clock-cells = <1>;
66 clock-output-names = "i2s_cdclk0";
169 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
170 clock-names = "bus_clk", "pll_clk";
[all …]
Domap3430es1-clocks.dtsi2 * Device Tree Source for OMAP3430 ES1 clock data
12 #clock-cells = <0>;
13 compatible = "ti,wait-gate-clock";
20 #clock-cells = <0>;
21 compatible = "ti,divider-clock";
29 #clock-cells = <0>;
30 compatible = "fixed-factor-clock";
32 clock-mult = <1>;
33 clock-div = <1>;
37 #clock-cells = <0>;
[all …]
Dexynos5250.dtsi20 #include <dt-bindings/clock/exynos5250.h>
24 #include <dt-bindings/clock/exynos-audss-clk.h>
65 clock-frequency = <1700000000>;
74 clock-frequency = <1700000000>;
114 clock: clock-controller@10010000 { label
115 compatible = "samsung,exynos5250-clock";
117 #clock-cells = <1>;
120 clock_audss: audss-clock-controller@3810000 {
121 compatible = "samsung,exynos5250-audss-clock";
123 #clock-cells = <1>;
[all …]
Dbcm11351.dtsi17 #include "dt-bindings/clock/bcm281xx.h"
231 #clock-cells = <1>;
232 clock-output-names = "frac_1m";
238 #clock-cells = <1>;
239 clock-output-names = "tmon_1m";
245 #clock-cells = <1>;
246 clock-output-names = "hub_timer",
254 #clock-cells = <1>;
255 clock-output-names = "sdio1",
267 #clock-cells = <1>;
[all …]
Dsh73a0.dtsi13 #include <dt-bindings/clock/sh73a0-clock.h>
29 clock-frequency = <1196000000>;
36 clock-frequency = <1196000000>;
85 clock-names = "fck";
304 clock-names = "sci_ick";
314 clock-names = "sci_ick";
324 clock-names = "sci_ick";
334 clock-names = "sci_ick";
344 clock-names = "sci_ick";
354 clock-names = "sci_ick";
[all …]
Dste-u300.dts37 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-frequency = <32768>;
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <13000000>;
48 #clock-cells = <0>;
50 clock-type = <0>; /* Slow */
51 clock-id = <0>;
55 #clock-cells = <0>;
[all …]
Dexynos4x12.dtsi73 clock: clock-controller@10030000 { label
74 compatible = "samsung,exynos4412-clock";
76 #clock-cells = <1>;
84 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
85 clock-names = "fin_pll", "mct";
130 clocks = <&clock CLK_TSADC>;
131 clock-names = "adc";
153 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
155 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
156 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
[all …]
Dr8a7740.dtsi13 #include <dt-bindings/clock/r8a7740-clock.h>
27 clock-frequency = <800000000>;
61 clock-names = "fck";
203 clock-names = "sci_ick";
213 clock-names = "sci_ick";
223 clock-names = "sci_ick";
233 clock-names = "sci_ick";
243 clock-names = "sci_ick";
253 clock-names = "sci_ick";
263 clock-names = "sci_ick";
[all …]
Dr8a73a4.dtsi12 #include <dt-bindings/clock/r8a73a4-clock.h>
30 clock-frequency = <1500000000>;
121 clock-names = "fck";
329 clock-names = "sci_ick";
339 clock-names = "sci_ick";
349 clock-names = "sci_ick";
359 clock-names = "sci_ick";
369 clock-names = "sci_ick";
379 clock-names = "sci_ick";
464 compatible = "fixed-clock";
[all …]
Dpicoxcell-pc3x3.dtsi27 cpu-clock = <&arm_clk>, "cpu";
46 tzprot_clk: clock@0 {
48 clock-outputs = "bus";
50 clock-frequency = <200000000>;
51 ref-clock = <&ref_clk>, "ref";
54 spi_clk: clock@1 {
56 clock-outputs = "bus";
58 clock-frequency = <200000000>;
59 ref-clock = <&ref_clk>, "ref";
62 dmac0_clk: clock@2 {
[all …]
Dbcm21664.dtsi17 #include "dt-bindings/clock/bcm21664.h"
209 #clock-cells = <0>;
210 compatible = "fixed-clock";
211 clock-frequency = <32768>;
215 #clock-cells = <0>;
216 compatible = "fixed-clock";
217 clock-frequency = <32768>;
221 #clock-cells = <0>;
222 compatible = "fixed-clock";
223 clock-frequency = <13000000>;
[all …]
Dam35xx-clocks.dtsi2 * Device Tree Source for OMAP3 clock data
12 #clock-cells = <0>;
13 compatible = "ti,am35xx-gate-clock";
20 #clock-cells = <0>;
21 compatible = "ti,gate-clock";
28 #clock-cells = <0>;
29 compatible = "ti,am35xx-gate-clock";
36 #clock-cells = <0>;
37 compatible = "ti,gate-clock";
44 #clock-cells = <0>;
[all …]
Dintegratorcp.dts24 #clock-cells = <0>;
25 compatible = "fixed-clock";
26 clock-frequency = <24576000>;
29 /* The chrystal is divided by 2 by the codec for the AACI bit clock */
31 #clock-cells = <0>;
32 compatible = "fixed-factor-clock";
33 clock-div = <2>;
34 clock-mult = <1>;
40 #clock-cells = <0>;
41 compatible = "fixed-clock";
[all …]
Dwm8750.dtsi76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <24000000>;
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <25000000>;
88 #clock-cells = <0>;
89 compatible = "wm,wm8750-pll-clock";
95 #clock-cells = <0>;
96 compatible = "wm,wm8750-pll-clock";
[all …]
Dbcm-cygnus-clock.dtsi39 compatible = "fixed-clock";
40 #clock-cells = <1>;
41 clock-frequency = <25000000>;
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <1000000000>;
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <500000000>;
57 compatible = "fixed-clock";
[all …]
Dhisi-x5hd2.dtsi11 #include <dt-bindings/clock/hix5hd2-clock.h>
45 clocks = <&clock HIX5HD2_FIXED_24M>;
59 clocks = <&clock HIX5HD2_FIXED_24M>;
68 clocks = <&clock HIX5HD2_FIXED_24M>;
77 clocks = <&clock HIX5HD2_FIXED_24M>;
86 clocks = <&clock HIX5HD2_FIXED_24M>;
94 clocks = <&clock HIX5HD2_FIXED_83M>;
95 clock-names = "apb_pclk";
103 clocks = <&clock HIX5HD2_FIXED_83M>;
104 clock-names = "apb_pclk";
[all …]
Dexynos5260.dtsi14 #include <dt-bindings/clock/exynos5260-clk.h>
83 clock_top: clock-controller@10010000 {
84 compatible = "samsung,exynos5260-clock-top";
86 #clock-cells = <1>;
89 clock_peri: clock-controller@10200000 {
90 compatible = "samsung,exynos5260-clock-peri";
92 #clock-cells = <1>;
95 clock_egl: clock-controller@10600000 {
96 compatible = "samsung,exynos5260-clock-egl";
98 #clock-cells = <1>;
[all …]
Dwm8850.dtsi73 #clock-cells = <0>;
74 compatible = "fixed-clock";
75 clock-frequency = <25000000>;
79 #clock-cells = <0>;
80 compatible = "fixed-clock";
81 clock-frequency = <24000000>;
85 #clock-cells = <0>;
86 compatible = "wm,wm8850-pll-clock";
92 #clock-cells = <0>;
93 compatible = "wm,wm8850-pll-clock";
[all …]
Dstih407-clock.dtsi8 #include <dt-bindings/clock/stih407-clks.h>
19 #clock-cells = <0>;
20 compatible = "fixed-clock";
21 clock-frequency = <30000000>;
25 * ARM Peripheral clock for timers
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
32 clock-div = <2>;
33 clock-mult = <1>;
44 #clock-cells = <1>;
[all …]
Dhi3620.dtsi15 #include <dt-bindings/clock/hi3620-clock.h>
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <26000000>;
30 clock-output-names = "apb_pclk";
103 clock: clock@0 { label
104 compatible = "hisilicon,hi3620-clock";
106 #clock-cells = <1>;
115 clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
116 clock-names = "apb_pclk";
[all …]
Dr8a7790.dtsi13 #include <dt-bindings/clock/r8a7790-clock.h>
51 clock-frequency = <1300000000>;
54 clock-latency = <300000>; /* 300 us */
69 clock-frequency = <1300000000>;
76 clock-frequency = <1300000000>;
83 clock-frequency = <1300000000>;
90 clock-frequency = <780000000>;
97 clock-frequency = <780000000>;
104 clock-frequency = <780000000>;
111 clock-frequency = <780000000>;
[all …]
Dstih410-clock.dtsi8 #include <dt-bindings/clock/stih410-clks.h>
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
24 clock-output-names = "CLK_SYSIN";
28 * ARM Peripheral clock for timers
31 #clock-cells = <0>;
32 compatible = "fixed-factor-clock";
34 clock-div = <2>;
35 clock-mult = <1>;
[all …]
Dstih418-clock.dtsi8 #include <dt-bindings/clock/stih418-clks.h>
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
24 clock-output-names = "CLK_SYSIN";
28 * ARM Peripheral clock for timers
31 #clock-cells = <0>;
32 compatible = "fixed-factor-clock";
34 clock-div = <2>;
35 clock-mult = <1>;
[all …]
Dr8a7791.dtsi13 #include <dt-bindings/clock/r8a7791-clock.h>
50 clock-frequency = <1500000000>;
53 clock-latency = <300000>; /* 300 us */
68 clock-frequency = <1500000000>;
201 clock-names = "fck";
220 clock-names = "fck";
269 clock-names = "fck";
299 clock-names = "fck";
327 clock-names = "fck";
355 clock-names = "fck";
[all …]
Dstih416-clock.dtsi10 #include <dt-bindings/clock/stih416-clks.h>
22 #clock-cells = <0>;
23 compatible = "fixed-clock";
24 clock-frequency = <30000000>;
34 #clock-cells = <1>;
39 clock-output-names = "clk-s-a0-pll0-hs",
45 #clock-cells = <0>;
51 clock-output-names = "clk-s-a0-osc-prediv";
55 #clock-cells = <1>;
63 clock-output-names = "clk-s-fdma-0",
[all …]
Dk2e-clocks.dtsi13 #clock-cells = <0>;
14 compatible = "ti,keystone,main-pll-clock";
21 #clock-cells = <0>;
22 compatible = "ti,keystone,pll-clock";
24 clock-output-names = "papllclk";
30 #clock-cells = <0>;
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "ddr-3a-pll-clk";
39 #clock-cells = <0>;
40 compatible = "ti,keystone,psc-clock";
[all …]
Dexynos5440.dtsi12 #include <dt-bindings/clock/exynos5440.h>
29 clock: clock-controller@160000 { label
30 compatible = "samsung,exynos5440-clock";
32 #clock-cells = <1>;
87 clock-frequency = <50000000>;
111 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
112 clock-names = "uart", "clk_uart_baud0";
119 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
120 clock-names = "uart", "clk_uart_baud0";
131 clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
[all …]
Dwm8650.dtsi70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <25000000>;
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <24000000>;
82 #clock-cells = <0>;
83 compatible = "wm,wm8650-pll-clock";
89 #clock-cells = <0>;
90 compatible = "wm,wm8650-pll-clock";
[all …]
Dstih415-clock.dtsi9 #include <dt-bindings/clock/stih415-clks.h>
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
33 #clock-cells = <1>;
38 clock-output-names = "clk-s-a0-pll0-hs",
44 #clock-cells = <0>;
50 clock-output-names = "clk-s-a0-osc-prediv";
54 #clock-cells = <1>;
62 clock-output-names = "clk-s-fdma-0",
[all …]
Dwm8505.dtsi73 #clock-cells = <0>;
74 compatible = "fixed-clock";
75 clock-frequency = <24000000>;
79 #clock-cells = <0>;
80 compatible = "fixed-clock";
81 clock-frequency = <25000000>;
85 #clock-cells = <0>;
86 compatible = "via,vt8500-pll-clock";
92 #clock-cells = <0>;
93 compatible = "via,vt8500-pll-clock";
[all …]
Dexynos4210.dtsi56 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
58 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
59 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
60 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
61 <&clock CLK_XUSBXTI>;
62 #clock-cells = <1>;
115 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
116 clock-names = "fin_pll", "mct";
131 clock: clock-controller@10030000 { label
132 compatible = "samsung,exynos4210-clock";
[all …]
Dr7s72100.dtsi12 #include <dt-bindings/clock/r7s72100-clock.h>
40 #clock-cells = <0>;
41 compatible = "fixed-clock";
43 clock-frequency = <0>;
44 clock-output-names = "extal";
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
51 clock-frequency = <0>;
52 clock-output-names = "usb_x1";
57 #clock-cells = <0>;
[all …]
Dexynos5410.dtsi17 #include <dt-bindings/clock/exynos5410.h>
37 clock-frequency = <1600000000>;
44 clock-frequency = <1600000000>;
51 clock-frequency = <1600000000>;
58 clock-frequency = <1600000000>;
112 clocks = <&fin_pll>, <&clock CLK_MCT>;
113 clock-names = "fin_pll", "mct";
152 clock: clock-controller@10010000 { label
153 compatible = "samsung,exynos5410-clock";
155 #clock-cells = <1>;
[all …]
Dversatile-ab.dts27 #clock-cells = <0>;
28 compatible = "fixed-clock";
29 clock-frequency = <24000000>;
38 #clock-cells = <0>;
43 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
45 #clock-cells = <0>;
46 compatible = "fixed-factor-clock";
47 clock-div = <24>;
48 clock-mult = <1>;
53 #clock-cells = <0>;
[all …]
Domap36xx-clocks.dtsi2 * Device Tree Source for OMAP36xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,omap3-dpll-per-j-type-clock";
19 #clock-cells = <0>;
20 compatible = "ti,hsdiv-gate-clock";
29 #clock-cells = <0>;
30 compatible = "ti,hsdiv-gate-clock";
38 #clock-cells = <0>;
39 compatible = "ti,hsdiv-gate-clock";
47 #clock-cells = <0>;
[all …]
Dr8a7778.dtsi19 #include <dt-bindings/clock/r8a7778-clock.h>
34 clock-frequency = <800000000>;
195 clock-names = "fck";
209 clock-names = "fck";
223 clock-names = "fck";
256 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
290 clock-names = "sci_ick";
299 clock-names = "sci_ick";
308 clock-names = "sci_ick";
317 clock-names = "sci_ick";
[all …]
Dsun5i-a13.dtsi47 clock-latency = <244144>; /* 8 32k periods */
105 * This is a dummy clock, to be used as placeholder on
106 * other mux clocks when a specific parent clock is not
111 #clock-cells = <0>;
112 compatible = "fixed-clock";
113 clock-frequency = <0>;
117 #clock-cells = <0>;
120 clock-frequency = <24000000>;
121 clock-output-names = "osc24M";
125 #clock-cells = <0>;
[all …]
Dsun5i-a10s.dtsi64 * This is a dummy clock, to be used as placeholder on
65 * other mux clocks when a specific parent clock is not
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <0>;
76 #clock-cells = <0>;
79 clock-frequency = <24000000>;
80 clock-output-names = "osc24M";
84 #clock-cells = <0>;
85 compatible = "fixed-clock";
[all …]
Dk2hk-evm.dts22 #clock-cells = <0>;
23 compatible = "fixed-clock";
24 clock-frequency = <122880000>;
25 clock-output-names = "refclk-sys";
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <122880000>;
32 clock-output-names = "refclk-pass";
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
[all …]
Decx-common.dtsi61 clock-names = "apb_pclk";
71 clock-names = "apb_pclk";
82 clock-names = "apb_pclk";
93 clock-names = "apb_pclk";
104 clock-names = "apb_pclk";
113 clock-names = "apb_pclk";
121 clock-names = "apb_pclk";
129 clock-names = "apb_pclk";
150 #clock-cells = <0>;
151 compatible = "fixed-clock";
[all …]
Dsocfpga.dtsi91 clock-names = "apb_pclk";
120 #clock-cells = <0>;
121 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 compatible = "fixed-clock";
142 #clock-cells = <0>;
[all …]
Dr8a7779.dtsi14 #include <dt-bindings/clock/r8a7779-clock.h>
30 clock-frequency = <1000000000>;
36 clock-frequency = <1000000000>;
42 clock-frequency = <1000000000>;
48 clock-frequency = <1000000000>;
213 clock-names = "sci_ick";
222 clock-names = "sci_ick";
231 clock-names = "sci_ick";
240 clock-names = "sci_ick";
249 clock-names = "sci_ick";
[all …]
Dexynos3250.dtsi22 #include <dt-bindings/clock/exynos3250.h>
55 clock-frequency = <1000000000>;
62 clock-frequency = <1000000000>;
76 xusbxti: clock@0 {
77 compatible = "fixed-clock";
81 clock-frequency = <0>;
82 #clock-cells = <0>;
83 clock-output-names = "xusbxti";
86 xxti: clock@1 {
87 compatible = "fixed-clock";
[all …]
Dsun4i-a10.dtsi75 clock-latency = <244144>; /* 8 32k periods */
131 * This is a dummy clock, to be used as placeholder on
132 * other mux clocks when a specific parent clock is not
137 #clock-cells = <0>;
138 compatible = "fixed-clock";
139 clock-frequency = <0>;
143 #clock-cells = <0>;
146 clock-frequency = <24000000>;
147 clock-output-names = "osc24M";
151 #clock-cells = <0>;
[all …]
Dsun8i-a23.dtsi100 #clock-cells = <0>;
101 compatible = "fixed-clock";
102 clock-frequency = <24000000>;
103 clock-output-names = "osc24M";
107 #clock-cells = <0>;
108 compatible = "fixed-clock";
109 clock-frequency = <32768>;
110 clock-output-names = "osc32k";
114 #clock-cells = <0>;
118 clock-output-names = "pll1";
[all …]
Dsun9i-a80.dtsi127 #clock-cells = <0>;
128 compatible = "fixed-clock";
129 clock-frequency = <24000000>;
130 clock-output-names = "osc24M";
134 #clock-cells = <0>;
135 compatible = "fixed-clock";
136 clock-frequency = <32768>;
137 clock-output-names = "osc32k";
141 #clock-cells = <0>;
145 clock-output-names = "pll4";
[all …]
Darm-realview-pb1176.dts57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
63 #clock-cells = <0>;
64 compatible = "fixed-factor-clock";
65 clock-div = <24>;
66 clock-mult = <1>;
71 #clock-cells = <0>;
72 compatible = "fixed-factor-clock";
73 clock-div = <1>;
[all …]
Dsun6i-a31.dtsi90 clock-frequency = <24000000>;
142 #clock-cells = <0>;
143 compatible = "fixed-clock";
144 clock-frequency = <24000000>;
148 #clock-cells = <0>;
149 compatible = "fixed-clock";
150 clock-frequency = <32768>;
151 clock-output-names = "osc32k";
155 #clock-cells = <0>;
159 clock-output-names = "pll1";
[all …]
Ds5pv210.dtsi23 #include <dt-bindings/clock/s5pv210.h>
24 #include <dt-bindings/clock/s5pv210-audss.h>
66 compatible = "fixed-clock";
68 clock-frequency = <0>;
69 clock-output-names = "xxti";
70 #clock-cells = <0>;
74 compatible = "fixed-clock";
76 clock-frequency = <0>;
77 clock-output-names = "xusbxti";
78 #clock-cells = <0>;
[all …]
Demev2.dtsi34 clock-frequency = <533000000>;
40 clock-frequency = <533000000>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 #clock-cells = <0>;
70 compatible = "fixed-factor-clock";
72 clock-div = <1>;
73 clock-mult = <7000>;
74 #clock-cells = <0>;
80 #clock-cells = <0>;
[all …]
Dvexpress-v2m-rs1.dtsi101 clock-names = "refclk", "timclk", "apb_pclk";
102 #clock-cells = <1>;
103 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
125 clock-names = "apb_pclk";
137 clock-names = "mclk", "apb_pclk";
145 clock-names = "KMIREFCLK", "apb_pclk";
153 clock-names = "KMIREFCLK", "apb_pclk";
161 clock-names = "uartclk", "apb_pclk";
169 clock-names = "uartclk", "apb_pclk";
177 clock-names = "uartclk", "apb_pclk";
[all …]
Dvexpress-v2m.dtsi100 clock-names = "refclk", "timclk", "apb_pclk";
101 #clock-cells = <1>;
102 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
124 clock-names = "apb_pclk";
136 clock-names = "mclk", "apb_pclk";
144 clock-names = "KMIREFCLK", "apb_pclk";
152 clock-names = "KMIREFCLK", "apb_pclk";
160 clock-names = "uartclk", "apb_pclk";
168 clock-names = "uartclk", "apb_pclk";
176 clock-names = "uartclk", "apb_pclk";
[all …]
Dat91sam9261.dtsi13 #include <dt-bindings/clock/at91.h>
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <0>;
79 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
90 clock-names = "lcdc_clk", "hclk";
123 clock-names = "t0_clk", "t1_clk", "t2_clk";
[all …]
Dvexpress-v2p-ca15-tc1.dts59 clock-names = "pxlclk";
66 clock-names = "apb_pclk";
75 clock-names = "apb_pclk";
96 clock-names = "apb_pclk";
108 clock-names = "apb_pclk";
130 /* CPU PLL reference clock */
134 #clock-cells = <0>;
135 clock-output-names = "oscclk0";
139 /* Multiplexed AXI master clock */
143 #clock-cells = <0>;
[all …]
Dvexpress-v2p-ca15_a7.dts105 clock-names = "wdogclk", "apb_pclk";
113 clock-names = "pxlclk";
120 clock-names = "apb_pclk";
161 clock-names = "apb_pclk";
173 clock-names = "apb_pclk";
198 /* Reference 24MHz clock */
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <24000000>;
202 clock-output-names = "oscclk6a";
[all …]
Dat91sam9n12.dtsi15 #include <dt-bindings/clock/at91.h>
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <0>;
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <0>;
96 clock-names = "ddrck";
110 #clock-cells = <0>;
112 clock-frequency = <12000000>;
[all …]
Ds3c2416.dtsi11 #include <dt-bindings/clock/s3c2443.h>
36 clocks: clock-controller@0x4c000000 {
37 compatible = "samsung,s3c2416-clock";
39 #clock-cells = <1>;
48 clock-names = "timers";
53 clock-names = "uart", "clk_uart_baud2",
61 clock-names = "uart", "clk_uart_baud2",
69 clock-names = "uart", "clk_uart_baud2",
79 clock-names = "uart", "clk_uart_baud2",
90 clock-names = "hsmmc", "mmc_busclk.0",
[all …]
Dbcm2835.dtsi22 clock-frequency = <1000000>;
90 clock-frequency = <3000000>;
159 clk_mmc: clock@0 {
160 compatible = "fixed-clock";
162 #clock-cells = <0>;
163 clock-output-names = "mmc";
164 clock-frequency = <100000000>;
167 clk_i2c: clock@1 {
168 compatible = "fixed-clock";
170 #clock-cells = <0>;
[all …]
Daxm55xx.dtsi13 #include <dt-bindings/clock/lsi,axm5516-clks.h>
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <125000000>;
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <125000000>;
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <125000000>;
[all …]
Dqcom-ipq8064.dtsi4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
66 compatible = "fixed-clock";
67 clock-frequency = <32768>;
68 #clock-cells = <0>;
84 clock-names = "ahbix-clk",
120 clock-frequency = <25000000>,
123 clock-names = "sleep";
127 acc0: clock-controller@2088000 {
132 acc1: clock-controller@2098000 {
[all …]
Dsun7i-a20.dtsi105 clock-latency = <244144>; /* 8 32k periods */
184 #clock-cells = <0>;
187 clock-frequency = <24000000>;
188 clock-output-names = "osc24M";
192 #clock-cells = <0>;
193 compatible = "fixed-clock";
194 clock-frequency = <32768>;
195 clock-output-names = "osc32k";
199 #clock-cells = <0>;
203 clock-output-names = "pll1";
[all …]
/linux-4.1.27/arch/arm64/boot/dts/amd/
Damd-seattle-clks.dtsi8 compatible = "fixed-clock";
9 #clock-cells = <0>;
10 clock-frequency = <100000000>;
11 clock-output-names = "adl3clk_100mhz";
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <375000000>;
18 clock-output-names = "ccpclk_375mhz";
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/clock/
Dmvebu-core-clock.txt3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
7 The following is a list of provided IDs and clock names on Armada 370/XP:
8 0 = tclk (Internal Bus clock)
9 1 = cpuclk (CPU clock)
10 2 = nbclk (L2 Cache clock)
11 3 = hclk (DRAM control clock)
12 4 = dramclk (DDR clock)
14 The following is a list of provided IDs and clock names on Armada 375:
[all …]
Dste-u300-syscon-clock.txt7 - #clock-cells: must be <0>
8 - clock-type: specifies the type of clock:
9 0 = slow clock
10 1 = fast clock
11 2 = rest/remaining clock
12 - clock-id: specifies the clock in the type range
15 - clocks: parent clock(s)
21 0 0 Slow peripheral bridge clock
22 0 1 UART0 clock
23 0 4 GPIO clock
[all …]
Dexynos5260-clock.txt3 Exynos5260 has 13 clock controllers which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos5260-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
21 - "xrtcxti" - input clock from XRTCXTI
22 - "ioclk_pcm_extclk" - pcm external operation clock
[all …]
Dexynos5433-clock.txt3 The Exynos5433 clock controller generates and supplies clock to various
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
[all …]
Dpistachio-clock.txt1 Imagination Technologies Pistachio SoC clock controllers
4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
25 - reg: Must contain the base address and length of the core clock controller.
26 - #clock-cells: Must be 1. The single cell is the clock identifier.
[all …]
Dsamsung,s3c64xx-clock.txt3 The S3C64xx clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to all SoCs in
10 - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
11 - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
16 - #clock-cells: should be 1.
18 Each clock is assigned an identifier and client nodes can use this identifier
19 to specify the clock which they consume. Some of the clocks are available only
23 dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
29 that they are defined using standard clock bindings with following
30 clock-output-names:
[all …]
Dclock-bindings.txt4 Sources of clock signal can be represented by any node in the device
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs. Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device. The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
18 with a single clock output and 1 for nodes with multiple
19 clock outputs.
[all …]
Dsamsung,s5pv210-clock.txt3 Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
4 controller, which generates and supplies clock to various controllers
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
26 that they are defined using standard clock bindings with following
27 clock-output-names:
34 board device tree, including the system base clock, as selected by XOM[0]
35 pin of the SoC. Refer to generic fixed rate clock bindings
[all …]
Dexynos7-clock.txt3 Exynos7 clock controller has various blocks which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos7-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
24 - compatible: clock controllers will use one of the following
25 compatible strings to indicate the clock controller
[all …]
Dvt8500.txt3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
13 "via,vt8500-device-clock" - for a VT/WM device clock
16 - reg : shall be the control register offset from PMC base for the pll clock.
17 - clocks : shall be the input parent clock phandle for the clock. This should
18 be the reference clock.
[all …]
Dfixed-clock.txt1 Binding for simple fixed-rate clock sources.
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be "fixed-clock".
9 - #clock-cells : from common clock binding; shall be set to 0.
10 - clock-frequency : frequency of clock in Hz. Should be a single cell.
13 - clock-accuracy : accuracy of clock in ppb (parts per billion).
15 - clock-output-names : From common clock binding.
18 clock {
19 compatible = "fixed-clock";
[all …]
Dfixed-factor-clock.txt1 Binding for simple fixed factor rate clock sources.
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be "fixed-factor-clock".
9 - #clock-cells : from common clock binding; shall be set to 0.
10 - clock-div: fixed divider.
11 - clock-mult: fixed multiplier.
12 - clocks: parent clock.
15 - clock-output-names : From common clock binding.
18 clock {
[all …]
Dxgene.txt3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-device-clock" - for a X-Gene device clock
14 - reg : shall be the physical PLL register address for the pll clock.
15 - clocks : shall be the input parent clock phandle for the clock. This should
16 be the reference clock.
17 - #clock-cells : shall be set to 1.
18 - clock-output-names : shall be the name of the PLL referenced by derive
[all …]
Dexynos5410-clock.txt3 The Exynos5410 clock controller generates and supplies clock to various
8 - compatible: should be "samsung,exynos5410-clock"
13 - #clock-cells: should be 1.
16 dt-bindings/clock/exynos5410.h header and can be used in device
19 External clock:
21 There is clock that is generated outside the SoC. It
22 is expected that it is defined using standard clock bindings
23 with following clock-output-name:
25 - "fin_pll" - PLL input clock from XXTI
27 Example 1: An example of a clock controller node is listed below.
[all …]
Dcalxeda.txt3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 "calxeda,hb-pll-clock" - for a PLL clock
10 "calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the
11 A9 clock.
12 "calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.
13 "calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller.
14 - reg : shall be the control register offset from SYSREGs base for the clock.
15 - clocks : shall be the input parent clock phandle for the clock. This is
17 - #clock-cells : from common clock binding; shall be set to 0.
Dkeystone-pll.txt9 This binding uses the common clock binding[1].
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - #clock-cells : from common clock binding; shall be set to 0.
15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
16 - clocks : parent clock phandle
19 post-divider registers are applicable only for main pll clock
25 #clock-cells = <0>;
26 compatible = "ti,keystone,main-pll-clock";
34 #clock-cells = <0>;
35 compatible = "ti,keystone,pll-clock";
[all …]
Dclk-exynos-audss.txt3 The Samsung Audio Subsystem clock controller generates and supplies clocks
4 to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
10 - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
11 - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
13 - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
17 - #clock-cells: should be 1.
20 - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
24 - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
26 - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
28 - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
[all …]
Dat91-clock.txt3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
11 This node contains the slow clock definitions.
39 at91 main clock
43 at91 master clock
64 at91 SMD (Soft Modem) clock
72 at91 usb clock
75 at91 utmi clock
78 at91 h32mx clock
98 - #clock-cells : from common clock binding; shall be set to 0.
[all …]
Dmoxa,moxart-clock.txt3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - compatible : Must be "moxa,moxart-pll-clock"
15 - #clock-cells : Should be 0
17 - clocks : Should contain phandle + clock-specifier for the parent clock
20 - clock-output-names : Should contain clock name
26 - compatible : Must be "moxa,moxart-apb-clock"
27 - #clock-cells : Should be 0
29 - clocks : Should contain phandle + clock-specifier for the parent clock
32 - clock-output-names : Should contain clock name
[all …]
Dsilabs,si5351.txt1 Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
7 The Si5351a/b/c are programmable i2c clock generators with up to 8 output
9 3 output clocks are accessible. The internal structure of the clock
17 - #clock-cells: from common clock binding; shall be set to 1.
18 - clocks: from common clock binding; list of parent clock
19 handles, shall be xtal reference clock or xtal and clkin for
20 si5351c only. Corresponding clock input names are "xtal" and
27 to overwrite clock source of pll A (number=0) or B (number=1).
31 Each of the clock outputs can be overwritten individually by
32 using a child node to the I2C device node. If a child node for a clock
[all …]
Dexynos4-clock.txt3 The Exynos4 clock controller generates and supplies clock to various controllers
4 within the Exynos4 SoC. The clock binding described here is applicable to all
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
16 - #clock-cells: should be 1.
18 Each clock is assigned an identifier and client nodes can use this identifier
19 to specify the clock which they consume.
22 dt-bindings/clock/exynos4.h header and can be used in device
25 Example 1: An example of a clock controller node is listed below.
27 clock: clock-controller@0x10030000 {
[all …]
Dexynos5420-clock.txt3 The Exynos5420 clock controller generates and supplies clock to various
9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
10 - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
15 - #clock-cells: should be 1.
17 Each clock is assigned an identifier and client nodes can use this identifier
18 to specify the clock which they consume.
21 dt-bindings/clock/exynos5420.h header and can be used in device
24 Example 1: An example of a clock controller node is listed below.
26 clock: clock-controller@0x10010000 {
27 compatible = "samsung,exynos5420-clock";
[all …]
Dexynos5250-clock.txt3 The Exynos5250 clock controller generates and supplies clock to various
9 - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
14 - #clock-cells: should be 1.
16 Each clock is assigned an identifier and client nodes can use this identifier
17 to specify the clock which they consume.
20 dt-bindings/clock/exynos5250.h header and can be used in device
23 Example 1: An example of a clock controller node is listed below.
25 clock: clock-controller@0x10010000 {
26 compatible = "samsung,exynos5250-clock";
28 #clock-cells = <1>;
[all …]
Dqoriq-clock.txt21 - compatible: Should contain a specific clock block compatible string
22 and a single chassis clock compatible string.
33 Chassis clock strings include:
38 represents the clock register set
39 - clock-frequency: Input system clock frequency
53 Most of the bindings are from the common clock binding[1].
54 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
62 * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
63 It takes parent's clock-frequency as its clock.
64 * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
[all …]
Dpwm-clock.txt1 Binding for an external clock signal driven by a PWM pin.
3 This binding uses the common clock binding[1] and the common PWM binding[2].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 - compatible : shall be "pwm-clock".
10 - #clock-cells : from common clock binding; shall be set to 0.
11 - pwms : from common PWM binding; this determines the clock frequency
15 - clock-output-names : From common clock binding.
16 - clock-frequency : Exact output frequency, in case the PWM period
20 clock {
21 compatible = "pwm-clock";
[all …]
Dsamsung,s3c2443-clock.txt3 The S3C2443 clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to all SoCs in
10 - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
11 - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
12 - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
15 - #clock-cells: should be 1.
17 Each clock is assigned an identifier and client nodes can use this identifier
18 to specify the clock which they consume. Some of the clocks are available only
22 dt-bindings/clock/s3c2443.h header and can be used in device
28 that they are defined using standard clock bindings with following
[all …]
Dnvidia,tegra124-car.txt3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - clocks : Should contain phandle and clock specifiers for two clocks:
14 - #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
21 In clock consumers, this cell represents the bit number in the CAR's
27 tegra_car: clock {
30 #clock-cells = <1>;
[all …]
Dnvidia,tegra30-car.txt3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - clocks : Should contain phandle and clock specifiers for two clocks:
14 - #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
17 <dt-bindings/clock/tegra30-car.h>.
19 In clock consumers, this cell represents the bit number in the CAR's
25 tegra_car: clock {
28 #clock-cells = <1>;
45 osc: clock@0 {
[all …]
Dnvidia,tegra20-car.txt3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - clocks : Should contain phandle and clock specifiers for two clocks:
14 - #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
17 <dt-bindings/clock/tegra20-car.h>.
19 In clock consumers, this cell represents the bit number in the CAR's
25 tegra_car: clock {
28 #clock-cells = <1>;
45 osc: clock@0 {
[all …]
Dnvidia,tegra114-car.txt3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - clocks : Should contain phandle and clock specifiers for two clocks:
14 - #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
17 <dt-bindings/clock/tegra114-car.h>.
19 In clock consumers, this cell represents the bit number in the CAR's
25 tegra_car: clock {
28 #clock-cells = <1>;
45 osc: clock@0 {
[all …]
Demev2-clock.txt3 This binding uses the common clock binding.
7 This is not a clock provider, but clocks under SMU depend on it.
15 "Serial clock generator" in fig."Clock System Overview" of the manual,
17 This makes internal (neither input nor output) clock that is provided
23 - clocks: Parent clocks. Input clocks as described in clock-bindings.txt
24 - #clock-cells: Should be <0>
29 Registers are "xxx clock gate control register" (XXXGCLKCTRL).
34 - clocks: Input clock as described in clock-bindings.txt
35 - #clock-cells: Should be <0>
43 #clock-cells = <0>;
[all …]
Dsamsung,s3c2410-clock.txt3 The S3C2410 clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to the s3c2410,
10 - "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.
11 - "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.
12 - "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.
15 - #clock-cells: should be 1.
17 Each clock is assigned an identifier and client nodes can use this identifier
18 to specify the clock which they consume. Some of the clocks are available only
22 dt-bindings/clock/s3c2410.h header and can be used in device
27 The xti clock used as input for the plls is generated outside the SoC. It is
[all …]
Dsunxi.txt3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
14 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
15 "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
16 "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
17 "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
18 "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
[all …]
Dexynos3250-clock.txt3 The Exynos3250 clock controller generates and supplies clock to various
12 - "samsung,exynos3250-cmu-isp" - ISP block clock controller compatible
18 - #clock-cells: should be 1.
20 Each clock is assigned an identifier and client nodes can use this identifier
21 to specify the clock which they consume.
24 dt-bindings/clock/exynos3250.h header and can be used in device
27 Example 1: Examples of clock controller nodes are listed below.
29 cmu: clock-controller@10030000 {
32 #clock-cells = <1>;
35 cmu_dmc: clock-controller@105C0000 {
[all …]
Dbcm-cygnus-clock.txt3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the common clock framework to reference their core clocks. Proper support of
18 compatible = "fixed-clock";
19 #clock-cells = <1>;
20 clock-frequency = <25000000>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <1000000000>;
30 compatible = "fixed-clock";
[all …]
Dclk-s5pv210-audss.txt3 The Samsung Audio Subsystem clock controller generates and supplies clocks
8 - compatible: should be "samsung,s5pv210-audss-clock".
11 - #clock-cells: should be 1.
14 - hclk: AHB bus clock of the Audio Subsystem.
15 - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
17 a clock named "xxti".
19 - iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
20 specified, it is fixed to a clock named "iiscdclk0".
21 - sclk_audio0: Audio bus clock, parent of mout_i2s.
23 - clock-names: Aliases for the above clocks. They should be "hclk",
[all …]
Dhix5hd2-clock.txt3 The hix5hd2 clock controller generates and supplies clock to various
8 - compatible: should be "hisilicon,hix5hd2-clock"
10 - #clock-cells: Should be <1>
12 Each clock is assigned an identifier and client nodes use this identifier
13 to specify the clock which they consume.
15 All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.
18 clock: clock@f8a22000 {
19 compatible = "hisilicon,hix5hd2-clock";
21 #clock-cells = <1>;
28 clocks = <&clock HIX5HD2_FIXED_83M>;
[all …]
Dsamsung,s3c2412-clock.txt3 The S3C2412 clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to the s3c2412
9 - compatible: should be "samsung,s3c2412-clock"
12 - #clock-cells: should be 1.
14 Each clock is assigned an identifier and client nodes can use this identifier
15 to specify the clock which they consume. Some of the clocks are available only
19 dt-bindings/clock/s3c2412.h header and can be used in device
25 that they are defined using standard clock bindings with following
26 clock-output-names:
28 - "ext" - external clock source - optional,
[all …]
Dgpio-gate-clock.txt1 Binding for simple gpio gated clock.
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be "gpio-gate-clock".
9 - #clock-cells : from common clock binding; shall be set to 0.
10 - enable-gpios : GPIO reference for enabling and disabling the clock.
13 - clocks: Maximum of one parent clock is supported.
16 clock {
17 compatible = "gpio-gate-clock";
19 #clock-cells = <0>;
Dmaxim,max77686.txt1 Binding for Maxim MAX77686 32k clock generator block
6 The MAX77686 contains three 32.768khz clock outputs that can be controlled
13 - #clock-cells: from common clock binding; shall be set to 1.
16 - clock-output-names: From common clock binding.
18 Each clock is assigned an identifier and client nodes can use this identifier
19 to specify the clock which they consume. Following indices are allowed:
20 - 0: 32khz_ap clock,
21 - 1: 32khz_cp clock,
22 - 2: 32khz_pmic clock.
24 Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77686.h
[all …]
Dvf610-clock.txt6 - #clock-cells: Should be <1>
9 - clocks: list of clock identifiers which are external input clocks to the
10 given clock controller. Please refer the next section to find
12 - clock-names: list of names of clocks which are exteral input clocks to the
13 given clock controller.
15 Input clocks for top clock controller:
21 The clock consumer should specify the desired clock by having the clock
22 ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
23 for the full list of VF610 clock IDs.
30 #clock-cells = <1>;
[all …]
Daxi-clkgen.txt1 Binding for the axi-clkgen clock generator
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 - #clock-cells : from common clock binding; Should always be set to 0.
11 - clocks : Phandle and clock specifier for the parent clock.
14 - clock-output-names : From common clock binding.
17 clock@0xff000000 {
19 #clock-cells = <0>;
Drenesas,cpg-div6-clocks.txt4 Generator (CPG). They clock input is divided by a configurable factor from 1
10 - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
11 - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
12 - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
13 - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
14 - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
15 - "renesas,cpg-div6-clock" for generic DIV6 clocks
16 - reg: Base address and length of the memory resource used by the DIV6 clock
17 - clocks: Reference to the parent clock(s); either one, four, or eight
20 - #clock-cells: Must be 0
[all …]
Daltr_socfpga.txt3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
24 - div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
26 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
[all …]
Drockchip,rk3288-cru.txt3 The RK3288 clock controller generates and supplies clock to various
12 - #clock-cells: should be 1.
20 Each clock is assigned an identifier and client nodes can use this identifier
21 to specify the clock which they consume. All available clocks are defined as
22 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
29 that they are defined using standard clock bindings with following
30 clock-output-names:
32 - "xin32k" - rtc clock - optional,
33 - "ext_i2s" - external I2S clock - optional,
34 - "ext_hsadc" - external HSADC clock - optional,
[all …]
Dmaxim,max77802.txt1 Binding for Maxim MAX77802 32k clock generator block
6 The MAX77802 contains two 32.768khz clock outputs that can be controlled
12 - #clock-cells: From common clock binding; shall be set to 1.
15 - clock-output-names: From common clock binding.
17 Each clock is assigned an identifier and client nodes can use this identifier
18 to specify the clock which they consume. Following indices are allowed:
19 - 0: 32khz_ap clock,
20 - 1: 32khz_cp clock.
22 Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77802.h
32 #clock-cells = <1>;
[all …]
Dkeystone-gate.txt5 This binding uses the common clock binding[1].
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : shall be "ti,keystone,psc-clock".
11 - #clock-cells : from common clock binding; shall be set to 0.
12 - clocks : parent clock phandle
18 - clock-output-names : From common clock binding to override the
19 default output clock name
22 #clock-cells = <0>;
23 compatible = "ti,keystone,psc-clock";
25 clock-output-names = "usb";
Dexynos5440-clock.txt3 The Exynos5440 clock controller generates and supplies clock to various
8 - compatible: should be "samsung,exynos5440-clock".
13 - #clock-cells: should be 1.
15 Each clock is assigned an identifier and client nodes can use this identifier
16 to specify the clock which they consume.
19 dt-bindings/clock/exynos5440.h header and can be used in device
22 Example: An example of a clock controller node is listed below.
24 clock: clock-controller@0x10010000 {
25 compatible = "samsung,exynos5440-clock";
27 #clock-cells = <1>;
Dti,cdce706.txt1 Bindings for Texas Instruments CDCE706 programmable 3-PLL clock
9 - #clock-cells: from common clock binding; shall be set to 1.
10 - clocks: from common clock binding; list of parent clock
11 handles, shall be reference clock(s) connected to CLK_IN0
13 - clock-names: shall be clk_in0 and/or clk_in1. Use clk_in0
22 #clock-cells = <0>;
23 compatible = "fixed-clock";
24 clock-frequency = <54000000>;
30 cdce706: clock-synth@69 {
32 #clock-cells = <1>;
[all …]
Dexynos4415-clock.txt3 The Exynos4415 clock controller generates and supplies clock to various
10 (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
12 Controller (DMC) domain clock controller.
17 - #clock-cells: should be 1.
19 Each clock is assigned an identifier and client nodes can use this identifier
20 to specify the clock which they consume.
23 dt-bindings/clock/exynos4415.h header and can be used in device
26 Example 1: An example of a clock controller node is listed below.
28 cmu: clock-controller@10030000 {
31 #clock-cells = <1>;
[all …]
Drockchip,rk3188-cru.txt3 The RK3188/RK3066 clock controller generates and supplies clock to various
13 - #clock-cells: should be 1.
21 Each clock is assigned an identifier and client nodes can use this identifier
22 to specify the clock which they consume. All available clocks are defined as
23 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
24 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
30 that they are defined using standard clock bindings with following
31 clock-output-names:
33 - "xin32k" - rtc clock - optional,
35 - "ext_hsadc" - external HSADC clock - optional,
[all …]
Dimx6q-clock.txt7 - #clock-cells: Should be <1>
9 The clock consumer should specify the desired clock by having the clock
10 ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
11 for the full list of i.MX6 Quad and DualLite clock IDs.
15 #include <dt-bindings/clock/imx6qdl-clock.h>
21 #clock-cells = <1>;
29 clock-names = "ipg", "per";
Dimx6sx-clock.txt6 - #clock-cells: Should be <1>
7 - clocks: list of clock specifiers, must contain an entry for each required
8 entry in clock-names
9 - clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
11 The clock consumer should specify the desired clock by having the clock
12 ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h
13 for the full list of i.MX6 SoloX clock IDs.
Dlsi,axm5516-clks.txt1 AXM5516 clock driver bindings
7 - #clock-cells : shall contain 1
9 The consumer specifies the desired clock by having the clock ID in its "clocks"
10 phandle cell. See <dt-bindings/clock/lsi,axxia-clock.h> for the list of
11 supported clock IDs.
15 clks: clock-controller@2010020000 {
17 #clock-cells = <1>;
26 clock-names = "apb_pclk";
Drockchip.txt3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 one gate clock spanning all registers or they can be divided into
20 - reg : shall be the control register address(es) for the clock.
21 - #clock-cells : from common clock binding; shall be set to 1
22 - clock-output-names : the corresponding gate names that the clock controls
23 - clocks : should contain the parent clock for each individual gate,
25 clock-output-names
41 clock-output-names =
51 #clock-cells = <1>;
[all …]
Dst,nomadik.txt3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 PLLs and clock gates.
25 fixed frequency clock, as parent.
28 - compatible: must be "st,nomadik-pll-clock"
29 - clock-cells: must be 0
30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
31 - clocks: this clock will have main chrystal as parent
34 HCLK nodes: these represent the clock gates on individual
35 lines from the HCLK clock tree and the gate for individual
[all …]
Dmvebu-gated-clock.txt4 peripheral clocks to be gated to save some power. The clock consumer
5 should specify the desired clock by having the clock ID in its
6 "clocks" phandle cell. The clock ID is directly mapped to the
7 corresponding clock gating control bit in HW to ease manual clock
140 Note: gephy(30) is implemented as a parent clock of ge(2)
164 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
165 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
166 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
167 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
168 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
[all …]
Dhi3620-clock.txt3 The Hi3620 clock controller generates and supplies clock to various
9 - "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
10 - "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.
15 - #clock-cells: should be 1.
17 Each clock is assigned an identifier and client nodes use this identifier
18 to specify the clock which they consume.
20 All these identifier could be found in <dt-bindings/clock/hi3620-clock.h>.
Dmvebu-corediv-clock.txt3 The following is a list of provided IDs and clock names on Armada 370/XP:
4 0 = nand (NAND clock)
7 - compatible : must be "marvell,armada-370-corediv-clock",
8 "marvell,armada-375-corediv-clock",
9 "marvell,armada-380-corediv-clock",
12 - #clock-cells : from common clock binding; shall be set to 1
18 compatible = "marvell,armada-370-corediv-clock";
20 #clock-cells = <1>;
Dmvebu-cpu-clock.txt1 Device Tree Clock bindings for cpu clock of Marvell EBU platforms
5 "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
6 - reg : Address and length of the clock complex register set, followed
8 - #clock-cells : should be set to 1.
9 - clocks : shall be the input parent clock phandle for the clock.
11 cpuclk: clock-complex@d0018700 {
12 #clock-cells = <1>;
13 compatible = "marvell,armada-xp-cpu-clock";
Dsilabs,si570.txt2 I2C clock generators.
5 This binding uses the common clock binding[1]. Details about the devices can be
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - #clock-cells: From common clock bindings: Shall be 0.
27 - clock-output-names: From common clock bindings. Recommended to be "si570".
28 - clock-frequency: Output frequency to generate. This defines the output
30 runtime through the common clock framework.
33 si570: clock-generator@5d {
34 #clock-cells = <0>;
Drenesas,cpg-mstp-clocks.txt7 Clocks are referenced by user nodes by the MSTP node phandle and the clock
21 - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
23 clocks. The first register is the clock control register and is mandatory.
24 The second register is the clock status register and is optional when not
26 - clocks: Reference to the parent clocks, one per output clock. The parents
28 - #clock-cells: Must be 1
29 - clock-output-names: The name of the clocks as free-form strings
30 - clock-indices: Indices of the gate clocks into the group (0 to 31)
32 The clocks, clock-output-names and clock-indices properties contain one entry
33 per gate clock. The MSTP groups are sparsely populated. Unimplemented gate
[all …]
Dzynq-7000.txt6 See clock_bindings.txt for more information on the generic clock bindings.
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
11 required input clock frequencies from the devicetree and acts as clock provider
12 for all clock consumers of PS clocks.
15 - #clock-cells : Must be 1
20 - clock-output-names : List of strings used to name the clock outputs. Shall be
24 - clocks : as described in the clock bindings
25 - clock-names : as described in the clock bindings
32 The following strings are optional parameters to the 'clock-names' property in
33 order to provide an optional (E)MIO clock source.
[all …]
Dimx27-clock.txt7 - #clock-cells: Should be <1>
9 The clock consumer should specify the desired clock by having the clock
10 ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
11 for the full list of i.MX27 clock IDs.
17 #clock-cells = <1>;
26 clock-names = "ipg", "per";
Dimx1-clock.txt6 - #clock-cells: Should be <1>.
8 The clock consumer should specify the desired clock by having the clock
9 ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
10 for the full list of i.MX1 clock IDs.
14 #clock-cells = <1>;
25 clock-names = "ipg", "per";
/linux-4.1.27/Documentation/devicetree/bindings/clock/ti/
Dgate.txt1 Binding for Texas Instruments gate clock.
5 This binding uses the common clock binding[1]. This clock is
6 quite much similar to the basic gate-clock [2], however,
8 is provided for this clock, the code assumes that a clockdomain
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 [2] Documentation/devicetree/bindings/clock/gate-clock.txt
14 [3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
18 "ti,gate-clock" - basic gate clock
19 "ti,wait-gate-clock" - gate clock which waits until clock is active before
21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
[all …]
Dinterface.txt1 Binding for Texas Instruments interface clock.
5 This binding uses the common clock binding[1]. This clock is
6 quite much similar to the basic gate-clock [2], however,
8 companion clock finding (match corresponding functional gate
9 clock) and hardware autoidle enable / disable.
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 [2] Documentation/devicetree/bindings/clock/gate-clock.txt
16 "ti,omap3-interface-clock" - basic OMAP3 interface clock
17 "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
18 capability for waiting clock to be ready
[all …]
Ddpll.txt1 Binding for Texas Instruments DPLL clock.
5 This binding uses the common clock binding[1]. It assumes a
7 (reference clock and bypass clock), with digital phase locked
8 loop logic for multiplying the input clock to a desired output
9 clock. This clock also typically supports different operation
12 for the actual DPLL clock.
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
[all …]
Dfixed-factor-clock.txt1 Binding for TI fixed factor rate clock sources.
5 This binding uses the common clock binding[1], and also uses the autoidle
6 support from TI autoidle clock [2].
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 [2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
12 - compatible : shall be "ti,fixed-factor-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - ti,clock-div: fixed divider.
15 - ti,clock-mult: fixed multiplier.
16 - clocks: parent clock.
[all …]
Dcomposite.txt1 Binding for TI composite clock.
5 This binding uses the common clock binding[1]. It assumes a
6 register-mapped composite clock with multiple different sub-types;
8 a multiplexer clock with multiple input clock signals or parents, one
11 an adjustable clock rate divider, this behaves exactly as [3]
14 clock, this behaves exactly as [4]
17 merged to this clock. The component clocks shall be of one of the
18 "ti,*composite*-clock" types.
20 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
21 [2] Documentation/devicetree/bindings/clock/ti/mux.txt
[all …]
Dapll.txt1 Binding for Texas Instruments APLL clock.
5 This binding uses the common clock binding[1]. It assumes a
7 (reference clock and bypass clock), with analog phase locked
8 loop logic for multiplying the input clock to a desired output
9 clock. This clock also typically supports different operation
13 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 [2] Documentation/devicetree/bindings/clock/ti/dpll.txt
17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
18 - #clock-cells : from common clock binding; shall be set to 0.
25 - ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
[all …]
Ddra7-atl.txt3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
16 Since the clock instances are part of a single IP this binding is used as a node
17 for the DT clock tree, the IP driver is needed to handle the actual configuration
20 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
23 - compatible : shall be "ti,dra7-atl-clock"
[all …]
Dmux.txt1 Binding for TI mux clock.
5 This binding uses the common clock binding[1]. It assumes a
6 register-mapped multiplexer with multiple input clock signals or
7 parents, one of which can be selected as output. This clock does not
17 register value selected parent clock
22 Some clock controller IPs do not allow a value of zero to be programmed
26 register value selected clock parent
36 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
39 - compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
40 - #clock-cells : from common clock binding; shall be set to 0.
[all …]
Dfapll.txt1 Binding for Texas Instruments FAPLL clock.
5 This binding uses the common clock binding[1]. It assumes a
7 (reference clock and bypass clock), and one or more child
10 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - compatible : shall be "ti,dm816-fapll-clock"
14 - #clock-cells : from common clock binding; shall be set to 0.
20 #clock-cells = <1>;
21 compatible = "ti,dm816-fapll-clock";
24 clock-indices = <1>, <2>, <3>, <4>, <5>,
26 clock-output-names = "main_pll_clk1",
Dautoidle.txt1 Binding for Texas Instruments autoidle clock.
5 This binding uses the common clock binding[1]. It assumes a register mapped
6 clock which can be put to idle automatically by hardware based on the usage
7 and a configuration bit setting. Autoidle clock is never an individual
8 clock, it is always a derivative of some basic clock like a gate, divider,
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
20 #clock-cells = <0>;
21 compatible = "ti,divider-clock";
31 #clock-cells = <0>;
32 compatible = "ti,fixed-factor-clock";
[all …]
Ddivider.txt1 Binding for TI divider clock
5 This binding uses the common clock binding[1]. It assumes a
6 register-mapped adjustable clock rate divider that does not gate and has
7 only one input clock or parent. By default the value programmed into
52 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
53 [2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
57 - #clock-cells : from common clock binding; shall be set to 0.
58 - clocks : link to phandle of parent clock
62 - clock-output-names : from common clock binding.
[all …]
/linux-4.1.27/drivers/clk/shmobile/
Dclk-div6.c44 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_enable() local
47 val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) in cpg_div6_clock_enable()
48 | CPG_DIV6_DIV(clock->div - 1); in cpg_div6_clock_enable()
49 clk_writel(val, clock->reg); in cpg_div6_clock_enable()
56 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_disable() local
59 val = clk_readl(clock->reg); in cpg_div6_clock_disable()
69 clk_writel(val, clock->reg); in cpg_div6_clock_disable()
74 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_is_enabled() local
76 return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP); in cpg_div6_clock_is_enabled()
82 struct div6_clock *clock = to_div6_clock(hw); in cpg_div6_clock_recalc_rate() local
[all …]
Dclk-mstp.c58 struct mstp_clock *clock = to_mstp_clock(hw); in cpg_mstp_clock_endisable() local
59 struct mstp_clock_group *group = clock->group; in cpg_mstp_clock_endisable()
60 u32 bitmask = BIT(clock->bit_index); in cpg_mstp_clock_endisable()
87 group->smstpcr, clock->bit_index); in cpg_mstp_clock_endisable()
106 struct mstp_clock *clock = to_mstp_clock(hw); in cpg_mstp_clock_is_enabled() local
107 struct mstp_clock_group *group = clock->group; in cpg_mstp_clock_is_enabled()
115 return !(value & BIT(clock->bit_index)); in cpg_mstp_clock_is_enabled()
129 struct mstp_clock *clock; in cpg_mstp_clock_register() local
132 clock = kzalloc(sizeof(*clock), GFP_KERNEL); in cpg_mstp_clock_register()
133 if (!clock) { in cpg_mstp_clock_register()
[all …]
/linux-4.1.27/arch/arm64/boot/dts/arm/
Djuno-clocks.dtsi12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <7273800>;
15 clock-output-names = "juno:uartclk";
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <48000000>;
22 clock-output-names = "clk48mhz";
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
[all …]
Djuno-motherboard.dtsi11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <24000000>;
14 clock-output-names = "juno_mb:clk24mhz";
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <25000000>;
21 clock-output-names = "juno_mb:clk25mhz";
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
[all …]
Drtsm_ve-motherboard.dtsi37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <24000000>;
40 clock-output-names = "v2m:clk24mhz";
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <1000000>;
47 clock-output-names = "v2m:refclk1mhz";
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
[all …]
/linux-4.1.27/arch/sh/kernel/cpu/sh4a/
DMakefile24 clock-$(CONFIG_CPU_SUBTYPE_SH7757) := clock-sh7757.o
25 clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o
26 clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
27 clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
28 clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
29 clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
30 clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
31 clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
32 clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
33 clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
[all …]
/linux-4.1.27/sound/pci/lola/
Dlola_clock.c102 chip->clock.cur_freq)) in lola_set_granularity()
140 chip->clock.nid = nid; in lola_init_clock_widget()
141 chip->clock.items = val & 0xff; in lola_init_clock_widget()
143 chip->clock.items); in lola_init_clock_widget()
144 if (chip->clock.items > MAX_SAMPLE_CLOCK_COUNT) { in lola_init_clock_widget()
146 chip->clock.items); in lola_init_clock_widget()
150 nitems = chip->clock.items; in lola_init_clock_widget()
180 chip->clock.cur_index = idx_list; in lola_init_clock_widget()
181 chip->clock.cur_freq = 48000; in lola_init_clock_widget()
182 chip->clock.cur_valid = true; in lola_init_clock_widget()
[all …]
/linux-4.1.27/drivers/video/fbdev/via/
Dvia_clock.c297 void via_clock_init(struct via_clock *clock, int gfx_chip) in via_clock_init() argument
302 clock->set_primary_clock_state = dummy_set_clock_state; in via_clock_init()
303 clock->set_primary_clock_source = dummy_set_clock_source; in via_clock_init()
304 clock->set_primary_pll_state = dummy_set_pll_state; in via_clock_init()
305 clock->set_primary_pll = cle266_set_primary_pll; in via_clock_init()
307 clock->set_secondary_clock_state = dummy_set_clock_state; in via_clock_init()
308 clock->set_secondary_clock_source = dummy_set_clock_source; in via_clock_init()
309 clock->set_secondary_pll_state = dummy_set_pll_state; in via_clock_init()
310 clock->set_secondary_pll = cle266_set_secondary_pll; in via_clock_init()
312 clock->set_engine_pll_state = dummy_set_pll_state; in via_clock_init()
[all …]
/linux-4.1.27/drivers/gpu/drm/gma500/
Dcdv_intel_display.c223 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) in cdv_dpll_set_clock_cdv() argument
281 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
297 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
299 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
302 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
305 } else if (clock->vco < 3300000) { in cdv_dpll_set_clock_cdv()
321 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); in cdv_dpll_set_clock_cdv()
322 switch (clock->p2) { in cdv_dpll_set_clock_cdv()
336 DRM_ERROR("Bad P2 clock: %d\n", clock->p2); in cdv_dpll_set_clock_cdv()
402 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) in cdv_intel_clock() argument
[all …]
Doaktrail_crtc.c121 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
123 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
126 static void mrst_print_pll(struct gma_clock_t *clock) in mrst_print_pll() argument
129 clock->dot, clock->m, clock->m1, clock->m2, clock->n, in mrst_print_pll()
130 clock->p1, clock->p2); in mrst_print_pll()
137 struct gma_clock_t clock; in mrst_sdvo_find_best_pll() local
143 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { in mrst_sdvo_find_best_pll()
144 for (clock.n = limit->n.min; clock.n <= limit->n.max; in mrst_sdvo_find_best_pll()
145 clock.n++) { in mrst_sdvo_find_best_pll()
146 for (clock.p1 = limit->p1.min; in mrst_sdvo_find_best_pll()
[all …]
Dpsb_intel_display.c77 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) in psb_intel_clock() argument
79 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
80 clock->p = clock->p1 * clock->p2; in psb_intel_clock()
81 clock->vco = refclk * clock->m / (clock->n + 2); in psb_intel_clock()
82 clock->dot = clock->vco / clock->p; in psb_intel_clock()
115 struct gma_clock_t clock; in psb_intel_crtc_mode_set() local
153 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, in psb_intel_crtc_mode_set()
154 &clock); in psb_intel_crtc_mode_set()
157 adjusted_mode->clock, clock.dot); in psb_intel_crtc_mode_set()
161 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; in psb_intel_crtc_mode_set()
[all …]
/linux-4.1.27/drivers/net/phy/
Ddp83640.c111 struct dp83640_clock *clock; member
233 if (dp83640->clock->page != page) { in ext_read()
235 dp83640->clock->page = page; in ext_read()
248 if (dp83640->clock->page != page) { in ext_write()
250 dp83640->clock->page = page; in ext_write()
305 static int periodic_output(struct dp83640_clock *clock, in periodic_output() argument
309 struct dp83640_private *dp83640 = clock->chosen; in periodic_output()
315 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, in periodic_output()
333 mutex_lock(&clock->extreg_lock); in periodic_output()
336 mutex_unlock(&clock->extreg_lock); in periodic_output()
[all …]
/linux-4.1.27/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi12 #include <dt-bindings/clock/exynos7-clk.h>
81 compatible = "fixed-clock";
82 clock-output-names = "fin_pll";
83 #clock-cells = <0>;
97 clock_topc: clock-controller@10570000 {
98 compatible = "samsung,exynos7-clock-topc";
100 #clock-cells = <1>;
103 clock_top0: clock-controller@105d0000 {
104 compatible = "samsung,exynos7-clock-top0";
106 #clock-cells = <1>;
[all …]
/linux-4.1.27/sound/pci/echoaudio/
Ddarla24_dsp.c99 u8 clock; in set_sample_rate() local
103 clock = GD24_96000; in set_sample_rate()
106 clock = GD24_88200; in set_sample_rate()
109 clock = GD24_48000; in set_sample_rate()
112 clock = GD24_44100; in set_sample_rate()
115 clock = GD24_32000; in set_sample_rate()
118 clock = GD24_22050; in set_sample_rate()
121 clock = GD24_16000; in set_sample_rate()
124 clock = GD24_11025; in set_sample_rate()
127 clock = GD24_8000; in set_sample_rate()
[all …]
Dgina24_dsp.c33 static int set_input_clock(struct echoaudio *chip, u16 clock);
164 u32 control_reg, clock; in set_sample_rate() local
180 clock = 0; in set_sample_rate()
187 clock = GML_96KHZ; in set_sample_rate()
190 clock = GML_88KHZ; in set_sample_rate()
193 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1; in set_sample_rate()
196 clock = GML_44KHZ; in set_sample_rate()
199 clock |= GML_SPDIF_SAMPLE_RATE0; in set_sample_rate()
202 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 | in set_sample_rate()
206 clock = GML_22KHZ; in set_sample_rate()
[all …]
/linux-4.1.27/arch/sh/kernel/cpu/sh3/
DMakefile21 clock-$(CONFIG_CPU_SH3) := clock-sh3.o
22 clock-$(CONFIG_CPU_SUBTYPE_SH7705) := clock-sh7705.o
23 clock-$(CONFIG_CPU_SUBTYPE_SH7706) := clock-sh7706.o
24 clock-$(CONFIG_CPU_SUBTYPE_SH7709) := clock-sh7709.o
25 clock-$(CONFIG_CPU_SUBTYPE_SH7710) := clock-sh7710.o
26 clock-$(CONFIG_CPU_SUBTYPE_SH7720) := clock-sh7710.o
27 clock-$(CONFIG_CPU_SUBTYPE_SH7712) := clock-sh7712.o
32 obj-y += $(clock-y)
/linux-4.1.27/Documentation/devicetree/bindings/net/can/
Dmpc5xxx-mscan.txt10 also specify which clock source shall be used for the controller:
12 - fsl,mscan-clock-source : a string describing the clock source. Valid values
13 are: "ip" for ip bus clock
14 "ref" for reference clock (XTAL)
21 also specify which clock source and divider shall be used for the controller:
23 - fsl,mscan-clock-source : a string describing the clock source. Valid values
24 are: "ip" for ip bus clock
25 "ref" for reference clock
26 "sys" for system clock
28 clock source and frequency based on the system
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/clock/st/
Dst,clkgen-prediv.txt1 Binding for a ST pre-divider clock driver.
3 This binding uses the common clock binding[1].
4 Base address is located to the parent node. See clock binding[2]
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
15 - #clock-cells : From common clock binding; shall be set to 0.
17 - clocks : From common clock binding
19 - clock-output-names : From common clock binding.
27 #clock-cells = <0>;
33 clock-output-names = "clk-m-a2-osc-prediv";
Dst,clkgen.txt42 This binding uses the common clock binding[1].
45 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
46 [2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
47 [3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
48 [4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
49 [5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
50 [6] Documentation/devicetree/bindings/clock/st,vcc.txt
51 [7] Documentation/devicetree/bindings/clock/st,quadfs.txt
52 [8] Documentation/devicetree/bindings/clock/st,flexgen.txt
65 #clock-cells = <1>;
[all …]
Dst,clkgen-divmux.txt1 Binding for a ST divider and multiplexer clock driver.
3 This binding uses the common clock binding[1].
4 Base address is located to the parent node. See clock binding[2]
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
19 - #clock-cells : From common clock binding; shall be set to 1.
21 - clocks : From common clock binding
23 - clock-output-names : From common clock binding.
31 #clock-cells = <1>;
39 clock-output-names = "clk-m-rx-icn-ts",
Dst,clkgen-vcc.txt1 Binding for a type of STMicroelectronics clock crossbar (VCC).
7 that selected clock.
9 This binding uses the common clock binding[1].
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
19 - #clock-cells : from common clock binding; shall be set to 1.
23 - clocks : from common clock binding
25 - clock-output-names : From common clock binding. The block has 16
26 clock outputs but not all of them in a specific instance
27 have to be used in the SoC. If a clock name is left as
28 an empty string then no clock will be created for the
[all …]
Dst,quadfs.txt8 This binding uses the common clock binding[1].
10 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - #clock-cells : from common clock binding; shall be set to 1.
26 - clocks : from common clock binding
28 - clock-output-names : From common clock binding. The block has 4
29 clock outputs but not all of them in a specific instance
30 have to be used in the SoC. If a clock name is left as
31 an empty string then no clock will be created for the
39 #clock-cells = <1>;
44 clock-output-names = "clk-m-pix-mdtp-0",
Dst,clkgen-pll.txt1 Binding for a ST pll clock driver.
3 This binding uses the common clock binding[1].
4 Base address is located to the parent node. See clock binding[2]
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
30 - #clock-cells : From common clock binding; shall be set to 1.
32 - clocks : From common clock binding
34 - clock-output-names : From common clock binding.
42 #clock-cells = <1>;
47 clock-output-names = "clk-s-a0-pll0-hs",
/linux-4.1.27/kernel/sched/
Dclock.c130 u64 clock; member
155 scd->clock = ktime_now; in sched_clock_init()
197 u64 now, clock, old_clock, min_clock, max_clock; in sched_clock_local() local
206 old_clock = scd->clock; in sched_clock_local()
214 clock = scd->tick_gtod + delta; in sched_clock_local()
218 clock = wrap_max(clock, min_clock); in sched_clock_local()
219 clock = wrap_min(clock, max_clock); in sched_clock_local()
221 if (cmpxchg64(&scd->clock, old_clock, clock) != old_clock) in sched_clock_local()
224 return clock; in sched_clock_local()
252 remote_clock = cmpxchg64(&scd->clock, 0, 0); in sched_clock_remote()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/i2c/
Di2c-ocores.txt7 - clocks : handle to the controller clock; see the note below.
8 Mutually exclusive with opencores,ip-clock-frequency
9 - opencores,ip-clock-frequency: frequency of the controller clock in Hz;
15 - clock-frequency : frequency of bus clock in Hz; see the note below.
22 clock-frequency property is meant to control the bus frequency for i2c bus
23 drivers, but it was incorrectly used to specify i2c controller input clock
25 - if clock-frequency is present and neither opencores,ip-clock-frequency nor
26 clocks are, then clock-frequency specifies i2c controller clock frequency.
29 - if clocks is present it specifies i2c controller clock. clock-frequency
31 - if opencores,ip-clock-frequency is present it specifies i2c controller
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/
Ducc.txt24 - rx-clock-name: the UCC receive clock source
25 "none": clock source is disabled
26 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
27 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
28 - tx-clock-name: the UCC transmit clock source
29 "none": clock source is disabled
30 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
31 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
32 The following two properties are deprecated. rx-clock has been replaced
33 with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
[all …]
/linux-4.1.27/arch/arm64/boot/dts/apm/
Dapm-storm.dtsi97 clock-frequency = <50000000>;
112 compatible = "fixed-clock";
113 #clock-cells = <1>;
114 clock-frequency = <100000000>;
115 clock-output-names = "refclk";
119 compatible = "apm,xgene-pcppll-clock";
120 #clock-cells = <1>;
122 clock-names = "pcppll";
124 clock-output-names = "pcppll";
129 compatible = "apm,xgene-socpll-clock";
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/net/
Drockchip-dwmac.txt11 - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.
12 <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC
13 <&cru SCLK_MAC_RX>: clock gate for RX
14 <&cru SCLK_MAC_TX>: clock gate for TX
15 <&cru SCLK_MACREF>: clock gate for RMII referce clock
16 <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
17 <&cru ACLK_GMAC>: AXI clock gate for GMAC
18 <&cru PCLK_GMAC>: APB clock gate for GMAC
19 - clock-names: One name for each entry in the clocks property.
23 - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/drm/armada/
Dmarvell,dove-lcd.txt11 - clocks: as described by clock-bindings.txt
12 - clock-names: as described by clock-bindings.txt
13 "axiclk" - axi bus clock for pixel clock
14 "plldivider" - pll divider clock for pixel clock
15 "ext_ref_clk0" - external clock 0 for pixel clock
16 "ext_ref_clk1" - external clock 1 for pixel clock
29 clock-names = "ext_ref_clk_1";
/linux-4.1.27/Documentation/devicetree/bindings/media/
Dimg-ir-rev1.txt13 - clocks: List of clock specifiers as described in standard
14 clock bindings.
16 1st: Core clock (defaults to 32.768KHz if omitted).
17 2nd: System side (fast) clock.
18 3rd: Power modulation clock.
19 - clock-names: List of clock names corresponding to the clocks
21 Accepted clock names are:
22 "core": Core clock.
23 "sys": System clock.
24 "mod": Power modulation clock.
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt35 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
36 clock-names.
38 - clock-names: should include:
40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
[all …]
Dsun6i-prcm.txt11 - see Documentation/devicetree/clk/sunxi.txt for clock devices
12 - see Documentation/devicetree/reset/allwinner,sunxi-clock-reset.txt for reset
25 #clock-cells = <0>;
30 compatible = "fixed-factor-clock";
31 #clock-cells = <0>;
32 clock-div = <1>;
33 clock-mult = <1>;
35 clock-output-names = "ahb0";
40 #clock-cells = <0>;
42 clock-output-names = "apb0";
[all …]
/linux-4.1.27/Documentation/ptp/
Dptp.txt2 * PTP hardware clock infrastructure for Linux
10 A new class driver exports a kernel interface for specific clock
12 complete set of PTP hardware clock functionality.
14 + Basic clock operations
17 - Shift the clock by a given offset atomically
18 - Adjust clock frequency
20 + Ancillary clock features
26 ** PTP hardware clock kernel API
28 A PTP clock driver registers itself with the class driver. The
30 author of a clock driver need only implement the details of
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/arm/samsung/
Dpmu.txt18 - #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
21 0 : SoC clock output (CLKOUT pin)
23 - clock-names : list of clock names for particular CLKOUT mux inputs in
30 clock-names property.
53 #clock-cells = <1>;
54 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
56 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
57 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
58 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
59 <&clock CLK_XUSBXTI>;
[all …]
/linux-4.1.27/sound/firewire/fireworks/
Dfireworks_command.c275 command_get_clock(struct snd_efw *efw, struct efc_clock *clock) in command_get_clock() argument
282 (__be32 *)clock, sizeof(struct efc_clock)); in command_get_clock()
284 be32_to_cpus(&clock->source); in command_get_clock()
285 be32_to_cpus(&clock->sampling_rate); in command_get_clock()
286 be32_to_cpus(&clock->index); in command_get_clock()
297 struct efc_clock clock = {0}; in command_set_clock() local
307 err = command_get_clock(efw, &clock); in command_set_clock()
312 if ((clock.source == source) && (clock.sampling_rate == rate)) in command_set_clock()
316 if ((source != UINT_MAX) && (clock.source != source)) in command_set_clock()
317 clock.source = source; in command_set_clock()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/thermal/
Dexynos-thermal.txt13 Exynos5420 (Must pass triminfo base and triminfo clock)
26 register, also provide clock to access that base.
34 -- 1. operational clock for TMU channel
35 -- 2. optional clock to access the shared registers of TMU channel
36 -- 3. optional special clock for functional operation
37 - clock-names : Thermal system clock name
38 -- "tmu_apbif" operational clock for current TMU channel
39 -- "tmu_triminfo_apbif" clock to access the shared triminfo register
41 -- "tmu_sclk" clock for functional operation of the current TMU
66 clocks = <&clock 383>;
[all …]
/linux-4.1.27/arch/powerpc/boot/dts/
Dmpc5121.dtsi12 #include <dt-bindings/clock/mpc512x-clock.h>
41 clock-frequency = <396000000>; /* 396 MHz ppc core */
57 clock-names = "mbx-bus", "mbx-3d", "mbx";
72 clock-names = "ipg";
89 compatible = "fixed-clock";
90 #clock-cells = <0>;
91 clock-frequency = <33000000>;
125 /* Real time clock */
139 clks: clock@f00 {
140 compatible = "fsl,mpc5121-clock";
[all …]
/linux-4.1.27/drivers/clocksource/
Dclps711x-timer.c34 static int __init _clps711x_clksrc_init(struct clk *clock, void __iomem *base) in _clps711x_clksrc_init() argument
40 if (IS_ERR(clock)) in _clps711x_clksrc_init()
41 return PTR_ERR(clock); in _clps711x_clksrc_init()
43 rate = clk_get_rate(clock); in _clps711x_clksrc_init()
69 static int __init _clps711x_clkevt_init(struct clk *clock, void __iomem *base, in _clps711x_clkevt_init() argument
79 if (IS_ERR(clock)) in _clps711x_clkevt_init()
80 return PTR_ERR(clock); in _clps711x_clkevt_init()
86 rate = clk_get_rate(clock); in _clps711x_clkevt_init()
116 struct clk *clock = of_clk_get(np, 0); in clps711x_timer_init() local
121 BUG_ON(_clps711x_clksrc_init(clock, base)); in clps711x_timer_init()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/sound/
Dadi,axi-i2s.txt7 The controller expects two clocks, the clock used for the AXI interface and
8 the clock used as the sampling rate reference clock sample.
9 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
10 rate reference clock.
16 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
19 * clock/clock-bindings.txt
28 clock-names = "axi", "ref";
Dadi,axi-spdif-tx.txt7 The controller expects two clocks, the clock used for the AXI interface and
8 the clock used as the sampling rate reference clock sample.
9 - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample
10 rate reference clock.
15 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
18 * clock/clock-bindings.txt
27 clock-names = "axi", "ref";
Dsamsung-i2s.txt26 - clocks: Handle to iis clock and RCLK source clk.
27 - clock-names:
29 clock controller. The clock names for i2s0 should be "iis", "i2s_opclk0" and
31 i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should
33 "iis" is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root
36 - #clock-cells: should be 1, this property must be present if the I2S device
37 is a clock provider in terms of the common clock bindings, described in
38 ../clock/clock-bindings.txt.
39 - clock-output-names: from the common clock bindings, names of the CDCLK
44 CLK_I2S_CDCLK - the CDCLK (CODECLKO) gate clock,
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/usb/
Dusb-nop-xceiv.txt7 - clocks: phandle to the PHY clock. Use as per Documentation/devicetree
8 /bindings/clock/clock-bindings.txt
9 This property is required if clock-frequency is specified.
11 - clock-names: Should be "main_clk"
13 - clock-frequency: the clock frequency (in Hz) that the PHY clock must
29 clock-frequency = <19200000>;
31 clock-names = "main_clk";
38 hsusb1_phy is a NOP USB PHY device that gets its clock from an oscillator
39 and expects that clock to be configured to 19.2MHz by the NOP PHY driver.
/linux-4.1.27/Documentation/devicetree/bindings/rtc/
Ddw-apb.txt11 - either clocks+clock-names or clock-frequency properties
14 - clocks : list of clock specifiers, corresponding to entries in
15 the clock-names property;
16 - clock-names : should contain "timer" and "pclk" entries, matching entries
18 - clock-frequency: The frequency in HZ of the timer.
19 - clock-freq: For backwards compatibility with picoxcell
21 If using the clock specifiers, the pclk clock is optional, as not all
31 clock-names = "timer", "pclk";

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