| /linux-4.4.14/drivers/clk/ux500/ |
| D | u8540_clk.c | 35 struct clk *clk; in u8540_clk_init() local
58 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, in u8540_clk_init()
60 clk_register_clkdev(clk, "soc0_pll", NULL); in u8540_clk_init()
62 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, in u8540_clk_init()
64 clk_register_clkdev(clk, "soc1_pll", NULL); in u8540_clk_init()
66 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, in u8540_clk_init()
68 clk_register_clkdev(clk, "ddr_pll", NULL); in u8540_clk_init()
70 clk = clk_register_fixed_rate(NULL, "rtc32k", NULL, in u8540_clk_init()
73 clk_register_clkdev(clk, "clk32k", NULL); in u8540_clk_init()
74 clk_register_clkdev(clk, "apb_pclk", "rtc-pl031"); in u8540_clk_init()
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| D | u8500_of_clk.c | 20 static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
21 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
24 #define PRCC_SHOW(clk, base, bit) \ argument
25 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
26 #define PRCC_PCLK_STORE(clk, base, bit) \ argument
27 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
28 #define PRCC_KCLK_STORE(clk, base, bit) \ argument
29 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
31 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, in ux500_twocell_get()
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| D | clk-sysctrl.c | 39 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_prepare() local
41 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0], in clk_sysctrl_prepare()
42 clk->reg_bits[0]); in clk_sysctrl_prepare()
44 if (!ret && clk->enable_delay_us) in clk_sysctrl_prepare()
45 usleep_range(clk->enable_delay_us, clk->enable_delay_us); in clk_sysctrl_prepare()
52 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_unprepare() local
53 if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0])) in clk_sysctrl_unprepare()
54 dev_err(clk->dev, "clk_sysctrl: %s fail to clear %s.\n", in clk_sysctrl_unprepare()
61 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_recalc_rate() local
62 return clk->rate; in clk_sysctrl_recalc_rate()
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| D | clk-prcmu.c | 32 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_prepare() local
34 ret = prcmu_request_clock(clk->cg_sel, true); in clk_prcmu_prepare()
36 clk->is_prepared = 1; in clk_prcmu_prepare()
43 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_unprepare() local
44 if (prcmu_request_clock(clk->cg_sel, false)) in clk_prcmu_unprepare()
48 clk->is_prepared = 0; in clk_prcmu_unprepare()
53 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_is_prepared() local
54 return clk->is_prepared; in clk_prcmu_is_prepared()
59 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_enable() local
60 clk->is_enabled = 1; in clk_prcmu_enable()
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| D | clk-prcc.c | 38 struct clk_prcc *clk = to_clk_prcc(hw); in clk_prcc_pclk_enable() local
40 writel(clk->cg_sel, (clk->base + PRCC_PCKEN)); in clk_prcc_pclk_enable()
41 while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel)) in clk_prcc_pclk_enable()
44 clk->is_enabled = 1; in clk_prcc_pclk_enable()
50 struct clk_prcc *clk = to_clk_prcc(hw); in clk_prcc_pclk_disable() local
52 writel(clk->cg_sel, (clk->base + PRCC_PCKDIS)); in clk_prcc_pclk_disable()
53 clk->is_enabled = 0; in clk_prcc_pclk_disable()
58 struct clk_prcc *clk = to_clk_prcc(hw); in clk_prcc_kclk_enable() local
60 writel(clk->cg_sel, (clk->base + PRCC_KCKEN)); in clk_prcc_kclk_enable()
61 while (!(readl(clk->base + PRCC_KCKSR) & clk->cg_sel)) in clk_prcc_kclk_enable()
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| D | abx500-clk.c | 25 struct clk *clk; in ab8500_reg_clks() local
43 clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, in ab8500_reg_clks()
45 clk_register_clkdev(clk, "sysclk", "ab8500-usb.0"); in ab8500_reg_clks()
46 clk_register_clkdev(clk, "sysclk", "ab-iddet.0"); in ab8500_reg_clks()
47 clk_register_clkdev(clk, "sysclk", "snd-soc-mop500.0"); in ab8500_reg_clks()
48 clk_register_clkdev(clk, "sysclk", "shrm_bus"); in ab8500_reg_clks()
51 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk", in ab8500_reg_clks()
54 clk_register_clkdev(clk, "sysclk", "0-0070"); in ab8500_reg_clks()
57 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk", in ab8500_reg_clks()
60 clk_register_clkdev(clk, "sysclk", "cg1960_core.0"); in ab8500_reg_clks()
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| D | clk.h | 16 struct clk;
18 struct clk *clk_reg_prcc_pclk(const char *name,
24 struct clk *clk_reg_prcc_kclk(const char *name,
30 struct clk *clk_reg_prcmu_scalable(const char *name,
36 struct clk *clk_reg_prcmu_gate(const char *name,
41 struct clk *clk_reg_prcmu_scalable_rate(const char *name,
47 struct clk *clk_reg_prcmu_rate(const char *name,
52 struct clk *clk_reg_prcmu_opp_gate(const char *name,
57 struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
63 struct clk *clk_reg_sysctrl_gate(struct device *dev,
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| /linux-4.4.14/include/linux/ |
| D | clk.h | 21 struct clk;
59 struct clk *clk; member
76 struct clk *clk; member
90 int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
97 int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
107 long clk_get_accuracy(struct clk *clk);
117 int clk_set_phase(struct clk *clk, int degrees);
126 int clk_get_phase(struct clk *clk);
139 bool clk_is_match(const struct clk *p, const struct clk *q);
143 static inline long clk_get_accuracy(struct clk *clk) in clk_get_accuracy() argument
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| D | sh_clk.h | 12 struct clk;
23 void (*init)(struct clk *clk);
25 int (*enable)(struct clk *clk);
26 void (*disable)(struct clk *clk);
27 unsigned long (*recalc)(struct clk *clk);
28 int (*set_rate)(struct clk *clk, unsigned long rate);
29 int (*set_parent)(struct clk *clk, struct clk *parent);
30 long (*round_rate)(struct clk *clk, unsigned long rate);
37 struct clk { struct
39 struct clk *parent; argument
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| D | clkdev.h | 17 struct clk;
24 struct clk *clk; member
32 .clk = c, \
35 struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
41 struct clk_lookup *clkdev_create(struct clk *clk, const char *con_id,
47 int clk_register_clkdev(struct clk *, const char *, const char *, ...)
49 int clk_register_clkdevs(struct clk *, struct clk_lookup *, size_t);
52 int __clk_get(struct clk *clk);
53 void __clk_put(struct clk *clk);
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| D | clk-provider.h | 35 struct clk;
253 struct clk *clk; member
279 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
282 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
320 struct clk *clk_register_gate(struct device *dev, const char *name,
324 void clk_unregister_gate(struct clk *clk);
399 struct clk *clk_register_divider(struct device *dev, const char *name,
403 struct clk *clk_register_divider_table(struct device *dev, const char *name,
408 void clk_unregister_divider(struct clk *clk);
452 struct clk *clk_register_mux(struct device *dev, const char *name,
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| /linux-4.4.14/arch/arm/mach-omap1/ |
| D | clock.h | 22 struct clk;
35 .clk = ck, \
48 #define __clk_get_name(clk) (clk->name) argument
49 #define __clk_get_parent(clk) (clk->parent) argument
50 #define __clk_get_rate(clk) (clk->rate) argument
71 int (*enable)(struct clk *);
72 void (*disable)(struct clk *);
73 void (*find_idlest)(struct clk *, void __iomem **,
75 void (*find_companion)(struct clk *, void __iomem **,
77 void (*allow_idle)(struct clk *);
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| D | clock.c | 34 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
44 unsigned long omap1_uart_recalc(struct clk *clk) in omap1_uart_recalc() argument
46 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
47 return val & clk->enable_bit ? 48000000 : 12000000; in omap1_uart_recalc()
50 unsigned long omap1_sossi_recalc(struct clk *clk) in omap1_sossi_recalc() argument
57 return clk->parent->rate / div; in omap1_sossi_recalc()
60 static void omap1_clk_allow_idle(struct clk *clk) in omap1_clk_allow_idle() argument
62 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; in omap1_clk_allow_idle()
64 if (!(clk->flags & CLOCK_IDLE_CONTROL)) in omap1_clk_allow_idle()
71 static void omap1_clk_deny_idle(struct clk *clk) in omap1_clk_deny_idle() argument
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| D | clock_data.c | 78 static struct clk ck_ref = {
84 static struct clk ck_dpll1 = {
95 .clk = {
108 static struct clk sossi_ck = {
111 .parent = &ck_dpll1out.clk,
119 static struct clk arm_ck = {
130 .clk = {
149 static struct clk arm_gpio_ck = {
160 .clk = {
173 .clk = {
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| /linux-4.4.14/drivers/clk/imx/ |
| D | clk-imx27.c | 47 static struct clk *clk[IMX27_CLK_MAX]; variable
50 static struct clk ** const uart_clks[] __initconst = {
51 &clk[IMX27_CLK_PER1_GATE],
52 &clk[IMX27_CLK_UART1_IPG_GATE],
53 &clk[IMX27_CLK_UART2_IPG_GATE],
54 &clk[IMX27_CLK_UART3_IPG_GATE],
55 &clk[IMX27_CLK_UART4_IPG_GATE],
56 &clk[IMX27_CLK_UART5_IPG_GATE],
57 &clk[IMX27_CLK_UART6_IPG_GATE],
65 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx27_clocks_init()
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| D | clk-imx51-imx53.c | 130 static struct clk *clk[IMX5_CLK_END]; variable
133 static struct clk ** const uart_clks[] __initconst = {
134 &clk[IMX5_CLK_UART1_IPG_GATE],
135 &clk[IMX5_CLK_UART1_PER_GATE],
136 &clk[IMX5_CLK_UART2_IPG_GATE],
137 &clk[IMX5_CLK_UART2_PER_GATE],
138 &clk[IMX5_CLK_UART3_IPG_GATE],
139 &clk[IMX5_CLK_UART3_PER_GATE],
140 &clk[IMX5_CLK_UART4_IPG_GATE],
141 &clk[IMX5_CLK_UART4_PER_GATE],
[all …]
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| D | clk-imx6q.c | 84 static struct clk *clk[IMX6QDL_CLK_END]; variable
134 static struct clk ** const uart_clks[] __initconst = {
135 &clk[IMX6QDL_CLK_UART_IPG],
136 &clk[IMX6QDL_CLK_UART_SERIAL],
147 clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6q_clocks_init()
148 clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); in imx6q_clocks_init()
149 clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0); in imx6q_clocks_init()
150 clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); in imx6q_clocks_init()
152 clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); in imx6q_clocks_init()
153 clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0); in imx6q_clocks_init()
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| D | clk-vf610.c | 115 static struct clk *clk[VF610_CLK_END]; variable
124 static struct clk * __init vf610_get_fixed_clock( in vf610_get_fixed_clock()
127 struct clk *clk = of_clk_get_by_name(ccm_node, name); in vf610_get_fixed_clock() local
130 if (IS_ERR(clk)) in vf610_get_fixed_clock()
131 clk = imx_obtain_fixed_clock(name, 0); in vf610_get_fixed_clock()
132 return clk; in vf610_get_fixed_clock()
140 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in vf610_clocks_init()
141 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); in vf610_clocks_init()
142 clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000); in vf610_clocks_init()
143 clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000); in vf610_clocks_init()
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| D | clk-imx21.c | 42 static struct clk *clk[IMX21_CLK_MAX]; variable
49 clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx21_clocks_init()
50 clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref); in _mx21_clocks_init()
51 clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href); in _mx21_clocks_init()
52 clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); in _mx21_clocks_init()
53 clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); in _mx21_clocks_init()
55 clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); in _mx21_clocks_init()
56 clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); in _mx21_clocks_init()
57 clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2); in _mx21_clocks_init()
58 clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); in _mx21_clocks_init()
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| D | clk-imx35.c | 85 static struct clk *clk[clk_max]; variable
87 static struct clk ** const uart_clks[] __initconst = {
88 &clk[ipg],
89 &clk[uart1_gate],
90 &clk[uart2_gate],
91 &clk[uart3_gate],
117 clk[ckih] = imx_clk_fixed("ckih", 24000000); in _mx35_clocks_init()
118 clk[ckil] = imx_clk_fixed("ckih", 32768); in _mx35_clocks_init()
119 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
120 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
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| D | clk-imx31.c | 62 static struct clk *clk[clk_max]; variable
65 static struct clk ** const uart_clks[] __initconst = {
66 &clk[ipg],
67 &clk[uart1_gate],
68 &clk[uart2_gate],
69 &clk[uart3_gate],
70 &clk[uart4_gate],
71 &clk[uart5_gate],
83 clk[dummy] = imx_clk_fixed("dummy", 0); in _mx31_clocks_init()
84 clk[ckih] = imx_clk_fixed("ckih", fref); in _mx31_clocks_init()
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| D | clk-imx25.c | 87 static struct clk *clk[clk_max]; variable
89 static struct clk ** const uart_clks[] __initconst = {
90 &clk[uart_ipg_per],
91 &clk[uart1_ipg],
92 &clk[uart2_ipg],
93 &clk[uart3_ipg],
94 &clk[uart4_ipg],
95 &clk[uart5_ipg],
104 clk[dummy] = imx_clk_fixed("dummy", 0); in __mx25_clocks_init()
105 clk[osc] = imx_clk_fixed("osc", osc_rate); in __mx25_clocks_init()
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| D | clk-imx1.c | 38 static struct clk *clk[IMX1_CLK_MAX]; variable
50 clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx1_clocks_init()
51 clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref); in _mx1_clocks_init()
52 clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000); in _mx1_clocks_init()
53 clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); in _mx1_clocks_init()
54 clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); in _mx1_clocks_init()
55 …clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks)… in _mx1_clocks_init()
56 clk[IMX1_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "mpll", "clk32_premult", CCM_MPCTL0); in _mx1_clocks_init()
57 clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); in _mx1_clocks_init()
58 clk[IMX1_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "spll", "prem", CCM_SPCTL0); in _mx1_clocks_init()
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| D | Makefile | 3 clk.o \
4 clk-busy.o \
5 clk-cpu.o \
6 clk-fixup-div.o \
7 clk-fixup-mux.o \
8 clk-gate-exclusive.o \
9 clk-gate2.o \
10 clk-pllv1.o \
11 clk-pllv2.o \
12 clk-pllv3.o \
[all …]
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| D | clk.h | 9 void imx_check_clocks(struct clk *clks[], unsigned int count);
10 void imx_register_uart_clocks(struct clk ** const clks[]);
23 struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
26 struct clk *imx_clk_pllv2(const char *name, const char *parent,
39 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
42 struct clk *clk_register_gate2(struct device *dev, const char *name,
48 struct clk * imx_obtain_fixed_clock(
51 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
54 static inline struct clk *imx_clk_gate2(const char *name, const char *parent, in imx_clk_gate2()
61 static inline struct clk *imx_clk_gate2_shared(const char *name, in imx_clk_gate2_shared()
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| D | clk.c | 10 void __init imx_check_clocks(struct clk *clks[], unsigned int count) in imx_check_clocks()
20 static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) in imx_obtain_fixed_clock_from_dt()
23 struct clk *clk = ERR_PTR(-ENODEV); in imx_obtain_fixed_clock_from_dt() local
34 clk = of_clk_get_from_provider(&phandle); in imx_obtain_fixed_clock_from_dt()
37 return clk; in imx_obtain_fixed_clock_from_dt()
40 struct clk * __init imx_obtain_fixed_clock( in imx_obtain_fixed_clock()
43 struct clk *clk; in imx_obtain_fixed_clock() local
45 clk = imx_obtain_fixed_clock_from_dt(name); in imx_obtain_fixed_clock()
46 if (IS_ERR(clk)) in imx_obtain_fixed_clock()
47 clk = imx_clk_fixed(name, rate); in imx_obtain_fixed_clock()
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| D | clk-cpu.c | 19 struct clk *div;
20 struct clk *mux;
21 struct clk *pll;
22 struct clk *step;
78 struct clk *imx_clk_cpu(const char *name, const char *parent_name, in imx_clk_cpu()
79 struct clk *div, struct clk *mux, struct clk *pll, in imx_clk_cpu()
80 struct clk *step) in imx_clk_cpu()
83 struct clk *clk; in imx_clk_cpu() local
103 clk = clk_register(NULL, &cpu->hw); in imx_clk_cpu()
104 if (IS_ERR(clk)) in imx_clk_cpu()
[all …]
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| /linux-4.4.14/arch/c6x/platforms/ |
| D | pll.c | 31 static void __clk_enable(struct clk *clk) in __clk_enable() argument
33 if (clk->parent) in __clk_enable()
34 __clk_enable(clk->parent); in __clk_enable()
35 clk->usecount++; in __clk_enable()
38 static void __clk_disable(struct clk *clk) in __clk_disable() argument
40 if (WARN_ON(clk->usecount == 0)) in __clk_disable()
42 --clk->usecount; in __clk_disable()
44 if (clk->parent) in __clk_disable()
45 __clk_disable(clk->parent); in __clk_disable()
48 int clk_enable(struct clk *clk) in clk_enable() argument
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| /linux-4.4.14/arch/arm/mach-davinci/ |
| D | clock.c | 34 static void __clk_enable(struct clk *clk) in __clk_enable() argument
36 if (clk->parent) in __clk_enable()
37 __clk_enable(clk->parent); in __clk_enable()
38 if (clk->usecount++ == 0) { in __clk_enable()
39 if (clk->flags & CLK_PSC) in __clk_enable()
40 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, in __clk_enable()
41 true, clk->flags); in __clk_enable()
42 else if (clk->clk_enable) in __clk_enable()
43 clk->clk_enable(clk); in __clk_enable()
47 static void __clk_disable(struct clk *clk) in __clk_disable() argument
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| D | clock.h | 87 struct clk { struct
98 struct clk *parent; argument
103 unsigned long (*recalc) (struct clk *); argument
104 int (*set_rate) (struct clk *clk, unsigned long rate); argument
105 int (*round_rate) (struct clk *clk, unsigned long rate); argument
106 int (*reset) (struct clk *clk, bool reset); argument
107 void (*clk_enable) (struct clk *clk); argument
108 void (*clk_disable) (struct clk *clk); argument
124 .clk = ck, \
130 int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
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| D | da850.c | 50 static int da850_set_armrate(struct clk *clk, unsigned long rate);
51 static int da850_round_armrate(struct clk *clk, unsigned long rate);
52 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
60 static struct clk ref_clk = {
66 static struct clk pll0_clk = {
74 static struct clk pll0_aux_clk = {
80 static struct clk pll0_sysclk1 = {
87 static struct clk pll0_sysclk2 = {
94 static struct clk pll0_sysclk3 = {
103 static struct clk pll0_sysclk4 = {
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| /linux-4.4.14/drivers/media/v4l2-core/ |
| D | v4l2-clk.c | 29 struct v4l2_clk *clk; in v4l2_clk_find() local
31 list_for_each_entry(clk, &clk_list, list) in v4l2_clk_find()
32 if (!strcmp(dev_id, clk->dev_id)) in v4l2_clk_find()
33 return clk; in v4l2_clk_find()
40 struct v4l2_clk *clk; in v4l2_clk_get() local
41 struct clk *ccf_clk = clk_get(dev, id); in v4l2_clk_get()
47 clk = kzalloc(sizeof(*clk), GFP_KERNEL); in v4l2_clk_get()
48 if (!clk) { in v4l2_clk_get()
52 clk->clk = ccf_clk; in v4l2_clk_get()
54 return clk; in v4l2_clk_get()
[all …]
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| /linux-4.4.14/drivers/sh/clk/ |
| D | cpg.c | 19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) in sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
32 iowrite8(value, clk->mapped_reg); in sh_clk_write()
33 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_write()
[all …]
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| D | core.c | 39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
137 long clk_rate_table_round(struct clk *clk, in clk_rate_table_round() argument
143 .max = clk->nr_freqs - 1, in clk_rate_table_round()
149 if (clk->nr_freqs < 1) in clk_rate_table_round()
161 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, in clk_rate_div_range_round() argument
168 .arg = clk_get_parent(clk), in clk_rate_div_range_round()
181 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, in clk_rate_mult_range_round() argument
188 .arg = clk_get_parent(clk), in clk_rate_mult_range_round()
[all …]
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| /linux-4.4.14/drivers/clk/mmp/ |
| D | clk-mmp2.c | 79 struct clk *clk; in mmp2_clk_init() local
80 struct clk *vctcxo; in mmp2_clk_init()
103 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); in mmp2_clk_init()
104 clk_register_clkdev(clk, "clk32", NULL); in mmp2_clk_init()
110 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, in mmp2_clk_init()
112 clk_register_clkdev(clk, "pll1", NULL); in mmp2_clk_init()
114 clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT, in mmp2_clk_init()
116 clk_register_clkdev(clk, "usb_pll", NULL); in mmp2_clk_init()
118 clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT, in mmp2_clk_init()
120 clk_register_clkdev(clk, "pll2", NULL); in mmp2_clk_init()
[all …]
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| D | clk-pxa168.c | 72 struct clk *clk; in pxa168_clk_init() local
73 struct clk *uart_pll; in pxa168_clk_init()
96 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); in pxa168_clk_init()
97 clk_register_clkdev(clk, "clk32", NULL); in pxa168_clk_init()
99 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, in pxa168_clk_init()
101 clk_register_clkdev(clk, "vctcxo", NULL); in pxa168_clk_init()
103 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, in pxa168_clk_init()
105 clk_register_clkdev(clk, "pll1", NULL); in pxa168_clk_init()
107 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa168_clk_init()
109 clk_register_clkdev(clk, "pll1_2", NULL); in pxa168_clk_init()
[all …]
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| D | clk-pxa910.c | 70 struct clk *clk; in pxa910_clk_init() local
71 struct clk *uart_pll; in pxa910_clk_init()
101 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); in pxa910_clk_init()
102 clk_register_clkdev(clk, "clk32", NULL); in pxa910_clk_init()
104 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, in pxa910_clk_init()
106 clk_register_clkdev(clk, "vctcxo", NULL); in pxa910_clk_init()
108 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, in pxa910_clk_init()
110 clk_register_clkdev(clk, "pll1", NULL); in pxa910_clk_init()
112 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa910_clk_init()
114 clk_register_clkdev(clk, "pll1_2", NULL); in pxa910_clk_init()
[all …]
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| D | clk.c | 12 static struct clk **clk_table; in mmp_clk_init()
14 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); in mmp_clk_init()
30 struct clk *clk; in mmp_register_fixed_rate_clks() local
33 clk = clk_register_fixed_rate(NULL, clks[i].name, in mmp_register_fixed_rate_clks()
37 if (IS_ERR(clk)) { in mmp_register_fixed_rate_clks()
43 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
51 struct clk *clk; in mmp_register_fixed_factor_clks() local
55 clk = clk_register_fixed_factor(NULL, clks[i].name, in mmp_register_fixed_factor_clks()
59 if (IS_ERR(clk)) { in mmp_register_fixed_factor_clks()
65 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_factor_clks()
[all …]
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| D | Makefile | 5 obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
9 obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
10 obj-$(CONFIG_MACH_MMP2_DT) += clk-of-mmp2.o
12 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
13 obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
14 obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
16 obj-y += clk-of-pxa1928.o
|
| /linux-4.4.14/arch/mips/lantiq/ |
| D | clk.c | 29 static struct clk cpu_clk_generic[4];
40 struct clk *clk_get_cpu(void) in clk_get_cpu()
45 struct clk *clk_get_fpi(void) in clk_get_fpi()
51 struct clk *clk_get_io(void) in clk_get_io()
56 struct clk *clk_get_ppe(void) in clk_get_ppe()
62 static inline int clk_good(struct clk *clk) in clk_good() argument
64 return clk && !IS_ERR(clk); in clk_good()
67 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
69 if (unlikely(!clk_good(clk))) in clk_get_rate()
72 if (clk->rate != 0) in clk_get_rate()
[all …]
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| D | clk.h | 60 struct clk { struct
67 int (*enable) (struct clk *clk); argument
68 void (*disable) (struct clk *clk); argument
69 int (*activate) (struct clk *clk); argument
70 void (*deactivate) (struct clk *clk); argument
71 void (*reboot) (struct clk *clk); argument
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| /linux-4.4.14/drivers/clk/spear/ |
| D | spear3xx_clock.c | 143 struct clk *clk; in spear300_clk_init() local
145 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, in spear300_clk_init()
147 clk_register_clkdev(clk, NULL, "60000000.clcd"); in spear300_clk_init()
149 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
151 clk_register_clkdev(clk, NULL, "94000000.flash"); in spear300_clk_init()
153 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
155 clk_register_clkdev(clk, NULL, "70000000.sdhci"); in spear300_clk_init()
157 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1, in spear300_clk_init()
159 clk_register_clkdev(clk, NULL, "a9000000.gpio"); in spear300_clk_init()
161 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1, in spear300_clk_init()
[all …]
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| D | spear1310_clock.c | 387 struct clk *clk, *clk1; in spear1310_clk_init() local
389 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, in spear1310_clk_init()
391 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear1310_clk_init()
393 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, in spear1310_clk_init()
395 clk_register_clkdev(clk, "osc_24m_clk", NULL); in spear1310_clk_init()
397 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, in spear1310_clk_init()
399 clk_register_clkdev(clk, "osc_25m_clk", NULL); in spear1310_clk_init()
401 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, in spear1310_clk_init()
403 clk_register_clkdev(clk, "gmii_pad_clk", NULL); in spear1310_clk_init()
405 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, in spear1310_clk_init()
[all …]
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| D | spear6xx_clock.c | 118 struct clk *clk, *clk1; in spear6xx_clk_init() local
120 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, in spear6xx_clk_init()
122 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear6xx_clk_init()
124 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT, in spear6xx_clk_init()
126 clk_register_clkdev(clk, "osc_30m_clk", NULL); in spear6xx_clk_init()
129 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, in spear6xx_clk_init()
131 clk_register_clkdev(clk, NULL, "rtc-spear"); in spear6xx_clk_init()
134 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, in spear6xx_clk_init()
136 clk_register_clkdev(clk, "pll3_clk", NULL); in spear6xx_clk_init()
138 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", in spear6xx_clk_init()
[all …]
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| D | spear1340_clock.c | 444 struct clk *clk, *clk1; in spear1340_clk_init() local
446 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, in spear1340_clk_init()
448 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear1340_clk_init()
450 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, in spear1340_clk_init()
452 clk_register_clkdev(clk, "osc_24m_clk", NULL); in spear1340_clk_init()
454 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, in spear1340_clk_init()
456 clk_register_clkdev(clk, "osc_25m_clk", NULL); in spear1340_clk_init()
458 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, in spear1340_clk_init()
460 clk_register_clkdev(clk, "gmii_pad_clk", NULL); in spear1340_clk_init()
462 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, in spear1340_clk_init()
[all …]
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| /linux-4.4.14/drivers/clk/zte/ |
| D | clk-zx296702.c | 21 static struct clk *topclk[ZX296702_TOPCLK_END];
22 static struct clk *lsp0clk[ZX296702_LSP0CLK_END];
23 static struct clk *lsp1clk[ZX296702_LSP1CLK_END];
199 static inline struct clk *zx_divtbl(const char *name, const char *parent, in zx_divtbl()
207 static inline struct clk *zx_div(const char *name, const char *parent, in zx_div()
214 static inline struct clk *zx_mux(const char *name, const char * const *parents, in zx_mux()
221 static inline struct clk *zx_gate(const char *name, const char *parent, in zx_gate()
230 struct clk **clk = topclk; in zx296702_top_clocks_init() local
236 clk[ZX296702_OSC] = in zx296702_top_clocks_init()
239 clk[ZX296702_PLL_A9] = in zx296702_top_clocks_init()
[all …]
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| /linux-4.4.14/arch/avr32/mach-at32ap/ |
| D | clock.c | 31 void at32_clk_register(struct clk *clk) in at32_clk_register() argument
35 list_add_tail(&clk->list, &at32_clock_list); in at32_clk_register()
39 static struct clk *__clk_get(struct device *dev, const char *id) in __clk_get()
41 struct clk *clk; in __clk_get() local
43 list_for_each_entry(clk, &at32_clock_list, list) { in __clk_get()
44 if (clk->dev == dev && strcmp(id, clk->name) == 0) { in __clk_get()
45 return clk; in __clk_get()
52 struct clk *clk_get(struct device *dev, const char *id) in clk_get()
54 struct clk *clk; in clk_get() local
57 clk = __clk_get(dev, id); in clk_get()
[all …]
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| D | clock.h | 18 void at32_clk_register(struct clk *clk);
20 struct clk { struct
24 struct clk *parent; /* Parent clock, if any */ argument
25 void (*mode)(struct clk *clk, int enabled); argument
26 unsigned long (*get_rate)(struct clk *clk); argument
27 long (*set_rate)(struct clk *clk, unsigned long rate, argument
29 int (*set_parent)(struct clk *clk, struct clk *parent); argument
34 unsigned long pba_clk_get_rate(struct clk *clk); argument
35 void pba_clk_mode(struct clk *clk, int enabled);
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| D | at32ap700x.c | 96 static struct clk devname##_##_name = { \
107 static struct clk osc0;
108 static struct clk osc1;
110 static unsigned long osc_get_rate(struct clk *clk) in osc_get_rate() argument
112 return at32_board_osc_rates[clk->index]; in osc_get_rate()
115 static unsigned long pll_get_rate(struct clk *clk, unsigned long control) in pll_get_rate() argument
122 rate = clk->parent->get_rate(clk->parent); in pll_get_rate()
129 static long pll_set_rate(struct clk *clk, unsigned long rate, in pll_set_rate() argument
150 base = clk->parent->get_rate(clk->parent); in pll_set_rate()
186 if (clk->parent == &osc1) in pll_set_rate()
[all …]
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| /linux-4.4.14/arch/m68k/coldfire/ |
| D | clk.c | 30 void __clk_init_enabled(struct clk *clk) in __clk_init_enabled() argument
32 clk->enabled = 1; in __clk_init_enabled()
33 clk->clk_ops->enable(clk); in __clk_init_enabled()
36 void __clk_init_disabled(struct clk *clk) in __clk_init_disabled() argument
38 clk->enabled = 0; in __clk_init_disabled()
39 clk->clk_ops->disable(clk); in __clk_init_disabled()
42 static void __clk_enable0(struct clk *clk) in __clk_enable0() argument
44 __raw_writeb(clk->slot, MCFPM_PPMCR0); in __clk_enable0()
47 static void __clk_disable0(struct clk *clk) in __clk_disable0() argument
49 __raw_writeb(clk->slot, MCFPM_PPMSR0); in __clk_disable0()
[all …]
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| /linux-4.4.14/kernel/time/ |
| D | posix-clock.c | 35 struct posix_clock *clk = fp->private_data; in get_posix_clock() local
37 down_read(&clk->rwsem); in get_posix_clock()
39 if (!clk->zombie) in get_posix_clock()
40 return clk; in get_posix_clock()
42 up_read(&clk->rwsem); in get_posix_clock()
47 static void put_posix_clock(struct posix_clock *clk) in put_posix_clock() argument
49 up_read(&clk->rwsem); in put_posix_clock()
55 struct posix_clock *clk = get_posix_clock(fp); in posix_clock_read() local
58 if (!clk) in posix_clock_read()
61 if (clk->ops.read) in posix_clock_read()
[all …]
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| /linux-4.4.14/arch/blackfin/mach-bf609/ |
| D | clock.c | 57 .clk = &_clk, \
89 int clk_enable(struct clk *clk) in clk_enable() argument
92 if (clk->ops && clk->ops->enable) in clk_enable()
93 ret = clk->ops->enable(clk); in clk_enable()
98 void clk_disable(struct clk *clk) in clk_disable() argument
100 if (clk->ops && clk->ops->disable) in clk_disable()
101 clk->ops->disable(clk); in clk_disable()
106 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
109 if (clk->ops && clk->ops->get_rate) in clk_get_rate()
110 ret = clk->ops->get_rate(clk); in clk_get_rate()
[all …]
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| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | base.c | 40 nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, in nvkm_clk_adjust() argument
43 struct nvkm_bios *bios = clk->subdev.device->bios; in nvkm_clk_adjust()
78 nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) in nvkm_cstate_prog() argument
80 struct nvkm_subdev *subdev = &clk->subdev; in nvkm_cstate_prog()
109 ret = clk->func->calc(clk, cstate); in nvkm_cstate_prog()
111 ret = clk->func->prog(clk); in nvkm_cstate_prog()
112 clk->func->tidy(clk); in nvkm_cstate_prog()
138 nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate) in nvkm_cstate_new() argument
140 struct nvkm_bios *bios = clk->subdev.device->bios; in nvkm_cstate_new()
141 const struct nvkm_domain *domain = clk->domains; in nvkm_cstate_new()
[all …]
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| D | mcp77.c | 42 read_div(struct mcp77_clk *clk) in read_div() argument
44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
49 read_pll(struct mcp77_clk *clk, u32 base) in read_pll() argument
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
83 struct mcp77_clk *clk = mcp77_clk(base); in mcp77_clk_read() local
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
95 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; in mcp77_clk_read()
97 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 2 / 3; in mcp77_clk_read()
100 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); in mcp77_clk_read()
[all …]
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| D | gf100.c | 49 read_vco(struct gf100_clk *clk, u32 dsrc) in read_vco() argument
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
59 read_pll(struct gf100_clk *clk, u32 pll) in read_pll() argument
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
98 read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl) in read_div() argument
[all …]
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| D | gt215.c | 43 read_vco(struct gt215_clk *clk, int idx) in read_vco() argument
45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
52 return read_pll(clk, 0x41, 0x00e820); in read_vco()
54 return read_pll(clk, 0x42, 0x00e8a0); in read_vco()
61 read_clk(struct gt215_clk *clk, int idx, bool ignore_en) in read_clk() argument
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
99 sclk = read_vco(clk, idx); in read_clk()
108 read_pll(struct gt215_clk *clk, int idx, u32 pll) in read_pll() argument
110 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
127 sclk = read_clk(clk, 0x00 + idx, false); in read_pll()
[all …]
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| D | gk104.c | 50 read_vco(struct gk104_clk *clk, u32 dsrc) in read_vco() argument
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
55 return read_pll(clk, 0x00e800); in read_vco()
56 return read_pll(clk, 0x00e820); in read_vco()
60 read_pll(struct gk104_clk *clk, u32 pll) in read_pll() argument
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
81 sclk = read_pll(clk, 0x132020); in read_pll()
85 sclk = read_div(clk, 0, 0x137320, 0x137330); in read_pll()
92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
106 read_div(struct gk104_clk *clk, int doff, u32 dsrc, u32 dctl) in read_div() argument
[all …]
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| D | gk20a.c | 125 gk20a_pllg_read_mnp(struct gk20a_clk *clk) in gk20a_pllg_read_mnp() argument
127 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_read_mnp()
131 clk->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp()
132 clk->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); in gk20a_pllg_read_mnp()
133 clk->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); in gk20a_pllg_read_mnp()
137 gk20a_pllg_calc_rate(struct gk20a_clk *clk) in gk20a_pllg_calc_rate() argument
142 rate = clk->parent_rate * clk->n; in gk20a_pllg_calc_rate()
143 divider = clk->m * pl_to_div[clk->pl]; in gk20a_pllg_calc_rate()
150 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) in gk20a_pllg_calc_mnp() argument
152 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_pllg_calc_mnp()
[all …]
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| D | nv50.c | 32 read_div(struct nv50_clk *clk) in read_div() argument
34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
52 read_pll_src(struct nv50_clk *clk, u32 base) in read_pll_src() argument
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
103 case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
104 case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll_src()
125 read_pll_ref(struct nv50_clk *clk, u32 base) in read_pll_ref() argument
127 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_ref()
145 return nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_ref()
[all …]
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| D | nv40.c | 40 read_pll_1(struct nv40_clk *clk, u32 reg) in read_pll_1() argument
42 struct nvkm_device *device = clk->base.subdev.device; in read_pll_1()
56 read_pll_2(struct nv40_clk *clk, u32 reg) in read_pll_2() argument
58 struct nvkm_device *device = clk->base.subdev.device; in read_pll_2()
82 read_clk(struct nv40_clk *clk, u32 src) in read_clk() argument
86 return read_pll_2(clk, 0x004000); in read_clk()
88 return read_pll_1(clk, 0x004008); in read_clk()
99 struct nv40_clk *clk = nv40_clk(base); in nv40_clk_read() local
100 struct nvkm_subdev *subdev = &clk->base.subdev; in nv40_clk_read()
110 return read_clk(clk, (mast & 0x00000003) >> 0); in nv40_clk_read()
[all …]
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| D | Kbuild | 1 nvkm-y += nvkm/subdev/clk/base.o
2 nvkm-y += nvkm/subdev/clk/nv04.o
3 nvkm-y += nvkm/subdev/clk/nv40.o
4 nvkm-y += nvkm/subdev/clk/nv50.o
5 nvkm-y += nvkm/subdev/clk/g84.o
6 nvkm-y += nvkm/subdev/clk/gt215.o
7 nvkm-y += nvkm/subdev/clk/mcp77.o
8 nvkm-y += nvkm/subdev/clk/gf100.o
9 nvkm-y += nvkm/subdev/clk/gk104.o
10 nvkm-y += nvkm/subdev/clk/gk20a.o
[all …]
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| D | pllnv04.c | 29 getMNP_single(struct nvkm_subdev *subdev, struct nvbios_pll *info, int clk, in getMNP_single() argument
59 if (clk > 250000) in getMNP_single()
61 if (clk > 340000) in getMNP_single()
64 if (clk > 150000) in getMNP_single()
66 if (clk > 200000) in getMNP_single()
68 if (clk > 340000) in getMNP_single()
74 if ((clk * P) < minvco) { in getMNP_single()
75 minvco = clk * maxP; in getMNP_single()
79 if (clk + clk/200 > maxvco) /* +0.5% */ in getMNP_single()
80 maxvco = clk + clk/200; in getMNP_single()
[all …]
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| /linux-4.4.14/arch/mips/bcm63xx/ |
| D | clk.c | 19 struct clk { struct
20 void (*set)(struct clk *, int); argument
29 static void clk_enable_unlocked(struct clk *clk) in clk_enable_unlocked() argument
31 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
32 clk->set(clk, 1); in clk_enable_unlocked()
35 static void clk_disable_unlocked(struct clk *clk) in clk_disable_unlocked() argument
37 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
38 clk->set(clk, 0); in clk_disable_unlocked()
56 static void enet_misc_set(struct clk *clk, int enable) in enet_misc_set() argument
72 static struct clk clk_enet_misc = {
[all …]
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| /linux-4.4.14/arch/arm/boot/dts/ |
| D | stih410-clock.dtsi | 15 compatible = "st,stih410-clk", "simple-bus";
20 clk_sysin: clk-sysin {
30 arm_periph_clk: clk-m-a9-periphs {
58 clk_m_a9: clk-m-a9@92b0000 {
72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
78 clock-output-names = "clk-m-a9-ext2f-div2";
92 clock-output-names = "clk-s-icn-reg-0";
99 clk_s_a0_pll: clk-s-a0-pll {
105 clock-output-names = "clk-s-a0-pll-ofd-0";
108 clk_s_a0_flexgen: clk-s-a0-flexgen {
[all …]
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| D | stih418-clock.dtsi | 15 compatible = "st,stih418-clk", "simple-bus";
20 clk_sysin: clk-sysin {
30 arm_periph_clk: clk-m-a9-periphs {
58 clk_m_a9: clk-m-a9@92b0000 {
72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
78 clock-output-names = "clk-m-a9-ext2f-div2";
92 clock-output-names = "clk-s-icn-reg-0";
99 clk_s_a0_pll: clk-s-a0-pll {
105 clock-output-names = "clk-s-a0-pll-ofd-0";
108 clk_s_a0_flexgen: clk-s-a0-flexgen {
[all …]
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| D | stih407-clock.dtsi | 18 clk_sysin: clk-sysin {
27 arm_periph_clk: clk-m-a9-periphs {
56 clk_m_a9: clk-m-a9@92b0000 {
70 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
76 clock-output-names = "clk-m-a9-ext2f-div2";
90 clock-output-names = "clk-s-icn-reg-0";
97 clk_s_a0_pll: clk-s-a0-pll {
103 clock-output-names = "clk-s-a0-pll-ofd-0";
106 clk_s_a0_flexgen: clk-s-a0-flexgen {
114 clock-output-names = "clk-ic-lmi0";
[all …]
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| D | stih416-clock.dtsi | 21 clk_sysin: clk-sysin {
33 clk_s_a0_pll: clk-s-a0-pll {
39 clock-output-names = "clk-s-a0-pll0-hs",
40 "clk-s-a0-pll0-ls",
41 "clk-s-a0-pll1";
44 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
51 clock-output-names = "clk-s-a0-osc-prediv";
54 clk_s_a0_hs: clk-s-a0-hs {
63 clock-output-names = "clk-s-fdma-0",
64 "clk-s-fdma-1",
[all …]
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| D | stih415-clock.dtsi | 20 clk_sysin: clk-sysin {
32 clk_s_a0_pll: clk-s-a0-pll {
38 clock-output-names = "clk-s-a0-pll0-hs",
39 "clk-s-a0-pll0-ls",
40 "clk-s-a0-pll1";
43 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
50 clock-output-names = "clk-s-a0-osc-prediv";
53 clk_s_a0_hs: clk-s-a0-hs {
62 clock-output-names = "clk-s-fdma-0",
63 "clk-s-fdma-1",
[all …]
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| D | socfpga.dtsi | 113 compatible = "altr,clk-mgr";
150 compatible = "altr,socfpga-perip-clk";
158 compatible = "altr,socfpga-perip-clk";
166 compatible = "altr,socfpga-perip-clk";
174 compatible = "altr,socfpga-perip-clk";
181 compatible = "altr,socfpga-perip-clk";
188 compatible = "altr,socfpga-perip-clk";
204 compatible = "altr,socfpga-perip-clk";
211 compatible = "altr,socfpga-perip-clk";
218 compatible = "altr,socfpga-perip-clk";
[all …]
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| /linux-4.4.14/arch/arm/mach-ep93xx/ |
| D | clock.c | 30 struct clk { struct
31 struct clk *parent; argument
38 unsigned long (*get_rate)(struct clk *clk); argument
39 int (*set_rate)(struct clk *clk, unsigned long rate); argument
43 static unsigned long get_uart_rate(struct clk *clk);
45 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
46 static int set_div_rate(struct clk *clk, unsigned long rate);
47 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
48 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
50 static struct clk clk_xtali = {
[all …]
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| /linux-4.4.14/arch/arm/mach-mmp/ |
| D | clock.c | 19 static void apbc_clk_enable(struct clk *clk) in apbc_clk_enable() argument
23 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel); in apbc_clk_enable()
24 __raw_writel(clk_rst, clk->clk_rst); in apbc_clk_enable()
27 static void apbc_clk_disable(struct clk *clk) in apbc_clk_disable() argument
29 __raw_writel(0, clk->clk_rst); in apbc_clk_disable()
37 static void apmu_clk_enable(struct clk *clk) in apmu_clk_enable() argument
39 __raw_writel(clk->enable_val, clk->clk_rst); in apmu_clk_enable()
42 static void apmu_clk_disable(struct clk *clk) in apmu_clk_disable() argument
44 __raw_writel(0, clk->clk_rst); in apmu_clk_disable()
54 int clk_enable(struct clk *clk) in clk_enable() argument
[all …]
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| D | clock.h | 12 void (*enable)(struct clk *);
13 void (*disable)(struct clk *);
14 unsigned long (*getrate)(struct clk *);
15 int (*setrate)(struct clk *, unsigned long);
18 struct clk { struct
32 struct clk clk_##_name = { \ argument
40 struct clk clk_##_name = { \
48 struct clk clk_##_name = { \
56 struct clk clk_##_name = { \
65 .clk = _clk, \
[all …]
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| /linux-4.4.14/arch/arm/mach-sa1100/ |
| D | clock.c | 21 void (*enable)(struct clk *);
22 void (*disable)(struct clk *);
23 unsigned long (*get_rate)(struct clk *);
26 struct clk { struct
32 struct clk clk_##_name = { \ argument
38 static void clk_gpio27_enable(struct clk *clk) in clk_gpio27_enable() argument
49 static void clk_gpio27_disable(struct clk *clk) in clk_gpio27_disable() argument
56 static void clk_cpu_enable(struct clk *clk) in clk_cpu_enable() argument
60 static void clk_cpu_disable(struct clk *clk) in clk_cpu_disable() argument
64 static unsigned long clk_cpu_get_rate(struct clk *clk) in clk_cpu_get_rate() argument
[all …]
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| /linux-4.4.14/drivers/clk/ti/ |
| D | clkt_dflt.c | 58 static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, in _wait_idlest_generic() argument
92 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) in _omap2_module_wait_ready() argument
100 if (clk->ops->find_companion) { in _omap2_module_wait_ready()
101 clk->ops->find_companion(clk, &companion_reg, &other_bit); in _omap2_module_wait_ready()
107 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); in _omap2_module_wait_ready()
112 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), in _omap2_module_wait_ready()
113 idlest_val, clk_hw_get_name(&clk->hw)); in _omap2_module_wait_ready()
141 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, in omap2_clk_dflt_find_companion() argument
150 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); in omap2_clk_dflt_find_companion()
153 *other_bit = clk->enable_bit; in omap2_clk_dflt_find_companion()
[all …]
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| D | dpll3xxx.c | 43 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
44 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
45 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
50 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) in _omap3_dpll_write_clken() argument
55 dd = clk->dpll_data; in _omap3_dpll_write_clken()
64 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) in _omap3_wait_dpll_status() argument
71 dd = clk->dpll_data; in _omap3_wait_dpll_status()
72 clk_name = clk_hw_get_name(&clk->hw); in _omap3_wait_dpll_status()
96 static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) in _omap3_dpll_compute_freqsel() argument
101 fint = clk_get_rate(clk->dpll_data->clk_ref) / n; in _omap3_dpll_compute_freqsel()
[all …]
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| D | autoidle.c | 46 int omap2_clk_deny_idle(struct clk *clk) in omap2_clk_deny_idle() argument
50 c = to_clk_hw_omap(__clk_get_hw(clk)); in omap2_clk_deny_idle()
62 int omap2_clk_allow_idle(struct clk *clk) in omap2_clk_allow_idle() argument
66 c = to_clk_hw_omap(__clk_get_hw(clk)); in omap2_clk_allow_idle()
72 static void _allow_autoidle(struct clk_ti_autoidle *clk) in _allow_autoidle() argument
76 val = ti_clk_ll_ops->clk_readl(clk->reg); in _allow_autoidle()
78 if (clk->flags & AUTOIDLE_LOW) in _allow_autoidle()
79 val &= ~(1 << clk->shift); in _allow_autoidle()
81 val |= (1 << clk->shift); in _allow_autoidle()
83 ti_clk_ll_ops->clk_writel(val, clk->reg); in _allow_autoidle()
[all …]
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| D | Makefile | 1 obj-y += clk.o autoidle.o clockdomain.o
2 clk-common = dpll.o composite.o divider.o gate.o \
5 obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o
6 obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o
7 obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
8 obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
9 clk-3xxx.o dpll3xxx.o
10 obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o \
12 obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \
14 obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
[all …]
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| D | clk.c | 106 struct clk *clk; in ti_dt_clocks_register() local
112 clk = of_clk_get_from_provider(&clkspec); in ti_dt_clocks_register()
114 if (!IS_ERR(clk)) { in ti_dt_clocks_register()
115 c->lk.clk = clk; in ti_dt_clocks_register()
294 struct clk __init *ti_clk_register_clk(struct ti_clk *setup) in ti_clk_register_clk()
296 struct clk *clk; in ti_clk_register_clk() local
301 if (setup->clk) in ti_clk_register_clk()
302 return setup->clk; in ti_clk_register_clk()
308 clk = clk_register_fixed_rate(NULL, setup->name, NULL, in ti_clk_register_clk()
312 clk = ti_clk_register_mux(setup); in ti_clk_register_clk()
[all …]
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| D | clockdomain.c | 44 struct clk_hw_omap *clk; in omap2_clkops_enable_clkdm() local
47 clk = to_clk_hw_omap(hw); in omap2_clkops_enable_clkdm()
49 if (unlikely(!clk->clkdm)) { in omap2_clkops_enable_clkdm()
55 if (unlikely(clk->enable_reg)) in omap2_clkops_enable_clkdm()
65 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); in omap2_clkops_enable_clkdm()
67 __func__, clk_hw_get_name(hw), clk->clkdm_name, ret); in omap2_clkops_enable_clkdm()
83 struct clk_hw_omap *clk; in omap2_clkops_disable_clkdm() local
85 clk = to_clk_hw_omap(hw); in omap2_clkops_disable_clkdm()
87 if (unlikely(!clk->clkdm)) { in omap2_clkops_disable_clkdm()
93 if (unlikely(clk->enable_reg)) in omap2_clkops_disable_clkdm()
[all …]
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| D | dpll44xx.c | 40 static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) in omap4_dpllmx_allow_gatectrl() argument
45 if (!clk || !clk->clksel_reg) in omap4_dpllmx_allow_gatectrl()
48 mask = clk->flags & CLOCK_CLKOUTX2 ? in omap4_dpllmx_allow_gatectrl()
52 v = ti_clk_ll_ops->clk_readl(clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
55 ti_clk_ll_ops->clk_writel(v, clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
58 static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) in omap4_dpllmx_deny_gatectrl() argument
63 if (!clk || !clk->clksel_reg) in omap4_dpllmx_deny_gatectrl()
66 mask = clk->flags & CLOCK_CLKOUTX2 ? in omap4_dpllmx_deny_gatectrl()
70 v = ti_clk_ll_ops->clk_readl(clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
73 ti_clk_ll_ops->clk_writel(v, clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
[all …]
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| D | composite.c | 108 static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx) in _get_hw() argument
110 if (!clk) in _get_hw()
113 if (!clk->comp_clks[idx]) in _get_hw()
116 return clk->comp_clks[idx]->hw; in _get_hw()
122 struct clk *ti_clk_register_composite(struct ti_clk *setup) in ti_clk_register_composite()
130 struct clk *clk; in ti_clk_register_composite() local
149 clk = clk_register_composite(NULL, setup->name, in ti_clk_register_composite()
155 return clk; in ti_clk_register_composite()
162 struct clk *clk; in _register_composite() local
213 clk = clk_register_composite(NULL, node->name, in _register_composite()
[all …]
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| D | apll.c | 42 struct clk_hw_omap *clk = to_clk_hw_omap(hw); in dra7_apll_enable() local
49 ad = clk->dpll_data; in dra7_apll_enable()
53 clk_name = clk_hw_get_name(&clk->hw); in dra7_apll_enable()
93 struct clk_hw_omap *clk = to_clk_hw_omap(hw); in dra7_apll_disable() local
98 ad = clk->dpll_data; in dra7_apll_disable()
110 struct clk_hw_omap *clk = to_clk_hw_omap(hw); in dra7_apll_is_enabled() local
114 ad = clk->dpll_data; in dra7_apll_is_enabled()
141 struct clk *clk; in omap_clk_register_apll() local
155 clk = clk_register(NULL, &clk_hw->hw); in omap_clk_register_apll()
156 if (!IS_ERR(clk)) { in omap_clk_register_apll()
[all …]
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| /linux-4.4.14/arch/mips/ralink/ |
| D | clk.c | 19 struct clk { struct
26 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); in ralink_clk_add() local
28 if (!clk) in ralink_clk_add()
31 clk->cl.dev_id = dev; in ralink_clk_add()
32 clk->cl.clk = clk; in ralink_clk_add()
34 clk->rate = rate; in ralink_clk_add()
36 clkdev_add(&clk->cl); in ralink_clk_add()
42 int clk_enable(struct clk *clk) in clk_enable() argument
48 void clk_disable(struct clk *clk) in clk_disable() argument
53 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
[all …]
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| /linux-4.4.14/arch/arm/plat-versatile/ |
| D | clock.c | 21 int clk_enable(struct clk *clk) in clk_enable() argument
27 void clk_disable(struct clk *clk) in clk_disable() argument
32 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
34 return clk->rate; in clk_get_rate()
38 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
41 if (clk->ops && clk->ops->round) in clk_round_rate()
42 ret = clk->ops->round(clk, rate); in clk_round_rate()
47 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
50 if (clk->ops && clk->ops->set) in clk_set_rate()
51 ret = clk->ops->set(clk, rate); in clk_set_rate()
[all …]
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| /linux-4.4.14/arch/mips/lantiq/falcon/ |
| D | sysctrl.c | 82 static inline void sysctl_wait(struct clk *clk, in sysctl_wait() argument
87 do {} while (--err && ((sysctl_r32(clk->module, reg) in sysctl_wait()
88 & clk->bits) != test)); in sysctl_wait()
91 clk->module, clk->bits, test, in sysctl_wait()
92 sysctl_r32(clk->module, reg) & clk->bits); in sysctl_wait()
95 static int sysctl_activate(struct clk *clk) in sysctl_activate() argument
97 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); in sysctl_activate()
98 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); in sysctl_activate()
99 sysctl_wait(clk, clk->bits, SYSCTL_ACTS); in sysctl_activate()
103 static void sysctl_deactivate(struct clk *clk) in sysctl_deactivate() argument
[all …]
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| /linux-4.4.14/arch/arm/mach-lpc32xx/ |
| D | clock.c | 106 static struct clk clk_armpll;
107 static struct clk clk_usbpll;
114 static unsigned long local_return_parent_rate(struct clk *clk) in local_return_parent_rate() argument
120 while (clk->rate == 0) in local_return_parent_rate()
121 clk = clk->parent; in local_return_parent_rate()
123 return clk->rate; in local_return_parent_rate()
127 static struct clk osc_32KHz = {
132 static int local_pll397_enable(struct clk *clk, int enable) in local_pll397_enable() argument
161 static int local_oscmain_enable(struct clk *clk, int enable) in local_oscmain_enable() argument
190 static struct clk osc_pll397 = {
[all …]
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| /linux-4.4.14/arch/mips/lantiq/xway/ |
| D | clk.c | 59 unsigned long clk; in ltq_danube_pp32_hz() local
63 clk = CLOCK_240M; in ltq_danube_pp32_hz()
66 clk = CLOCK_222M; in ltq_danube_pp32_hz()
69 clk = CLOCK_133M; in ltq_danube_pp32_hz()
72 clk = CLOCK_266M; in ltq_danube_pp32_hz()
76 return clk; in ltq_danube_pp32_hz()
107 unsigned long clk; in ltq_vr9_cpu_hz() local
113 clk = CLOCK_600M; in ltq_vr9_cpu_hz()
116 clk = CLOCK_500M; in ltq_vr9_cpu_hz()
119 clk = CLOCK_393M; in ltq_vr9_cpu_hz()
[all …]
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| D | sysctrl.c | 196 static int cgu_enable(struct clk *clk) in cgu_enable() argument
198 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); in cgu_enable()
203 static void cgu_disable(struct clk *clk) in cgu_disable() argument
205 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); in cgu_disable()
209 static int pmu_enable(struct clk *clk) in pmu_enable() argument
215 pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module)); in pmu_enable()
217 (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits))); in pmu_enable()
221 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits, in pmu_enable()
222 PWDCR(clk->module)); in pmu_enable()
224 (pmu_r32(PWDSR(clk->module)) & clk->bits)); in pmu_enable()
[all …]
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| D | gptu.c | 96 static int gptu_enable(struct clk *clk) in gptu_enable() argument
98 int ret = request_irq(irqres[clk->bits].start, timer_irq_handler, in gptu_enable()
106 GPTU_CON(clk->bits)); in gptu_enable()
107 gptu_w32(1, GPTU_RLD(clk->bits)); in gptu_enable()
108 gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN); in gptu_enable()
109 gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits)); in gptu_enable()
113 static void gptu_disable(struct clk *clk) in gptu_disable() argument
115 gptu_w32(0, GPTU_RUN(clk->bits)); in gptu_disable()
116 gptu_w32(0, GPTU_CON(clk->bits)); in gptu_disable()
117 gptu_w32(0, GPTU_RLD(clk->bits)); in gptu_disable()
[all …]
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| /linux-4.4.14/arch/sh/kernel/cpu/sh4/ |
| D | clock-sh4-202.c | 25 static unsigned long emi_clk_recalc(struct clk *clk) in emi_clk_recalc() argument
28 return clk->parent->rate / frqcr3_divisors[idx]; in emi_clk_recalc()
31 static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) in frqcr3_lookup() argument
33 int divisor = clk->parent->rate / rate; in frqcr3_lookup()
48 static struct clk sh4202_emi_clk = {
53 static unsigned long femi_clk_recalc(struct clk *clk) in femi_clk_recalc() argument
56 return clk->parent->rate / frqcr3_divisors[idx]; in femi_clk_recalc()
63 static struct clk sh4202_femi_clk = {
68 static void shoc_clk_init(struct clk *clk) in shoc_clk_init() argument
84 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init()
[all …]
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| D | clock-sh4.c | 29 static void master_clk_init(struct clk *clk) in master_clk_init() argument
31 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007]; in master_clk_init()
38 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
41 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
48 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
51 return clk->parent->rate / bfc_divisors[idx]; in bus_clk_recalc()
58 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
61 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| /linux-4.4.14/drivers/clk/ |
| D | Makefile | 2 obj-$(CONFIG_HAVE_CLK) += clk-devres.o
4 obj-$(CONFIG_COMMON_CLK) += clk.o
5 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
6 obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
7 obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
8 obj-$(CONFIG_COMMON_CLK) += clk-gate.o
9 obj-$(CONFIG_COMMON_CLK) += clk-multiplier.o
10 obj-$(CONFIG_COMMON_CLK) += clk-mux.o
11 obj-$(CONFIG_COMMON_CLK) += clk-composite.o
12 obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o
[all …]
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| D | clk-ls1x.c | 51 static struct clk *__init clk_register_pll(struct device *dev, in clk_register_pll()
57 struct clk *clk; in clk_register_pll() local
75 clk = clk_register(dev, hw); in clk_register_pll()
77 if (IS_ERR(clk)) in clk_register_pll()
80 return clk; in clk_register_pll()
89 struct clk *clk; in ls1x_clk_init() local
91 clk = clk_register_fixed_rate(NULL, "osc_33m_clk", NULL, CLK_IS_ROOT, in ls1x_clk_init()
93 clk_register_clkdev(clk, "osc_33m_clk", NULL); in ls1x_clk_init()
96 clk = clk_register_pll(NULL, "pll_clk", "osc_33m_clk", 0); in ls1x_clk_init()
97 clk_register_clkdev(clk, "pll_clk", NULL); in ls1x_clk_init()
[all …]
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| D | clkdev.c | 31 static struct clk *__of_clk_get(struct device_node *np, int index, in __of_clk_get()
35 struct clk *clk; in __of_clk_get() local
46 clk = __of_clk_get_from_provider(&clkspec, dev_id, con_id); in __of_clk_get()
49 return clk; in __of_clk_get()
52 struct clk *of_clk_get(struct device_node *np, int index) in of_clk_get()
58 static struct clk *__of_clk_get_by_name(struct device_node *np, in __of_clk_get_by_name()
62 struct clk *clk = ERR_PTR(-ENOENT); in __of_clk_get_by_name() local
75 clk = __of_clk_get(np, index, dev_id, name); in __of_clk_get_by_name()
76 if (!IS_ERR(clk)) { in __of_clk_get_by_name()
79 if (PTR_ERR(clk) != -EPROBE_DEFER) in __of_clk_get_by_name()
[all …]
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| D | clk-efm32gg.c | 18 static struct clk *clk[37]; variable
20 .clks = clk,
21 .clk_num = ARRAY_SIZE(clk),
29 for (i = 0; i < ARRAY_SIZE(clk); ++i) in efm32gg_cmu_init()
30 clk[i] = ERR_PTR(-ENOENT); in efm32gg_cmu_init()
38 clk[clk_HFXO] = clk_register_fixed_rate(NULL, "HFXO", NULL, in efm32gg_cmu_init()
41 clk[clk_HFPERCLKUSART0] = clk_register_gate(NULL, "HFPERCLK.USART0", in efm32gg_cmu_init()
43 clk[clk_HFPERCLKUSART1] = clk_register_gate(NULL, "HFPERCLK.USART1", in efm32gg_cmu_init()
45 clk[clk_HFPERCLKUSART2] = clk_register_gate(NULL, "HFPERCLK.USART2", in efm32gg_cmu_init()
47 clk[clk_HFPERCLKUART0] = clk_register_gate(NULL, "HFPERCLK.UART0", in efm32gg_cmu_init()
[all …]
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| D | clk-scpi.c | 35 #define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw) argument
42 struct scpi_clk *clk = to_scpi_clk(hw); in scpi_clk_recalc_rate() local
44 return clk->scpi_ops->clk_get_val(clk->id); in scpi_clk_recalc_rate()
62 struct scpi_clk *clk = to_scpi_clk(hw); in scpi_clk_set_rate() local
64 return clk->scpi_ops->clk_set_val(clk->id, rate); in scpi_clk_set_rate()
74 static int __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate) in __scpi_dvfs_round_rate() argument
78 const struct scpi_opp *opp = clk->info->opps; in __scpi_dvfs_round_rate()
80 for (idx = 0; idx < clk->info->count; idx++, opp++) { in __scpi_dvfs_round_rate()
96 struct scpi_clk *clk = to_scpi_clk(hw); in scpi_dvfs_recalc_rate() local
97 int idx = clk->scpi_ops->dvfs_get_idx(clk->id); in scpi_dvfs_recalc_rate()
[all …]
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| D | clk.c | 81 struct clk { struct
275 const char *__clk_get_name(const struct clk *clk) in __clk_get_name() argument
277 return !clk ? NULL : clk->core->name; in __clk_get_name()
287 struct clk_hw *__clk_get_hw(struct clk *clk) in __clk_get_hw() argument
289 return !clk ? NULL : clk->core->hw; in __clk_get_hw()
373 unsigned int __clk_get_enable_count(struct clk *clk) in __clk_get_enable_count() argument
375 return !clk ? 0 : clk->core->enable_count; in __clk_get_enable_count()
413 unsigned long __clk_get_flags(struct clk *clk) in __clk_get_flags() argument
415 return !clk ? 0 : clk->core->flags; in __clk_get_flags()
435 bool __clk_is_enabled(struct clk *clk) in __clk_is_enabled() argument
[all …]
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| D | clk-gpio.c | 38 struct clk_gpio *clk = to_clk_gpio(hw); in clk_gpio_gate_enable() local
40 gpiod_set_value(clk->gpiod, 1); in clk_gpio_gate_enable()
47 struct clk_gpio *clk = to_clk_gpio(hw); in clk_gpio_gate_disable() local
49 gpiod_set_value(clk->gpiod, 0); in clk_gpio_gate_disable()
54 struct clk_gpio *clk = to_clk_gpio(hw); in clk_gpio_gate_is_enabled() local
56 return gpiod_get_value(clk->gpiod); in clk_gpio_gate_is_enabled()
76 struct clk_gpio *clk = to_clk_gpio(hw); in clk_gpio_mux_get_parent() local
78 return gpiod_get_value(clk->gpiod); in clk_gpio_mux_get_parent()
83 struct clk_gpio *clk = to_clk_gpio(hw); in clk_gpio_mux_set_parent() local
85 gpiod_set_value(clk->gpiod, index); in clk_gpio_mux_set_parent()
[all …]
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| D | clk-nspire.c | 45 static void nspire_clkinfo_cx(u32 val, struct nspire_clk_info *clk) in nspire_clkinfo_cx() argument
48 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
50 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
52 clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * EXTRACT(val, CX_UNKNOWN); in nspire_clkinfo_cx()
53 clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1); in nspire_clkinfo_cx()
56 static void nspire_clkinfo_classic(u32 val, struct nspire_clk_info *clk) in nspire_clkinfo_classic() argument
59 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
61 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
63 clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * 2; in nspire_clkinfo_classic()
64 clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1); in nspire_clkinfo_classic()
[all …]
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| D | clk.h | 15 struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
20 struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
22 void __clk_free_clk(struct clk *clk);
25 static inline struct clk *
28 return (struct clk *)hw; in __clk_create_clk()
30 static inline void __clk_free_clk(struct clk *clk) { } in __clk_free_clk() argument
31 static struct clk_hw *__clk_get_hw(struct clk *clk) in __clk_get_hw() argument
33 return (struct clk_hw *)clk; in __clk_get_hw()
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| D | clk-conf.c | 21 struct clk *clk, *pclk; in __set_clk_parents() local
56 clk = of_clk_get_from_provider(&clkspec); in __set_clk_parents()
57 if (IS_ERR(clk)) { in __set_clk_parents()
60 rc = PTR_ERR(clk); in __set_clk_parents()
64 rc = clk_set_parent(clk, pclk); in __set_clk_parents()
67 __clk_get_name(clk), __clk_get_name(pclk), rc); in __set_clk_parents()
68 clk_put(clk); in __set_clk_parents()
83 struct clk *clk; in __set_clk_rates() local
100 clk = of_clk_get_from_provider(&clkspec); in __set_clk_rates()
101 if (IS_ERR(clk)) { in __set_clk_rates()
[all …]
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| D | clk-qoriq.c | 38 struct clk *clk; member
90 struct clk *sysclk;
92 struct clk *cmux[NUM_CMUX];
93 struct clk *hwaccel[NUM_HWACCEL];
94 struct clk *fman[2];
355 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
357 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p2041_init_periph()
367 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
369 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
372 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
[all …]
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| D | clk-devres.c | 14 clk_put(*(struct clk **)res); in devm_clk_release()
17 struct clk *devm_clk_get(struct device *dev, const char *id) in devm_clk_get()
19 struct clk **ptr, *clk; in devm_clk_get() local
25 clk = clk_get(dev, id); in devm_clk_get()
26 if (!IS_ERR(clk)) { in devm_clk_get()
27 *ptr = clk; in devm_clk_get()
33 return clk; in devm_clk_get()
39 struct clk **c = res; in devm_clk_match()
47 void devm_clk_put(struct device *dev, struct clk *clk) in devm_clk_put() argument
51 ret = devres_release(dev, devm_clk_release, devm_clk_match, clk); in devm_clk_put()
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| D | clk-moxart.c | 22 struct clk *clk, *ref_clk; in moxart_of_pll_clk_init() local
45 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mul, 1); in moxart_of_pll_clk_init()
46 if (IS_ERR(clk)) { in moxart_of_pll_clk_init()
51 clk_register_clkdev(clk, NULL, name); in moxart_of_pll_clk_init()
52 of_clk_add_provider(node, of_clk_src_simple_get, clk); in moxart_of_pll_clk_init()
60 struct clk *clk, *pll_clk; in moxart_of_apb_clk_init() local
88 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, 1, div); in moxart_of_apb_clk_init()
89 if (IS_ERR(clk)) { in moxart_of_apb_clk_init()
94 clk_register_clkdev(clk, NULL, name); in moxart_of_apb_clk_init()
95 of_clk_add_provider(node, of_clk_src_simple_get, clk); in moxart_of_apb_clk_init()
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| D | clk-fixed-rate.c | 59 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, in clk_register_fixed_rate_with_accuracy()
64 struct clk *clk; in clk_register_fixed_rate_with_accuracy() local
84 clk = clk_register(dev, &fixed->hw); in clk_register_fixed_rate_with_accuracy()
85 if (IS_ERR(clk)) in clk_register_fixed_rate_with_accuracy()
88 return clk; in clk_register_fixed_rate_with_accuracy()
100 struct clk *clk_register_fixed_rate(struct device *dev, const char *name, in clk_register_fixed_rate()
115 struct clk *clk; in of_fixed_clk_setup() local
127 clk = clk_register_fixed_rate_with_accuracy(NULL, clk_name, NULL, in of_fixed_clk_setup()
130 if (!IS_ERR(clk)) in of_fixed_clk_setup()
131 of_clk_add_provider(node, of_clk_src_simple_get, clk); in of_fixed_clk_setup()
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| /linux-4.4.14/arch/mips/include/asm/ |
| D | clock.h | 9 struct clk;
12 void (*init) (struct clk *clk);
13 void (*enable) (struct clk *clk);
14 void (*disable) (struct clk *clk);
15 void (*recalc) (struct clk *clk);
16 int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
17 long (*round_rate) (struct clk *clk, unsigned long rate);
20 struct clk { struct
26 struct clk *parent; argument
40 int __clk_enable(struct clk *); argument
[all …]
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| /linux-4.4.14/arch/mips/loongson64/lemote-2f/ |
| D | clock.c | 44 static struct clk cpu_clk = {
50 struct clk *clk_get(struct device *dev, const char *id) in clk_get()
56 static void propagate_rate(struct clk *clk) in propagate_rate() argument
58 struct clk *clkp; in propagate_rate()
61 if (likely(clkp->parent != clk)) in propagate_rate()
70 int clk_enable(struct clk *clk) in clk_enable() argument
76 void clk_disable(struct clk *clk) in clk_disable() argument
81 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
83 return (unsigned long)clk->rate; in clk_get_rate()
87 void clk_put(struct clk *clk) in clk_put() argument
[all …]
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| /linux-4.4.14/drivers/clk/samsung/ |
| D | Makefile | 5 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
6 obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
7 obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
8 obj-$(CONFIG_SOC_EXYNOS4415) += clk-exynos4415.o
9 obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
10 obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
11 obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
12 obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
13 obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos5433.o
14 obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
[all …]
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| D | clk.c | 63 struct clk **clk_table; in samsung_clk_init()
70 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); in samsung_clk_init()
96 void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, in samsung_clk_add_lookup() argument
100 ctx->clk_data.clks[id] = clk; in samsung_clk_add_lookup()
108 struct clk *clk; in samsung_clk_register_alias() local
123 clk = ctx->clk_data.clks[list->id]; in samsung_clk_register_alias()
124 if (!clk) { in samsung_clk_register_alias()
130 ret = clk_register_clkdev(clk, list->alias, list->dev_name); in samsung_clk_register_alias()
142 struct clk *clk; in samsung_clk_register_fixed_rate() local
146 clk = clk_register_fixed_rate(NULL, list->name, in samsung_clk_register_fixed_rate()
[all …]
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| /linux-4.4.14/drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 48 struct iproc_asiu_clk *clk = to_asiu_clk(hw); in iproc_asiu_clk_enable() local
49 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_enable()
53 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) in iproc_asiu_clk_enable()
56 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
57 val |= (1 << clk->gate.en_shift); in iproc_asiu_clk_enable()
58 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
65 struct iproc_asiu_clk *clk = to_asiu_clk(hw); in iproc_asiu_clk_disable() local
66 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_disable()
70 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) in iproc_asiu_clk_disable()
73 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_disable()
[all …]
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| D | Makefile | 1 obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
2 obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
3 obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
4 obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
5 obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
6 obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
7 obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.o
8 obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
9 obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o
10 obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o
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| /linux-4.4.14/Documentation/devicetree/bindings/clock/st/ |
| D | st,flexgen.txt | 74 clk_s_c0_flexgen: clk-s-c0-flexgen {
87 clock-output-names = "clk-icn-gpu",
88 "clk-fdma",
89 "clk-nand",
90 "clk-hva",
91 "clk-proc-stfe",
92 "clk-proc-tp",
93 "clk-rx-icn-dmu",
94 "clk-rx-icn-hva",
95 "clk-icn-cpu",
[all …]
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| D | st,clkgen-vcc.txt | 45 clock-output-names = "clk-s-pix-hdmi",
46 "clk-s-pix-dvo",
47 "clk-s-out-dvo",
48 "clk-s-pix-hd",
49 "clk-s-hddac",
50 "clk-s-denc",
51 "clk-s-sddac",
52 "clk-s-pix-main",
53 "clk-s-pix-aux",
54 "clk-s-stfe-frc-0",
[all …]
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| /linux-4.4.14/drivers/clk/versatile/ |
| D | clk-realview.c | 52 struct clk *clk; in realview_clk_init() local
55 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); in realview_clk_init()
56 clk_register_clkdev(clk, "apb_pclk", NULL); in realview_clk_init()
59 clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT, in realview_clk_init()
61 clk_register_clkdev(clk, NULL, "dev:uart0"); in realview_clk_init()
62 clk_register_clkdev(clk, NULL, "dev:uart1"); in realview_clk_init()
63 clk_register_clkdev(clk, NULL, "dev:uart2"); in realview_clk_init()
64 clk_register_clkdev(clk, NULL, "fpga:kmi0"); in realview_clk_init()
65 clk_register_clkdev(clk, NULL, "fpga:kmi1"); in realview_clk_init()
66 clk_register_clkdev(clk, NULL, "fpga:mmc0"); in realview_clk_init()
[all …]
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| D | clk-impd1.c | 23 struct clk *pclk;
25 struct clk *vco1clk;
27 struct clk *vco2clk;
28 struct clk *mmciclk;
30 struct clk *uartclk;
32 struct clk *spiclk;
34 struct clk *scclk;
89 struct clk *clk; in integrator_impd1_clk_init() local
90 struct clk *pclk; in integrator_impd1_clk_init()
106 clk = icst_clk_register(NULL, &impd1_icst1_desc, imc->vco1name, NULL, in integrator_impd1_clk_init()
[all …]
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| /linux-4.4.14/drivers/clk/tegra/ |
| D | Makefile | 1 obj-y += clk.o
2 obj-y += clk-audio-sync.o
3 obj-y += clk-dfll.o
4 obj-y += clk-divider.o
5 obj-y += clk-periph.o
6 obj-y += clk-periph-gate.o
7 obj-y += clk-pll.o
8 obj-y += clk-pll-out.o
9 obj-y += clk-super.o
10 obj-y += clk-tegra-audio.o
[all …]
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| D | clk-tegra-super-gen4.c | 57 struct clk *clk; in tegra_sclk_init() local
58 struct clk **dt_clk; in tegra_sclk_init()
63 clk = tegra_clk_register_super_mux("sclk", sclk_parents, in tegra_sclk_init()
68 *dt_clk = clk; in tegra_sclk_init()
74 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, in tegra_sclk_init()
77 clk = clk_register_gate(NULL, "hclk", "hclk_div", in tegra_sclk_init()
81 *dt_clk = clk; in tegra_sclk_init()
89 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, in tegra_sclk_init()
92 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | in tegra_sclk_init()
95 *dt_clk = clk; in tegra_sclk_init()
[all …]
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| D | clk-tegra-fixed.c | 37 struct clk *clk, *osc; in tegra_osc_clk_init() local
38 struct clk **dt_clk; in tegra_osc_clk_init()
62 clk = clk_register_fixed_factor(NULL, "clk_m", "osc", in tegra_osc_clk_init()
64 *dt_clk = clk; in tegra_osc_clk_init()
73 clk = clk_register_fixed_factor(NULL, "pll_ref", "osc", in tegra_osc_clk_init()
75 *dt_clk = clk; in tegra_osc_clk_init()
85 struct clk *clk; in tegra_fixed_clk_init() local
86 struct clk **dt_clk; in tegra_fixed_clk_init()
91 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, in tegra_fixed_clk_init()
93 *dt_clk = clk; in tegra_fixed_clk_init()
[all …]
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| D | clk-tegra20.c | 166 static struct clk **clks;
637 struct clk *clk; in tegra20_pll_init() local
640 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
642 clks[TEGRA20_CLK_PLL_C] = clk; in tegra20_pll_init()
645 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", in tegra20_pll_init()
648 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", in tegra20_pll_init()
651 clks[TEGRA20_CLK_PLL_C_OUT1] = clk; in tegra20_pll_init()
654 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
657 clks[TEGRA20_CLK_PLL_M] = clk; in tegra20_pll_init()
660 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", in tegra20_pll_init()
[all …]
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| D | clk.c | 78 static struct clk **clks;
197 struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) in tegra_clk_init()
211 clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL); in tegra_clk_init()
221 struct clk *clks[], int clk_max) in tegra_init_dup_clks()
223 struct clk *clk; in tegra_init_dup_clks() local
226 clk = clks[dup_list->clk_id]; in tegra_init_dup_clks()
227 dup_list->lookup.clk = clk; in tegra_init_dup_clks()
233 struct clk *clks[], int clk_max) in tegra_init_from_table()
235 struct clk *clk; in tegra_init_from_table() local
238 clk = clks[tbl->clk_id]; in tegra_init_from_table()
[all …]
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| D | clk-tegra-audio.c | 131 struct clk *clk; in tegra_audio_clk_init() local
132 struct clk **dt_clk; in tegra_audio_clk_init()
146 clk = tegra_clk_register_pll(info->name, info->parent, in tegra_audio_clk_init()
149 *dt_clk = clk; in tegra_audio_clk_init()
156 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", in tegra_audio_clk_init()
159 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", in tegra_audio_clk_init()
162 *dt_clk = clk; in tegra_audio_clk_init()
174 clk = tegra_clk_register_sync_source(data->name, in tegra_audio_clk_init()
176 *dt_clk = clk; in tegra_audio_clk_init()
187 clk = clk_register_mux(NULL, data->mux_name, mux_audio_sync_clk, in tegra_audio_clk_init()
[all …]
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| D | clk-tegra-pmc.c | 84 struct clk *clk; in tegra_pmc_clk_init() local
85 struct clk **dt_clk; in tegra_pmc_clk_init()
97 clk = clk_register_mux(NULL, data->mux_name, data->parents, in tegra_pmc_clk_init()
101 *dt_clk = clk; in tegra_pmc_clk_init()
108 clk = clk_register_gate(NULL, data->gate_name, data->mux_name, in tegra_pmc_clk_init()
111 *dt_clk = clk; in tegra_pmc_clk_init()
112 clk_register_clkdev(clk, data->dev_name, data->gate_name); in tegra_pmc_clk_init()
117 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, in tegra_pmc_clk_init()
125 clk = clk_register_gate(NULL, "blink", "blink_override", 0, in tegra_pmc_clk_init()
128 clk_register_clkdev(clk, "blink", NULL); in tegra_pmc_clk_init()
[all …]
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| /linux-4.4.14/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7780.c | 25 static void master_clk_init(struct clk *clk) in master_clk_init() argument
27 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; in master_clk_init()
34 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
37 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
44 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
47 return clk->parent->rate / bfc_divisors[idx]; in bus_clk_recalc()
54 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
57 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
77 static unsigned long shyway_clk_recalc(struct clk *clk) in shyway_clk_recalc() argument
80 return clk->parent->rate / cfc_divisors[idx]; in shyway_clk_recalc()
[all …]
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| D | clock-sh7763.c | 25 static void master_clk_init(struct clk *clk) in master_clk_init() argument
27 clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; in master_clk_init()
34 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
37 return clk->parent->rate / p0fc_divisors[idx]; in module_clk_recalc()
44 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
47 return clk->parent->rate / bfc_divisors[idx]; in bus_clk_recalc()
71 static unsigned long shyway_clk_recalc(struct clk *clk) in shyway_clk_recalc() argument
74 return clk->parent->rate / cfc_divisors[idx]; in shyway_clk_recalc()
81 static struct clk sh7763_shyway_clk = {
90 static struct clk *sh7763_onchip_clocks[] = {
[all …]
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| D | clock-sh7770.c | 22 static void master_clk_init(struct clk *clk) in master_clk_init() argument
24 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; in master_clk_init()
31 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
34 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
41 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
44 return clk->parent->rate / bfc_divisors[idx]; in bus_clk_recalc()
51 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
54 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
|
| /linux-4.4.14/arch/arm/mach-w90x900/ |
| D | clock.c | 32 int clk_enable(struct clk *clk) in clk_enable() argument
37 if (clk->enabled++ == 0) in clk_enable()
38 (clk->enable)(clk, 1); in clk_enable()
45 void clk_disable(struct clk *clk) in clk_disable() argument
49 WARN_ON(clk->enabled == 0); in clk_disable()
52 if (--clk->enabled == 0) in clk_disable()
53 (clk->enable)(clk, 0); in clk_disable()
58 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
64 void nuc900_clk_enable(struct clk *clk, int enable) in nuc900_clk_enable() argument
66 unsigned int clocks = clk->cken; in nuc900_clk_enable()
[all …]
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| D | clock.h | 15 void nuc900_clk_enable(struct clk *clk, int enable);
16 void nuc900_subclk_enable(struct clk *clk, int enable);
18 struct clk { struct
21 void (*enable)(struct clk *, int enable); argument
25 struct clk clk_##_name = { \
31 struct clk clk_##_name = { \
39 .clk = _clk, \
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| /linux-4.4.14/arch/arm/mach-omap2/ |
| D | omap_hwmod_33xx_43xx_interconnect_data.c | 25 .clk = "dpll_mpu_m2_ck",
33 .clk = "l3s_gclk",
41 .clk = "l3s_gclk",
49 .clk = "l3s_gclk",
57 .clk = "l3s_gclk",
65 .clk = "dpll_mpu_m2_ck",
73 .clk = "l3s_gclk",
81 .clk = "l3_gclk",
89 .clk = "dpll_core_m4_ck",
97 .clk = "dpll_core_m4_ck",
[all …]
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| D | omap_hwmod_2xxx_interconnect_data.c | 65 .clk = "uart1_ick",
73 .clk = "uart2_ick",
81 .clk = "uart3_ick",
89 .clk = "mcspi1_ick",
97 .clk = "mcspi2_ick",
105 .clk = "gpt2_ick",
113 .clk = "gpt3_ick",
121 .clk = "gpt4_ick",
129 .clk = "gpt5_ick",
137 .clk = "gpt6_ick",
[all …]
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| D | omap_hwmod_43xx_data.c | 93 { .role = "dbclk", .clk = "gpio0_dbclk" },
295 { .role = "dbclk", .clk = "gpio4_dbclk" },
316 { .role = "dbclk", .clk = "gpio5_dbclk" },
603 .clk = "dpll_core_m4_ck",
610 .clk = "l3s_gclk",
617 .clk = "sys_clkin_ck",
624 .clk = "sys_clkin_ck",
631 .clk = "dpll_core_m4_ck",
638 .clk = "sys_clkin_ck",
645 .clk = "sys_clkin_ck",
[all …]
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| D | omap_hwmod_44xx_data.c | 578 { .role = "sys_clk", .clk = "dss_sys_clk" },
579 { .role = "tv_clk", .clk = "dss_tv_clk" },
580 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
690 { .role = "sys_clk", .clk = "dss_sys_clk" },
724 { .role = "sys_clk", .clk = "dss_sys_clk" },
778 { .role = "sys_clk", .clk = "dss_sys_clk" },
832 { .role = "ick", .clk = "l3_div_ck" },
1031 { .role = "dbclk", .clk = "gpio1_dbclk" },
1053 { .role = "dbclk", .clk = "gpio2_dbclk" },
1076 { .role = "dbclk", .clk = "gpio3_dbclk" },
[all …]
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| D | omap_hwmod_54xx_data.c | 355 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
356 { .role = "sys_clk", .clk = "dss_sys_clk" },
357 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
402 { .role = "sys_clk", .clk = "dss_sys_clk" },
451 { .role = "sys_clk", .clk = "dss_sys_clk" },
472 { .role = "sys_clk", .clk = "dss_sys_clk" },
512 { .role = "sys_clk", .clk = "dss_sys_clk" },
553 { .role = "ick", .clk = "l3_iclk_div" },
648 { .role = "dbclk", .clk = "gpio1_dbclk" },
670 { .role = "dbclk", .clk = "gpio2_dbclk" },
[all …]
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| D | omap_hwmod_7xx_data.c | 456 { .role = "dss_clk", .clk = "dss_dss_clk" },
457 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
458 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
459 { .role = "video2_clk", .clk = "dss_video2_clk" },
460 { .role = "video1_clk", .clk = "dss_video1_clk" },
461 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
462 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
551 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
638 { .role = "dbclk", .clk = "gpio1_dbclk" },
660 { .role = "dbclk", .clk = "gpio2_dbclk" },
[all …]
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| /linux-4.4.14/drivers/gpu/drm/armada/ |
| D | armada_510.c | 20 struct clk *clk; in armada510_crtc_init() local
22 clk = devm_clk_get(dev, "ext_ref_clk1"); in armada510_crtc_init()
23 if (IS_ERR(clk)) in armada510_crtc_init()
24 return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk); in armada510_crtc_init()
26 dcrtc->extclk[0] = clk; in armada510_crtc_init()
47 struct clk *clk = dcrtc->extclk[0]; in armada510_crtc_compute_clock() local
53 if (IS_ERR(clk)) in armada510_crtc_compute_clock()
54 return PTR_ERR(clk); in armada510_crtc_compute_clock()
56 if (dcrtc->clk != clk) { in armada510_crtc_compute_clock()
57 ret = clk_prepare_enable(clk); in armada510_crtc_compute_clock()
[all …]
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| /linux-4.4.14/drivers/clk/hisilicon/ |
| D | clk.c | 44 struct clk **clk_table; in hisi_clk_init()
60 clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); in hisi_clk_init()
78 struct clk *clk; in hisi_clk_register_fixed_rate() local
82 clk = clk_register_fixed_rate(NULL, clks[i].name, in hisi_clk_register_fixed_rate()
86 if (IS_ERR(clk)) { in hisi_clk_register_fixed_rate()
91 data->clk_data.clks[clks[i].id] = clk; in hisi_clk_register_fixed_rate()
99 struct clk *clk; in hisi_clk_register_fixed_factor() local
103 clk = clk_register_fixed_factor(NULL, clks[i].name, in hisi_clk_register_fixed_factor()
107 if (IS_ERR(clk)) { in hisi_clk_register_fixed_factor()
112 data->clk_data.clks[clks[i].id] = clk; in hisi_clk_register_fixed_factor()
[all …]
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| D | clk-hix5hd2.c | 174 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); in clk_ether_prepare() local
177 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()
178 val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask; in clk_ether_prepare()
179 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
180 val &= ~(clk->ctrl_rst_mask); in clk_ether_prepare()
181 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
183 val = readl_relaxed(clk->phy_reg); in clk_ether_prepare()
184 val |= clk->phy_clk_mask; in clk_ether_prepare()
185 val &= ~(clk->phy_rst_mask); in clk_ether_prepare()
186 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare()
[all …]
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| /linux-4.4.14/Documentation/devicetree/bindings/clock/ |
| D | sunxi.txt | 9 "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13 "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
14 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
15 "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
16 "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
17 "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
18 "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
[all …]
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| D | at91-clock.txt | 13 "atmel,at91sam9x5-clk-slow-osc":
16 "atmel,at91sam9x5-clk-slow-rc-osc":
28 "atmel,at91sam9x5-clk-slow" (under sckc node)
30 "atmel,at91sam9260-clk-slow" (under pmc node):
31 at91 slow clk
33 "atmel,at91rm9200-clk-main-osc"
34 "atmel,at91sam9x5-clk-main-rc-osc"
35 at91 main clk sources
37 "atmel,at91sam9x5-clk-main"
38 "atmel,at91rm9200-clk-main":
[all …]
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| /linux-4.4.14/drivers/clk/sunxi/ |
| D | Makefile | 5 obj-y += clk-sunxi.o clk-factors.o
6 obj-y += clk-a10-codec.o
7 obj-y += clk-a10-hosc.o
8 obj-y += clk-a10-mod1.o
9 obj-y += clk-a10-pll2.o
10 obj-y += clk-a20-gmac.o
11 obj-y += clk-mod0.o
12 obj-y += clk-simple-gates.o
13 obj-y += clk-sun8i-mbus.o
14 obj-y += clk-sun9i-core.o
[all …]
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| /linux-4.4.14/drivers/clk/sirf/ |
| D | clk-atlas7.c | 357 struct clk_pll *clk = to_pllclk(hw); in pll_clk_recalc_rate() local
359 u32 regctrl0 = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_CTRL0 - in pll_clk_recalc_rate()
361 u32 regfreq = clkc_readl(clk->regofs); in pll_clk_recalc_rate()
362 u32 regssc = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_SSC - in pll_clk_recalc_rate()
489 struct clk_dto *clk = to_dtoclk(hw); in dto_clk_is_enabled() local
492 reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; in dto_clk_is_enabled()
500 struct clk_dto *clk = to_dtoclk(hw); in dto_clk_enable() local
502 reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; in dto_clk_enable()
512 struct clk_dto *clk = to_dtoclk(hw); in dto_clk_disable() local
514 reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; in dto_clk_disable()
[all …]
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| D | clk-common.c | 78 struct clk_pll *clk = to_pllclk(hw); in pll_clk_recalc_rate() local
79 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - in pll_clk_recalc_rate()
87 u32 cfg0 = clkc_readl(clk->regofs); in pll_clk_recalc_rate()
130 struct clk_pll *clk = to_pllclk(hw); in pll_clk_set_rate() local
151 clkc_writel(reg, clk->regofs); in pll_clk_set_rate()
153 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; in pll_clk_set_rate()
156 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; in pll_clk_set_rate()
255 static void usb_pll_clk_disable(struct clk_hw *clk) in usb_pll_clk_disable() argument
299 struct clk_dmn *clk = to_dmnclk(hw); in dmn_clk_get_parent() local
300 u32 cfg = clkc_readl(clk->regofs); in dmn_clk_get_parent()
[all …]
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| /linux-4.4.14/drivers/cpufreq/ |
| D | ls1x-cpufreq.c | 25 struct clk *clk; /* CPU clk */ member
26 struct clk *mux_clk; /* MUX of CPU clk */
27 struct clk *pll_clk; /* PLL clk */
28 struct clk *osc_clk; /* OSC clk */
64 clk_set_parent(policy->clk, ls1x_cpufreq.osc_clk); in ls1x_cpufreq_target()
70 clk_set_parent(policy->clk, ls1x_cpufreq.mux_clk); in ls1x_cpufreq_target()
105 policy->clk = ls1x_cpufreq.clk; in ls1x_cpufreq_init()
142 struct clk *clk; in ls1x_cpufreq_probe() local
150 clk = devm_clk_get(&pdev->dev, pdata->clk_name); in ls1x_cpufreq_probe()
151 if (IS_ERR(clk)) { in ls1x_cpufreq_probe()
[all …]
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| D | spear-cpufreq.c | 28 struct clk *clk; member
34 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq) in spear1340_cpu_get_possible_parent()
36 struct clk *sys_pclk; in spear1340_cpu_get_possible_parent()
76 static int spear1340_set_cpu_rate(struct clk *sys_pclk, unsigned long newfreq) in spear1340_set_cpu_rate()
78 struct clk *sys_clk; in spear1340_set_cpu_rate()
81 sys_clk = clk_get_parent(spear_cpufreq.clk); in spear1340_set_cpu_rate()
107 struct clk *srcclk; in spear_cpufreq_target()
133 srcclk = spear_cpufreq.clk; in spear_cpufreq_target()
145 ret = clk_set_rate(spear_cpufreq.clk, newfreq); in spear_cpufreq_target()
155 policy->clk = spear_cpufreq.clk; in spear_cpufreq_init()
[all …]
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| /linux-4.4.14/drivers/clk/qcom/ |
| D | Makefile | 1 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
3 clk-qcom-y += common.o
4 clk-qcom-y += clk-regmap.o
5 clk-qcom-y += clk-pll.o
6 clk-qcom-y += clk-rcg.o
7 clk-qcom-y += clk-rcg2.o
8 clk-qcom-y += clk-branch.o
9 clk-qcom-y += clk-regmap-divider.o
10 clk-qcom-y += clk-regmap-mux.o
11 clk-qcom-y += reset.o
[all …]
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| /linux-4.4.14/drivers/clk/meson/ |
| D | clkc.c | 26 static struct clk **clks;
29 struct clk ** __init meson_clk_init(struct device_node *np, in meson_clk_init()
43 static void meson_clk_add_lookup(struct clk *clk, unsigned int id) in meson_clk_add_lookup() argument
46 clks[id] = clk; in meson_clk_add_lookup()
49 static struct clk * __init
53 struct clk *clk; in meson_clk_register_composite() local
81 clk = ERR_PTR(-ENOMEM); in meson_clk_register_composite()
97 clk = ERR_PTR(-ENOMEM); in meson_clk_register_composite()
108 clk = clk_register_composite(NULL, clk_conf->clk_name, in meson_clk_register_composite()
115 if (IS_ERR(clk)) in meson_clk_register_composite()
[all …]
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| /linux-4.4.14/arch/c6x/include/asm/ |
| D | clock.h | 82 struct clk { struct
89 struct clk *parent; argument
94 unsigned long (*recalc) (struct clk *); argument
95 int (*set_rate) (struct clk *clk, unsigned long rate); argument
96 int (*round_rate) (struct clk *clk, unsigned long rate); argument
116 struct clk sysclks[MAX_PLL_SYSCLKS + 1];
128 .clk = ck, \
132 extern int clk_register(struct clk *clk);
133 extern void clk_unregister(struct clk *clk);
138 extern struct clk clkin1;
[all …]
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| /linux-4.4.14/drivers/clk/zynq/ |
| D | pll.c | 86 struct zynq_pll *clk = to_zynq_pll(hw); in zynq_pll_recalc_rate() local
93 fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> in zynq_pll_recalc_rate()
111 struct zynq_pll *clk = to_zynq_pll(hw); in zynq_pll_is_enabled() local
113 spin_lock_irqsave(clk->lock, flags); in zynq_pll_is_enabled()
115 reg = clk_readl(clk->pll_ctrl); in zynq_pll_is_enabled()
117 spin_unlock_irqrestore(clk->lock, flags); in zynq_pll_is_enabled()
131 struct zynq_pll *clk = to_zynq_pll(hw); in zynq_pll_enable() local
139 spin_lock_irqsave(clk->lock, flags); in zynq_pll_enable()
141 reg = clk_readl(clk->pll_ctrl); in zynq_pll_enable()
143 clk_writel(reg, clk->pll_ctrl); in zynq_pll_enable()
[all …]
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| /linux-4.4.14/drivers/clocksource/ |
| D | timer-sp804.c | 37 static long __init sp804_get_clock_rate(struct clk *clk) in sp804_get_clock_rate() argument
42 err = clk_prepare(clk); in sp804_get_clock_rate()
45 clk_put(clk); in sp804_get_clock_rate()
49 err = clk_enable(clk); in sp804_get_clock_rate()
52 clk_unprepare(clk); in sp804_get_clock_rate()
53 clk_put(clk); in sp804_get_clock_rate()
57 rate = clk_get_rate(clk); in sp804_get_clock_rate()
60 clk_disable(clk); in sp804_get_clock_rate()
61 clk_unprepare(clk); in sp804_get_clock_rate()
62 clk_put(clk); in sp804_get_clock_rate()
[all …]
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| D | clksrc_st_lpc.c | 30 struct clk *clk; member
54 rate = clk_get_rate(ddata.clk); in st_clksrc_init()
71 struct clk *clk; in st_clksrc_setup_clk() local
73 clk = of_clk_get(np, 0); in st_clksrc_setup_clk()
74 if (IS_ERR(clk)) { in st_clksrc_setup_clk()
76 return PTR_ERR(clk); in st_clksrc_setup_clk()
79 if (clk_prepare_enable(clk)) { in st_clksrc_setup_clk()
84 if (!clk_get_rate(clk)) { in st_clksrc_setup_clk()
86 clk_disable_unprepare(clk); in st_clksrc_setup_clk()
90 ddata.clk = clk; in st_clksrc_setup_clk()
[all …]
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| D | arm_arch_timer.c | 80 struct clock_event_device *clk) in arch_timer_reg_write() argument
83 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_write()
93 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_write()
109 struct clock_event_device *clk) in arch_timer_reg_read() argument
114 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_read()
124 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_read()
185 struct clock_event_device *clk) in timer_shutdown() argument
189 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); in timer_shutdown()
191 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); in timer_shutdown()
196 static int arch_timer_shutdown_virt(struct clock_event_device *clk) in arch_timer_shutdown_virt() argument
[all …]
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| D | time-lpc32xx.c | 123 struct clk *clk; in lpc32xx_clocksource_init() local
126 clk = of_clk_get_by_name(np, "timerclk"); in lpc32xx_clocksource_init()
127 if (IS_ERR(clk)) { in lpc32xx_clocksource_init()
128 pr_err("clock get failed (%lu)\n", PTR_ERR(clk)); in lpc32xx_clocksource_init()
129 return PTR_ERR(clk); in lpc32xx_clocksource_init()
132 ret = clk_prepare_enable(clk); in lpc32xx_clocksource_init()
156 rate = clk_get_rate(clk); in lpc32xx_clocksource_init()
172 clk_disable_unprepare(clk); in lpc32xx_clocksource_init()
174 clk_put(clk); in lpc32xx_clocksource_init()
182 struct clk *clk; in lpc32xx_clockevent_init() local
[all …]
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| D | metag_generic.c | 96 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); in arch_timer_setup() local
107 clk->name = name; in arch_timer_setup()
108 clk->features = CLOCK_EVT_FEAT_ONESHOT, in arch_timer_setup()
110 clk->rating = 200, in arch_timer_setup()
111 clk->shift = 12, in arch_timer_setup()
112 clk->irq = tbisig_map(TBID_SIGNUM_TRT), in arch_timer_setup()
113 clk->set_next_event = metag_timer_set_next_event, in arch_timer_setup()
115 clk->mult = div_sc(hwtimer_freq, NSEC_PER_SEC, clk->shift); in arch_timer_setup()
116 clk->max_delta_ns = clockevent_delta2ns(0x7fffffff, clk); in arch_timer_setup()
117 clk->min_delta_ns = clockevent_delta2ns(0xf, clk); in arch_timer_setup()
[all …]
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| D | timer-sun5i.c | 42 struct clk *clk; member
187 struct clk *clk, int irq) in sun5i_setup_clocksource() argument
197 ret = clk_prepare_enable(clk); in sun5i_setup_clocksource()
203 rate = clk_get_rate(clk); in sun5i_setup_clocksource()
206 cs->timer.clk = clk; in sun5i_setup_clocksource()
210 ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb); in sun5i_setup_clocksource()
235 clk_notifier_unregister(clk, &cs->timer.clk_rate_cb); in sun5i_setup_clocksource()
237 clk_disable_unprepare(clk); in sun5i_setup_clocksource()
259 struct clk *clk, int irq) in sun5i_setup_clockevent() argument
270 ret = clk_prepare_enable(clk); in sun5i_setup_clockevent()
[all …]
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| D | time-armada-370-xp.c | 334 struct clk *clk = of_clk_get_by_name(np, "fixed"); in armada_xp_timer_init() local
337 BUG_ON(IS_ERR(clk)); in armada_xp_timer_init()
338 clk_prepare_enable(clk); in armada_xp_timer_init()
339 timer_clk = clk_get_rate(clk); in armada_xp_timer_init()
348 struct clk *clk; in armada_375_timer_init() local
350 clk = of_clk_get_by_name(np, "fixed"); in armada_375_timer_init()
351 if (!IS_ERR(clk)) { in armada_375_timer_init()
352 clk_prepare_enable(clk); in armada_375_timer_init()
353 timer_clk = clk_get_rate(clk); in armada_375_timer_init()
360 clk = of_clk_get(np, 0); in armada_375_timer_init()
[all …]
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| /linux-4.4.14/drivers/clk/at91/ |
| D | clk-slow.c | 75 static struct clk *slow_clk;
123 static struct clk * __init
131 struct clk *clk = NULL; in at91_clk_register_slow_osc() local
155 clk = clk_register(NULL, &osc->hw); in at91_clk_register_slow_osc()
156 if (IS_ERR(clk)) in at91_clk_register_slow_osc()
159 return clk; in at91_clk_register_slow_osc()
165 struct clk *clk; in of_at91sam9x5_clk_slow_osc_setup() local
176 clk = at91_clk_register_slow_osc(sckcr, name, parent_name, startup, in of_at91sam9x5_clk_slow_osc_setup()
178 if (IS_ERR(clk)) in of_at91sam9x5_clk_slow_osc_setup()
181 of_clk_add_provider(np, of_clk_src_simple_get, clk); in of_at91sam9x5_clk_slow_osc_setup()
[all …]
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| D | Makefile | 6 obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o
7 obj-y += clk-system.o clk-peripheral.o clk-programmable.o
9 obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
10 obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
11 obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
12 obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
13 obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o
|
| D | clk-usb.c | 199 static struct clk * __init
204 struct clk *clk = NULL; in at91sam9x5_clk_register_usb() local
221 clk = clk_register(NULL, &usb->hw); in at91sam9x5_clk_register_usb()
222 if (IS_ERR(clk)) in at91sam9x5_clk_register_usb()
225 return clk; in at91sam9x5_clk_register_usb()
228 static struct clk * __init
233 struct clk *clk = NULL; in at91sam9n12_clk_register_usb() local
249 clk = clk_register(NULL, &usb->hw); in at91sam9n12_clk_register_usb()
250 if (IS_ERR(clk)) in at91sam9n12_clk_register_usb()
253 return clk; in at91sam9n12_clk_register_usb()
[all …]
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| D | clk-main.c | 141 static struct clk * __init
150 struct clk *clk = NULL; in at91_clk_register_main_osc() local
185 clk = clk_register(NULL, &osc->hw); in at91_clk_register_main_osc()
186 if (IS_ERR(clk)) { in at91_clk_register_main_osc()
191 return clk; in at91_clk_register_main_osc()
197 struct clk *clk; in of_at91rm9200_clk_main_osc_setup() local
211 clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass); in of_at91rm9200_clk_main_osc_setup()
212 if (IS_ERR(clk)) in of_at91rm9200_clk_main_osc_setup()
215 of_clk_add_provider(np, of_clk_src_simple_get, clk); in of_at91rm9200_clk_main_osc_setup()
296 static struct clk * __init
[all …]
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| /linux-4.4.14/drivers/clk/mediatek/ |
| D | clk-mtk.c | 56 struct clk *clk; in mtk_clk_register_fixed_clks() local
61 clk = clk_register_fixed_rate(NULL, rc->name, rc->parent, in mtk_clk_register_fixed_clks()
64 if (IS_ERR(clk)) { in mtk_clk_register_fixed_clks()
66 rc->name, PTR_ERR(clk)); in mtk_clk_register_fixed_clks()
71 clk_data->clks[rc->id] = clk; in mtk_clk_register_fixed_clks()
79 struct clk *clk; in mtk_clk_register_factors() local
84 clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name, in mtk_clk_register_factors()
87 if (IS_ERR(clk)) { in mtk_clk_register_factors()
89 ff->name, PTR_ERR(clk)); in mtk_clk_register_factors()
94 clk_data->clks[ff->id] = clk; in mtk_clk_register_factors()
[all …]
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| /linux-4.4.14/drivers/clk/rockchip/ |
| D | clk.c | 41 static struct clk *rockchip_clk_register_branch(const char *name, in rockchip_clk_register_branch()
49 struct clk *clk; in rockchip_clk_register_branch() local
98 clk = clk_register_composite(NULL, name, parent_names, num_parents, in rockchip_clk_register_branch()
104 return clk; in rockchip_clk_register_branch()
112 static struct clk *rockchip_clk_register_frac_branch(const char *name, in rockchip_clk_register_frac_branch()
118 struct clk *clk; in rockchip_clk_register_frac_branch() local
153 clk = clk_register_composite(NULL, name, parent_names, num_parents, in rockchip_clk_register_frac_branch()
159 return clk; in rockchip_clk_register_frac_branch()
163 static struct clk **clk_table;
176 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); in rockchip_clk_init()
[all …]
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| D | Makefile | 5 obj-y += clk-rockchip.o
6 obj-y += clk.o
7 obj-y += clk-pll.o
8 obj-y += clk-cpu.o
9 obj-y += clk-inverter.o
10 obj-y += clk-mmc-phase.o
13 obj-y += clk-rk3188.o
14 obj-y += clk-rk3288.o
15 obj-y += clk-rk3368.o
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| /linux-4.4.14/drivers/rtc/ |
| D | rtc-coh901331.c | 45 struct clk *clk; member
57 clk_enable(rtap->clk); in coh901331_interrupt()
68 clk_disable(rtap->clk); in coh901331_interrupt()
80 clk_enable(rtap->clk); in coh901331_read_time()
84 clk_disable(rtap->clk); in coh901331_read_time()
87 clk_disable(rtap->clk); in coh901331_read_time()
95 clk_enable(rtap->clk); in coh901331_set_mmss()
97 clk_disable(rtap->clk); in coh901331_set_mmss()
106 clk_enable(rtap->clk); in coh901331_read_alarm()
110 clk_disable(rtap->clk); in coh901331_read_alarm()
[all …]
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| /linux-4.4.14/drivers/clk/pistachio/ |
| D | clk.c | 27 p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL); in pistachio_clk_alloc_provider()
64 struct clk *clk; in pistachio_clk_register_gate() local
68 clk = clk_register_gate(NULL, gate[i].name, gate[i].parent, in pistachio_clk_register_gate()
72 p->clk_data.clks[gate[i].id] = clk; in pistachio_clk_register_gate()
80 struct clk *clk; in pistachio_clk_register_mux() local
84 clk = clk_register_mux(NULL, mux[i].name, mux[i].parents, in pistachio_clk_register_mux()
90 p->clk_data.clks[mux[i].id] = clk; in pistachio_clk_register_mux()
98 struct clk *clk; in pistachio_clk_register_div() local
102 clk = clk_register_divider(NULL, div[i].name, div[i].parent, in pistachio_clk_register_div()
106 p->clk_data.clks[div[i].id] = clk; in pistachio_clk_register_div()
[all …]
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| /linux-4.4.14/include/media/ |
| D | v4l2-clk.h | 25 struct clk;
33 struct clk *clk; member
39 int (*enable)(struct v4l2_clk *clk);
40 void (*disable)(struct v4l2_clk *clk);
41 unsigned long (*get_rate)(struct v4l2_clk *clk);
42 int (*set_rate)(struct v4l2_clk *clk, unsigned long);
48 void v4l2_clk_unregister(struct v4l2_clk *clk);
50 void v4l2_clk_put(struct v4l2_clk *clk);
51 int v4l2_clk_enable(struct v4l2_clk *clk);
52 void v4l2_clk_disable(struct v4l2_clk *clk);
[all …]
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| /linux-4.4.14/drivers/clk/shmobile/ |
| D | Makefile | 1 obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
2 obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
3 obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o
4 obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o
5 obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
6 obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
7 obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
8 obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
9 obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o
10 obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o
[all …]
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| D | clk-rcar-gen2.c | 138 static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) in cpg_z_clk_register()
143 struct clk *clk; in cpg_z_clk_register() local
159 clk = clk_register(NULL, &zclk->hw); in cpg_z_clk_register()
160 if (IS_ERR(clk)) in cpg_z_clk_register()
163 return clk; in cpg_z_clk_register()
166 static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg, in cpg_rcan_clk_register()
172 struct clk *clk; in cpg_rcan_clk_register() local
192 clk = clk_register_composite(NULL, "rcan", &parent_name, 1, NULL, NULL, in cpg_rcan_clk_register()
195 if (IS_ERR(clk)) { in cpg_rcan_clk_register()
200 return clk; in cpg_rcan_clk_register()
[all …]
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| D | clk-emev2.c | 80 struct clk *clk; in emev2_smu_clkdiv_init() local
86 clk = clk_register_divider(NULL, np->name, parent_name, 0, in emev2_smu_clkdiv_init()
88 of_clk_add_provider(np, of_clk_src_simple_get, clk); in emev2_smu_clkdiv_init()
89 clk_register_clkdev(clk, np->name, NULL); in emev2_smu_clkdiv_init()
90 pr_debug("## %s %s %p\n", __func__, np->name, clk); in emev2_smu_clkdiv_init()
98 struct clk *clk; in emev2_smu_gclk_init() local
104 clk = clk_register_gate(NULL, np->name, parent_name, 0, in emev2_smu_gclk_init()
106 of_clk_add_provider(np, of_clk_src_simple_get, clk); in emev2_smu_gclk_init()
107 clk_register_clkdev(clk, np->name, NULL); in emev2_smu_gclk_init()
108 pr_debug("## %s %s %p\n", __func__, np->name, clk); in emev2_smu_gclk_init()
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| /linux-4.4.14/drivers/base/power/ |
| D | clock_ops.c | 32 struct clk *clk; member
46 ret = clk_enable(ce->clk); in __pm_clk_enable()
51 __func__, ce->clk, ret); in __pm_clk_enable()
62 if (!ce->clk) in pm_clk_acquire()
63 ce->clk = clk_get(dev, ce->con_id); in pm_clk_acquire()
64 if (IS_ERR(ce->clk)) { in pm_clk_acquire()
67 clk_prepare(ce->clk); in pm_clk_acquire()
70 ce->clk, ce->con_id); in pm_clk_acquire()
75 struct clk *clk) in __pm_clk_add() argument
96 if (IS_ERR(clk)) { in __pm_clk_add()
[all …]
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| /linux-4.4.14/drivers/usb/host/ |
| D | ohci-st.c | 34 struct clk *clks[USB_MAX_CLKS];
35 struct clk *clk48;
52 int clk, ret; in st_ohci_platform_power_on() local
70 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { in st_ohci_platform_power_on()
71 ret = clk_prepare_enable(priv->clks[clk]); in st_ohci_platform_power_on()
89 while (--clk >= 0) in st_ohci_platform_power_on()
90 clk_disable_unprepare(priv->clks[clk]); in st_ohci_platform_power_on()
104 int clk; in st_ohci_platform_power_off() local
114 for (clk = USB_MAX_CLKS - 1; clk >= 0; clk--) in st_ohci_platform_power_off()
115 if (priv->clks[clk]) in st_ohci_platform_power_off()
[all …]
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| D | ehci-st.c | 35 struct clk *clks[USB_MAX_CLKS];
36 struct clk *clk48;
71 int clk, ret; in st_ehci_platform_power_on() local
89 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { in st_ehci_platform_power_on()
90 ret = clk_prepare_enable(priv->clks[clk]); in st_ehci_platform_power_on()
108 while (--clk >= 0) in st_ehci_platform_power_on()
109 clk_disable_unprepare(priv->clks[clk]); in st_ehci_platform_power_on()
122 int clk; in st_ehci_platform_power_off() local
132 for (clk = USB_MAX_CLKS - 1; clk >= 0; clk--) in st_ehci_platform_power_off()
133 if (priv->clks[clk]) in st_ehci_platform_power_off()
[all …]
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| D | ohci-platform.c | 39 struct clk *clks[OHCI_MAX_CLKS];
51 int clk, ret, phy_num; in ohci_platform_power_on() local
53 for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++) { in ohci_platform_power_on()
54 ret = clk_prepare_enable(priv->clks[clk]); in ohci_platform_power_on()
78 while (--clk >= 0) in ohci_platform_power_on()
79 clk_disable_unprepare(priv->clks[clk]); in ohci_platform_power_on()
88 int clk, phy_num; in ohci_platform_power_off() local
95 for (clk = OHCI_MAX_CLKS - 1; clk >= 0; clk--) in ohci_platform_power_off()
96 if (priv->clks[clk]) in ohci_platform_power_off()
97 clk_disable_unprepare(priv->clks[clk]); in ohci_platform_power_off()
[all …]
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| D | ehci-platform.c | 45 struct clk *clks[EHCI_MAX_CLKS];
83 int clk, ret, phy_num; in ehci_platform_power_on() local
85 for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) { in ehci_platform_power_on()
86 ret = clk_prepare_enable(priv->clks[clk]); in ehci_platform_power_on()
110 while (--clk >= 0) in ehci_platform_power_on()
111 clk_disable_unprepare(priv->clks[clk]); in ehci_platform_power_on()
120 int clk, phy_num; in ehci_platform_power_off() local
127 for (clk = EHCI_MAX_CLKS - 1; clk >= 0; clk--) in ehci_platform_power_off()
128 if (priv->clks[clk]) in ehci_platform_power_off()
129 clk_disable_unprepare(priv->clks[clk]); in ehci_platform_power_off()
[all …]
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| /linux-4.4.14/arch/blackfin/mach-common/ |
| D | clock.h | 7 unsigned long (*get_rate)(struct clk *clk);
8 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
9 int (*set_rate)(struct clk *clk, unsigned long rate);
10 int (*enable)(struct clk *clk);
11 int (*disable)(struct clk *clk);
14 struct clk { struct
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| /linux-4.4.14/arch/sh/kernel/ |
| D | localtimer.c | 35 struct clock_event_device *clk = this_cpu_ptr(&local_clockevent); in local_timer_interrupt() local
38 clk->event_handler(clk); in local_timer_interrupt()
44 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); in local_timer_setup() local
46 clk->name = "dummy_timer"; in local_timer_setup()
47 clk->features = CLOCK_EVT_FEAT_ONESHOT | in local_timer_setup()
50 clk->rating = 400; in local_timer_setup()
51 clk->mult = 1; in local_timer_setup()
52 clk->broadcast = smp_timer_broadcast; in local_timer_setup()
53 clk->cpumask = cpumask_of(cpu); in local_timer_setup()
55 clockevents_register_device(clk); in local_timer_setup()
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| /linux-4.4.14/arch/unicore32/kernel/ |
| D | clock.c | 30 struct clk { struct
36 static struct clk clk_ost_clk = { argument
41 static struct clk clk_mclk_clk = {
45 static struct clk clk_bclk32_clk = {
49 static struct clk clk_ddr_clk = {
53 static struct clk clk_vga_clk = {
60 struct clk *clk_get(struct device *dev, const char *id) in clk_get()
62 struct clk *p, *clk = ERR_PTR(-ENOENT); in clk_get() local
67 clk = p; in clk_get()
73 return clk; in clk_get()
[all …]
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| /linux-4.4.14/arch/sh/kernel/cpu/sh3/ |
| D | clock-sh7710.c | 27 static void master_clk_init(struct clk *clk) in master_clk_init() argument
29 clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007]; in master_clk_init()
36 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
39 return clk->parent->rate / md_table[idx]; in module_clk_recalc()
46 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
49 return clk->parent->rate / md_table[idx]; in bus_clk_recalc()
56 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
59 return clk->parent->rate / md_table[idx]; in cpu_clk_recalc()
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| D | clock-sh7705.c | 33 static void master_clk_init(struct clk *clk) in master_clk_init() argument
35 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003]; in master_clk_init()
42 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
45 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
52 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
55 return clk->parent->rate / stc_multipliers[idx]; in bus_clk_recalc()
62 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
65 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| D | clock-sh7706.c | 25 static void master_clk_init(struct clk *clk) in master_clk_init() argument
30 clk->rate *= pfc_divisors[idx]; in master_clk_init()
37 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
42 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
49 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
54 return clk->parent->rate / stc_multipliers[idx]; in bus_clk_recalc()
61 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
66 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| D | clock-sh7709.c | 25 static void master_clk_init(struct clk *clk) in master_clk_init() argument
30 clk->rate *= pfc_divisors[idx]; in master_clk_init()
37 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
42 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
49 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
55 return clk->parent->rate * stc_multipliers[idx]; in bus_clk_recalc()
62 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
67 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| D | clock-sh3.c | 29 static void master_clk_init(struct clk *clk) in master_clk_init() argument
34 clk->rate *= pfc_divisors[idx]; in master_clk_init()
41 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
46 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
53 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
58 return clk->parent->rate / stc_multipliers[idx]; in bus_clk_recalc()
65 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
70 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| D | clock-sh7712.c | 24 static void master_clk_init(struct clk *clk) in master_clk_init() argument
29 clk->rate *= multipliers[idx]; in master_clk_init()
36 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
41 return clk->parent->rate / divisors[idx]; in module_clk_recalc()
48 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
53 return clk->parent->rate / divisors[idx]; in cpu_clk_recalc()
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| /linux-4.4.14/arch/blackfin/include/asm/ |
| D | clocks.h | 54 unsigned long (*get_rate)(struct clk *clk);
55 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
56 int (*set_rate)(struct clk *clk, unsigned long rate);
57 int (*enable)(struct clk *clk);
58 int (*disable)(struct clk *clk);
61 struct clk { struct
62 struct clk *parent; argument
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| /linux-4.4.14/arch/sh/kernel/cpu/sh5/ |
| D | clock-sh5.c | 25 static void master_clk_init(struct clk *clk) in master_clk_init() argument
28 clk->rate *= ifc_table[idx]; in master_clk_init()
35 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
38 return clk->parent->rate / ifc_table[idx]; in module_clk_recalc()
45 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
48 return clk->parent->rate / ifc_table[idx]; in bus_clk_recalc()
55 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
58 return clk->parent->rate / ifc_table[idx]; in cpu_clk_recalc()
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| /linux-4.4.14/arch/sh/kernel/cpu/sh2a/ |
| D | clock-sh7206.c | 27 static void master_clk_init(struct clk *clk) in master_clk_init() argument
29 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in master_clk_init()
36 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
39 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
46 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
48 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in bus_clk_recalc()
55 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
58 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| D | clock-sh7201.c | 27 static void master_clk_init(struct clk *clk) in master_clk_init() argument
29 clk->rate = 10000000 * pll2_mult * in master_clk_init()
37 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
40 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
47 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
50 return clk->parent->rate / pfc_divisors[idx]; in bus_clk_recalc()
57 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
60 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| D | clock-sh7269.c | 29 static struct clk r_clk = {
37 static struct clk extal_clk = {
41 static unsigned long pll_recalc(struct clk *clk) in pll_recalc() argument
43 return clk->parent->rate * PLL_RATE; in pll_recalc()
50 static struct clk pll_clk = {
56 static unsigned long peripheral0_recalc(struct clk *clk) in peripheral0_recalc() argument
58 return clk->parent->rate / 8; in peripheral0_recalc()
65 static struct clk peripheral0_clk = {
71 static unsigned long peripheral1_recalc(struct clk *clk) in peripheral1_recalc() argument
73 return clk->parent->rate / 4; in peripheral1_recalc()
[all …]
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| /linux-4.4.14/drivers/clk/nxp/ |
| D | clk-lpc18xx-cgu.c | 533 static struct clk *lpc18xx_cgu_register_div(struct lpc18xx_cgu_src_clk_div *clk, in lpc18xx_cgu_register_div() argument
537 const char *name = clk_src_names[clk->clk_id]; in lpc18xx_cgu_register_div()
540 clk->div.reg = reg; in lpc18xx_cgu_register_div()
541 clk->mux.reg = reg; in lpc18xx_cgu_register_div()
542 clk->gate.reg = reg; in lpc18xx_cgu_register_div()
544 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); in lpc18xx_cgu_register_div()
546 return clk_register_composite(NULL, name, parents, clk->n_parents, in lpc18xx_cgu_register_div()
547 &clk->mux.hw, &clk_mux_ops, in lpc18xx_cgu_register_div()
548 &clk->div.hw, &clk_divider_ops, in lpc18xx_cgu_register_div()
549 &clk->gate.hw, &lpc18xx_gate_ops, 0); in lpc18xx_cgu_register_div()
[all …]
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| /linux-4.4.14/drivers/clk/berlin/ |
| D | bg2.c | 95 static struct clk *clks[MAX_CLKS];
507 struct clk *clk; in berlin2_clock_setup() local
516 clk = of_clk_get_by_name(np, clk_names[REFCLK]); in berlin2_clock_setup()
517 if (!IS_ERR(clk)) { in berlin2_clock_setup()
518 clk_names[REFCLK] = __clk_get_name(clk); in berlin2_clock_setup()
519 clk_put(clk); in berlin2_clock_setup()
522 clk = of_clk_get_by_name(np, clk_names[VIDEO_EXT0]); in berlin2_clock_setup()
523 if (!IS_ERR(clk)) { in berlin2_clock_setup()
524 clk_names[VIDEO_EXT0] = __clk_get_name(clk); in berlin2_clock_setup()
525 clk_put(clk); in berlin2_clock_setup()
[all …]
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| /linux-4.4.14/sound/soc/sh/rcar/ |
| D | adg.c | 32 struct clk *clk[CLKMAX]; member
33 struct clk *clkout[CLKOUTMAX];
44 ((pos) = adg->clk[i]); \
176 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */ in rsnd_adg_set_convert_clk_gen2()
177 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */ in rsnd_adg_set_convert_clk_gen2()
178 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */ in rsnd_adg_set_convert_clk_gen2()
257 clk_get_rate(adg->clk[CLKA]), /* 000: CLKA */ in rsnd_adg_set_convert_clk_gen1()
258 clk_get_rate(adg->clk[CLKB]), /* 001: CLKB */ in rsnd_adg_set_convert_clk_gen1()
259 clk_get_rate(adg->clk[CLKC]), /* 010: CLKC */ in rsnd_adg_set_convert_clk_gen1()
356 struct clk *clk; in rsnd_adg_ssi_clk_try_start() local
[all …]
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| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/device/ |
| D | ctrl.c | 39 struct nvkm_clk *clk = ctrl->device->clk; in nvkm_control_mthd_pstate_info() local
49 if (clk) { in nvkm_control_mthd_pstate_info()
50 args->v0.count = clk->state_nr; in nvkm_control_mthd_pstate_info()
51 args->v0.ustate_ac = clk->ustate_ac; in nvkm_control_mthd_pstate_info()
52 args->v0.ustate_dc = clk->ustate_dc; in nvkm_control_mthd_pstate_info()
53 args->v0.pwrsrc = clk->pwrsrc; in nvkm_control_mthd_pstate_info()
54 args->v0.pstate = clk->pstate; in nvkm_control_mthd_pstate_info()
72 struct nvkm_clk *clk = ctrl->device->clk; in nvkm_control_mthd_pstate_attr() local
85 if (!clk) in nvkm_control_mthd_pstate_attr()
89 if (args->v0.state >= clk->state_nr) in nvkm_control_mthd_pstate_attr()
[all …]
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| /linux-4.4.14/arch/arm/kernel/ |
| D | smp_twd.c | 31 static struct clk *twd_clk;
40 static int twd_shutdown(struct clock_event_device *clk) in twd_shutdown() argument
46 static int twd_set_oneshot(struct clock_event_device *clk) in twd_set_oneshot() argument
54 static int twd_set_periodic(struct clock_event_device *clk) in twd_set_periodic() argument
97 struct clock_event_device *clk = raw_cpu_ptr(twd_evt); in twd_timer_stop() local
99 twd_shutdown(clk); in twd_timer_stop()
100 disable_percpu_irq(clk->irq); in twd_timer_stop()
274 struct clock_event_device *clk = raw_cpu_ptr(twd_evt); in twd_timer_setup() local
283 clockevents_register_device(clk); in twd_timer_setup()
284 enable_percpu_irq(clk->irq, 0); in twd_timer_setup()
[all …]
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| /linux-4.4.14/sound/soc/pxa/ |
| D | raumfeld.c | 44 static void set_max9485_clk(char clk) in set_max9485_clk() argument
46 i2c_master_send(max9486_client, &clk, 1); in set_max9485_clk()
91 unsigned int clk = 0; in raumfeld_cs4270_hw_params() local
97 clk = 11289600; in raumfeld_cs4270_hw_params()
101 clk = 12288000; in raumfeld_cs4270_hw_params()
105 clk = 22579200; in raumfeld_cs4270_hw_params()
109 clk = 24576000; in raumfeld_cs4270_hw_params()
115 ret = snd_soc_dai_set_sysclk(codec_dai, 0, clk, 0); in raumfeld_cs4270_hw_params()
120 ret = snd_soc_dai_set_pll(cpu_dai, 0, 0, 0, clk); in raumfeld_cs4270_hw_params()
128 ret = snd_soc_dai_set_sysclk(cpu_dai, PXA_SSP_CLK_EXT, clk, 1); in raumfeld_cs4270_hw_params()
[all …]
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| /linux-4.4.14/arch/m68k/include/asm/ |
| D | mcfclk.h | 9 struct clk;
12 void (*enable)(struct clk *);
13 void (*disable)(struct clk *);
16 struct clk { struct
24 extern struct clk *mcf_clks[]; argument
33 static struct clk __clk_##clk_bank##_##clk_slot = { \
40 void __clk_init_enabled(struct clk *);
41 void __clk_init_disabled(struct clk *);
44 static struct clk clk_##clk_ref = { \
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| /linux-4.4.14/drivers/gpu/host1x/ |
| D | mipi.c | 91 unsigned long clk; member
124 struct clk *clk; member
153 err = clk_enable(mipi->clk); in tegra_mipi_power_up()
169 clk_disable(mipi->clk); in tegra_mipi_power_up()
179 err = clk_enable(mipi->clk); in tegra_mipi_power_down()
321 err = clk_enable(device->mipi->clk); in tegra_mipi_calibrate()
339 u32 clk = 0, data = 0; in tegra_mipi_calibrate() local
346 clk = MIPI_CAL_CONFIG_SELECT | in tegra_mipi_calibrate()
353 if (soc->has_clk_lane && soc->pads[i].clk != 0) in tegra_mipi_calibrate()
354 tegra_mipi_writel(device->mipi, clk, soc->pads[i].clk); in tegra_mipi_calibrate()
[all …]
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| /linux-4.4.14/drivers/clk/mxs/ |
| D | Makefile | 5 obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o clk-ssp.o
7 obj-$(CONFIG_SOC_IMX23) += clk-imx23.o
8 obj-$(CONFIG_SOC_IMX28) += clk-imx28.o
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| /linux-4.4.14/arch/sh/kernel/cpu/ |
| D | clock-cpg.c | 8 static struct clk master_clk = {
13 static struct clk peripheral_clk = {
18 static struct clk bus_clk = {
23 static struct clk cpu_clk = {
31 static struct clk *onchip_clocks[] = {
51 struct clk *clk = onchip_clocks[i]; in cpg_clk_init() local
52 arch_init_clk_ops(&clk->ops, i); in cpg_clk_init()
53 if (clk->ops) in cpg_clk_init()
54 ret |= clk_register(clk); in cpg_clk_init()
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| /linux-4.4.14/drivers/memory/ |
| D | atmel-sdramc.c | 57 struct clk *clk; in atmel_ramc_probe() local
63 clk = devm_clk_get(&pdev->dev, "ddrck"); in atmel_ramc_probe()
64 if (IS_ERR(clk)) in atmel_ramc_probe()
65 return PTR_ERR(clk); in atmel_ramc_probe()
66 clk_prepare_enable(clk); in atmel_ramc_probe()
70 clk = devm_clk_get(&pdev->dev, "mpddr"); in atmel_ramc_probe()
71 if (IS_ERR(clk)) { in atmel_ramc_probe()
73 return PTR_ERR(clk); in atmel_ramc_probe()
75 clk_prepare_enable(clk); in atmel_ramc_probe()
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| /linux-4.4.14/drivers/clk/keystone/ |
| D | pll.c | 124 static struct clk *clk_register_pll(struct device *dev, in clk_register_pll()
131 struct clk *clk; in clk_register_pll() local
146 clk = clk_register(NULL, &pll->hw); in clk_register_pll()
147 if (IS_ERR(clk)) in clk_register_pll()
150 return clk; in clk_register_pll()
166 struct clk *clk; in _of_pll_clk_init() local
215 clk = clk_register_pll(NULL, node->name, parent_name, pll_data); in _of_pll_clk_init()
216 if (clk) { in _of_pll_clk_init()
217 of_clk_add_provider(node, of_clk_src_simple_get, clk); in _of_pll_clk_init()
257 struct clk *clk; in of_pll_div_clk_init() local
[all …]
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| /linux-4.4.14/drivers/pwm/ |
| D | pwm-fsl-ftm.c | 91 struct clk *clk[FSL_PWM_CLK_MAX]; member
103 return clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); in fsl_pwm_request()
110 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); in fsl_pwm_free()
119 sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]); in fsl_pwm_calculate_default_ps()
123 cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]); in fsl_pwm_calculate_default_ps()
153 c = clk_get_rate(fpc->clk[fpc->cnt_select]); in fsl_pwm_calculate_cycles()
197 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]); in fsl_pwm_calculate_period()
198 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]); in fsl_pwm_calculate_period()
310 ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]); in fsl_counter_clock_enable()
314 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); in fsl_counter_clock_enable()
[all …]
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| /linux-4.4.14/drivers/watchdog/ |
| D | coh901327_wdt.c | 82 static struct clk *clk; variable
93 clk_enable(clk); in coh901327_enable()
106 freq = clk_get_rate(clk); in coh901327_enable()
121 clk_disable(clk); in coh901327_enable()
132 clk_enable(clk); in coh901327_disable()
147 clk_disable(clk); in coh901327_disable()
168 clk_enable(clk); in coh901327_ping()
172 clk_disable(clk); in coh901327_ping()
180 clk_enable(clk); in coh901327_settimeout()
186 clk_disable(clk); in coh901327_settimeout()
[all …]
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