| /linux-4.1.27/arch/alpha/lib/ |
| D | fpreg.c | 8 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); argument
10 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); argument
16 unsigned long val; in alpha_read_fp_reg() local
19 case 0: STT( 0, val); break; in alpha_read_fp_reg()
20 case 1: STT( 1, val); break; in alpha_read_fp_reg()
21 case 2: STT( 2, val); break; in alpha_read_fp_reg()
22 case 3: STT( 3, val); break; in alpha_read_fp_reg()
23 case 4: STT( 4, val); break; in alpha_read_fp_reg()
24 case 5: STT( 5, val); break; in alpha_read_fp_reg()
25 case 6: STT( 6, val); break; in alpha_read_fp_reg()
[all …]
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| /linux-4.1.27/arch/blackfin/mach-bf561/include/mach/ |
| D | cdefBF561.h | 17 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) argument
20 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) argument
22 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) argument
27 #define bfin_write_SWRST(val) bfin_write16(SWRST,val) argument
29 #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) argument
31 #define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val) argument
33 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val) argument
35 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val) argument
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) argument
39 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) argument
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| D | blackfin.h | 24 #define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val) argument
26 #define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val) argument
28 #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) argument
33 #define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val) argument
35 #define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val) argument
37 #define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val) argument
39 #define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val) argument
|
| /linux-4.1.27/arch/blackfin/mach-bf609/include/mach/ |
| D | cdefBF60x_base.h | 17 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) argument
23 #define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val) argument
25 #define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val) argument
27 #define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val) argument
30 #define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val) argument
33 #define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC_SCTL0 + (sid) * 8), val) argument
36 #define bfin_write_SEC_SSTAT(sid, val) bfin_write32((SEC_SSTAT0 + (sid) * 8), val) argument
40 #define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val) argument
44 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) argument
46 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) argument
[all …]
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| /linux-4.1.27/arch/blackfin/mach-bf537/include/mach/ |
| D | cdefBF534.h | 13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) argument
16 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) argument
18 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) argument
23 #define bfin_write_SWRST(val) bfin_write16(SWRST,val) argument
25 #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) argument
27 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val) argument
29 #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val) argument
31 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) argument
33 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) argument
35 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) argument
[all …]
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| D | cdefBF537.h | 16 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val) argument
18 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val) argument
20 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val) argument
22 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val) argument
24 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val) argument
26 #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD,val) argument
28 #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT,val) argument
30 #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC,val) argument
32 #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1,val) argument
34 #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2,val) argument
[all …]
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| /linux-4.1.27/arch/blackfin/mach-bf548/include/mach/ |
| D | cdefBF54x_base.h | 18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) argument
21 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) argument
23 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) argument
28 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) argument
33 #define bfin_write_SWRST(val) bfin_write16(SWRST, val) argument
35 #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) argument
40 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) argument
42 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) argument
44 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) argument
46 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) argument
[all …]
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| D | cdefBF547.h | 18 #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) argument
20 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) argument
22 #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) argument
24 #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) argument
26 #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) argument
28 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) argument
30 #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) argument
32 #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) argument
34 #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) argument
36 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) argument
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| D | cdefBF544.h | 18 #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) argument
20 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) argument
22 #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) argument
24 #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) argument
26 #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) argument
28 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) argument
30 #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) argument
32 #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) argument
34 #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) argument
36 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) argument
[all …]
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| D | cdefBF548.h | 19 #define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) argument
21 #define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) argument
23 #define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) argument
25 #define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) argument
27 #define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) argument
29 #define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) argument
31 #define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) argument
33 #define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) argument
35 #define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) argument
37 #define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) argument
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| D | cdefBF542.h | 18 #define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) argument
20 #define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) argument
22 #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) argument
24 #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) argument
26 #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) argument
28 #define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) argument
30 #define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) argument
32 #define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) argument
34 #define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) argument
36 #define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) argument
[all …]
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| D | cdefBF549.h | 19 #define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val) argument
21 #define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val) argument
23 #define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val) argument
25 #define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val) argument
27 #define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val) argument
29 #define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val) argument
31 #define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val) argument
33 #define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val) argument
35 #define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val) argument
37 #define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val) argument
[all …]
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| /linux-4.1.27/drivers/media/tuners/ |
| D | tda18271-maps.c | 31 u8 val; member
202 { .rfmax = 62000, .val = 0x00 },
203 { .rfmax = 84000, .val = 0x01 },
204 { .rfmax = 100000, .val = 0x02 },
205 { .rfmax = 140000, .val = 0x03 },
206 { .rfmax = 170000, .val = 0x04 },
207 { .rfmax = 180000, .val = 0x05 },
208 { .rfmax = 865000, .val = 0x06 },
209 { .rfmax = 0, .val = 0x00 }, /* end */
213 { .rfmax = 61100, .val = 0x74 },
[all …]
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| D | qt1010.c | 25 static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val) in qt1010_readreg() argument
31 .flags = I2C_M_RD, .buf = val, .len = 1 }, in qt1010_readreg()
43 static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val) in qt1010_writereg() argument
45 u8 buf[2] = { reg, val }; in qt1010_writereg()
136 rd[2].val = reg05; in qt1010_set_params()
139 rd[4].val = (freq + QT1010_OFFSET) / FREQ1; in qt1010_set_params()
142 if (mod1 < 8000000) rd[6].val = 0x1d; in qt1010_set_params()
143 else rd[6].val = 0x1c; in qt1010_set_params()
146 if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */ in qt1010_set_params()
147 else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /* +4 MHz */ in qt1010_set_params()
[all …]
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| D | mc44s803.c | 37 static int mc44s803_writereg(struct mc44s803_priv *priv, u32 val) in mc44s803_writereg() argument
44 buf[0] = (val & 0xff0000) >> 16; in mc44s803_writereg()
45 buf[1] = (val & 0xff00) >> 8; in mc44s803_writereg()
46 buf[2] = (val & 0xff); in mc44s803_writereg()
56 static int mc44s803_readreg(struct mc44s803_priv *priv, u8 reg, u32 *val) in mc44s803_readreg() argument
78 *val = (buf[0] << 16) | (buf[1] << 8) | buf[2]; in mc44s803_readreg()
96 u32 val; in mc44s803_init() local
103 val = MC44S803_REG_SM(MC44S803_REG_RESET, MC44S803_ADDR) | in mc44s803_init()
106 err = mc44s803_writereg(priv, val); in mc44s803_init()
110 val = MC44S803_REG_SM(MC44S803_REG_RESET, MC44S803_ADDR); in mc44s803_init()
[all …]
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| /linux-4.1.27/arch/blackfin/mach-bf538/include/mach/ |
| D | cdefBF538.h | 10 #define bfin_writePTR(addr, val) bfin_write32(addr, val) argument
14 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) argument
17 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) argument
19 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) argument
21 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) argument
23 #define bfin_write_SWRST(val) bfin_write16(SWRST, val) argument
25 #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) argument
27 #define bfin_write_SIC_RVECT(val) bfin_writePTR(SIC_RVECT, val) argument
29 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) argument
31 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) argument
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| D | cdefBF539.h | 14 #define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val) argument
16 #define bfin_write_MXVR_PLL_CTL_0(val) bfin_write32(MXVR_PLL_CTL_0, val) argument
18 #define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val) argument
20 #define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val) argument
22 #define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val) argument
24 #define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val) argument
26 #define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val) argument
28 #define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val) argument
30 #define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val) argument
32 #define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val) argument
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| /linux-4.1.27/arch/blackfin/mach-bf518/include/mach/ |
| D | cdefBF512.h | 13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) argument
16 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) argument
18 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) argument
20 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) argument
25 #define bfin_write_SWRST(val) bfin_write16(SWRST, val) argument
27 #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) argument
30 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) argument
32 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) argument
34 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) argument
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) argument
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| D | cdefBF516.h | 16 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) argument
18 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) argument
20 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) argument
22 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) argument
24 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) argument
26 #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) argument
28 #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) argument
30 #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) argument
32 #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) argument
34 #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) argument
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| D | cdefBF514.h | 16 #define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val) argument
18 #define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val) argument
20 #define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) argument
22 #define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) argument
24 #define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) argument
26 #define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) argument
28 #define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) argument
30 #define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) argument
32 #define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) argument
34 #define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) argument
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| D | cdefBF518.h | 16 #define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val) argument
18 #define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val) argument
20 #define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val) argument
22 #define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val) argument
24 #define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val) argument
26 #define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val) argument
28 #define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val) argument
30 #define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val) argument
32 #define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val) argument
34 #define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val) argument
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| /linux-4.1.27/arch/blackfin/mach-bf527/include/mach/ |
| D | cdefBF522.h | 13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) argument
16 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) argument
18 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) argument
20 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) argument
25 #define bfin_write_SWRST(val) bfin_write16(SWRST, val) argument
27 #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) argument
30 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) argument
32 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) argument
34 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) argument
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) argument
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| D | cdefBF525.h | 16 #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) argument
18 #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) argument
20 #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) argument
22 #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) argument
24 #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) argument
26 #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) argument
28 #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) argument
30 #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) argument
32 #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) argument
34 #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) argument
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| D | cdefBF527.h | 16 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) argument
18 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) argument
20 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) argument
22 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) argument
24 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) argument
26 #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) argument
28 #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) argument
30 #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) argument
32 #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) argument
34 #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) argument
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| /linux-4.1.27/arch/blackfin/mach-bf533/include/mach/ |
| D | cdefBF532.h | 13 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) argument
15 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) argument
18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) argument
23 #define bfin_write_SWRST(val) bfin_write16(SWRST,val) argument
25 #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) argument
27 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) argument
29 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) argument
31 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) argument
33 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) argument
35 #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val) argument
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| /linux-4.1.27/arch/blackfin/include/asm/ |
| D | cdef_LPBlackfin.h | 18 #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) argument
20 #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) argument
22 #define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val) argument
24 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val) argument
29 #define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val) argument
31 #define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val) argument
33 #define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val) argument
35 #define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val) argument
37 #define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val) argument
39 #define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val) argument
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| /linux-4.1.27/drivers/hwtracing/coresight/ |
| D | coresight-etm-cp14.c | 22 int etm_readl_cp14(u32 reg, unsigned int *val) in etm_readl_cp14() argument
26 *val = etm_read(ETMCR); in etm_readl_cp14()
29 *val = etm_read(ETMCCR); in etm_readl_cp14()
32 *val = etm_read(ETMTRIGGER); in etm_readl_cp14()
35 *val = etm_read(ETMSR); in etm_readl_cp14()
38 *val = etm_read(ETMSCR); in etm_readl_cp14()
41 *val = etm_read(ETMTSSCR); in etm_readl_cp14()
44 *val = etm_read(ETMTEEVR); in etm_readl_cp14()
47 *val = etm_read(ETMTECR1); in etm_readl_cp14()
50 *val = etm_read(ETMFFLR); in etm_readl_cp14()
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| D | coresight-etm3x.c | 45 u32 val, u32 off) in etm_writel() argument
48 if (etm_writel_cp14(off, val)) { in etm_writel()
53 writel_relaxed(val, drvdata->base + off); in etm_writel()
59 u32 val; in etm_readl() local
62 if (etm_readl_cp14(off, &val)) { in etm_readl()
67 val = readl_relaxed(drvdata->base + off); in etm_readl()
70 return val; in etm_readl()
152 u32 val; in coresight_timeout_etm() local
155 val = etm_readl(drvdata, offset); in coresight_timeout_etm()
158 if (val & BIT(position)) in coresight_timeout_etm()
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| /linux-4.1.27/arch/arm/include/asm/hardware/ |
| D | cp14.h | 20 #define dbg_write(val, reg) WCP14_##reg(val) argument
22 #define etm_write(val, reg) WCP14_##reg(val) argument
27 u32 val; \
28 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
29 val; \
32 #define MCR14(val, op1, crn, crm, op2) \ argument
34 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
160 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0) argument
161 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0) argument
162 #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0) argument
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| /linux-4.1.27/drivers/net/ethernet/neterion/vxge/ |
| D | vxge-reg.h | 25 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
26 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
54 #define VXGE_EPROM_IMG_MAJOR(val) (u32) vxge_bVALn(val, 48, 4) argument
55 #define VXGE_EPROM_IMG_MINOR(val) (u32) vxge_bVALn(val, 52, 4) argument
56 #define VXGE_EPROM_IMG_FIX(val) (u32) vxge_bVALn(val, 56, 4) argument
57 #define VXGE_EPROM_IMG_BUILD(val) (u32) vxge_bVALn(val, 60, 4) argument
59 #define VXGE_HW_GET_EPROM_IMAGE_INDEX(val) vxge_bVALn(val, 16, 8) argument
60 #define VXGE_HW_GET_EPROM_IMAGE_VALID(val) vxge_bVALn(val, 31, 1) argument
61 #define VXGE_HW_GET_EPROM_IMAGE_TYPE(val) vxge_bVALn(val, 40, 8) argument
62 #define VXGE_HW_GET_EPROM_IMAGE_REV(val) vxge_bVALn(val, 48, 16) argument
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| /linux-4.1.27/drivers/net/wireless/brcm80211/brcmsmac/ |
| D | types.h | 133 #define CONF_HAS(config, val) ((config) & (1 << (val))) argument
138 #define CONF_IS(config, val) ((config) == (1 << (val))) argument
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) argument
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) argument
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) argument
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) argument
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val) argument
148 #define NCONF_IS(val) CONF_IS(NCONF, val) argument
149 #define NCONF_GE(val) CONF_GE(NCONF, val) argument
150 #define NCONF_GT(val) CONF_GT(NCONF, val) argument
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| /linux-4.1.27/drivers/gpu/drm/msm/adreno/ |
| D | a3xx.xml.h | 660 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument
662 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
666 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument
668 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
674 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET() argument
676 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; in A3XX_GRAS_CL_VPORT_XOFFSET()
682 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE() argument
684 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; in A3XX_GRAS_CL_VPORT_XSCALE()
690 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) in A3XX_GRAS_CL_VPORT_YOFFSET() argument
692 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; in A3XX_GRAS_CL_VPORT_YOFFSET()
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| D | a2xx.xml.h | 262 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR() argument
264 …return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR()
268 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR() argument
270 …return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR()
274 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR() argument
276 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR()
280 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR() argument
282 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR()
286 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR() argument
288 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR()
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| D | a4xx.xml.h | 180 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC() argument
182 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; in A4XX_CGC_HLSQ_EARLY_CYC()
231 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument
233 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WID… in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
237 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument
239 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HE… in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
253 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH() argument
255 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; in A4XX_RB_MODE_CONTROL_WIDTH()
259 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT() argument
261 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; in A4XX_RB_MODE_CONTROL_HEIGHT()
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| D | adreno_pm4.xml.h | 217 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF() argument
219 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; in CP_LOAD_STATE_0_DST_OFF()
223 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC() argument
225 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; in CP_LOAD_STATE_0_STATE_SRC()
229 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK() argument
231 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; in CP_LOAD_STATE_0_STATE_BLOCK()
235 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT() argument
237 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; in CP_LOAD_STATE_0_NUM_UNIT()
243 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE() argument
245 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; in CP_LOAD_STATE_1_STATE_TYPE()
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| D | adreno_common.xml.h | 157 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) in AXXX_CP_RB_CNTL_BUFSZ() argument
159 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; in AXXX_CP_RB_CNTL_BUFSZ()
163 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) in AXXX_CP_RB_CNTL_BLKSZ() argument
165 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; in AXXX_CP_RB_CNTL_BLKSZ()
169 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) in AXXX_CP_RB_CNTL_BUF_SWAP() argument
171 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; in AXXX_CP_RB_CNTL_BUF_SWAP()
180 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) in AXXX_CP_RB_RPTR_ADDR_SWAP() argument
182 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; in AXXX_CP_RB_RPTR_ADDR_SWAP()
186 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) in AXXX_CP_RB_RPTR_ADDR_ADDR() argument
188 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; in AXXX_CP_RB_RPTR_ADDR_ADDR()
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| /linux-4.1.27/arch/arm64/include/asm/ |
| D | percpu.h | 49 unsigned long val, int size) \
62 : [val] "Ir" (val)); \
73 : [val] "Ir" (val)); \
84 : [val] "Ir" (val)); \
95 : [val] "Ir" (val)); \
134 static inline void __percpu_write(void *ptr, unsigned long val, int size) in __percpu_write() argument
138 ACCESS_ONCE(*(u8 *)ptr) = (u8)val; in __percpu_write()
141 ACCESS_ONCE(*(u16 *)ptr) = (u16)val; in __percpu_write()
144 ACCESS_ONCE(*(u32 *)ptr) = (u32)val; in __percpu_write()
147 ACCESS_ONCE(*(u64 *)ptr) = (u64)val; in __percpu_write()
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| D | arch_timer.h | 36 void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) in arch_timer_reg_write_cp15() argument
41 asm volatile("msr cntp_ctl_el0, %0" : : "r" (val)); in arch_timer_reg_write_cp15()
44 asm volatile("msr cntp_tval_el0, %0" : : "r" (val)); in arch_timer_reg_write_cp15()
50 asm volatile("msr cntv_ctl_el0, %0" : : "r" (val)); in arch_timer_reg_write_cp15()
53 asm volatile("msr cntv_tval_el0, %0" : : "r" (val)); in arch_timer_reg_write_cp15()
64 u32 val; in arch_timer_reg_read_cp15() local
69 asm volatile("mrs %0, cntp_ctl_el0" : "=r" (val)); in arch_timer_reg_read_cp15()
72 asm volatile("mrs %0, cntp_tval_el0" : "=r" (val)); in arch_timer_reg_read_cp15()
78 asm volatile("mrs %0, cntv_ctl_el0" : "=r" (val)); in arch_timer_reg_read_cp15()
81 asm volatile("mrs %0, cntv_tval_el0" : "=r" (val)); in arch_timer_reg_read_cp15()
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| /linux-4.1.27/drivers/phy/ |
| D | phy-xgene.c | 566 u32 val; in sds_wr() local
576 val = readl(csr_base + indirect_cmd_reg); in sds_wr()
577 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr()
579 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr()
588 u32 val; in sds_rd() local
596 val = readl(csr_base + indirect_cmd_reg); in sds_rd()
597 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd()
600 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd()
609 u32 val; in cmu_wr() local
618 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr()
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| D | phy-omap-control.c | 36 u32 val; in omap_control_pcie_pcs() local
55 val = readl(control_phy->pcie_pcs); in omap_control_pcie_pcs()
56 val &= ~(OMAP_CTRL_PCIE_PCS_MASK << in omap_control_pcie_pcs()
58 val |= (delay << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT); in omap_control_pcie_pcs()
59 writel(val, control_phy->pcie_pcs); in omap_control_pcie_pcs()
70 u32 val; in omap_control_phy_power() local
88 val = readl(control_phy->power); in omap_control_phy_power()
93 val &= ~OMAP_CTRL_DEV_PHY_PD; in omap_control_phy_power()
95 val |= OMAP_CTRL_DEV_PHY_PD; in omap_control_phy_power()
104 val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | in omap_control_phy_power()
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| D | phy-hix5hd2-sata.c | 68 u32 val, data[2]; in hix5hd2_sata_phy_init() local
85 val = readl_relaxed(priv->base + SATA_PHY0_CTLL); in hix5hd2_sata_phy_init()
86 val &= ~(MPLL_MULTIPLIER_MASK | REF_USE_PAD); in hix5hd2_sata_phy_init()
87 val |= MPLL_MULTIPLIER_50M << MPLL_MULTIPLIER_SHIFT | in hix5hd2_sata_phy_init()
89 writel_relaxed(val, priv->base + SATA_PHY0_CTLL); in hix5hd2_sata_phy_init()
91 val &= ~PHY_RESET; in hix5hd2_sata_phy_init()
92 writel_relaxed(val, priv->base + SATA_PHY0_CTLL); in hix5hd2_sata_phy_init()
94 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL1); in hix5hd2_sata_phy_init()
95 val &= ~AMPLITUDE_MASK; in hix5hd2_sata_phy_init()
96 val |= AMPLITUDE_GEN3 << AMPLITUDE_GEN3_SHIFT | in hix5hd2_sata_phy_init()
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| D | phy-exynos5250-sata.c | 92 u32 val = 0; in exynos_sata_phy_init() local
102 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
104 val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
105 val |= RESET_GLOBAL_RST_N | RESET_CMN_RST_N | RESET_CMN_BLOCK_RST_N in exynos_sata_phy_init()
108 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
110 val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
111 val |= LINK_RESET; in exynos_sata_phy_init()
112 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
114 val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
115 val |= RESET_CMN_RST_N; in exynos_sata_phy_init()
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| /linux-4.1.27/arch/mips/pci/ |
| D | pci-bcm63xx.c | 109 static void bcm63xx_int_cfg_writel(u32 val, u32 reg) in bcm63xx_int_cfg_writel() argument
116 bcm_mpi_writel(val, MPI_PCICFGDATA_REG); in bcm63xx_int_cfg_writel()
123 u32 val; in bcm63xx_reset_pcie() local
132 val = bcm_misc_readl(reg); in bcm63xx_reset_pcie()
133 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; in bcm63xx_reset_pcie()
134 bcm_misc_writel(val, reg); in bcm63xx_reset_pcie()
152 u32 val; in bcm63xx_register_pcie() local
164 val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); in bcm63xx_register_pcie()
165 val |= OPT1_RD_BE_OPT_EN; in bcm63xx_register_pcie()
166 val |= OPT1_RD_REPLY_BE_FIX_EN; in bcm63xx_register_pcie()
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| D | pci-vr41xx.c | 118 uint32_t val; in vr41xx_pciu_init() local
166 val = IBA(master->bus_base_address) | in vr41xx_pciu_init()
170 pciu_write(PCIMMAW1REG, val); in vr41xx_pciu_init()
172 val = pciu_read(PCIMMAW1REG); in vr41xx_pciu_init()
173 val &= ~WINEN; in vr41xx_pciu_init()
174 pciu_write(PCIMMAW1REG, val); in vr41xx_pciu_init()
179 val = IBA(master->bus_base_address) | in vr41xx_pciu_init()
183 pciu_write(PCIMMAW2REG, val); in vr41xx_pciu_init()
185 val = pciu_read(PCIMMAW2REG); in vr41xx_pciu_init()
186 val &= ~WINEN; in vr41xx_pciu_init()
[all …]
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| D | ops-bcm63xx.c | 39 static int preprocess_write(u32 orig_data, u32 val, int where, in preprocess_write() argument
48 (val << ((where & 3) << 3)); in preprocess_write()
52 (val << ((where & 3) << 3)); in preprocess_write()
55 ret = val; in preprocess_write()
68 u32 val; in bcm63xx_setup_cfg_access() local
85 val = (reg << MPI_L2PCFG_REG_SHIFT); in bcm63xx_setup_cfg_access()
86 val |= (func << MPI_L2PCFG_FUNC_SHIFT); in bcm63xx_setup_cfg_access()
87 val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT); in bcm63xx_setup_cfg_access()
88 val |= MPI_L2PCFG_CFG_USEREG_MASK; in bcm63xx_setup_cfg_access()
89 val |= MPI_L2PCFG_CFG_SEL_MASK; in bcm63xx_setup_cfg_access()
[all …]
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| /linux-4.1.27/arch/mips/include/asm/ |
| D | mipsregs.h | 871 #define write_r10k_perf_cntr(counter,val) \ argument
876 : "r" (val), "i" (counter)); \
890 #define write_r10k_perf_cntl(counter,val) \ argument
895 : "r" (val), "i" (counter)); \
974 #define __write_ulong_c0_register(reg, sel, val) \ argument
977 __write_32bit_c0_register(reg, sel, val); \
979 __write_64bit_c0_register(reg, sel, val); \
1033 #define __write_64bit_c0_split(source, sel, val) \ argument
1047 : : "r" (val)); \
1057 : : "r" (val)); \
[all …]
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| D | mipsmtregs.h | 20 #define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val) argument
26 #define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val) argument
29 #define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) argument
32 #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) argument
35 #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) argument
39 #define write_c0_tchalt(val) __write_32bit_c0_register($2, 4, val) argument
42 #define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val) argument
374 #define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) argument
376 #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) argument
378 #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) argument
[all …]
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| /linux-4.1.27/drivers/net/wireless/ath/ath5k/ |
| D | eeprom.c | 43 u16 val; in ath5k_eeprom_bin2freq() local
50 val = (5 * bin) + 4800; in ath5k_eeprom_bin2freq()
52 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : in ath5k_eeprom_bin2freq()
56 val = bin + 2300; in ath5k_eeprom_bin2freq()
58 val = bin + 2400; in ath5k_eeprom_bin2freq()
61 return val; in ath5k_eeprom_bin2freq()
76 u16 val; in ath5k_eeprom_init_header() local
96 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val); in ath5k_eeprom_init_header()
97 if (val) { in ath5k_eeprom_init_header()
98 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) << in ath5k_eeprom_init_header()
[all …]
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| /linux-4.1.27/sound/pci/ac97/ |
| D | ac97_proc.c | 110 unsigned short val, tmp, ext, mext; in snd_ac97_proc_read_main() local
130 val = snd_ac97_read(ac97, AC97_INT_PAGING); in snd_ac97_proc_read_main()
141 AC97_PAGE_MASK, val & AC97_PAGE_MASK); in snd_ac97_proc_read_main()
145 val = ac97->caps; in snd_ac97_proc_read_main()
147 val & AC97_BC_DEDICATED_MIC ? " -dedicated MIC PCM IN channel-" : "", in snd_ac97_proc_read_main()
148 val & AC97_BC_RESERVED1 ? " -reserved1-" : "", in snd_ac97_proc_read_main()
149 val & AC97_BC_BASS_TREBLE ? " -bass & treble-" : "", in snd_ac97_proc_read_main()
150 val & AC97_BC_SIM_STEREO ? " -simulated stereo-" : "", in snd_ac97_proc_read_main()
151 val & AC97_BC_HEADPHONE ? " -headphone out-" : "", in snd_ac97_proc_read_main()
152 val & AC97_BC_LOUDNESS ? " -loudness-" : ""); in snd_ac97_proc_read_main()
[all …]
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| /linux-4.1.27/drivers/hwmon/ |
| D | hwmon-vid.c | 82 int vid_from_reg(int val, u8 vrm) in vid_from_reg() argument
90 val &= 0x3f; in vid_from_reg()
91 if ((val & 0x1f) == 0x1f) in vid_from_reg()
93 if ((val & 0x1f) <= 0x09 || val == 0x0a) in vid_from_reg()
94 vid = 1087500 - (val & 0x1f) * 25000; in vid_from_reg()
96 vid = 1862500 - (val & 0x1f) * 25000; in vid_from_reg()
97 if (val & 0x20) in vid_from_reg()
103 val &= 0xff; in vid_from_reg()
104 if (val < 0x02 || val > 0xb2) in vid_from_reg()
106 return (1600000 - (val - 2) * 6250 + 500) / 1000; in vid_from_reg()
[all …]
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| D | adt7411.c | 67 int val, tmp; in adt7411_read_10_bit() local
71 val = i2c_smbus_read_byte_data(client, lsb_reg); in adt7411_read_10_bit()
72 if (val < 0) in adt7411_read_10_bit()
75 tmp = (val >> lsb_shift) & 3; in adt7411_read_10_bit()
76 val = i2c_smbus_read_byte_data(client, msb_reg); in adt7411_read_10_bit()
78 if (val >= 0) in adt7411_read_10_bit()
79 val = (val << 2) | tmp; in adt7411_read_10_bit()
84 return val; in adt7411_read_10_bit()
91 int ret, val; in adt7411_modify_bit() local
100 val = ret | bit; in adt7411_modify_bit()
[all …]
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| D | sch5636.c | 86 int i, val; in sch5636_update_device() local
95 val = sch56xx_read_virtual_reg(data->addr, in sch5636_update_device()
97 if (unlikely(val < 0)) { in sch5636_update_device()
98 ret = ERR_PTR(val); in sch5636_update_device()
101 data->in[i] = val; in sch5636_update_device()
108 val = sch56xx_read_virtual_reg(data->addr, in sch5636_update_device()
110 if (unlikely(val < 0)) { in sch5636_update_device()
111 ret = ERR_PTR(val); in sch5636_update_device()
114 data->temp_val[i] = val; in sch5636_update_device()
116 val = sch56xx_read_virtual_reg(data->addr, in sch5636_update_device()
[all …]
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| D | lm95234.c | 82 int val; in lm95234_read_temp() local
86 val = i2c_smbus_read_byte_data(client, in lm95234_read_temp()
88 if (val < 0) in lm95234_read_temp()
89 return val; in lm95234_read_temp()
90 temp = val << 8; in lm95234_read_temp()
91 val = i2c_smbus_read_byte_data(client, in lm95234_read_temp()
93 if (val < 0) in lm95234_read_temp()
94 return val; in lm95234_read_temp()
95 temp |= val; in lm95234_read_temp()
103 val = i2c_smbus_read_byte_data(client, in lm95234_read_temp()
[all …]
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| D | sch5627.c | 101 int i, val; in sch5627_update_device() local
115 val = sch56xx_read_virtual_reg12(data->addr, in sch5627_update_device()
119 if (unlikely(val < 0)) { in sch5627_update_device()
120 ret = ERR_PTR(val); in sch5627_update_device()
123 data->temp[i] = val; in sch5627_update_device()
127 val = sch56xx_read_virtual_reg16(data->addr, in sch5627_update_device()
129 if (unlikely(val < 0)) { in sch5627_update_device()
130 ret = ERR_PTR(val); in sch5627_update_device()
133 data->fan[i] = val; in sch5627_update_device()
137 val = sch56xx_read_virtual_reg12(data->addr, in sch5627_update_device()
[all …]
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| /linux-4.1.27/arch/arm/mach-omap2/ |
| D | clock_common_data.c | 23 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX },
28 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
33 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
34 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX },
35 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX },
36 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX },
41 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
42 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
43 { .div = 3, .val = 3, .flags = RATE_IN_243X },
51 { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
[all …]
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| D | omap-wakeupgen.c | 69 static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu) in wakeupgen_writel() argument
71 writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 + in wakeupgen_writel()
75 static inline void sar_writel(u32 val, u32 offset, u8 idx) in sar_writel() argument
77 writel_relaxed(val, sar_base + offset + (idx * 4)); in sar_writel()
94 u32 val, bit_number; in _wakeupgen_clear() local
100 val = wakeupgen_readl(i, cpu); in _wakeupgen_clear()
101 val &= ~BIT(bit_number); in _wakeupgen_clear()
102 wakeupgen_writel(val, i, cpu); in _wakeupgen_clear()
107 u32 val, bit_number; in _wakeupgen_set() local
113 val = wakeupgen_readl(i, cpu); in _wakeupgen_set()
[all …]
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| /linux-4.1.27/drivers/usb/phy/ |
| D | phy-tegra-usb.c | 209 unsigned long val; in set_pts() local
212 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
213 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); in set_pts()
214 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); in set_pts()
215 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
217 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; in set_pts()
218 val &= ~TEGRA_USB_PORTSC1_PTS(~0); in set_pts()
219 val |= TEGRA_USB_PORTSC1_PTS(pts_val); in set_pts()
220 writel(val, base + TEGRA_USB_PORTSC1); in set_pts()
227 unsigned long val; in set_phcd() local
[all …]
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| D | phy-rcar-gen2-usb.c | 55 u32 val; in __rcar_gen2_usbhs_phy_enable() local
59 val = ioread32(base + USBHS_UGCTRL_REG); in __rcar_gen2_usbhs_phy_enable()
60 val &= ~USBHS_UGCTRL_PLLRESET; in __rcar_gen2_usbhs_phy_enable()
61 iowrite32(val, base + USBHS_UGCTRL_REG); in __rcar_gen2_usbhs_phy_enable()
63 val = ioread16(base + USBHS_LPSTS_REG); in __rcar_gen2_usbhs_phy_enable()
64 val |= USBHS_LPSTS_SUSPM; in __rcar_gen2_usbhs_phy_enable()
65 iowrite16(val, base + USBHS_LPSTS_REG); in __rcar_gen2_usbhs_phy_enable()
68 val = ioread32(base + USBHS_UGSTS_REG); in __rcar_gen2_usbhs_phy_enable()
69 if ((val & USBHS_UGSTS_LOCK) == USBHS_UGSTS_LOCK) { in __rcar_gen2_usbhs_phy_enable()
70 val = ioread32(base + USBHS_UGCTRL_REG); in __rcar_gen2_usbhs_phy_enable()
[all …]
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| /linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp4/ |
| D | mdp4.xml.h | 112 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR() argument
114 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK; in MDP4_VERSION_MINOR()
118 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR() argument
120 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK; in MDP4_VERSION_MAJOR()
140 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM() argument
142 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK; in MDP4_DISP_INTF_SEL_PRIM()
146 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC() argument
148 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK; in MDP4_DISP_INTF_SEL_SEC()
152 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT() argument
154 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK; in MDP4_DISP_INTF_SEL_EXT()
[all …]
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| /linux-4.1.27/drivers/gpu/drm/msm/dsi/ |
| D | dsi.xml.h | 103 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) in DSI_6G_HW_VERSION_MAJOR() argument
105 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; in DSI_6G_HW_VERSION_MAJOR()
109 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) in DSI_6G_HW_VERSION_MINOR() argument
111 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; in DSI_6G_HW_VERSION_MINOR()
115 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) in DSI_6G_HW_VERSION_STEP() argument
117 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; in DSI_6G_HW_VERSION_STEP()
146 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) in DSI_VID_CFG0_VIRT_CHANNEL() argument
148 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; in DSI_VID_CFG0_VIRT_CHANNEL()
152 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) in DSI_VID_CFG0_DST_FORMAT() argument
154 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; in DSI_VID_CFG0_DST_FORMAT()
[all …]
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| /linux-4.1.27/sound/synth/emux/ |
| D | emux_nrpn.c | 33 int (*convert)(int val);
54 int type, int val, int mode) in send_converted_effect() argument
59 cval = table[i].convert(val); in send_converted_effect()
99 static int fx_delay(int val);
100 static int fx_attack(int val);
101 static int fx_hold(int val);
102 static int fx_decay(int val);
103 static int fx_the_value(int val);
104 static int fx_twice_value(int val);
105 static int fx_conv_pitch(int val);
[all …]
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| /linux-4.1.27/include/asm-generic/ |
| D | percpu.h | 68 #define raw_cpu_generic_to_op(pcp, val, op) \ argument
70 *raw_cpu_ptr(&(pcp)) op val; \
73 #define raw_cpu_generic_add_return(pcp, val) \ argument
75 raw_cpu_add(pcp, val); \
117 #define this_cpu_generic_to_op(pcp, val, op) \ argument
121 *raw_cpu_ptr(&(pcp)) op val; \
125 #define this_cpu_generic_add_return(pcp, val) \ argument
130 raw_cpu_add(pcp, val); \
184 #define raw_cpu_write_1(pcp, val) raw_cpu_generic_to_op(pcp, val, =) argument
187 #define raw_cpu_write_2(pcp, val) raw_cpu_generic_to_op(pcp, val, =) argument
[all …]
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| /linux-4.1.27/arch/s390/include/asm/ |
| D | percpu.h | 26 #define arch_this_cpu_to_op_simple(pcp, val, op) \ argument
36 new__ = old__ op (val); \
43 #define this_cpu_add_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
44 #define this_cpu_add_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
45 #define this_cpu_add_return_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
46 #define this_cpu_add_return_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
47 #define this_cpu_and_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) argument
48 #define this_cpu_and_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) argument
49 #define this_cpu_or_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) argument
50 #define this_cpu_or_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) argument
[all …]
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| /linux-4.1.27/arch/sh/include/asm/ |
| D | unaligned-sh4a.h | 93 static inline void nonnative_put_le16(u16 val, u8 *p) in nonnative_put_le16() argument
95 *p++ = val; in nonnative_put_le16()
96 *p++ = val >> 8; in nonnative_put_le16()
99 static inline void nonnative_put_le32(u32 val, u8 *p) in nonnative_put_le32() argument
101 nonnative_put_le16(val, p); in nonnative_put_le32()
102 nonnative_put_le16(val >> 16, p + 2); in nonnative_put_le32()
105 static inline void nonnative_put_le64(u64 val, u8 *p) in nonnative_put_le64() argument
107 nonnative_put_le32(val, p); in nonnative_put_le64()
108 nonnative_put_le32(val >> 32, p + 4); in nonnative_put_le64()
111 static inline void nonnative_put_be16(u16 val, u8 *p) in nonnative_put_be16() argument
[all …]
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| /linux-4.1.27/arch/x86/include/asm/ |
| D | percpu.h | 89 #define percpu_to_op(op, var, val) \ argument
94 pto_tmp__ = (val); \
101 : "qi" ((pto_T__)(val))); \
106 : "ri" ((pto_T__)(val))); \
111 : "ri" ((pto_T__)(val))); \
116 : "re" ((pto_T__)(val))); \
126 #define percpu_add_op(var, val) \ argument
129 const int pao_ID__ = (__builtin_constant_p(val) && \
130 ((val) == 1 || (val) == -1)) ? \
131 (int)(val) : 0; \
[all …]
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| D | special_insns.h | 25 unsigned long val; in native_read_cr0() local
26 asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order)); in native_read_cr0()
27 return val; in native_read_cr0()
30 static inline void native_write_cr0(unsigned long val) in native_write_cr0() argument
32 asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order)); in native_write_cr0()
37 unsigned long val; in native_read_cr2() local
38 asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order)); in native_read_cr2()
39 return val; in native_read_cr2()
42 static inline void native_write_cr2(unsigned long val) in native_write_cr2() argument
44 asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order)); in native_write_cr2()
[all …]
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| D | msr.h | 49 #define DECLARE_ARGS(val, low, high) unsigned low, high argument
50 #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) argument
51 #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) argument
52 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) argument
54 #define DECLARE_ARGS(val, low, high) unsigned long long val argument
55 #define EAX_EDX_VAL(val, low, high) (val) argument
56 #define EAX_EDX_ARGS(val, low, high) "A" (val) argument
57 #define EAX_EDX_RET(val, low, high) "=A" (val) argument
62 DECLARE_ARGS(val, low, high); in native_read_msr()
64 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); in native_read_msr()
[all …]
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| /linux-4.1.27/include/sound/ |
| D | emu8000_reg.h | 122 #define EMU8000_CPF_WRITE(emu, chan, val) \ argument
123 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)), (val))
124 #define EMU8000_PTRX_WRITE(emu, chan, val) \ argument
125 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)), (val))
126 #define EMU8000_CVCF_WRITE(emu, chan, val) \ argument
127 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)), (val))
128 #define EMU8000_VTFT_WRITE(emu, chan, val) \ argument
129 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)), (val))
130 #define EMU8000_PSST_WRITE(emu, chan, val) \ argument
131 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan)), (val))
[all …]
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| /linux-4.1.27/arch/x86/oprofile/ |
| D | op_model_amd.c | 107 static inline u64 op_amd_randomize_ibs_op(u64 val) in op_amd_randomize_ibs_op() argument
125 val += (s8)(random >> 4); in op_amd_randomize_ibs_op()
127 val |= (u64)(random & IBS_RANDOM_MASK) << 32; in op_amd_randomize_ibs_op()
129 return val; in op_amd_randomize_ibs_op()
136 u64 val, ctl; in op_amd_handle_ibs() local
145 rdmsrl(MSR_AMD64_IBSFETCHLINAD, val); in op_amd_handle_ibs()
146 oprofile_write_reserve(&entry, regs, val, in op_amd_handle_ibs()
148 oprofile_add_data64(&entry, val); in op_amd_handle_ibs()
150 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val); in op_amd_handle_ibs()
151 oprofile_add_data64(&entry, val); in op_amd_handle_ibs()
[all …]
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| /linux-4.1.27/arch/tile/lib/ |
| D | spinlock_32.c | 106 u32 val; in arch_read_trylock() local
108 val = __insn_tns((int *)&rwlock->lock); in arch_read_trylock()
109 if (likely((val << _RD_COUNT_WIDTH) == 0)) { in arch_read_trylock()
110 val += 1 << RD_COUNT_SHIFT; in arch_read_trylock()
111 rwlock->lock = val; in arch_read_trylock()
113 BUG_ON(val == 0); /* we don't expect wraparound */ in arch_read_trylock()
116 if ((val & 1) == 0) in arch_read_trylock()
117 rwlock->lock = val; in arch_read_trylock()
141 u32 val, iterations = 0; in arch_read_unlock() local
146 val = __insn_tns((int *)&rwlock->lock); in arch_read_unlock()
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| D | spinlock_64.c | 43 u32 val = arch_spin_read_noalloc(lock); in arch_spin_lock_slow() local
44 u32 delta = my_ticket - arch_spin_current(val); in arch_spin_lock_slow()
57 u32 val = arch_spin_read_noalloc(lock); in arch_spin_trylock() local
58 if (unlikely(arch_spin_current(val) != arch_spin_next(val))) in arch_spin_trylock()
60 return cmpxchg(&lock->lock, val, (val + 1) & ~__ARCH_SPIN_NEXT_OVERFLOW) in arch_spin_trylock()
61 == val; in arch_spin_trylock()
79 u32 val; in __read_lock_failed() local
83 val = __insn_fetchaddgez4(&rw->lock, 1); in __read_lock_failed()
84 } while (unlikely(arch_write_val_locked(val))); in __read_lock_failed()
94 void __write_lock_failed(arch_rwlock_t *rw, u32 val) in __write_lock_failed() argument
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| /linux-4.1.27/drivers/media/dvb-frontends/ |
| D | lgdt3306a.c | 117 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val) in lgdt3306a_write_reg() argument
120 u8 buf[] = { reg >> 8, reg & 0xff, val }; in lgdt3306a_write_reg()
126 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); in lgdt3306a_write_reg()
141 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val) in lgdt3306a_read_reg() argument
149 .flags = I2C_M_RD, .buf = val, .len = 1 }, in lgdt3306a_read_reg()
162 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val); in lgdt3306a_read_reg()
179 u8 val; in lgdt3306a_set_reg_bit() local
184 ret = lgdt3306a_read_reg(state, reg, &val); in lgdt3306a_set_reg_bit()
188 val &= ~(1 << bit); in lgdt3306a_set_reg_bit()
189 val |= (onoff & 1) << bit; in lgdt3306a_set_reg_bit()
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| D | lg2160.c | 67 static int lg216x_write_reg(struct lg216x_state *state, u16 reg, u8 val) in lg216x_write_reg() argument
70 u8 buf[] = { reg >> 8, reg & 0xff, val }; in lg216x_write_reg()
76 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); in lg216x_write_reg()
91 static int lg216x_read_reg(struct lg216x_state *state, u16 reg, u8 *val) in lg216x_read_reg() argument
99 .flags = I2C_M_RD, .buf = val, .len = 1 }, in lg216x_read_reg()
119 u8 val; member
130 ret = lg216x_write_reg(state, regs[i].reg, regs[i].val); in lg216x_write_regs()
140 u8 val; in lg216x_set_reg_bit() local
145 ret = lg216x_read_reg(state, reg, &val); in lg216x_set_reg_bit()
149 val &= ~(1 << bit); in lg216x_set_reg_bit()
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| D | cx22702.c | 129 u8 val; in cx22702_set_inversion() local
131 val = cx22702_readreg(state, 0x0C); in cx22702_set_inversion()
136 val |= 0x01; in cx22702_set_inversion()
139 val &= 0xfe; in cx22702_set_inversion()
144 return cx22702_writereg(state, 0x0C, val); in cx22702_set_inversion()
151 u8 val; in cx22702_get_tps() local
157 val = cx22702_readreg(state, 0x01); in cx22702_get_tps()
158 switch ((val & 0x18) >> 3) { in cx22702_get_tps()
169 switch (val & 0x07) { in cx22702_get_tps()
185 val = cx22702_readreg(state, 0x02); in cx22702_get_tps()
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| D | lgdt3305.c | 115 static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val) in lgdt3305_write_reg() argument
118 u8 buf[] = { reg >> 8, reg & 0xff, val }; in lgdt3305_write_reg()
124 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); in lgdt3305_write_reg()
139 static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val) in lgdt3305_read_reg() argument
147 .flags = I2C_M_RD, .buf = val, .len = 1 }, in lgdt3305_read_reg()
177 u8 val; in lgdt3305_set_reg_bit() local
182 ret = lgdt3305_read_reg(state, reg, &val); in lgdt3305_set_reg_bit()
186 val &= ~(1 << bit); in lgdt3305_set_reg_bit()
187 val |= (onoff & 1) << bit; in lgdt3305_set_reg_bit()
189 ret = lgdt3305_write_reg(state, reg, val); in lgdt3305_set_reg_bit()
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| /linux-4.1.27/sound/soc/davinci/ |
| D | davinci-mcasp.h | 143 #define TXROT(val) (val) argument
145 #define TXSSZ(val) (val<<4) argument
146 #define TXPBIT(val) (val<<8) argument
147 #define TXPAD(val) (val<<13) argument
149 #define FSXDLY(val) (val<<16) argument
154 #define RXROT(val) (val) argument
156 #define RXSSZ(val) (val<<4) argument
157 #define RXPBIT(val) (val<<8) argument
158 #define RXPAD(val) (val<<13) argument
160 #define FSRDLY(val) (val<<16) argument
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| /linux-4.1.27/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi.xml.h | 84 static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val) in HDMI_ACR_PKT_CTRL_SELECT() argument
86 return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK; in HDMI_ACR_PKT_CTRL_SELECT()
91 static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val) in HDMI_ACR_PKT_CTRL_N_MULTIPLIER() argument
93 return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK; in HDMI_ACR_PKT_CTRL_N_MULTIPLIER()
118 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val) in HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE() argument
120 …return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MA… in HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE()
126 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val) in HDMI_GEN_PKT_CTRL_GENERIC0_LINE() argument
128 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK; in HDMI_GEN_PKT_CTRL_GENERIC0_LINE()
132 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val) in HDMI_GEN_PKT_CTRL_GENERIC1_LINE() argument
134 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK; in HDMI_GEN_PKT_CTRL_GENERIC1_LINE()
[all …]
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| D | hdmi_phy_8960.c | 49 uint32_t val; member
257 unsigned int val; in hdmi_pll_enable() local
276 val = hdmi_read(hdmi, REG_HDMI_8960_PHY_REG12); in hdmi_pll_enable()
277 val |= HDMI_8960_PHY_REG12_SW_RESET; in hdmi_pll_enable()
279 hdmi_write(hdmi, REG_HDMI_8960_PHY_REG12, val); in hdmi_pll_enable()
280 val &= ~HDMI_8960_PHY_REG12_SW_RESET; in hdmi_pll_enable()
287 hdmi_write(hdmi, REG_HDMI_8960_PHY_REG12, val); in hdmi_pll_enable()
290 val = hdmi_read(hdmi, REG_HDMI_8960_PHY_REG12); in hdmi_pll_enable()
291 val |= HDMI_8960_PHY_REG12_PWRDN_B; in hdmi_pll_enable()
292 hdmi_write(hdmi, REG_HDMI_8960_PHY_REG12, val); in hdmi_pll_enable()
[all …]
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| /linux-4.1.27/include/linux/ |
| D | iopoll.h | 43 #define readx_poll_timeout(op, addr, val, cond, sleep_us, timeout_us) \ argument
48 (val) = op(addr); \
52 (val) = op(addr); \
78 #define readx_poll_timeout_atomic(op, addr, val, cond, delay_us, timeout_us) \ argument
82 (val) = op(addr); \
86 (val) = op(addr); \
96 #define readb_poll_timeout(addr, val, cond, delay_us, timeout_us) \ argument
97 readx_poll_timeout(readb, addr, val, cond, delay_us, timeout_us)
99 #define readb_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \ argument
100 readx_poll_timeout_atomic(readb, addr, val, cond, delay_us, timeout_us)
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| D | virtio_byteorder.h | 11 static inline u16 __virtio16_to_cpu(bool little_endian, __virtio16 val) in __virtio16_to_cpu() argument
14 return le16_to_cpu((__force __le16)val); in __virtio16_to_cpu()
16 return (__force u16)val; in __virtio16_to_cpu()
19 static inline __virtio16 __cpu_to_virtio16(bool little_endian, u16 val) in __cpu_to_virtio16() argument
22 return (__force __virtio16)cpu_to_le16(val); in __cpu_to_virtio16()
24 return (__force __virtio16)val; in __cpu_to_virtio16()
27 static inline u32 __virtio32_to_cpu(bool little_endian, __virtio32 val) in __virtio32_to_cpu() argument
30 return le32_to_cpu((__force __le32)val); in __virtio32_to_cpu()
32 return (__force u32)val; in __virtio32_to_cpu()
35 static inline __virtio32 __cpu_to_virtio32(bool little_endian, u32 val) in __cpu_to_virtio32() argument
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| D | property.h | 32 u8 *val, size_t nval);
34 u16 *val, size_t nval);
36 u32 *val, size_t nval);
38 u64 *val, size_t nval);
40 const char **val, size_t nval);
42 const char **val);
46 const char *propname, u8 *val,
49 const char *propname, u16 *val,
52 const char *propname, u32 *val,
55 const char *propname, u64 *val,
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| D | percpu-defs.h | 408 #define raw_cpu_write(pcp, val) __pcpu_size_call(raw_cpu_write_, pcp, val) argument
409 #define raw_cpu_add(pcp, val) __pcpu_size_call(raw_cpu_add_, pcp, val) argument
410 #define raw_cpu_and(pcp, val) __pcpu_size_call(raw_cpu_and_, pcp, val) argument
411 #define raw_cpu_or(pcp, val) __pcpu_size_call(raw_cpu_or_, pcp, val) argument
412 #define raw_cpu_add_return(pcp, val) __pcpu_size_call_return2(raw_cpu_add_return_, pcp, val) argument
419 #define raw_cpu_sub(pcp, val) raw_cpu_add(pcp, -(val)) argument
422 #define raw_cpu_sub_return(pcp, val) raw_cpu_add_return(pcp, -(typeof(pcp))(val)) argument
436 #define __this_cpu_write(pcp, val) \ argument
439 raw_cpu_write(pcp, val); \
442 #define __this_cpu_add(pcp, val) \ argument
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| /linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp5/ |
| D | mdp5.xml.h | 153 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) in MDSS_HW_VERSION_STEP() argument
155 return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK; in MDSS_HW_VERSION_STEP()
159 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) in MDSS_HW_VERSION_MINOR() argument
161 return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK; in MDSS_HW_VERSION_MINOR()
165 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) in MDSS_HW_VERSION_MAJOR() argument
167 return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK; in MDSS_HW_VERSION_MAJOR()
189 static inline uint32_t MDP5_MDP_HW_VERSION_STEP(uint32_t val) in MDP5_MDP_HW_VERSION_STEP() argument
191 return ((val) << MDP5_MDP_HW_VERSION_STEP__SHIFT) & MDP5_MDP_HW_VERSION_STEP__MASK; in MDP5_MDP_HW_VERSION_STEP()
195 static inline uint32_t MDP5_MDP_HW_VERSION_MINOR(uint32_t val) in MDP5_MDP_HW_VERSION_MINOR() argument
197 return ((val) << MDP5_MDP_HW_VERSION_MINOR__SHIFT) & MDP5_MDP_HW_VERSION_MINOR__MASK; in MDP5_MDP_HW_VERSION_MINOR()
[all …]
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| /linux-4.1.27/arch/arm/mach-iop13xx/include/mach/ |
| D | time.h | 73 u32 val; in read_tmr0() local
74 asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val)); in read_tmr0()
75 return val; in read_tmr0()
78 static inline void write_tmr0(u32 val) in write_tmr0() argument
80 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); in write_tmr0()
83 static inline void write_tmr1(u32 val) in write_tmr1() argument
85 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val)); in write_tmr1()
90 u32 val; in read_tcr0() local
91 asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val)); in read_tcr0()
92 return val; in read_tcr0()
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| /linux-4.1.27/arch/alpha/include/uapi/asm/ |
| D | compiler.h | 13 # define __kernel_insbl(val, shift) __builtin_alpha_insbl(val, shift) argument
14 # define __kernel_inswl(val, shift) __builtin_alpha_inswl(val, shift) argument
15 # define __kernel_insql(val, shift) __builtin_alpha_insql(val, shift) argument
16 # define __kernel_inslh(val, shift) __builtin_alpha_inslh(val, shift) argument
17 # define __kernel_extbl(val, shift) __builtin_alpha_extbl(val, shift) argument
18 # define __kernel_extwl(val, shift) __builtin_alpha_extwl(val, shift) argument
21 # define __kernel_insbl(val, shift) \ argument
23 __asm__("insbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
25 # define __kernel_inswl(val, shift) \ argument
27 __asm__("inswl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \
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| /linux-4.1.27/arch/arm/mach-iop13xx/ |
| D | irq.c | 34 u32 val; in read_intctl_0() local
35 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val)); in read_intctl_0()
36 return val; in read_intctl_0()
38 static void write_intctl_0(u32 val) in write_intctl_0() argument
40 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val)); in write_intctl_0()
47 u32 val; in read_intctl_1() local
48 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val)); in read_intctl_1()
49 return val; in read_intctl_1()
51 static void write_intctl_1(u32 val) in write_intctl_1() argument
53 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val)); in write_intctl_1()
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| D | msi.c | 32 u32 val; in read_imipr_0() local
33 asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); in read_imipr_0()
34 return val; in read_imipr_0()
36 static void write_imipr_0(u32 val) in write_imipr_0() argument
38 asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); in write_imipr_0()
45 u32 val; in read_imipr_1() local
46 asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); in read_imipr_1()
47 return val; in read_imipr_1()
49 static void write_imipr_1(u32 val) in write_imipr_1() argument
51 asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); in write_imipr_1()
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| /linux-4.1.27/drivers/misc/cxl/ |
| D | pci.c | 55 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \ argument
56 pci_write_config_byte(dev, vsec + 0xa, val)
74 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \ argument
75 pci_write_config_byte(dev, vsec + 0x13, val)
93 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit))) argument
94 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be)) argument
97 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15) argument
98 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31) argument
99 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47) argument
100 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48) argument
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| /linux-4.1.27/arch/m32r/kernel/ |
| D | align.c | 12 int val; in get_reg() local
15 val = *(unsigned long *)(®s->r0 + nr); in get_reg()
17 val = *(unsigned long *)(®s->r4 + (nr - 4)); in get_reg()
19 val = *(unsigned long *)(®s->r7 + (nr - 7)); in get_reg()
21 val = *(unsigned long *)(®s->fp + (nr - 13)); in get_reg()
23 return val; in get_reg()
26 static void set_reg(struct pt_regs *regs, int nr, int val) in set_reg() argument
29 *(unsigned long *)(®s->r0 + nr) = val; in set_reg()
31 *(unsigned long *)(®s->r4 + (nr - 4)) = val; in set_reg()
33 *(unsigned long *)(®s->r7 + (nr - 7)) = val; in set_reg()
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| /linux-4.1.27/drivers/gpu/drm/gma500/ |
| D | oaktrail_lvds_i2c.c | 65 #define LPC_WRITE_REG(chan, r, val) outl((val), (chan)->reg + (r)) argument
70 u32 val, tmp; in get_clock() local
72 val = LPC_READ_REG(chan, RGIO); in get_clock()
73 val |= GPIO_CLOCK; in get_clock()
74 LPC_WRITE_REG(chan, RGIO, val); in get_clock()
76 val = (LPC_READ_REG(chan, RGLVL) & GPIO_CLOCK) ? 1 : 0; in get_clock()
78 return val; in get_clock()
84 u32 val, tmp; in get_data() local
86 val = LPC_READ_REG(chan, RGIO); in get_data()
87 val |= GPIO_DATA; in get_data()
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| /linux-4.1.27/arch/x86/kernel/ |
| D | quirks.c | 71 u32 val; in ich_force_hpet_resume() local
79 val = readl(rcba_base + 0x3404); in ich_force_hpet_resume()
80 if (!(val & 0x80)) { in ich_force_hpet_resume()
82 writel(val | 0x80, rcba_base + 0x3404); in ich_force_hpet_resume()
85 val = readl(rcba_base + 0x3404); in ich_force_hpet_resume()
86 if (!(val & 0x80)) in ich_force_hpet_resume()
96 u32 val; in ich_force_enable_hpet() local
120 val = readl(rcba_base + 0x3404); in ich_force_enable_hpet()
122 if (val & 0x80) { in ich_force_enable_hpet()
124 val = val & 0x3; in ich_force_enable_hpet()
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| /linux-4.1.27/drivers/gpu/drm/i915/ |
| D | intel_sideband.c | 43 u32 port, u32 opcode, u32 addr, u32 *val) in vlv_sideband_rw() argument
62 I915_WRITE(VLV_IOSF_DATA, *val); in vlv_sideband_rw()
72 *val = I915_READ(VLV_IOSF_DATA); in vlv_sideband_rw()
80 u32 val = 0; in vlv_punit_read() local
86 SB_CRRDDA_NP, addr, &val); in vlv_punit_read()
89 return val; in vlv_punit_read()
92 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val) in vlv_punit_write() argument
98 SB_CRWRDA_NP, addr, &val); in vlv_punit_write()
104 u32 val = 0; in vlv_bunit_read() local
107 SB_CRRDDA_NP, reg, &val); in vlv_bunit_read()
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| D | intel_hdmi.c | 140 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_write_infoframe() local
143 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); in g4x_write_infoframe()
145 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ in g4x_write_infoframe()
146 val |= g4x_infoframe_index(type); in g4x_write_infoframe()
148 val &= ~g4x_infoframe_enable(type); in g4x_write_infoframe()
150 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
162 val |= g4x_infoframe_enable(type); in g4x_write_infoframe()
163 val &= ~VIDEO_DIP_FREQ_MASK; in g4x_write_infoframe()
164 val |= VIDEO_DIP_FREQ_VSYNC; in g4x_write_infoframe()
166 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
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| D | dvo_ivch.c | 377 uint16_t val; in ivch_dump_regs() local
379 ivch_read(dvo, VR00, &val); in ivch_dump_regs()
380 DRM_DEBUG_KMS("VR00: 0x%04x\n", val); in ivch_dump_regs()
381 ivch_read(dvo, VR01, &val); in ivch_dump_regs()
382 DRM_DEBUG_KMS("VR01: 0x%04x\n", val); in ivch_dump_regs()
383 ivch_read(dvo, VR30, &val); in ivch_dump_regs()
384 DRM_DEBUG_KMS("VR30: 0x%04x\n", val); in ivch_dump_regs()
385 ivch_read(dvo, VR40, &val); in ivch_dump_regs()
386 DRM_DEBUG_KMS("VR40: 0x%04x\n", val); in ivch_dump_regs()
389 ivch_read(dvo, VR80, &val); in ivch_dump_regs()
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| /linux-4.1.27/drivers/watchdog/ |
| D | sp5100_tco.c | 78 u32 val; in tco_timer_start() local
82 val = readl(SP5100_WDT_CONTROL(tcobase)); in tco_timer_start()
83 val |= SP5100_WDT_START_STOP_BIT; in tco_timer_start()
84 writel(val, SP5100_WDT_CONTROL(tcobase)); in tco_timer_start()
90 u32 val; in tco_timer_stop() local
94 val = readl(SP5100_WDT_CONTROL(tcobase)); in tco_timer_stop()
95 val &= ~SP5100_WDT_START_STOP_BIT; in tco_timer_stop()
96 writel(val, SP5100_WDT_CONTROL(tcobase)); in tco_timer_stop()
102 u32 val; in tco_timer_keepalive() local
106 val = readl(SP5100_WDT_CONTROL(tcobase)); in tco_timer_keepalive()
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| D | nv_tco.c | 81 u32 val; in tco_timer_start() local
85 val = inl(TCO_CNT(tcobase)); in tco_timer_start()
86 val &= ~TCO_CNT_TCOHALT; in tco_timer_start()
87 outl(val, TCO_CNT(tcobase)); in tco_timer_start()
93 u32 val; in tco_timer_stop() local
97 val = inl(TCO_CNT(tcobase)); in tco_timer_stop()
98 val |= TCO_CNT_TCOHALT; in tco_timer_stop()
99 outl(val, TCO_CNT(tcobase)); in tco_timer_stop()
117 u8 val; in tco_timer_set_heartbeat() local
134 val = inb(TCO_TMR(tcobase)); in tco_timer_set_heartbeat()
[all …]
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| /linux-4.1.27/include/linux/mfd/ |
| D | ti_am335x_tscadc.h | 48 #define STEPENB(val) ((val) << 0) argument
49 #define ENB(val) (1 << (val)) argument
66 #define STEPCONFIG_MODE(val) ((val) << 0) argument
70 #define STEPCONFIG_AVG(val) ((val) << 2) argument
79 #define STEPCONFIG_INM(val) ((val) << 15) argument
82 #define STEPCONFIG_INP(val) ((val) << 19) argument
89 #define STEPDELAY_OPEN(val) ((val) << 0) argument
92 #define STEPDELAY_SAMPLE(val) ((val) << 24) argument
97 #define STEPCHARGE_RFP(val) ((val) << 12) argument
100 #define STEPCHARGE_INM(val) ((val) << 15) argument
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|
| /linux-4.1.27/arch/mips/bcm63xx/ |
| D | cs.c | 37 u32 val; in bcm63xx_set_cs_base() local
49 val = (base & MPI_CSBASE_BASE_MASK); in bcm63xx_set_cs_base()
51 val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT; in bcm63xx_set_cs_base()
54 bcm_mpi_writel(val, MPI_CSBASE_REG(cs)); in bcm63xx_set_cs_base()
69 u32 val; in bcm63xx_set_cs_timing() local
75 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); in bcm63xx_set_cs_timing()
76 val &= ~(MPI_CSCTL_WAIT_MASK); in bcm63xx_set_cs_timing()
77 val &= ~(MPI_CSCTL_SETUP_MASK); in bcm63xx_set_cs_timing()
78 val &= ~(MPI_CSCTL_HOLD_MASK); in bcm63xx_set_cs_timing()
79 val |= wait << MPI_CSCTL_WAIT_SHIFT; in bcm63xx_set_cs_timing()
[all …]
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| /linux-4.1.27/drivers/media/pci/cx18/ |
| D | cx18-io.c | 27 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count) in cx18_memset_io() argument
30 u16 val2 = val | (val << 8); in cx18_memset_io()
35 cx18_writeb(cx, (u8) val, dst); in cx18_memset_io()
55 cx18_writeb(cx, (u8) val, dst); in cx18_memset_io()
58 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) in cx18_sw1_irq_enable() argument
60 cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val); in cx18_sw1_irq_enable()
61 cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val; in cx18_sw1_irq_enable()
65 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val) in cx18_sw1_irq_disable() argument
67 cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val; in cx18_sw1_irq_disable()
71 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val) in cx18_sw2_irq_enable() argument
[all …]
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| D | cx18-io.h | 44 void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_raw_writel_noretry() argument
46 __raw_writel(val, addr); in cx18_raw_writel_noretry()
49 static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_raw_writel() argument
53 cx18_raw_writel_noretry(cx, val, addr); in cx18_raw_writel()
54 if (val == cx18_raw_readl(cx, addr)) in cx18_raw_writel()
66 void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_writel_noretry() argument
68 writel(val, addr); in cx18_writel_noretry()
71 static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_writel() argument
75 cx18_writel_noretry(cx, val, addr); in cx18_writel()
76 if (val == cx18_readl(cx, addr)) in cx18_writel()
[all …]
|
| /linux-4.1.27/drivers/gpu/drm/msm/edp/ |
| D | edp.xml.h | 82 static inline uint32_t EDP_CONFIGURATION_CTRL_LANES(uint32_t val) in EDP_CONFIGURATION_CTRL_LANES() argument
84 return ((val) << EDP_CONFIGURATION_CTRL_LANES__SHIFT) & EDP_CONFIGURATION_CTRL_LANES__MASK; in EDP_CONFIGURATION_CTRL_LANES()
89 static inline uint32_t EDP_CONFIGURATION_CTRL_COLOR(enum edp_color_depth val) in EDP_CONFIGURATION_CTRL_COLOR() argument
91 return ((val) << EDP_CONFIGURATION_CTRL_COLOR__SHIFT) & EDP_CONFIGURATION_CTRL_COLOR__MASK; in EDP_CONFIGURATION_CTRL_COLOR()
101 static inline uint32_t EDP_TOTAL_HOR_VER_HORIZ(uint32_t val) in EDP_TOTAL_HOR_VER_HORIZ() argument
103 return ((val) << EDP_TOTAL_HOR_VER_HORIZ__SHIFT) & EDP_TOTAL_HOR_VER_HORIZ__MASK; in EDP_TOTAL_HOR_VER_HORIZ()
107 static inline uint32_t EDP_TOTAL_HOR_VER_VERT(uint32_t val) in EDP_TOTAL_HOR_VER_VERT() argument
109 return ((val) << EDP_TOTAL_HOR_VER_VERT__SHIFT) & EDP_TOTAL_HOR_VER_VERT__MASK; in EDP_TOTAL_HOR_VER_VERT()
115 static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_HORIZ(uint32_t val) in EDP_START_HOR_VER_FROM_SYNC_HORIZ() argument
117 …return ((val) << EDP_START_HOR_VER_FROM_SYNC_HORIZ__SHIFT) & EDP_START_HOR_VER_FROM_SYNC_HORIZ__MA… in EDP_START_HOR_VER_FROM_SYNC_HORIZ()
[all …]
|
| /linux-4.1.27/scripts/dtc/libfdt/ |
| D | libfdt.h | 157 static inline void fdt_set_##name(void *fdt, uint32_t val) \
160 fdth->name = cpu_to_fdt32(val); \
852 const void *val, int len);
883 const char *name, uint32_t val) in fdt_setprop_inplace_u32() argument
885 val = cpu_to_fdt32(val); in fdt_setprop_inplace_u32()
886 return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val)); in fdt_setprop_inplace_u32()
918 const char *name, uint64_t val) in fdt_setprop_inplace_u64() argument
920 val = cpu_to_fdt64(val); in fdt_setprop_inplace_u64()
921 return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val)); in fdt_setprop_inplace_u64()
930 const char *name, uint32_t val) in fdt_setprop_inplace_cell() argument
[all …]
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| /linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/pinctrl/ |
| D | omap.h | 58 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) argument
59 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
60 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
61 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) argument
62 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) argument
63 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) argument
64 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
65 #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
66 #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
67 #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val) argument
[all …]
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| /linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/pinctrl/ |
| D | omap.h | 58 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) argument
59 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
60 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
61 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) argument
62 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) argument
63 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) argument
64 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
65 #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
66 #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
67 #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val) argument
[all …]
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| /linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/pinctrl/ |
| D | omap.h | 58 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) argument
59 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
60 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
61 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) argument
62 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) argument
63 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) argument
64 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
65 #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
66 #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
67 #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val) argument
[all …]
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| /linux-4.1.27/include/dt-bindings/pinctrl/ |
| D | omap.h | 58 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) argument
59 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
60 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
61 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) argument
62 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) argument
63 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) argument
64 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
65 #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
66 #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
67 #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val) argument
[all …]
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| /linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/pinctrl/ |
| D | omap.h | 58 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) argument
59 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
60 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
61 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) argument
62 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) argument
63 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) argument
64 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
65 #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
66 #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
67 #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val) argument
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| /linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/pinctrl/ |
| D | omap.h | 58 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) argument
59 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
60 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) argument
61 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) argument
62 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) argument
63 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) argument
64 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
65 #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
66 #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) argument
67 #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val) argument
[all …]
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| /linux-4.1.27/drivers/net/ethernet/chelsio/cxgb/ |
| D | my3126.c | 38 u32 val; in my3126_interrupt_handler() local
46 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); in my3126_interrupt_handler()
47 val16 = (u16) val; in my3126_interrupt_handler()
65 OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW), &val); in my3126_interrupt_handler()
66 act_count += val; in my3126_interrupt_handler()
69 t1_tpi_read(adapter, A_ELMER0_GPO, &val); in my3126_interrupt_handler()
70 cphy->elmer_gpo = val; in my3126_interrupt_handler()
72 if ( (val & (1 << 8)) || (val & (1 << 19)) || in my3126_interrupt_handler()
75 val |= (1 << 9); in my3126_interrupt_handler()
77 val |= (1 << 20); in my3126_interrupt_handler()
[all …]
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| D | mv88x201x.c | 121 u32 val; in mv88x201x_interrupt_clear() local
125 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val); in mv88x201x_interrupt_clear()
126 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val); in mv88x201x_interrupt_clear()
127 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val); in mv88x201x_interrupt_clear()
132 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); in mv88x201x_interrupt_clear()
136 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); in mv88x201x_interrupt_clear()
138 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val); in mv88x201x_interrupt_clear()
142 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val); in mv88x201x_interrupt_clear()
143 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val); in mv88x201x_interrupt_clear()
174 u32 val = 0; in mv88x201x_get_link_status() local
[all …]
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| /linux-4.1.27/arch/score/include/asm/ |
| D | tlbflush.h | 38 unsigned long val; in pevn_get() local
43 : "=r" (val)); in pevn_get()
45 return val; in pevn_get()
48 static inline void pevn_set(unsigned long val) in pevn_set() argument
53 : : "r" (val)); in pevn_set()
56 static inline void pectx_set(unsigned long val) in pectx_set() argument
61 : : "r" (val)); in pectx_set()
66 unsigned long val; in pectx_get() local
70 : "=r" (val)); in pectx_get()
71 return val; in pectx_get()
[all …]
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| /linux-4.1.27/sound/soc/nuc900/ |
| D | nuc900-ac97.c | 48 unsigned long timeout = 0x10000, val; in nuc900_ac97_read() local
52 val = nuc900_checkready(); in nuc900_ac97_read()
53 if (val) { in nuc900_ac97_read()
62 val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0); in nuc900_ac97_read()
63 val |= (VALID_FRAME | SLOT1_VALID); in nuc900_ac97_read()
64 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, val); in nuc900_ac97_read()
75 val = -EPERM; in nuc900_ac97_read()
79 val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0) ; in nuc900_ac97_read()
80 val &= ~SLOT1_VALID; in nuc900_ac97_read()
81 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, val); in nuc900_ac97_read()
[all …]
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| D | nuc900-pcm.c | 70 unsigned long val; in nuc900_dma_start() local
72 val = AUDIO_READ(nuc900_audio->mmio + ACTL_CON); in nuc900_dma_start()
73 val |= (T_DMA_IRQ | R_DMA_IRQ); in nuc900_dma_start()
74 AUDIO_WRITE(nuc900_audio->mmio + ACTL_CON, val); in nuc900_dma_start()
81 unsigned long val; in nuc900_dma_stop() local
83 val = AUDIO_READ(nuc900_audio->mmio + ACTL_CON); in nuc900_dma_stop()
84 val &= ~(T_DMA_IRQ | R_DMA_IRQ); in nuc900_dma_stop()
85 AUDIO_WRITE(nuc900_audio->mmio + ACTL_CON, val); in nuc900_dma_stop()
92 unsigned long val; in nuc900_dma_interrupt() local
96 val = AUDIO_READ(nuc900_audio->mmio + ACTL_CON); in nuc900_dma_interrupt()
[all …]
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| /linux-4.1.27/drivers/pci/host/ |
| D | pci-exynos.c | 105 static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg) in exynos_elb_writel() argument
107 writel(val, pcie->elbi_base + reg); in exynos_elb_writel()
115 static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg) in exynos_phy_writel() argument
117 writel(val, pcie->phy_base + reg); in exynos_phy_writel()
125 static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg) in exynos_blk_writel() argument
127 writel(val, pcie->block_base + reg); in exynos_blk_writel()
137 u32 val; in exynos_pcie_sideband_dbi_w_mode() local
141 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC); in exynos_pcie_sideband_dbi_w_mode()
142 val |= PCIE_ELBI_SLV_DBI_ENABLE; in exynos_pcie_sideband_dbi_w_mode()
143 exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC); in exynos_pcie_sideband_dbi_w_mode()
[all …]
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| /linux-4.1.27/include/trace/events/ |
| D | intel-sst.h | 20 TP_PROTO(unsigned int val),
22 TP_ARGS(val),
25 __field( unsigned int, val )
29 __entry->val = val;
32 TP_printk("0x%8.8x", (unsigned int)__entry->val)
37 TP_PROTO(unsigned int val),
39 TP_ARGS(val)
45 TP_PROTO(unsigned int val),
47 TP_ARGS(val)
53 TP_PROTO(unsigned int offset, unsigned int val),
[all …]
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| D | asoc.h | 20 TP_PROTO(struct snd_soc_card *card, int val),
22 TP_ARGS(card, val),
26 __field( int, val )
31 __entry->val = val;
34 TP_printk("card=%s val=%d", __get_str(name), (int)__entry->val)
39 TP_PROTO(struct snd_soc_card *card, int val),
41 TP_ARGS(card, val)
47 TP_PROTO(struct snd_soc_card *card, int val),
49 TP_ARGS(card, val)
88 TP_PROTO(struct snd_soc_dapm_widget *w, int val),
[all …]
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| /linux-4.1.27/sound/pcmcia/pdaudiocf/ |
| D | pdaudiocf_core.c | 63 static void pdacf_ak4117_write(void *private_data, unsigned char reg, unsigned char val) in pdacf_ak4117_write() argument
79 outw((u16)reg << 8 | val | (1<<13), chip->port + PDAUDIOCF_REG_AK_IFR); in pdacf_ak4117_write()
106 u16 val; in pdacf_reset() local
108 val = pdacf_reg_read(chip, PDAUDIOCF_REG_SCR); in pdacf_reset()
109 val |= PDAUDIOCF_PDN; in pdacf_reset()
110 val &= ~PDAUDIOCF_RECORD; /* for sure */ in pdacf_reset()
111 pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); in pdacf_reset()
113 val |= PDAUDIOCF_RST; in pdacf_reset()
114 pdacf_reg_write(chip, PDAUDIOCF_REG_SCR, val); in pdacf_reset()
116 val &= ~PDAUDIOCF_RST; in pdacf_reset()
[all …]
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| /linux-4.1.27/drivers/net/wireless/iwlwifi/ |
| D | iwl-devtrace-io.h | 36 TP_PROTO(const struct device *dev, u32 offs, u32 val),
37 TP_ARGS(dev, offs, val),
41 __field(u32, val)
46 __entry->val = val;
49 __get_str(dev), __entry->offs, __entry->val)
53 TP_PROTO(const struct device *dev, u32 offs, u8 val),
54 TP_ARGS(dev, offs, val),
58 __field(u8, val)
63 __entry->val = val;
66 __get_str(dev), __entry->offs, __entry->val)
[all …]
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| /linux-4.1.27/drivers/net/irda/ |
| D | via-ircc.h | 160 #define GetBit(val,bit) val = (unsigned char) ((val>>bit) & 0x1) argument
162 #define SetBit(val,bit) val= (unsigned char ) (val | (0x1 << bit)) argument
164 #define ResetBit(val,bit) val= (unsigned char ) (val & ~(0x1 << bit)) argument
318 #define CRC16(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,7,val) //0 for 32 CRC argument
325 #define SIRFilter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,3,val) argument
326 #define Filter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,2,val) argument
327 #define InvertTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,1,val) argument
328 #define InvertRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,0,val) argument
330 #define EnableTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,4,val) argument
331 #define EnableRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,3,val) argument
[all …]
|
| /linux-4.1.27/drivers/gpu/host1x/hw/ |
| D | debug_hw.c | 41 static unsigned int show_channel_command(struct output *o, u32 val) in show_channel_command() argument
46 switch (val >> 28) { in show_channel_command()
48 mask = val & 0x3f; in show_channel_command()
51 val >> 6 & 0x3ff, in show_channel_command()
52 val >> 16 & 0xfff, mask); in show_channel_command()
56 val >> 6 & 0x3ff); in show_channel_command()
62 val >> 16 & 0xfff); in show_channel_command()
63 return val & 0xffff; in show_channel_command()
67 val >> 16 & 0xfff); in show_channel_command()
68 return val & 0xffff; in show_channel_command()
[all …]
|
| /linux-4.1.27/drivers/media/pci/bt8xx/ |
| D | bttv-audio-hook.c | 78 unsigned int val, con; in gvbctv5pci_audio() local
83 val = gpio_read(); in gvbctv5pci_audio()
96 if (con != (val & 0x300)) { in gvbctv5pci_audio()
102 switch (val & 0x70) { in gvbctv5pci_audio()
145 int val = 0; in avermedia_tvphone_audio() local
149 val = 0x02; in avermedia_tvphone_audio()
151 val = 0x01; in avermedia_tvphone_audio()
152 if (val) { in avermedia_tvphone_audio()
153 gpio_bits(0x03,val); in avermedia_tvphone_audio()
167 int val = 0; in avermedia_tv_stereo_audio() local
[all …]
|
| /linux-4.1.27/drivers/video/fbdev/ |
| D | gbefb.c | 209 unsigned int val, x, y, vpixen_off; in gbe_turn_off() local
214 val = gbe->vt_xy; in gbe_turn_off()
215 if (GET_GBE_FIELD(VT_XY, FREEZE, val) == 1) in gbe_turn_off()
219 val = gbe->ovr_control; in gbe_turn_off()
220 SET_GBE_FIELD(OVR_CONTROL, OVR_DMA_ENABLE, val, 0); in gbe_turn_off()
221 gbe->ovr_control = val; in gbe_turn_off()
223 val = gbe->frm_control; in gbe_turn_off()
224 SET_GBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, val, 0); in gbe_turn_off()
225 gbe->frm_control = val; in gbe_turn_off()
227 val = gbe->did_control; in gbe_turn_off()
[all …]
|
| /linux-4.1.27/drivers/clk/tegra/ |
| D | clk-pll.c | 191 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) argument
192 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) argument
193 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) argument
194 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset) argument
225 u32 val; in clk_pll_enable_lock() local
233 val = pll_readl_misc(pll); in clk_pll_enable_lock()
234 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
235 pll_writel_misc(val, pll); in clk_pll_enable_lock()
241 u32 val, lock_mask; in clk_pll_wait_for_lock() local
258 val = readl_relaxed(lock_addr); in clk_pll_wait_for_lock()
[all …]
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| /linux-4.1.27/drivers/tty/serial/ |
| D | bcm63xx_uart.c | 97 unsigned int val; in bcm_uart_tx_empty() local
99 val = bcm_uart_readl(port, UART_IR_REG); in bcm_uart_tx_empty()
100 return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0; in bcm_uart_tx_empty()
108 unsigned int val; in bcm_uart_set_mctrl() local
110 val = bcm_uart_readl(port, UART_MCTL_REG); in bcm_uart_set_mctrl()
111 val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK); in bcm_uart_set_mctrl()
114 val |= UART_MCTL_DTR_MASK; in bcm_uart_set_mctrl()
116 val |= UART_MCTL_RTS_MASK; in bcm_uart_set_mctrl()
117 bcm_uart_writel(port, val, UART_MCTL_REG); in bcm_uart_set_mctrl()
119 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_set_mctrl()
[all …]
|
| /linux-4.1.27/arch/s390/kernel/ |
| D | module.c | 170 static int apply_rela_bits(Elf_Addr loc, Elf_Addr val, in apply_rela_bits() argument
176 if (val & ((1UL << shift) - 1)) in apply_rela_bits()
179 val = (Elf_Addr)(((long) val) >> shift); in apply_rela_bits()
182 if ((long) val < min || (long) val > max) in apply_rela_bits()
185 val >>= shift; in apply_rela_bits()
187 if ((unsigned long) val > umax) in apply_rela_bits()
192 *(unsigned char *) loc = val; in apply_rela_bits()
194 *(unsigned short *) loc = (val & 0xfff) | in apply_rela_bits()
197 *(unsigned short *) loc = val; in apply_rela_bits()
199 *(unsigned int *) loc = (val & 0xfff) << 16 | in apply_rela_bits()
[all …]
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| /linux-4.1.27/arch/sparc/kernel/ |
| D | pcr.c | 56 u64 val; in direct_pcr_read() local
59 __asm__ __volatile__("rd %%pcr, %0" : "=r" (val)); in direct_pcr_read()
60 return val; in direct_pcr_read()
63 static void direct_pcr_write(unsigned long reg_num, u64 val) in direct_pcr_write() argument
66 __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (val)); in direct_pcr_write()
71 u64 val; in direct_pic_read() local
74 __asm__ __volatile__("rd %%pic, %0" : "=r" (val)); in direct_pic_read()
75 return val; in direct_pic_read()
78 static void direct_pic_write(unsigned long reg_num, u64 val) in direct_pic_write() argument
90 "rd %%pic, %%g0" : : "r" (val)); in direct_pic_write()
[all …]
|
| /linux-4.1.27/drivers/staging/comedi/drivers/ |
| D | c6xdigio.c | 73 unsigned int val, unsigned int status) in c6xdigio_write_data() argument
75 outb_p(val, dev->iobase + C6XDIGIO_DATA_REG); in c6xdigio_write_data()
84 unsigned int val; in c6xdigio_get_encoder_bits() local
86 val = inb(dev->iobase + C6XDIGIO_STATUS_REG); in c6xdigio_get_encoder_bits()
87 val >>= 3; in c6xdigio_get_encoder_bits()
88 val &= 0x07; in c6xdigio_get_encoder_bits()
90 *bits = val; in c6xdigio_get_encoder_bits()
96 unsigned int chan, unsigned int val) in c6xdigio_pwm_write() argument
101 if (val > 498) in c6xdigio_pwm_write()
102 val = 498; in c6xdigio_pwm_write()
[all …]
|
| /linux-4.1.27/arch/powerpc/platforms/cell/ |
| D | pmu.c | 55 #define READ_SHADOW_REG(val, reg) \ argument
59 (val) = shadow_regs->reg; \
62 #define READ_MMIO_UPPER32(val, reg) \ argument
66 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \
76 u32 val_in_latch, val = 0; in cbe_read_phys_ctr() local
83 READ_SHADOW_REG(val, pm_ctr[phys_ctr]); in cbe_read_phys_ctr()
85 READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]); in cbe_read_phys_ctr()
89 return val; in cbe_read_phys_ctr()
93 void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val) in cbe_write_phys_ctr() argument
103 WRITE_WO_MMIO(pm_ctr[phys_ctr], val); in cbe_write_phys_ctr()
[all …]
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| /linux-4.1.27/arch/m68k/atari/ |
| D | time.c | 63 static void mste_read(struct MSTE_RTC *val) in mste_read() argument
65 #define COPY(v) val->v=(mste_rtc.v & 0xf) in mste_read()
73 } while (val->sec_ones != (mste_rtc.sec_ones & 0xf)); in mste_read()
77 static void mste_write(struct MSTE_RTC *val) in mste_write() argument
79 #define COPY(v) mste_rtc.v=val->v in mste_write()
87 } while (val->sec_ones != (mste_rtc.sec_ones & 0xf)); in mste_write()
98 #define RTC_WRITE(reg,val) \ argument
101 tt_rtc.data = (val); \
111 struct MSTE_RTC val; in atari_mste_hwclk() local
120 val.sec_ones = t->tm_sec % 10; in atari_mste_hwclk()
[all …]
|
| /linux-4.1.27/include/video/ |
| D | vga.h | 207 static inline void vga_io_w (unsigned short port, unsigned char val) in vga_io_w() argument
209 outb_p(val, port); in vga_io_w()
213 unsigned char val) in vga_io_w_fast() argument
215 outw(VGA_OUT16VAL (val, reg), port); in vga_io_w_fast()
223 static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val) in vga_mm_w() argument
225 writeb (val, regbase + port); in vga_mm_w()
229 unsigned char reg, unsigned char val) in vga_mm_w_fast() argument
231 writew (VGA_OUT16VAL (val, reg), regbase + port); in vga_mm_w_fast()
242 static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val) in vga_w() argument
245 vga_mm_w (regbase, port, val); in vga_w()
[all …]
|
| /linux-4.1.27/drivers/media/i2c/s5c73m3/ |
| D | s5c73m3-ctrls.c | 49 ctrl->val = V4L2_AUTO_FOCUS_STATUS_BUSY; in s5c73m3_get_af_status()
53 ctrl->val = V4L2_AUTO_FOCUS_STATUS_REACHED; in s5c73m3_get_af_status()
61 ctrl->val = V4L2_AUTO_FOCUS_STATUS_FAILED; in s5c73m3_get_af_status()
88 static int s5c73m3_set_colorfx(struct s5c73m3 *state, int val) in s5c73m3_set_colorfx() argument
100 if (colorfx[i][0] != val) in s5c73m3_set_colorfx()
123 switch (ctrls->exposure_metering->val) { in s5c73m3_set_exposure()
139 u16 exp_bias = ctrls->exposure_bias->val; in s5c73m3_set_exposure()
145 ctrls->exposure_bias->val, ctrls->exposure_metering->val, ret); in s5c73m3_set_exposure()
150 static int s5c73m3_set_white_balance(struct s5c73m3 *state, int val) in s5c73m3_set_white_balance() argument
163 if (wb[i][0] != val) in s5c73m3_set_white_balance()
[all …]
|
| /linux-4.1.27/arch/arm/kernel/ |
| D | perf_event_xscale.c | 99 u32 val; in xscale1pmu_read_pmnc() local
100 asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val)); in xscale1pmu_read_pmnc()
101 return val; in xscale1pmu_read_pmnc()
105 xscale1pmu_write_pmnc(u32 val) in xscale1pmu_write_pmnc() argument
108 val &= 0xffff77f; in xscale1pmu_write_pmnc()
109 asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val)); in xscale1pmu_write_pmnc()
198 unsigned long val, mask, evt, flags; in xscale1pmu_enable_event() local
225 val = xscale1pmu_read_pmnc(); in xscale1pmu_enable_event()
226 val &= ~mask; in xscale1pmu_enable_event()
227 val |= evt; in xscale1pmu_enable_event()
[all …]
|
| /linux-4.1.27/drivers/staging/media/davinci_vpfe/ |
| D | dm365_ipipe_hw.c | 40 u32 val; in rsz_set_common_params() local
46 val = (rsz_common->passthrough << RSZ_BYPASS_SHIFT) | in rsz_set_common_params()
48 regw_rsz(rsz_base, val, RSZ_SRC_FMT0); in rsz_set_common_params()
51 val = (rsz_common->raw_flip & 1) | in rsz_set_common_params()
54 regw_rsz(rsz_base, val, RSZ_SRC_FMT1); in rsz_set_common_params()
76 u32 val; in rsz_set_rsz_regs() local
83 val = rsc_params->h_flip << RSZA_H_FLIP_SHIFT; in rsz_set_rsz_regs()
84 val |= rsc_params->v_flip << RSZA_V_FLIP_SHIFT; in rsz_set_rsz_regs()
87 val = rsc_params->h_flip << RSZB_H_FLIP_SHIFT; in rsz_set_rsz_regs()
88 val |= rsc_params->v_flip << RSZB_V_FLIP_SHIFT; in rsz_set_rsz_regs()
[all …]
|
| /linux-4.1.27/arch/arm/mach-davinci/ |
| D | pm.c | 42 unsigned val; in davinci_pm_suspend() local
47 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
48 val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); in davinci_pm_suspend()
49 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
54 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
55 val |= PLLCTL_PLLPWRDN; in davinci_pm_suspend()
56 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
60 val = __raw_readl(pdata->deepsleep_reg); in davinci_pm_suspend()
61 val &= ~DEEPSLEEP_SLEEPCOUNT_MASK, in davinci_pm_suspend()
62 val |= pdata->sleepcount; in davinci_pm_suspend()
[all …]
|
| /linux-4.1.27/arch/arm/mach-rpc/ |
| D | irq.c | 12 unsigned int val, mask; in iomd_ack_irq_a() local
15 val = iomd_readb(IOMD_IRQMASKA); in iomd_ack_irq_a()
16 iomd_writeb(val & ~mask, IOMD_IRQMASKA); in iomd_ack_irq_a()
22 unsigned int val, mask; in iomd_mask_irq_a() local
25 val = iomd_readb(IOMD_IRQMASKA); in iomd_mask_irq_a()
26 iomd_writeb(val & ~mask, IOMD_IRQMASKA); in iomd_mask_irq_a()
31 unsigned int val, mask; in iomd_unmask_irq_a() local
34 val = iomd_readb(IOMD_IRQMASKA); in iomd_unmask_irq_a()
35 iomd_writeb(val | mask, IOMD_IRQMASKA); in iomd_unmask_irq_a()
46 unsigned int val, mask; in iomd_mask_irq_b() local
[all …]
|
| /linux-4.1.27/arch/arm/mach-hisi/ |
| D | hotplug.c | 81 u32 val = 0; in set_cpu_hi3620() local
94 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN in set_cpu_hi3620()
96 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
98 val |= CPU0_HPM_SRST_REQ_EN; in set_cpu_hi3620()
99 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); in set_cpu_hi3620()
108 val = readl_relaxed(ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
109 val &= ~(CPU0_WFI_MASK_CFG << cpu); in set_cpu_hi3620()
110 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
113 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN in set_cpu_hi3620()
115 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
[all …]
|
| /linux-4.1.27/arch/arm64/kernel/ |
| D | module.c | 49 static u64 do_reloc(enum aarch64_reloc_op reloc_op, void *place, u64 val) in do_reloc() argument
53 return val; in do_reloc()
55 return val - (u64)place; in do_reloc()
57 return (val & ~0xfff) - ((u64)place & ~0xfff); in do_reloc()
66 static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len) in reloc_data() argument
69 s64 sval = do_reloc(op, place, val); in reloc_data()
103 static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val, in reloc_insn_movw() argument
110 sval = do_reloc(op, place, val); in reloc_insn_movw()
161 static int reloc_insn_imm(enum aarch64_reloc_op op, void *place, u64 val, in reloc_insn_imm() argument
169 sval = do_reloc(op, place, val); in reloc_insn_imm()
[all …]
|
| /linux-4.1.27/arch/c6x/include/uapi/asm/ |
| D | swab.h | 12 static inline __attribute_const__ __u16 __c6x_swab16(__u16 val) in __c6x_swab16() argument
14 asm("swap4 .l1 %0,%0\n" : "+a"(val)); in __c6x_swab16()
15 return val; in __c6x_swab16()
18 static inline __attribute_const__ __u32 __c6x_swab32(__u32 val) in __c6x_swab32() argument
22 : "+a"(val)); in __c6x_swab32()
23 return val; in __c6x_swab32()
26 static inline __attribute_const__ __u64 __c6x_swab64(__u64 val) in __c6x_swab64() argument
32 : "+a"(val)); in __c6x_swab64()
33 return val; in __c6x_swab64()
36 static inline __attribute_const__ __u32 __c6x_swahw32(__u32 val) in __c6x_swahw32() argument
[all …]
|
| /linux-4.1.27/lib/ |
| D | clz_ctz.c | 19 int __weak __ctzsi2(int val);
20 int __weak __ctzsi2(int val) in __ctzsi2() argument
22 return __ffs(val); in __ctzsi2()
26 int __weak __clzsi2(int val);
27 int __weak __clzsi2(int val) in __clzsi2() argument
29 return 32 - fls(val); in __clzsi2()
33 int __weak __clzdi2(long val);
34 int __weak __ctzdi2(long val);
37 int __weak __clzdi2(long val) in __clzdi2() argument
39 return 32 - fls((int)val); in __clzdi2()
[all …]
|
| /linux-4.1.27/drivers/media/i2c/smiapp/ |
| D | smiapp-regs.c | 76 u16 len, u32 *val) in ____smiapp_read() argument
108 *val = 0; in ____smiapp_read()
112 *val = (data[0] << 24) + (data[1] << 16) + (data[2] << 8) + in ____smiapp_read()
116 *val = (data[0] << 8) + data[1]; in ____smiapp_read()
119 *val = data[0]; in ____smiapp_read()
135 u16 len, u32 *val) in ____smiapp_read_8only() argument
140 *val = 0; in ____smiapp_read_8only()
148 *val |= val8 << ((len - i - 1) << 3); in ____smiapp_read_8only()
158 static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val, in __smiapp_read() argument
170 rval = ____smiapp_read(sensor, SMIAPP_REG_ADDR(reg), len, val); in __smiapp_read()
[all …]
|
| /linux-4.1.27/drivers/char/hw_random/ |
| D | iproc-rng200.c | 59 uint32_t val; in iproc_rng200_restart() local
62 val = ioread32(rng_base + RNG_CTRL_OFFSET); in iproc_rng200_restart()
63 val &= ~RNG_CTRL_RNG_RBGEN_MASK; in iproc_rng200_restart()
64 val |= RNG_CTRL_RNG_RBGEN_DISABLE; in iproc_rng200_restart()
65 iowrite32(val, rng_base + RNG_CTRL_OFFSET); in iproc_rng200_restart()
71 val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET); in iproc_rng200_restart()
72 val |= RBG_SOFT_RESET; in iproc_rng200_restart()
73 iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET); in iproc_rng200_restart()
75 val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET); in iproc_rng200_restart()
76 val |= RNG_SOFT_RESET; in iproc_rng200_restart()
[all …]
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| D | xgene-rng.c | 135 u32 val; in xgene_rng_chk_overflow() local
137 val = readl(ctx->csr_base + RNG_INTR_STS_ACK); in xgene_rng_chk_overflow()
138 if (val & MONOBIT_FAIL_MASK) in xgene_rng_chk_overflow()
144 dev_err(ctx->dev, "test monobit failure error 0x%08X\n", val); in xgene_rng_chk_overflow()
145 if (val & POKER_FAIL_MASK) in xgene_rng_chk_overflow()
152 dev_err(ctx->dev, "test poker failure error 0x%08X\n", val); in xgene_rng_chk_overflow()
153 if (val & LONG_RUN_FAIL_MASK) in xgene_rng_chk_overflow()
158 dev_err(ctx->dev, "test long run failure error 0x%08X\n", val); in xgene_rng_chk_overflow()
159 if (val & RUN_FAIL_MASK) in xgene_rng_chk_overflow()
165 dev_err(ctx->dev, "test run failure error 0x%08X\n", val); in xgene_rng_chk_overflow()
[all …]
|
| /linux-4.1.27/tools/lib/traceevent/ |
| D | plugin_sched_switch.c | 26 static void write_state(struct trace_seq *s, int val) in write_state() argument
33 if (!(val & (1 << i))) in write_state()
72 unsigned long long val; in sched_wakeup_handler() local
74 if (pevent_get_field_val(s, event, "pid", record, &val, 1)) in sched_wakeup_handler()
79 write_and_save_comm(field, record, s, val); in sched_wakeup_handler()
82 trace_seq_printf(s, "%lld", val); in sched_wakeup_handler()
84 if (pevent_get_field_val(s, event, "prio", record, &val, 0) == 0) in sched_wakeup_handler()
85 trace_seq_printf(s, " [%lld]", val); in sched_wakeup_handler()
87 if (pevent_get_field_val(s, event, "success", record, &val, 1) == 0) in sched_wakeup_handler()
88 trace_seq_printf(s, " success=%lld", val); in sched_wakeup_handler()
[all …]
|
| /linux-4.1.27/drivers/clk/pistachio/ |
| D | clk-pll.c | 65 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) in pll_writel() argument
67 writel(val, pll->base + reg); in pll_writel()
115 u32 val; in pll_gf40lp_frac_enable() local
117 val = pll_readl(pll, PLL_CTRL3); in pll_gf40lp_frac_enable()
118 val &= ~(PLL_FRAC_CTRL3_PD | PLL_FRAC_CTRL3_FOUTPOSTDIVPD | in pll_gf40lp_frac_enable()
120 pll_writel(pll, val, PLL_CTRL3); in pll_gf40lp_frac_enable()
122 val = pll_readl(pll, PLL_CTRL4); in pll_gf40lp_frac_enable()
123 val &= ~PLL_FRAC_CTRL4_BYPASS; in pll_gf40lp_frac_enable()
124 pll_writel(pll, val, PLL_CTRL4); in pll_gf40lp_frac_enable()
132 u32 val; in pll_gf40lp_frac_disable() local
[all …]
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| /linux-4.1.27/arch/tile/include/asm/ |
| D | spinlock_64.h | 30 static inline u32 arch_spin_current(u32 val) in arch_spin_current() argument
32 return val >> __ARCH_SPIN_CURRENT_SHIFT; in arch_spin_current()
39 static inline u32 arch_spin_next(u32 val) in arch_spin_next() argument
41 return val & __ARCH_SPIN_NEXT_MASK; in arch_spin_next()
47 u32 val = lock->lock; in arch_spin_is_locked() local
48 return arch_spin_current(val) != arch_spin_next(val); in arch_spin_is_locked()
60 void arch_spin_lock_slow(arch_spinlock_t *lock, u32 val);
68 u32 val = __insn_fetchadd4(&lock->lock, 1); in arch_spin_lock() local
69 u32 ticket = val & (__ARCH_SPIN_NEXT_MASK | __ARCH_SPIN_NEXT_OVERFLOW); in arch_spin_lock()
70 if (unlikely(arch_spin_current(val) != ticket)) in arch_spin_lock()
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| /linux-4.1.27/scripts/dtc/ |
| D | treesource.c | 64 static void write_propval_string(FILE *f, struct data val) in write_propval_string() argument
66 const char *str = val.val; in write_propval_string()
68 struct marker *m = val.markers; in write_propval_string()
70 assert(str[val.len-1] == '\0'); in write_propval_string()
79 for (i = 0; i < (val.len-1); i++) { in write_propval_string()
132 assert (m->offset == val.len); in write_propval_string()
137 static void write_propval_cells(FILE *f, struct data val) in write_propval_cells() argument
139 void *propend = val.val + val.len; in write_propval_cells()
140 cell_t *cp = (cell_t *)val.val; in write_propval_cells()
141 struct marker *m = val.markers; in write_propval_cells()
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| /linux-4.1.27/drivers/amba/ |
| D | tegra-ahb.c | 157 u32 val; in tegra_ahb_enable_smmu() local
165 val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL); in tegra_ahb_enable_smmu()
166 val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE; in tegra_ahb_enable_smmu()
167 gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL); in tegra_ahb_enable_smmu()
201 u32 val; in tegra_ahb_gizmo_init() local
203 val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM); in tegra_ahb_gizmo_init()
204 val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR; in tegra_ahb_gizmo_init()
205 gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM); in tegra_ahb_gizmo_init()
207 val = gizmo_readl(ahb, AHB_GIZMO_USB); in tegra_ahb_gizmo_init()
208 val |= IMMEDIATE; in tegra_ahb_gizmo_init()
[all …]
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| /linux-4.1.27/arch/c6x/include/asm/ |
| D | unaligned.h | 34 static inline void put_unaligned_le16(u16 val, void *p) in put_unaligned_le16() argument
37 _p[0] = val; in put_unaligned_le16()
38 _p[1] = val >> 8; in put_unaligned_le16()
41 static inline void put_unaligned_be16(u16 val, void *p) in put_unaligned_be16() argument
44 _p[0] = val >> 8; in put_unaligned_be16()
45 _p[1] = val; in put_unaligned_be16()
50 u32 val = (u32) p; in get_unaligned32() local
53 : "+a"(val)); in get_unaligned32()
54 return val; in get_unaligned32()
57 static inline void put_unaligned32(u32 val, void *p) in put_unaligned32() argument
[all …]
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| /linux-4.1.27/drivers/gpu/drm/exynos/ |
| D | exynos_drm_fimd.c | 221 u32 val = readl(ctx->regs + WINCON(win)); in fimd_enable_video_output() local
224 val |= WINCONx_ENWIN; in fimd_enable_video_output()
226 val &= ~WINCONx_ENWIN; in fimd_enable_video_output()
228 writel(val, ctx->regs + WINCON(win)); in fimd_enable_video_output()
235 u32 val = readl(ctx->regs + SHADOWCON); in fimd_enable_shadow_channel_path() local
238 val |= SHADOWCON_CHx_ENABLE(win); in fimd_enable_shadow_channel_path()
240 val &= ~SHADOWCON_CHx_ENABLE(win); in fimd_enable_shadow_channel_path()
242 writel(val, ctx->regs + SHADOWCON); in fimd_enable_shadow_channel_path()
253 u32 val = readl(ctx->regs + WINCON(win)); in fimd_clear_channel() local
255 if (val & WINCONx_ENWIN) { in fimd_clear_channel()
[all …]
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| D | exynos7_drm_decon.c | 100 u32 val = readl(ctx->regs + WINCON(win)); in decon_clear_channel() local
102 if (val & WINCONx_ENWIN) { in decon_clear_channel()
103 val &= ~WINCONx_ENWIN; in decon_clear_channel()
104 writel(val, ctx->regs + WINCON(win)); in decon_clear_channel()
179 u32 val, clkdiv; in decon_commit() local
195 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); in decon_commit()
196 writel(val, ctx->regs + VIDTCON0); in decon_commit()
198 val = VIDTCON1_VSPW(vsync_len - 1); in decon_commit()
199 writel(val, ctx->regs + VIDTCON1); in decon_commit()
207 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); in decon_commit()
[all …]
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| D | exynos_drm_rotator.c | 107 u32 val = rot_read(ROT_CONFIG); in rotator_reg_set_irq() local
110 val |= ROT_CONFIG_IRQ; in rotator_reg_set_irq()
112 val &= ~ROT_CONFIG_IRQ; in rotator_reg_set_irq()
114 rot_write(val, ROT_CONFIG); in rotator_reg_set_irq()
119 u32 val = rot_read(ROT_CONTROL); in rotator_reg_get_fmt() local
121 val &= ROT_CONTROL_FMT_MASK; in rotator_reg_get_fmt()
123 return val; in rotator_reg_get_fmt()
128 u32 val = rot_read(ROT_STATUS); in rotator_reg_get_irq_status() local
130 val = ROT_STATUS_IRQ(val); in rotator_reg_get_irq_status()
132 if (val == ROT_STATUS_IRQ_VAL_COMPLETE) in rotator_reg_get_irq_status()
[all …]
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| /linux-4.1.27/drivers/net/ethernet/neterion/ |
| D | s2io-regs.h | 77 #define ADAPTER_UDPI(val) vBIT(val,36,4) argument
96 #define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60) argument
224 #define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) argument
228 #define TXREQTO_VAL(val) vBIT(val,0,32) argument
266 #define SET_UPDT_CLICKS(val) vBIT(val, 32, 32) argument
272 #define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16) argument
273 #define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5) argument
274 #define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5) argument
275 #define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4) argument
276 #define MDIO_OP(val) vBIT(val, 60, 2) argument
[all …]
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| /linux-4.1.27/drivers/media/platform/s5p-tv/ |
| D | mixer_reg.c | 27 static inline void vp_write(struct mxr_device *mdev, u32 reg_id, u32 val) in vp_write() argument
29 writel(val, mdev->res.vp_regs + reg_id); in vp_write()
33 u32 val, u32 mask) in vp_write_mask() argument
37 val = (val & mask) | (old & ~mask); in vp_write_mask()
38 writel(val, mdev->res.vp_regs + reg_id); in vp_write_mask()
46 static inline void mxr_write(struct mxr_device *mdev, u32 reg_id, u32 val) in mxr_write() argument
48 writel(val, mdev->res.mxr_regs + reg_id); in mxr_write()
52 u32 val, u32 mask) in mxr_write_mask() argument
56 val = (val & mask) | (old & ~mask); in mxr_write_mask()
57 writel(val, mdev->res.mxr_regs + reg_id); in mxr_write_mask()
[all …]
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| /linux-4.1.27/arch/parisc/kernel/ |
| D | module.c | 76 #define RELOC_REACHABLE(val, bits) \ argument
77 (( ( !((val) & (1<<((bits)-1))) && ((val)>>(bits)) != 0 ) || \
78 ( ((val) & (1<<((bits)-1))) && ((val)>>(bits)) != (((__typeof__(val))(~0))>>((bits)+2)))) ? \
81 #define CHECK_RELOC(val, bits) \ argument
82 if (!RELOC_REACHABLE(val, bits)) { \
84 me->name, strtab + sym->st_name, (unsigned long)val, bits); \
548 Elf32_Addr val; in apply_relocate_add() local
575 val = sym->st_value; in apply_relocate_add()
582 (uint32_t)loc, val, addend, in apply_relocate_add()
600 *loc = fsel(val, addend); in apply_relocate_add()
[all …]
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| /linux-4.1.27/drivers/scsi/aic94xx/ |
| D | aic94xx_reg.c | 36 unsigned long offs, u8 val) in asd_write_byte() argument
39 outb(val, in asd_write_byte()
42 writeb(val, asd_ha->io_handle[0].addr + offs); in asd_write_byte()
47 unsigned long offs, u16 val) in asd_write_word() argument
50 outw(val, in asd_write_word()
53 writew(val, asd_ha->io_handle[0].addr + offs); in asd_write_word()
58 unsigned long offs, u32 val) in asd_write_dword() argument
61 outl(val, in asd_write_dword()
64 writel(val, asd_ha->io_handle[0].addr + offs); in asd_write_dword()
72 u8 val; in asd_read_byte() local
[all …]
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| /linux-4.1.27/drivers/net/ethernet/atheros/alx/ |
| D | hw.c | 48 u32 val; in alx_wait_mdio_idle() local
52 val = alx_read_mem32(hw, ALX_MDIO); in alx_wait_mdio_idle()
53 if (!(val & ALX_MDIO_BUSY)) in alx_wait_mdio_idle()
64 u32 val, clk_sel; in alx_read_phy_core() local
75 val = dev << ALX_MDIO_EXTN_DEVAD_SHIFT | in alx_read_phy_core()
77 alx_write_mem32(hw, ALX_MDIO_EXTN, val); in alx_read_phy_core()
79 val = ALX_MDIO_SPRES_PRMBL | ALX_MDIO_START | in alx_read_phy_core()
83 val = ALX_MDIO_SPRES_PRMBL | in alx_read_phy_core()
88 alx_write_mem32(hw, ALX_MDIO, val); in alx_read_phy_core()
93 val = alx_read_mem32(hw, ALX_MDIO); in alx_read_phy_core()
[all …]
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| /linux-4.1.27/drivers/power/ |
| D | olpc_battery.c | 60 union power_supply_propval *val) in olpc_ac_get_prop() argument
71 val->intval = !!(status & BAT_STAT_AC); in olpc_ac_get_prop()
96 static int olpc_bat_get_status(union power_supply_propval *val, uint8_t ec_byte) in olpc_bat_get_status() argument
100 val->intval = POWER_SUPPLY_STATUS_CHARGING; in olpc_bat_get_status()
102 val->intval = POWER_SUPPLY_STATUS_DISCHARGING; in olpc_bat_get_status()
104 val->intval = POWER_SUPPLY_STATUS_FULL; in olpc_bat_get_status()
106 val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; in olpc_bat_get_status()
110 val->intval = POWER_SUPPLY_STATUS_DISCHARGING; in olpc_bat_get_status()
112 val->intval = POWER_SUPPLY_STATUS_FULL; in olpc_bat_get_status()
114 val->intval = POWER_SUPPLY_STATUS_CHARGING; in olpc_bat_get_status()
[all …]
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| D | da9150-charger.c | 50 union power_supply_propval *val) in da9150_charger_supply_online() argument
52 val->intval = (psy == charger->supply_online) ? 1 : 0; in da9150_charger_supply_online()
59 union power_supply_propval *val) in da9150_charger_vbus_voltage_now() argument
69 val->intval = v_val * 1000; in da9150_charger_vbus_voltage_now()
75 union power_supply_propval *val) in da9150_charger_ibus_current_avg() argument
85 val->intval = i_val * 1000; in da9150_charger_ibus_current_avg()
91 union power_supply_propval *val) in da9150_charger_tjunc_temp() argument
101 val->intval = t_val / 100; in da9150_charger_tjunc_temp()
115 union power_supply_propval *val) in da9150_charger_get_prop() argument
122 ret = da9150_charger_supply_online(charger, psy, val); in da9150_charger_get_prop()
[all …]
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| D | max14577_charger.c | 37 enum maxim_device_type dev_type, u8 val) { in maxim_get_charger_type() argument
38 switch (val) { in maxim_get_charger_type()
45 return val; in maxim_get_charger_type()
49 val |= 0x8; in maxim_get_charger_type()
50 return val; in maxim_get_charger_type()
52 WARN_ONCE(1, "max14577: Unsupported chgtyp register value 0x%02x", val); in maxim_get_charger_type()
53 return val; in maxim_get_charger_type()
57 static int max14577_get_charger_state(struct max14577_charger *chg, int *val) in max14577_get_charger_state() argument
79 *val = POWER_SUPPLY_STATUS_DISCHARGING; in max14577_get_charger_state()
90 *val = POWER_SUPPLY_STATUS_FULL; in max14577_get_charger_state()
[all …]
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| /linux-4.1.27/arch/powerpc/include/asm/ |
| D | feature-fixups.h | 40 #define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \ argument
47 FTR_ENTRY_LONG val; \
62 #define END_FTR_SECTION_NESTED(msk, val, label) \ argument
64 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
66 #define END_FTR_SECTION(msk, val) \ argument
67 END_FTR_SECTION_NESTED(msk, val, 97)
74 #define ALT_FTR_SECTION_END_NESTED(msk, val, label) \ argument
75 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
80 #define ALT_FTR_SECTION_END(msk, val) \ argument
81 ALT_FTR_SECTION_END_NESTED(msk, val, 97)
[all …]
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| /linux-4.1.27/arch/arm/mach-imx/ |
| D | pm-imx6.c | 200 u32 val = readl_relaxed(ccm_base + CGPR); in imx6q_set_int_mem_clk_lpm() local
202 val &= ~BM_CGPR_INT_MEM_CLK_LPM; in imx6q_set_int_mem_clk_lpm()
204 val |= BM_CGPR_INT_MEM_CLK_LPM; in imx6q_set_int_mem_clk_lpm()
205 writel_relaxed(val, ccm_base + CGPR); in imx6q_set_int_mem_clk_lpm()
210 u32 val; in imx6_enable_rbc() local
219 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
220 val &= ~BM_CCR_RBC_EN; in imx6_enable_rbc()
221 val |= enable ? BM_CCR_RBC_EN : 0; in imx6_enable_rbc()
222 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
225 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
[all …]
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| /linux-4.1.27/arch/arm/include/asm/ |
| D | cp15.h | 56 unsigned long val; in get_cr() local
57 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); in get_cr()
58 return val; in get_cr()
61 static inline void set_cr(unsigned long val) in set_cr() argument
64 : : "r" (val) : "cc"); in set_cr()
70 unsigned int val; in get_auxcr() local
71 asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val)); in get_auxcr()
72 return val; in get_auxcr()
75 static inline void set_auxcr(unsigned int val) in set_auxcr() argument
78 : : "r" (val)); in set_auxcr()
[all …]
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| D | arch_timer.h | 21 void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) in arch_timer_reg_write_cp15() argument
26 asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val)); in arch_timer_reg_write_cp15()
29 asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); in arch_timer_reg_write_cp15()
35 asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val)); in arch_timer_reg_write_cp15()
38 asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val)); in arch_timer_reg_write_cp15()
49 u32 val = 0; in arch_timer_reg_read_cp15() local
54 asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); in arch_timer_reg_read_cp15()
57 asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); in arch_timer_reg_read_cp15()
63 asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val)); in arch_timer_reg_read_cp15()
66 asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val)); in arch_timer_reg_read_cp15()
[all …]
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| /linux-4.1.27/sound/soc/ |
| D | soc-ops.c | 69 unsigned int val, item; in snd_soc_get_enum_double() local
76 val = (reg_val >> e->shift_l) & e->mask; in snd_soc_get_enum_double()
77 item = snd_soc_enum_val_to_item(e, val); in snd_soc_get_enum_double()
80 val = (reg_val >> e->shift_l) & e->mask; in snd_soc_get_enum_double()
81 item = snd_soc_enum_val_to_item(e, val); in snd_soc_get_enum_double()
104 unsigned int val; in snd_soc_put_enum_double() local
109 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; in snd_soc_put_enum_double()
114 val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r; in snd_soc_put_enum_double()
118 return snd_soc_component_update_bits(component, e->reg, mask, val); in snd_soc_put_enum_double()
142 unsigned int val; in snd_soc_read_signed() local
[all …]
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| D | soc-io.c | 29 unsigned int reg, unsigned int *val) in snd_soc_component_read() argument
34 ret = regmap_read(component->regmap, reg, val); in snd_soc_component_read()
36 ret = component->read(component, reg, val); in snd_soc_component_read()
53 unsigned int reg, unsigned int val) in snd_soc_component_write() argument
56 return regmap_write(component->regmap, reg, val); in snd_soc_component_write()
58 return component->write(component, reg, val); in snd_soc_component_write()
66 unsigned int mask, unsigned int val, bool *change) in snd_soc_component_update_bits_legacy() argument
80 new = (old & ~mask) | (val & mask); in snd_soc_component_update_bits_legacy()
102 unsigned int reg, unsigned int mask, unsigned int val) in snd_soc_component_update_bits() argument
109 val, &change); in snd_soc_component_update_bits()
[all …]
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| /linux-4.1.27/sound/hda/ |
| D | hdac_regmap.c | 153 unsigned int reg, unsigned int *val) in hda_reg_read_stereo_amp() argument
165 *val = left | (right << 8); in hda_reg_read_stereo_amp()
171 unsigned int reg, unsigned int val) in hda_reg_write_stereo_amp() argument
183 left = val & 0xff; in hda_reg_write_stereo_amp()
184 right = (val >> 8) & 0xff; in hda_reg_write_stereo_amp()
201 unsigned int *val) in hda_reg_read_coef() argument
214 return snd_hdac_exec_verb(codec, verb, 0, val); in hda_reg_read_coef()
219 unsigned int val) in hda_reg_write_coef() argument
232 (val & 0xffff); in hda_reg_write_coef()
236 static int hda_reg_read(void *context, unsigned int reg, unsigned int *val) in hda_reg_read() argument
[all …]
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| /linux-4.1.27/drivers/input/mouse/ |
| D | elan_i2c_i2c.c | 68 u16 reg, u8 *val, u16 len) in elan_i2c_read_block() argument
84 .buf = val, in elan_i2c_read_block()
93 static int elan_i2c_read_cmd(struct i2c_client *client, u16 reg, u8 *val) in elan_i2c_read_cmd() argument
97 retval = elan_i2c_read_block(client, reg, val, ETP_I2C_INF_LENGTH); in elan_i2c_read_cmd()
136 u8 val[256]; in elan_i2c_initialize() local
148 error = i2c_master_recv(client, val, ETP_I2C_INF_LENGTH); in elan_i2c_initialize()
155 val, ETP_I2C_DESC_LENGTH); in elan_i2c_initialize()
162 val, ETP_I2C_REPORT_DESC_LENGTH); in elan_i2c_initialize()
179 u8 val[2]; in elan_i2c_power_control() local
183 error = elan_i2c_read_cmd(client, ETP_I2C_POWER_CMD, val); in elan_i2c_power_control()
[all …]
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| D | elan_i2c_smbus.c | 117 static int elan_smbus_calibrate_result(struct i2c_client *client, u8 *val) in elan_smbus_calibrate_result() argument
122 ETP_SMBUS_CALIBRATE_QUERY, val); in elan_smbus_calibrate_result()
133 u8 val[3]; in elan_smbus_get_baseline_data() local
139 val); in elan_smbus_get_baseline_data()
143 *value = be16_to_cpup((__be16 *)val); in elan_smbus_get_baseline_data()
152 u8 val[3]; in elan_smbus_get_version() local
157 val); in elan_smbus_get_version()
164 *version = val[2]; in elan_smbus_get_version()
171 u8 val[3]; in elan_smbus_get_sm_version() local
174 ETP_SMBUS_SM_VERSION_CMD, val); in elan_smbus_get_sm_version()
[all …]
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| /linux-4.1.27/drivers/pcmcia/ |
| D | bcm63xx_pcmcia.c | 40 u32 val, u32 off) in pcmcia_writel() argument
42 bcm_writel(val, skt->base + off); in pcmcia_writel()
80 u32 val; in bcm63xx_pcmcia_set_socket() local
90 val = pcmcia_readl(skt, PCMCIA_C1_REG); in bcm63xx_pcmcia_set_socket()
92 val |= PCMCIA_C1_RESET_MASK; in bcm63xx_pcmcia_set_socket()
94 val &= ~PCMCIA_C1_RESET_MASK; in bcm63xx_pcmcia_set_socket()
98 val ^= PCMCIA_C1_RESET_MASK; in bcm63xx_pcmcia_set_socket()
100 pcmcia_writel(skt, val, PCMCIA_C1_REG); in bcm63xx_pcmcia_set_socket()
165 u32 val; in __get_socket_status() local
170 val = pcmcia_readl(skt, PCMCIA_C1_REG); in __get_socket_status()
[all …]
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| /linux-4.1.27/drivers/spi/ |
| D | spi-nuc900.c | 73 unsigned int val; in nuc900_slave_select() local
80 val = __raw_readl(hw->regs + USI_SSR); in nuc900_slave_select()
83 val &= ~SELECTLEV; in nuc900_slave_select()
85 val |= SELECTLEV; in nuc900_slave_select()
88 val &= ~SELECTSLAVE; in nuc900_slave_select()
90 val |= SELECTSLAVE; in nuc900_slave_select()
92 __raw_writel(val, hw->regs + USI_SSR); in nuc900_slave_select()
94 val = __raw_readl(hw->regs + USI_CNT); in nuc900_slave_select()
97 val &= ~SELECTPOL; in nuc900_slave_select()
99 val |= SELECTPOL; in nuc900_slave_select()
[all …]
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| /linux-4.1.27/drivers/usb/chipidea/ |
| D | usbmisc_imx.c | 93 u32 val = 0; in usbmisc_imx25_init() local
101 val = readl(usbmisc->base); in usbmisc_imx25_init()
102 val &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PP_BIT); in usbmisc_imx25_init()
103 val |= (MX25_EHCI_INTERFACE_DIFF_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; in usbmisc_imx25_init()
104 val |= (MX25_OTG_PM_BIT | MX25_OTG_OCPOL_BIT); in usbmisc_imx25_init()
105 writel(val, usbmisc->base); in usbmisc_imx25_init()
108 val = readl(usbmisc->base); in usbmisc_imx25_init()
109 val &= ~(MX25_H1_SIC_MASK | MX25_H1_PP_BIT | MX25_H1_IPPUE_UP_BIT); in usbmisc_imx25_init()
110 val |= (MX25_EHCI_INTERFACE_SINGLE_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; in usbmisc_imx25_init()
111 val |= (MX25_H1_PM_BIT | MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | in usbmisc_imx25_init()
[all …]
|
| /linux-4.1.27/sound/pci/lola/ |
| D | lola_proc.c | 32 unsigned int val; in print_audio_widget() local
34 lola_read_param(chip, nid, LOLA_PAR_AUDIO_WIDGET_CAP, &val); in print_audio_widget()
35 snd_iprintf(buffer, "Node 0x%02x %s wcaps 0x%x\n", nid, name, val); in print_audio_widget()
36 lola_read_param(chip, nid, LOLA_PAR_STREAM_FORMATS, &val); in print_audio_widget()
37 snd_iprintf(buffer, " Formats: 0x%x\n", val); in print_audio_widget()
44 unsigned int val; in print_pin_widget() local
46 lola_read_param(chip, nid, LOLA_PAR_AUDIO_WIDGET_CAP, &val); in print_pin_widget()
47 snd_iprintf(buffer, "Node 0x%02x %s wcaps 0x%x\n", nid, name, val); in print_pin_widget()
48 if (val == 0x00400200) in print_pin_widget()
50 lola_read_param(chip, nid, ampcap, &val); in print_pin_widget()
[all …]
|
| /linux-4.1.27/arch/ia64/include/asm/sn/ |
| D | io.h | 42 #define __sn_setq_relaxed(addr, val) \ argument
43 writeq((__sn_readq_relaxed(addr) | (val)), (addr))
44 #define __sn_clrq_relaxed(addr, val) \ argument
45 writeq((__sn_readq_relaxed(addr) & ~(val)), (addr))
99 ___sn_outb (unsigned char val, unsigned long port) in ___sn_outb() argument
104 *addr = val; in ___sn_outb()
110 ___sn_outw (unsigned short val, unsigned long port) in ___sn_outw() argument
115 *addr = val; in ___sn_outw()
121 ___sn_outl (unsigned int val, unsigned long port) in ___sn_outl() argument
126 *addr = val; in ___sn_outl()
[all …]
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| /linux-4.1.27/tools/power/cpupower/utils/helpers/ |
| D | msr.c | 26 int read_msr(int cpu, unsigned int idx, unsigned long long *val) in read_msr() argument
37 if (read(fd, val, sizeof *val) != sizeof *val) in read_msr()
55 int write_msr(int cpu, unsigned int idx, unsigned long long val) in write_msr() argument
66 if (write(fd, &val, sizeof val) != sizeof val) in write_msr()
77 unsigned long long val; in msr_intel_get_perf_bias() local
83 ret = read_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &val); in msr_intel_get_perf_bias()
86 return val; in msr_intel_get_perf_bias()
89 int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val) in msr_intel_set_perf_bias() argument
96 ret = write_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, val); in msr_intel_set_perf_bias()
104 unsigned long long val; in msr_intel_get_turbo_ratio() local
[all …]
|
| /linux-4.1.27/drivers/clk/ |
| D | clk-nomadik.c | 69 u32 val; in nomadik_clk_reboot_handler() local
72 val = readl(src_base + SRC_XTALCR); in nomadik_clk_reboot_handler()
73 val &= ~SRC_XTALCR_MXTALOVER; in nomadik_clk_reboot_handler()
74 val |= SRC_XTALCR_MXTALEN; in nomadik_clk_reboot_handler()
76 writel(val, src_base + SRC_XTALCR); in nomadik_clk_reboot_handler()
92 u32 val; in nomadik_src_init() local
107 val = readl(src_base + SRC_CR); in nomadik_src_init()
108 val |= SRC_CR_T0_ENSEL; in nomadik_src_init()
109 val |= SRC_CR_T1_ENSEL; in nomadik_src_init()
110 val |= SRC_CR_T2_ENSEL; in nomadik_src_init()
[all …]
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| /linux-4.1.27/drivers/gpu/drm/sti/ |
| D | sti_awg_utils.c | 121 long int val; in sti_awg_generate_code_data_enable_mode() local
127 val = timing->blanking_level; in sti_awg_generate_code_data_enable_mode()
129 ret |= awg_generate_instr(RPLSET, val, 0, data_en, fwparams); in sti_awg_generate_code_data_enable_mode()
131 val = timing->trailing_lines - 1; in sti_awg_generate_code_data_enable_mode()
133 ret |= awg_generate_instr(REPLAY, val, 0, data_en, fwparams); in sti_awg_generate_code_data_enable_mode()
138 val = timing->blanking_level; in sti_awg_generate_code_data_enable_mode()
140 ret |= awg_generate_instr(RPLSET, val, 0, data_en, fwparams); in sti_awg_generate_code_data_enable_mode()
142 val = timing->trailing_pixels - 1; in sti_awg_generate_code_data_enable_mode()
144 ret |= awg_generate_instr(SKIP, val, 0, data_en, fwparams); in sti_awg_generate_code_data_enable_mode()
148 val = timing->blanking_level; in sti_awg_generate_code_data_enable_mode()
[all …]
|
| /linux-4.1.27/tools/include/tools/ |
| D | le_byteshift.h | 22 static inline void __put_unaligned_le16(uint16_t val, uint8_t *p) in __put_unaligned_le16() argument
24 *p++ = val; in __put_unaligned_le16()
25 *p++ = val >> 8; in __put_unaligned_le16()
28 static inline void __put_unaligned_le32(uint32_t val, uint8_t *p) in __put_unaligned_le32() argument
30 __put_unaligned_le16(val >> 16, p + 2); in __put_unaligned_le32()
31 __put_unaligned_le16(val, p); in __put_unaligned_le32()
34 static inline void __put_unaligned_le64(uint64_t val, uint8_t *p) in __put_unaligned_le64() argument
36 __put_unaligned_le32(val >> 32, p + 4); in __put_unaligned_le64()
37 __put_unaligned_le32(val, p); in __put_unaligned_le64()
55 static inline void put_unaligned_le16(uint16_t val, void *p) in put_unaligned_le16() argument
[all …]
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| D | be_byteshift.h | 22 static inline void __put_unaligned_be16(uint16_t val, uint8_t *p) in __put_unaligned_be16() argument
24 *p++ = val >> 8; in __put_unaligned_be16()
25 *p++ = val; in __put_unaligned_be16()
28 static inline void __put_unaligned_be32(uint32_t val, uint8_t *p) in __put_unaligned_be32() argument
30 __put_unaligned_be16(val >> 16, p); in __put_unaligned_be32()
31 __put_unaligned_be16(val, p + 2); in __put_unaligned_be32()
34 static inline void __put_unaligned_be64(uint64_t val, uint8_t *p) in __put_unaligned_be64() argument
36 __put_unaligned_be32(val >> 32, p); in __put_unaligned_be64()
37 __put_unaligned_be32(val, p + 4); in __put_unaligned_be64()
55 static inline void put_unaligned_be16(uint16_t val, void *p) in put_unaligned_be16() argument
[all …]
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| /linux-4.1.27/include/linux/unaligned/ |
| D | le_byteshift.h | 22 static inline void __put_unaligned_le16(u16 val, u8 *p) in __put_unaligned_le16() argument
24 *p++ = val; in __put_unaligned_le16()
25 *p++ = val >> 8; in __put_unaligned_le16()
28 static inline void __put_unaligned_le32(u32 val, u8 *p) in __put_unaligned_le32() argument
30 __put_unaligned_le16(val >> 16, p + 2); in __put_unaligned_le32()
31 __put_unaligned_le16(val, p); in __put_unaligned_le32()
34 static inline void __put_unaligned_le64(u64 val, u8 *p) in __put_unaligned_le64() argument
36 __put_unaligned_le32(val >> 32, p + 4); in __put_unaligned_le64()
37 __put_unaligned_le32(val, p); in __put_unaligned_le64()
55 static inline void put_unaligned_le16(u16 val, void *p) in put_unaligned_le16() argument
[all …]
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| D | be_byteshift.h | 22 static inline void __put_unaligned_be16(u16 val, u8 *p) in __put_unaligned_be16() argument
24 *p++ = val >> 8; in __put_unaligned_be16()
25 *p++ = val; in __put_unaligned_be16()
28 static inline void __put_unaligned_be32(u32 val, u8 *p) in __put_unaligned_be32() argument
30 __put_unaligned_be16(val >> 16, p); in __put_unaligned_be32()
31 __put_unaligned_be16(val, p + 2); in __put_unaligned_be32()
34 static inline void __put_unaligned_be64(u64 val, u8 *p) in __put_unaligned_be64() argument
36 __put_unaligned_be32(val >> 32, p); in __put_unaligned_be64()
37 __put_unaligned_be32(val, p + 4); in __put_unaligned_be64()
55 static inline void put_unaligned_be16(u16 val, void *p) in put_unaligned_be16() argument
[all …]
|
| /linux-4.1.27/include/linux/amba/ |
| D | clcd.h | 192 u32 val, cpl; in clcdfb_decode() local
197 val = ((var->xres / 16) - 1) << 2; in clcdfb_decode()
198 val |= (var->hsync_len - 1) << 8; in clcdfb_decode()
199 val |= (var->right_margin - 1) << 16; in clcdfb_decode()
200 val |= (var->left_margin - 1) << 24; in clcdfb_decode()
201 regs->tim0 = val; in clcdfb_decode()
203 val = var->yres; in clcdfb_decode()
205 val /= 2; in clcdfb_decode()
206 val -= 1; in clcdfb_decode()
207 val |= (var->vsync_len - 1) << 10; in clcdfb_decode()
[all …]
|
| /linux-4.1.27/drivers/input/touchscreen/ |
| D | bcm_iproc_tsc.c | 266 u32 val; in iproc_ts_start() local
281 val = TS_PEN_INTR_MASK | TS_FIFO_INTR_MASK; in iproc_ts_start()
282 writel(val, priv->regs + INTERRUPT_MASK); in iproc_ts_start()
287 val = 0; in iproc_ts_start()
288 val |= priv->cfg_params.scanning_period << SCANNING_PERIOD_SHIFT; in iproc_ts_start()
289 val |= priv->cfg_params.debounce_timeout << DEBOUNCE_TIMEOUT_SHIFT; in iproc_ts_start()
290 val |= priv->cfg_params.settling_timeout << SETTLING_TIMEOUT_SHIFT; in iproc_ts_start()
291 val |= priv->cfg_params.touch_timeout << TOUCH_TIMEOUT_SHIFT; in iproc_ts_start()
292 writel(val, priv->regs + REGCTL1); in iproc_ts_start()
295 val = readl(priv->regs + INTERRUPT_STATUS); in iproc_ts_start()
[all …]
|
| /linux-4.1.27/drivers/clk/hisilicon/ |
| D | clk-hix5hd2.c | 175 u32 val; in clk_ether_prepare() local
177 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()
178 val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask; in clk_ether_prepare()
179 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
180 val &= ~(clk->ctrl_rst_mask); in clk_ether_prepare()
181 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
183 val = readl_relaxed(clk->phy_reg); in clk_ether_prepare()
184 val |= clk->phy_clk_mask; in clk_ether_prepare()
185 val &= ~(clk->phy_rst_mask); in clk_ether_prepare()
186 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare()
[all …]
|
| /linux-4.1.27/drivers/net/ethernet/dec/tulip/ |
| D | xircom_cb.c | 43 #define xw32(reg, val) iowrite32(val, ioaddr + (reg)) argument
502 u32 val; in initialize_card() local
507 val = xr32(CSR0); in initialize_card()
508 val |= 0x01; /* Software reset */ in initialize_card()
509 xw32(CSR0, val); in initialize_card()
513 val = xr32(CSR0); in initialize_card()
514 val &= ~0x01; /* disable Software reset */ in initialize_card()
515 xw32(CSR0, val); in initialize_card()
518 val = 0; /* Value 0x00 is a safe and conservative value in initialize_card()
520 xw32(CSR0, val); in initialize_card()
[all …]
|
| /linux-4.1.27/arch/powerpc/perf/ |
| D | core-fsl-emb.c | 58 unsigned long val; in read_pmc() local
62 val = mfpmr(PMRN_PMC0); in read_pmc()
65 val = mfpmr(PMRN_PMC1); in read_pmc()
68 val = mfpmr(PMRN_PMC2); in read_pmc()
71 val = mfpmr(PMRN_PMC3); in read_pmc()
74 val = mfpmr(PMRN_PMC4); in read_pmc()
77 val = mfpmr(PMRN_PMC5); in read_pmc()
81 val = 0; in read_pmc()
83 return val; in read_pmc()
89 static void write_pmc(int idx, unsigned long val) in write_pmc() argument
[all …]
|
| /linux-4.1.27/drivers/media/usb/gspca/stv06xx/ |
| D | stv06xx_pb0100.c | 98 err = pb0100_set_autogain(gspca_dev, ctrl->val); in pb0100_s_ctrl()
101 if (ctrl->val) in pb0100_s_ctrl()
103 err = pb0100_set_gain(gspca_dev, ctrls->gain->val); in pb0100_s_ctrl()
106 err = pb0100_set_exposure(gspca_dev, ctrls->exposure->val); in pb0100_s_ctrl()
109 err = pb0100_set_autogain_target(gspca_dev, ctrl->val); in pb0100_s_ctrl()
330 static int pb0100_set_gain(struct gspca_dev *gspca_dev, __s32 val) in pb0100_set_gain() argument
336 err = stv06xx_write_sensor(sd, PB_G1GAIN, val); in pb0100_set_gain()
338 err = stv06xx_write_sensor(sd, PB_G2GAIN, val); in pb0100_set_gain()
339 PDEBUG(D_CONF, "Set green gain to %d, status: %d", val, err); in pb0100_set_gain()
342 err = pb0100_set_red_balance(gspca_dev, ctrls->red->val); in pb0100_set_gain()
[all …]
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| /linux-4.1.27/drivers/base/ |
| D | property.c | 64 enum dev_prop_type type, void *val, size_t nval) in pset_prop_read_array() argument
76 if (!val) in pset_prop_read_array()
101 memcpy(val, prop->value.raw_data, nval * item_size); in pset_prop_read_array()
158 u8 *val, size_t nval) in device_property_read_u8_array() argument
160 return fwnode_property_read_u8_array(dev_fwnode(dev), propname, val, nval); in device_property_read_u8_array()
182 u16 *val, size_t nval) in device_property_read_u16_array() argument
184 return fwnode_property_read_u16_array(dev_fwnode(dev), propname, val, nval); in device_property_read_u16_array()
206 u32 *val, size_t nval) in device_property_read_u32_array() argument
208 return fwnode_property_read_u32_array(dev_fwnode(dev), propname, val, nval); in device_property_read_u32_array()
230 u64 *val, size_t nval) in device_property_read_u64_array() argument
[all …]
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| /linux-4.1.27/drivers/pinctrl/qcom/ |
| D | pinctrl-msm.c | 145 u32 val; in msm_pinmux_set_mux() local
160 val = readl(pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
161 val &= ~(0x7 << g->mux_bit); in msm_pinmux_set_mux()
162 val |= i << g->mux_bit; in msm_pinmux_set_mux()
163 writel(val, pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
212 static unsigned msm_regval_to_drive(u32 val) in msm_regval_to_drive() argument
214 return (val + 1) * 2; in msm_regval_to_drive()
228 u32 val; in msm_config_group_get() local
236 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_get()
237 arg = (val >> bit) & mask; in msm_config_group_get()
[all …]
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| /linux-4.1.27/drivers/media/usb/gspca/ |
| D | ov534.c | 136 const u8 (*val)[2]; member
610 static void ov534_reg_write(struct gspca_dev *gspca_dev, u16 reg, u8 val) in ov534_reg_write() argument
618 PDEBUG(D_USBO, "SET 01 0000 %04x %02x", reg, val); in ov534_reg_write()
619 gspca_dev->usb_buf[0] = val; in ov534_reg_write()
702 static void sccb_reg_write(struct gspca_dev *gspca_dev, u8 reg, u8 val) in sccb_reg_write() argument
704 PDEBUG(D_USBO, "sccb write: %02x %02x", reg, val); in sccb_reg_write()
706 ov534_reg_write(gspca_dev, OV534_REG_WRITE, val); in sccb_reg_write()
809 static void sethue(struct gspca_dev *gspca_dev, s32 val) in sethue() argument
827 huesin = fixp_sin16(val) * 0x80 / 0x7fff; in sethue()
828 huecos = fixp_cos16(val) * 0x80 / 0x7fff; in sethue()
[all …]
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| D | ov534_9.c | 1119 static void reg_w_i(struct gspca_dev *gspca_dev, u16 reg, u8 val) in reg_w_i() argument
1126 gspca_dev->usb_buf[0] = val; in reg_w_i()
1138 static void reg_w(struct gspca_dev *gspca_dev, u16 reg, u8 val) in reg_w() argument
1140 PDEBUG(D_USBO, "reg_w [%04x] = %02x", reg, val); in reg_w()
1141 reg_w_i(gspca_dev, reg, val); in reg_w()
1189 static void sccb_write(struct gspca_dev *gspca_dev, u8 reg, u8 val) in sccb_write() argument
1191 PDEBUG(D_USBO, "sccb_write [%02x] = %02x", reg, val); in sccb_write()
1193 reg_w_i(gspca_dev, OV534_REG_WRITE, val); in sccb_write()
1269 u8 val; in setbrightness() local
1274 val = 0x76; in setbrightness()
[all …]
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| /linux-4.1.27/drivers/pwm/ |
| D | pwm-twl.c | 109 u8 val; in twl4030_pwm_enable() local
112 ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, &val, TWL4030_GPBR1_REG); in twl4030_pwm_enable()
118 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_enable()
120 ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_GPBR1_REG); in twl4030_pwm_enable()
124 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_enable()
126 ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_GPBR1_REG); in twl4030_pwm_enable()
139 u8 val; in twl4030_pwm_disable() local
142 ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, &val, TWL4030_GPBR1_REG); in twl4030_pwm_disable()
148 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_disable()
150 ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_GPBR1_REG); in twl4030_pwm_disable()
[all …]
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| /linux-4.1.27/arch/arm/mm/ |
| D | alignment.c | 198 #define __get8_unaligned_check(ins,val,addr,err) \ argument
213 : "=r" (err), "=&r" (val), "=r" (addr) \
216 #define __get16_unaligned_check(ins,val,addr) \ argument
220 val = v << ((BE) ? 8 : 0); \
222 val |= v << ((BE) ? 0 : 8); \
227 #define get16_unaligned_check(val,addr) \ argument
228 __get16_unaligned_check("ldrb",val,addr)
230 #define get16t_unaligned_check(val,addr) \ argument
231 __get16_unaligned_check("ldrbt",val,addr)
233 #define __get32_unaligned_check(ins,val,addr) \ argument
[all …]
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| /linux-4.1.27/net/sched/ |
| D | em_cmp.c | 30 u32 val = 0; in em_cmp_match() local
37 val = *ptr; in em_cmp_match()
41 val = get_unaligned_be16(ptr); in em_cmp_match()
44 val = be16_to_cpu(val); in em_cmp_match()
51 val = get_unaligned_be32(ptr); in em_cmp_match()
54 val = be32_to_cpu(val); in em_cmp_match()
62 val &= cmp->mask; in em_cmp_match()
66 return val == cmp->val; in em_cmp_match()
68 return val < cmp->val; in em_cmp_match()
70 return val > cmp->val; in em_cmp_match()
|
| /linux-4.1.27/drivers/net/ethernet/apm/xgene/ |
| D | xgene_enet_hw.h | 31 static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len) in xgene_set_bits() argument
37 *dst |= (val << start) & mask; in xgene_set_bits()
40 static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) in xgene_get_bits() argument
42 return (val & GENMASK(end, start)) >> start; in xgene_get_bits()
127 #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16) argument
145 #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3) argument
147 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2) argument
148 #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12) argument
149 #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) argument
150 #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2) argument
[all …]
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| /linux-4.1.27/drivers/misc/ |
| D | isl29020.c | 39 int val; in als_sensing_range_show() local
41 val = i2c_smbus_read_byte_data(client, 0x00); in als_sensing_range_show()
43 if (val < 0) in als_sensing_range_show()
44 return val; in als_sensing_range_show()
45 return sprintf(buf, "%d000\n", 1 << (2 * (val & 3))); in als_sensing_range_show()
53 int ret_val, val; in als_lux_input_data_show() local
77 val = i2c_smbus_read_byte_data(client, 0x00); in als_lux_input_data_show()
79 if (val < 0) in als_lux_input_data_show()
80 return val; in als_lux_input_data_show()
81 lux = ((((1 << (2 * (val & 3))))*1000) * ret_val) / 65536; in als_lux_input_data_show()
[all …]
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| /linux-4.1.27/drivers/clocksource/ |
| D | mtk_timer.c | 30 #define GPT_IRQ_ENABLE(val) BIT((val) - 1) argument
32 #define GPT_IRQ_ACK(val) BIT((val) - 1) argument
34 #define TIMER_CTRL_REG(val) (0x10 * (val)) argument
35 #define TIMER_CTRL_OP(val) (((val) & 0x3) << 4) argument
43 #define TIMER_CLK_REG(val) (0x04 + (0x10 * (val))) argument
44 #define TIMER_CLK_SRC(val) (((val) & 0x1) << 4) argument
50 #define TIMER_CNT_REG(val) (0x08 + (0x10 * (val))) argument
51 #define TIMER_CMP_REG(val) (0x0C + (0x10 * (val))) argument
70 u32 val; in mtk_clkevt_time_stop() local
72 val = readl(evt->gpt_base + TIMER_CTRL_REG(timer)); in mtk_clkevt_time_stop()
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| /linux-4.1.27/include/media/ |
| D | lirc.h | 23 #define LIRC_SPACE(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_SPACE) argument
24 #define LIRC_PULSE(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_PULSE) argument
25 #define LIRC_FREQUENCY(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_FREQUENCY) argument
26 #define LIRC_TIMEOUT(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_TIMEOUT) argument
28 #define LIRC_VALUE(val) ((val)&LIRC_VALUE_MASK) argument
29 #define LIRC_MODE2(val) ((val)&LIRC_MODE2_MASK) argument
31 #define LIRC_IS_SPACE(val) (LIRC_MODE2(val) == LIRC_MODE2_SPACE) argument
32 #define LIRC_IS_PULSE(val) (LIRC_MODE2(val) == LIRC_MODE2_PULSE) argument
33 #define LIRC_IS_FREQUENCY(val) (LIRC_MODE2(val) == LIRC_MODE2_FREQUENCY) argument
34 #define LIRC_IS_TIMEOUT(val) (LIRC_MODE2(val) == LIRC_MODE2_TIMEOUT) argument
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| /linux-4.1.27/drivers/pinctrl/spear/ |
| D | pinctrl-spear320.c | 38 .val = 0x0,
46 .val = 0x1,
54 .val = 0x2,
62 .val = 0x3,
70 .val = 0x1,
467 .val = PMX_CLCD_PL_69_VAL,
473 .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
480 .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
486 .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
524 .val = 0,
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| /linux-4.1.27/sound/oss/ |
| D | sound_timer.c | 184 int val; in timer_ioctl() local
189 val = TMR_INTERNAL; in timer_ioctl()
206 if (get_user(val, p)) in timer_ioctl()
208 if (val) in timer_ioctl()
210 if (val < 1) in timer_ioctl()
211 val = 1; in timer_ioctl()
212 if (val > 1000) in timer_ioctl()
213 val = 1000; in timer_ioctl()
214 curr_timebase = val; in timer_ioctl()
216 val = curr_timebase; in timer_ioctl()
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| /linux-4.1.27/net/netfilter/ |
| D | nf_sockopt.c | 62 int val, int get) in nf_sockopt_find() argument
73 if (val >= ops->get_optmin && in nf_sockopt_find()
74 val < ops->get_optmax) in nf_sockopt_find()
77 if (val >= ops->set_optmin && in nf_sockopt_find()
78 val < ops->set_optmax) in nf_sockopt_find()
92 static int nf_sockopt(struct sock *sk, u_int8_t pf, int val, in nf_sockopt() argument
98 ops = nf_sockopt_find(sk, pf, val, get); in nf_sockopt()
103 ret = ops->get(sk, val, opt, len); in nf_sockopt()
105 ret = ops->set(sk, val, opt, *len); in nf_sockopt()
111 int nf_setsockopt(struct sock *sk, u_int8_t pf, int val, char __user *opt, in nf_setsockopt() argument
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